Silicon-based Thin Film

Transistor Technologies
Prof. Po-Tsun Liu
Institute of Electro-Optical Engineering,
National Yang Ming Chiao Tung University
TEL: (03) 5712121 ext. 52994 1
Active Matrix TFT-LCD Display

Adapted from E. Kaneko, “Liquid Crystal TV Displays,” KTK Scientific (1987)

active element is used as a switch to store charge on LC capacitor

2
Cross Section of A Pixel and Equivalent Circuit

TFT

Scan line LC layer

ITO (TFT) Capacitor

Data line
Example: a-Si TFT LCD
ITO (CF) COM line

3
 TFT-LCD Display Basics

上偏光片
(TOP POLARIZER)
彩色濾光片 (CF)
光源經液晶
層扭轉90°
液晶層 (LC)
TFT Turn
TFT Turn
OFF
~ ~ ON
TFT基板 (TFT PANEL)

下偏光片
(DOWN POLARIZER)
背光源 (BACKLIGHT)

In each pixel, the liquid crystal layer functions as a light shutter, in which the switch is
controlled by the TFT. An unpolarization backlight is incident to pass or not to pass a pair
of polarizer, whose polarization direction is vertical to each other.
4
 Full Color Display of TFT-LCD

紅
黃 紫
白
綠 青 藍

DATA DRIVER IC

R G B R G B
R G B R G B
R G B R G B
R G B R G B
R G B R G B
5
SCAN DRIVER IC TFT
 Functions of TFT Device
1. In the TFT-LCD display, TFT device acts as a switch to conduct
electric current charging the LC capacitor and storage capacitor.
2. When the TFT device is turned on, the “signal” is written (recorded)
into the LC capacitor. With TFT turned-off, “signal” will be locked on
the LC capacitor and prevent it from being leaky.
VD> 0
“off” TFT acts as a switch in AMLCDs !
Electron flow
VG> VT> 0
D S TFT元件
Metal Gate
+++++++
SiO2 -------
n+ n+
Glass
G 液晶
S (source) D (drain) 保持電容
“on”
D S 加入電壓

Glass
6
G (gate) G
 TFT in AMOLEDs

TFT acts as a driver in AMOLEDs !

Bottom Emission Top Emission 7

 Classification of Semiconductor Silicon
Amorphous Polycrystalline Single Crystal
Structure Structure Structure

Grain
Boundary

Grain
VG VD
VD> 0
VG> VT> 0
S (source) D (drain)
Metal Gate
+++++++ SiO2
SiO2 ------- n+ n+
n+ n+ p-Si
Glass Source Drain
Glass
G (gate)

8
 TFT Device Structures
• TFT devices can be made with a wide variety of structures, defined by the order of
deposition of the semiconductor layer, the source-drain contacts, and the gate electrode.
• The staggered TFT structures have the source and drain contacts on one side of the
semiconductor and the gate electrode on the opposite side, while the coplanar structures have
all three electrodes on the same side of the semiconductor film.
• In the “inverted” structures, the gate electrode is the first layer deposited on the glass
substrate.
• Amorphous-silicon thin-film transistors (a-Si TFT) in practical applications use the inverted
staggered structures. This in contrast to polycrystalline silicon TFT (poly-TFT), which are
usually coplanar, which is the nearest thin-film analog of the crystalline Si MOSFET.

a-Si TFT Poly-Si TFT

9
非晶矽薄膜電晶體技術
(Amorphous Si TFT)

10
 a-Si TFT-array Manufacture

TFT Process
Glass Substrate 薄膜
基板投入 Thin Film

蝕刻 黃光
Etch Photo

測試
Array Test
11
a-Si TFT-array Process Flow

CLEANING

P.R PROCESS
CYCLE P.R
Stripping
coating

Developer

mask

12
 a-Si TFT-array Processes
(A). 清洗製程 (Cleaning)
(1).濕式洗淨 (Wet cleaning) (2).乾式洗淨 (Dry cleaning)
(B). 成膜製程 (Thin Film Deposition)
(1).PECVD : (a) a-Si channel layer (b). Dielectric layer
(2).Sputtering : Mo/Al-Nd, Mo/Al/Mo, MoW, ITO

(C). 微影製程 (Photolithography process)

(1).塗抹(coating) (2).曝光(exposure) (3). 顯影(development)
(4).光阻剝離工程(Photoresistor stripping)

(D). 蝕刻製程 (Etch process)

(1).濕式蝕刻 (Wet etching) (2).乾式蝕刻 (dry etching) 13
c-Si/a-Si/a-Si:H Structure and
Band Diagram
C-Si a-Si a-Si:H

14
Dangling Bonds

15
Hydrogen for a-Si Thin Film

16
 Doped a-Si :H Film

The heavily doped n-type a-Si:H is commonly used as the ohmic

contact material in devices affiliated with the a-Si:H TFT. The formation
of ohmic contact can significantly reduce parasitic resistance of TFT
device at source/drain sides, and enhance electrical conduction.
S (source) D (drain)

Glass
17
G (gate)
 微影製程 (Photolithography)
• Temporarily coat photoresist on glass substrate
• Transfers designed pattern to photoresist
• Determines the minimum feature size
• Basic Steps of Photolithography
Photoresist coating ; Alignment and exposure; Development
光源 (light source) Development
PR dispenser 透鏡
nozzle
(lenses)
Glass

吸盤
(Chuck) 光罩
轉軸 (Mask)
(Spindle)
光阻
至真空幫浦
(Photoresist) 基板( substrate)
(Vacuum pump) 18
 Photoresist
• Photo sensitive material
• Temporarily coated on glass surface
• Transfer design image on it through exposure
• Very similar to the photo sensitive coating on the
film for camera
• Photoresist Composition:
> Polymer : solid organic material
> Solvents
> Sensitizers
> Additives
19
Negative and Positive Photoresists
Photoresist
Substrate

UV light
Mask/reticle
Photoresist
Exposure
Substrate
Negative
Photoresist
Substrate After
Positive Development
Photoresist
Substrate
20
 正負光阻的解析度

- PR + PR
Film Film

Substrate Substrate

21
 基本步驟
• 晶圓清洗
• 脫水烘烤 (或稱預烤)
光阻塗佈
• 底漆層(使用六甲基二戊烷; HMDS)及光阻塗佈
• 軟烤 驅除光阻內部大部份的溶劑,增加光阻在晶圓表面的附著力
• 對準及曝光
• 顯影 正光阻的顯影液常使用((CH ) NOH); i.e. TMAH
3 4

• 圖案檢視 顯影
• 硬烘烤 去除光阻內殘存溶劑,增加光阻強度,藉著進一步的聚合
作用來改進光阻蝕刻與離子佈植的抵抗力
22
 底漆層(primer); 附著層
閘極氧化層

多晶矽膜
多晶矽膜
STI USG
STI USG
P-Well
P-Well

(a) 晶圓清洗 (b) 預烤及底漆層蒸氣塗佈

附著增強層

光阻
光阻
多晶矽膜
多晶矽膜
STI USG
STI USG
P-Well
P-Well
(c) 光阻塗佈 (d) 軟烘烤 23
 閘極光罩 閘極光罩

光阻 光阻
多晶矽膜 多晶矽膜
STI USG STI USG

P-Well P-Well
(e) 對準 (f) 曝光

光阻
光阻
多晶矽膜
多晶矽膜
STI USG
STI USG
P-Well
P-Well

(g) 曝光後烘烤 (h) 顯影、硬烘烤及圖案檢視 24

 Alignment and Exposure
• Photo mask must be aligned precisely with glass
substrate by exposure machine, otherwise causing
difference in pattern size
• Exposure controlled by production of light
intensity and exposure time
• Very similar to the exposure of a camera
• Intensity controlled by electrical power
• Adjustable light intensity
• Routine light intensity calibration
25
 Exposure Systems (selected)

Reference
Light Mark
Source

Light Source
Alignment
Reticle Laser
Lenses
Stage Reticle

Interferometer Laser
Projection
Lens
Mask Y
X
Photoresist Interferomet
Glass er Mirror Set
Wafer
Wafer Stage

Contact Printer Step&Repeat Alignment System

26
 步進機
•在先進IC製造廠中，步進機是最廣為使用的曝光系統
• 影像的降低可以得到較高的解析度
• 可應用於0.25 mm及以下的製程
• 造價很昂貴 UV light

曝光光源需具有的特性: Reticle field size

20 mm × 15mm,
4 die per field
•短波長
•高強度 5:1 reduction lens

•具有穩定性
Image exposure on
光源來源: Serpenti
ne
wafer 1/5 of reticle
field
4 mm × 3 mm,
• 高壓汞燈 (mercury lamp) stepping
pattern 4 die per exposure
Wafer
•激發雷射光 (Excimer laser)
27
 汞燈的光譜圖

I-line G-line
(365) (436)
Intensity (a.u)

H-line
(405)

Deep UV
(<260)

300 400 500 600

Wavelength (nm)

28
 微影光源
Name Wavelength (nm) Application feature
size (mm)
G-line 436 0.50
Mercury Lamp H-line 405
I-line 365 0.35 to 0.25
XeF 351
XeCl 308
Excimer Laser KrF (DUV) 248 0.25 to 0.15
ArF 193 0.18 to 0.13
Fluorine Laser F2 157 0.13 to 0.1

29
 光的散射現象

偏離的散射光
D 光罩
散射光 光罩

投射在晶圓 透鏡 ro
上的光強度 被透鏡所收集
的散射光 經透鏡收集後,所得
到的較少散射

理想的光強度分
佈圖

30
 數值孔徑 (NA)
(Numerical Aperture)

• NA 是指透鏡收集散射光的能力
• NA = 2 r0 / D
– r0 : 透鏡的半徑
– D = 物體(or光罩)距離透鏡的距離
•具有較大NA的透鏡可以收集較高階的散射
光並產生對比鮮明的影像

31
 解析度 (R)
(Resolution)

K1
R
NA
• K1 是系統常數,  是光波波長,
NA = 2 ro/D, 是數值孔徑
• NA 是指透鏡收集散射光的能力

32
 聚焦深度(DOF)
(Depth of Focus)
• 能夠透過聚焦的光線得到清晰投射影像的
空間範圍
• 聚焦深度可表示為:

K 2
DOF  2
2( NA) DOF Focus

33
Focus on the Mid-Plain to Optimize
the Resolution

Center of focus Depth of focus

Photoresist
Substrate

34
 增加解析度的方法
K1
R
•增加NA NA
– Larger lens, could be too expensive and unpractical
– Reduce DOF and cause fabrication difficulties
• 降低曝光波長
– Need develop light source, PR and equipment
– Limitation for reducing wavelength
– UV to DUV, to EUV, and to X-Ray
• 降低 K1
– 設計光罩
35
Phase Shift Mask Patterning
Normal Mask Phase Shift Mask

Constructive Phase shift

Interference coating Total Light
Intensity
Total Light
Intensity Destructive
Interference

PR PR
Substrate Substrate
Final Pattern Final Pattern

PR PR
Substrate Substrate
Designed Pattern Designed Pattern
36
 表面平坦化的需要
• 為了達到曝光的高解析度
K1
– Shorter  R
NA
– Larger NA.
K 2
DOF 
• 此兩方法都會降低 DOF 2( NA) 2
•晶片的表面必須具有高程度的平坦性
• 針對IC技術，當圖案尺寸小於0.25 mm時，必
須要執行化學機械研磨(CMP) 的技術來達到
晶片表面的平坦

37
 顯影 (Development)

• Developer solvent dissolves the softened

part of photoresist
• Transfer the pattern from mask or reticle to
photoresist
• Three basic steps:
– Development
– Rinse
– Dry

38
Photolithography Steps

39
 Definition of Etch
• Process that removes material from surface
• Chemical, physical or combination of the two
• Selective or blanket etch
• Selective etch transfers Mask design image on the photoresist
to the surface layer on glass
• Two existing technologies: Wet etch and Dry Etch
閘極氧化層 多晶矽 (poly-Si)

PR PR
多晶矽 (poly-Si)
STI USG STI USG
P型井區 P型井區

Pattern of Gate electrode on PR Etching poly-Si film 40

 Wet Etch
• Chemical solution to dissolve the materials on
the wafer surface
• The byproducts are gases, liquids or materials
that are soluble in the etchant solution.
• Three basic steps, etch, rinse and dry
Etchant Sink
Spin Dryer

D.I. Wafer Rinse

41
 Wet Etch
• Pure chemical process, isotropic profile
• Was widely used in IC industry when feature size was
larger than 3 micron
• Still used in advanced IC fabs
– Wafer clean
– Blanket film strip
– Test wafer film strip and clean
7 - 8 mm 3 mm
Etch
Photoresist Bias PR
Film 3mm Film
Substrate Substrate 42
 Advantages of wet etch :
• High selectivity
• Relatively inexpensive equipment
• Batch system, high throughput

Disadvantages of wet etch:

• Isotropic Profile
• Can’t pattern sub-3mm feature
• High chemical usage
• Chemical hazards
– Direct exposure to liquids
– Direct and indirect exposure to fumes
– Potential for explosion 43
Application of Wet Etch

44
 Dry Etch
• Gas in, gas out
• Plasma generates free radicals and ion
bombardment
• RIE (Reactive Ion Etch)
– combined chemical and physical etch
• Most patterned etches are RIEs

45
 Dry Etch Process Sequence
Plasma

1 Generation of
Etchant Species Gas Flow

2 Diffusion to Surface
Ion Diffusion into
Bombardment 6
convection flow Sheath
3 Adsorption Boundary layer
5 Desorption layer
Byproducts

4 Reaction
Film
46
 Etch Mechanism of Plasma Etch
• Heavy ion bombardment damages chemical bonds
• Exposed surface atoms are easier to react with etchant free
radicals
• Ion bombardment is mainly in vertical direction
• Etch rate on vertical direction is much higher than on horizontal
direction  anisotropic etch
PR PR
Exposed Ions
atom Broken
bonds

Etched Etchant
Atom or Etch
free radical Byproduct 47
molecule
Benefits of Plasma Etch Process
• High etch rate
• Anisotropic etch profile
• Optical endpoint

48
 Application of Dry Etch
Materials RIE etchants
Si CF4/O2;Cl2;NF3
SiNx CF4/O2;CF4
Al Cl2/BCl3;CCl4/BCl3
Mo CF4/O2;CCl4/O2;CF4
Ta CF4
W CF4/O2;CCl4/O2;CF4
Cr CF4/O2;CCl4/O2
Ti CF4/O2;CCl4/CF4
ITO CCl4;HBr;HI 49
 Schematic of an RIE System
Process
gases

Process
chamber Plasma Magnet
Wafer coils

Chuck
By-products to
the pump RF Power
Helium For
backside cooling
50
 Endpoint
(蝕刻製程終點)
• Each atom has its own emission wavelength
• Color of plasma changes when etch
different materials
• Optical sensors can be used to detect the
change and indicate the endpoint for plasma
etch processes

51
 Etch Endpoint Wavelengths

Film Etchant Wavelength (Å ) Emitter

Al Cl2, BCl3 2614 AlCl
3962 Al
Poly Si Cl2 2882 Si
6156 O
3370 N2
Si3N4 CF4/O2 3862 CN
7037 F
6740 N
7037 F
SiO2 CF4 and CHF3 4835 CO
6156 O
PSG, BPSG CF4 and CHF3 2535 P
W SF6 7037 F
52
 PR Stripping
分類 方法 (Methods) 特徵 (Features)

溼式 有機溶劑 適用於所有的光阻劑
(Wet) (organic solvent) (suitable for all PRs)
無機化學液 H2O2/H2SO4 適用於不被
(Inorganic solvent) 氧化層蝕刻之基層
乾式 O2 plasma 氧化作用,表面易被氧化
(Dry) (oxidation reaction)
H2 plasma 還原作用,去除速率較慢
(Reduction reaction)

53
 Photoresist Dry Strip

• O2, H2O chemistry

plasma
H2O  2H + O

• O + PR  H2O + CO + CO2 +

54
 TFT Process Cycle (I)

空白玻璃 鍍第一層膜 上光阻 (PR coating)

(Bare glass panel ) (Metal film deposition)

酸, 顯影
氣體 液
光罩

蝕刻(etching) 顯影(developing) 對準,曝光

(Alignment, Light exposure)55
 TFT Process Cycle (II)
去光
阻液

鍍第二層膜 上光阻
去光阻(PR striping)
酸, 顯影
氣體 液
光罩

蝕刻 顯 影 對準,曝光 56
 TFT Process Cycle (III)

去光 Please think about the

阻液
following steps……….

PR Stripping

57
 a-Si TFT-array Process Flow

5道光罩

薄膜

素玻璃 蝕刻 黃光

TFT 基板
BOX

58
 Structure between E/S and
BCE Structure
Gate

Island stopper n+ a-Si

a-Si
a-Si
insulator
insulator

Source Source Drain

n+ a-Si

Passivation

Display
electrode

60
Parameters Influencing a-Si:H TFT

61
複晶矽薄膜電晶體技術
(Poly-Si TFT)

62
 Poly-Si TFT Device Structure
• The poly-Si TFT technology is similar to the conventional very large-scale
integrated circuit (VLSI) metal-oxide semiconductor field effect transistor
(MOSFET). For example, both of them are field effect transistors, contain
layers of semiconductor, dielectric, conductive thin film and has a fixed
coplanar structure.
• For MOSFET, the channel region is formed in the single crystal silicon bulk
wafer, and thermally grown silicon dioxide used as the gate dielectric. Several
high-temperature (> 700oC) process steps are involved.
• For poly-Si TFT, all thin film layers are deposited at temperatures lower than
500oC. V >0
D
V <0
D
V >V >0 V <V <0
G T G T

Metal Gate Metal Gate

+++++++ -------
SiO2 SiO2
------- p+ +++++++ p+
n+ n+
Glass Glass 63
 I-V Transfer Characteristic Comparison

10 -3 10 -3 10 -3
Vds = 5 V
10 -4 10 -4 Vds = 5 V
10 -4 Vds = 5 V
10 -5 10 -5 10 -5
10 -6
Drain current [A]

10 -6 10 -6

Drain current
10 -7

Drain current
10 -7 10 -7
10 -8 10 -8 10 -8
10 -9 10 -9 10 -9
10 -10 10 -10 10 -10
10 -11 10 -11 10 -11
10 -12 10 -12 10 -12
10 -13 10 -13
10 -13
10 -14 10 -14
10 -14
-10 -5 0 5 10 15 -10 -5 0 5 10 15
-10 -5 0 5 10 15
Gate-source voltage [V] Gate-source voltage [V] Gate-source voltage [V]

Crystalline TFT Polysilicon TFT Amorphous TFT

64
Advantages of Poly-Si TFT
Technology
• Higher pixel aperture ratio
– higher brightness, or lower power displays
• Higher resolution
– not limited by TAB-IC connection pitch
• More compact and reliable display module
– ~95% fewer external connections (“3 sides
free”)
– reduced number of electronic components

65
Electron Mobility of a-Si and poly-Si

66
Aperture Ratio in a-Si and Poly-Si TFTs
W
Driving current : ID  m
L

67
Reliability in a-Si and poly-Si TFTs

68
 a-Si v.s. poly-Si TFTs
a-Si:H TFTs
Advantage: Cheap and reliable
technology for very large
area IC.
Application: Flat panel displays, imagers,
printers, copiers, consumer
products.
Market: Probably the second most
important technology (after
CMOS and MOS
technology).
Disadvantage: Very slow technology and
sensitive to heat and light,
reduced brightness.
Polysilicon TFTs
Higher speed , Inherent
stability, brighter and
higher resolution.
High-resolution
projection displays.
Challenge a-Si:H in
future.
Expensive due to the
higher processing
temperatures, larger OFF
state current leakage.
69
 LTPS TFT Technology Modules
(A). 清洗製程 (Cleaning)
(1).濕式洗淨 (Wet cleaning) (2).乾式洗淨 (Dry cleaning)

(B). 成膜製程 (Thin Film Deposition)

(1).PECVD : (a) a-Si channel layer (b). Dielectric layer
(2).Sputtering : Mo/Al-Nd, Mo/Al/Mo, MoW, ITO
(3) Laser Crystallization/ Solid Phase Crystallization

(C). 摻雜製程 (Doping process) : 離子佈植 (Ion implantation)

(D). 微影製程 (Photolithography process)

(1).塗抹(coating) (2).曝光(exposure) (3). 顯影(development)
(4).光阻剝離工程(Photoresistor stripping)

(E). 蝕刻製程 (Etch process)

(1).濕式蝕刻 (Wet etching) (2).乾式蝕刻 (dry etching)
70
Low-Temperature Poly-Si Film
Formation
1. Deposition of a-Si thin film
• provides a smooth film surface
• low-temperature process
– LPCVD
– PECVD: H content should be low
– PVD: impurity concentration should be low
2. Crystallization of a-Si film
• solid-phase crystallization and/or
• pulsed excimer laser annealing
71
Crystal Size of a-Si and poly-Si

or SPC

72
 Solid-Phase Crystallization (SPC)
• a-Si is a noncrystalline solid that is considered to be at a
metastable state. When it is annealed at a sufficiently high
temperature, it is driven thermodynamically to the crystalline
state.
– furnace annealing at temperatures  550oC
• The higher the temperature, the shorter the time required
for crystallization.
• Crystallization occurs by nucleation + grain growth
– Nucleation typically occurs heterogeneously, e.g. at the
interface with SiO2
– Lower nucleation rate  larger grain size
• Depends on deposition process and anneal temperature 73
 Laser Crystallization
1. In order to fabricate poly-Si TFTs with low cost, it is desired
to choose glass or plastics as substructure.

2. Laser crystallization of amorphous silicon thin film is

presently widely used for preparing poly-Si thin film on
foreign substrates.

3. Laser crystallization can produce large-grained poly-Si thin

film with low intra-grain defects.

4. Due to the short time scale of laser crystallization ,the thermal

strain on low temperature substrates does not lead to severe
damage or destruction of these substrates.
74
Excimer Laser Crystallization
A pulsed, rectangular UV laser beam is scanned across
the substrate to crystallize the amorphous silicon film

W=3 mm

L=350 mm

76
SPC and Laser Crystallization
Comparison

77
 Polycrystalline Si Structure
• Small crystals (“crystallites” or “grains”) of Si atoms
– Average lateral grain size can TEM of a Poly-Si Film
range from several nm to mm
• depends on deposition, annealing conditions
– Different crystalline orientations
 discontinuity from one grain to another

• The border between crystallites is called a “grain

boundary”
– contains disoriented bonds
and dangling bonds
locally allowed energy states
within the Si bandgap 79
 Defect Passivation
• Because the traps located at grain boundaries degrade the
electrical properties of poly-Si, it is desirable to reduce the
active trap density, e.g. by termination of dangling bonds with
hydrogen atoms

 Improves conductivity
of moderately doped
poly-Si films

 Reduces junction
leakage current

80
 摻雜的方法- 離子佈植法
• 所謂離子佈植法，是先將摻質離子化 (ionized) ，而後藉加速器
的加速把這些離子化的摻質，如P+及BF2+直接打入矽晶片裡，
來進行摻質的預置 (pre-deposition) 。
• 可以獨立控制摻質在晶片裡的分佈(藉由離子加速的能量)及摻
質的濃度 (藉由離子束電流的大小及佈植時間來控制) 。
• 為一非等向性的(Anisotropic)摻質濃度分佈(dopant profile)
• 容易實施重摻質元素如磷及砷的高濃度摻雜。
 NMOSFET emerged !

81
 離子佈植磷元素 (Phosphorus)

SiO2 Gate P+

n+ n+

P-type Silicon

• Beam current and implantation time control

dopant concentration
• Ion energy controls junction depth
• Dopant profile is anisotropic

82
 離子佈植與擴散製程的比較
Doped region

SiO2 PR

Si Si

Junction depth
Diffusion Ion implantation
Deposited Dopant Oxide

SiO2

Si Substrate
83
 離子佈植機台組態
氣體櫃 抑制電極
分析磁鐵
(質譜儀)

真空幫浦 射線束
離子源
四極聚焦器 及
掃描器 等
萃取電極 後段加(減)速電極

電荷中性化系統 真空幫浦

晶片
終端分析儀
www2.austin.cc.tx.us/HongXiao/Book.htm

86
 Implantation Processes

Ion Random Collisions

(S=Sn+Se)

Channeling
(SSe)

Back Scattering (SSn)

87
 Prevention of Channeling Effects

• Ways to avoid channeling effect

– Tilt wafer, 7° is most commonly used
– Screen oxide
– Pre-amorphous implantation, Germanium

88
Damages from Ion Implantation Process
Light Ion

Damaged
Region

Heavy Ion
Single Crystal
Silicon

單晶結構 非晶結構

Before Implantation After Implantation

89
 Post-Implant Annealing
• Why post-implant annealing ?
- To activate the dopants
- To eliminate the defect
• Types of post-implant annealing
- Furnace annealing (FA)
- Rapid thermal annealing (RTA)
- ELA annealing
• Main issues for annealing
- Thermal budget (profile control)
- Extent of dopant activation and defect elimination
90
Dopants Activation

91
 Dopants Activation

Lattice Dopant Lattice Dopant Lattice Dopant

Atoms Atom Atoms Atom Atoms Atom

Lattice Dopant Lattice Dopant Lattice Dopant

Atoms Atom Atoms Atom Atoms Atoms
92
Dopant Activation Anneal

93
 Poly-Si TFT Manufacture
Processes
G
Fabrication steps
S D
1. Glass substrate
2. 50nm a-Si thin film deposition
3. Laser or SPC crystallization
4. Active region definition
Metal gate
5. Gate definition
Gate oxide 6. N- and N+ ion implantation &
N- N- N+ activation
N+
7. Contact hole and metallization
Glass 8. H2/NH3 plasma passivation

AA’ cross-section plot of proposed TFT 94

 Low Temperature Poly-Si
(LTPS) TFT Process
1. Crystallization
• Solid Phase Crystallization (SPC)
• Excimer Laser Crystallization (ELC)
2. Gate oxide
• TEOS Oxide
• ECR Oxide
3. Doping process
• Ion implantation
95
 LTPS TFT Process
3. Anneal
• Furnace anneal
• Laser anneal
• Rapid thermal anneal (RTA)
• Gas immersion laser doping
4. Passivation
• H2 Passivation
• D2 Passivation
• F2 Passivation
• NH3 Passivation 96
The Process Procedure of Fabricating ELA
LTPS TFTs

97
金屬氧化物透明薄膜電晶體
(Metal Oxide TFT)

98
 Transparent ZnO
Zinc oxide (ZnO) Advantage:
Hexagonal wurtzite 1. High band gap
Insensitive to visible light
2. High mobility
Over 200 (cm2 V-1 s-1)
3. Transparent
transparency 70~90%
Issues:
(Poly-crystallization)
1. Sensitive to the quantity of defects in itself
2. Uniformity issues
Zn 3. Excess background carrier concentration
• Larger than 1017 cm-3 in as deposited states
O • Ioff leakage current

 ZnO has been studied intensively also for channel layers in TFTs
because ZnO TFTs exhibit better performances than hydrogenated
amorphous silicon. 99
 AOS Materials
• Increase the uniformity in film deposition
• Using transparent amorphous oxide semiconductors (TAOS), ex:
a-IZO, a-IGZO, a-AZTO, a-HIZO, a-ZTO…
(In;銦) (Hf; 鉿) (Sn; 錫)

1. Polycrystalline →
amorphous
2. Carrier supply
1. Stabilize the IGZO
material
2. Suppresses extra
electrons

Hosono, NPG Asia Mater. 2(1) 15–22 (2010) 100

 Advantages of AOSs
Large mobility (10 cm2V-1s-1)
- achieve 10–20 times higher electron mobility and offer the potential
of 10 times greater display resolution
Transparent of visible light
- larger optical bandgap about 3.2eV
Low temperature deposition
- sputtering system, PLD system,
solution process
Great uniformity (AOSs)
- amorphous type material

101
 Lattice Structure
--Silicon vs. Metal oxide
Silicon (IV) Metal oxide (II-VI)
Schematic orbital drawings (b), Amorphous oxide
for the carrier transport semiconductors composed of
paths (that is, conduction post-transition-metal cations.
band bottoms) in crystalline Spheres
and amorphous denote metal s orbitals. The
semiconductors. contribution of oxygen 2p
(a), Covalent semiconductors orbitals is small. Direct
have carrier transport paths overlap
composed of strongly between neighbouring metal
directive sp 3 orbitals, so s orbitals is rather large, and
structural is not significantly affected
randomness greatly degrades even
the magnitude of bond overlap, in an amorphous structure.
that is, carrier mobility.
Note that the orbitals shown
are illustrative, and do not
show exact wavefunctions.

ZnO  poly type (grain boundary, uniformity)

In-Ga-Zn-O  amorphous type (Nature, 2004)
102
 Comparison to Conventional TFTs
Characteristic a-Si TFT poly-Si TFT a-IGZO TFT Pentacene TFT

Stability in ambient Excellent Excellent Excellent poor

Uniformity good Vth Dispersion Good Vth Dispersion

Design/Device NMOS CMOS NMOS PMOS

Performance μn=0.7cm2/Vs μn=200cm2/Vs μn=1~100cm2/Vs μp=0.1~5cm2/Vs

μp=100cm2/Vs

Off current low high lowest fair

Driver Integration Scan Driver SOG SOG None

Profits Tremendous Infra Excellent TFT Transparent Flexible

Low cost Integration Access Low cost

Process 3-5 masks 7-9masks 3-5 masks 3-5 masks

( ELC+Implantation)

a-IGZO TFT is a good candidate for next generation LCD backplane.

Seldom fundamental studies have been reported.
103
State of the Art - AOSs Tech.

Transparent
showcase

SID 2010, 2011,

by Samsung
Wirelessly-powered TVs are nice, and transparent displays are cool and all, but what about an ambient light-powered transparent
LCD? Well, that's nothing short of awesome. Samsung showed off just such a device at CeBIT 2011 last week -- a prototype 46-inch
display with 1920 x 1080 resolution and ten-finger touch screen capability. We aren't sure what kind of black magic Sammy put in
this thing, but it's an incredible feat of engineering to make such a large display -- and its accompanying solar cells -- efficient
enough to run exclusively off the juice it pulls from surrounding light sources. No word on how the photon-powered LCD compares
to existing HD monitors in terms of brightness, refresh rates, or color reproduction, but a muted picture is a small price to pay for
cutting the electrical cord forever.
104
 State of the Art - AOSs Tech.
Samsung Electronics, 70” Oxide
semiconductor LCD Display

2011, AUO, 65” Transparent LCD Display, 2011, Samsung Electronics, 46” Transparent 2012, LG, 55’’ OLED-TV
Transmittance 15% or more, RGB & W LCD Display
Structure

105
Thanks for your attentions!

106