AN-1417

APPLICATION NOTE
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com

Overvoltage Robustness Testing in the AD4110-1

by Dan O’Donnell and Brendan Somers

INTRODUCTION AIN(+)
AD4110-1 VDD

34 37
The AD4110-1 is a complete, single-channel, universal input, 10Ω
47nF 39
analog-to-digital front end for industrial process control ESD INTERNAL ESD
AGND VDD
systems where sensor type flexibility is required. 36

14899-001
SILICON
40 SUBSTRATE
VSS
The high voltage input is fully software configurable for current
Figure 1. Analog Input Pin Structure
or voltage signals and allows a direct interface to all standard
industrial analog signal sources, for example, ±20 mA, ±4 mA This application note outlines the test circuit configurations
to ±20 mA, ±10 V, and all thermocouple types. Field power is that confirm the data sheet specification for overvoltage
supplied for loop powered, current output sensors. A range of protection. All possible operating modes of the AD4110-1 are
excitation current sources for resistance temperature detectors tested. A socketed evaluation board was used for the test board,
(RTDs) and other resistive sensors are included. The integrated, as shown in Figure 2. Refer to the AD4110-1 data sheet for
fully differential, programmable gain amplifier (PGA) offers details of the operating modes.
16 gain settings from 0.2 to 24. INPUT POWER
TEST SUPPLY
The high voltage input can be programmed to power up in VOLTAGE ±12V TO ±20V

either voltage mode or current mode. When programmed to

current mode, the unique input circuit architecture provides a
path for the loop current, even in the absence of the system
power supply. For full details, see the AD4110-1 data sheet.
In some applications, an event can occur where the inputs of an
analog input module are driven by voltages outside the level of
the module power supply, known as an overvoltage condition.
When an input pin goes more than one diode drop beyond the
power supply rails, the internal diodes of the input amplifier can
be forward-biased, causing excessive current to flow, which can
damage the amplifier. This damage can result in a shift in the

14899-002
electrical specification parameters beyond the limits specified in
the AD4110-1 data sheet, or cause the permanent failure of the
Figure 2. Test Board
input amplifier.
The AD4110-1 is designed on a high voltage silicon process and
provides overvoltage protection of ±30 V dc on the input pins
through the use of an external resistor-capacitor (RC) low-pass
filter circuit. A diode is also required on the negative power
supply.

Rev. 0 | Page 1 of 13
AN-1417 Application Note

TABLE OF CONTENTS
Introduction ...................................................................................... 1 Current Mode ................................................................................6
Revision History ............................................................................... 2 2-Wire RTD Mode ........................................................................7
Testing System and Method ............................................................ 3 3-Wire RTD Mode ........................................................................8
Test System .................................................................................... 3 4-Wire RTD Mode ..................................................................... 10
Test Method................................................................................... 3 Field Power Supply Mode.......................................................... 12
Results Summary .............................................................................. 4 No Power Supply Mode (NPSM) ............................................. 13
Test Results ........................................................................................ 5
Voltage Mode ................................................................................ 5
REVISION HISTORY
3/2019—Revision 0: Initial Version

Rev. 0 | Page 2 of 13
Application Note AN-1417

TESTING SYSTEM AND METHOD

TEST SYSTEM As shown in Figure 4 through Figure 35, the overvoltage condition
A socketed version of the EVAL-AD4110-1SDZ evaluation is applied to the input terminals five times in quick succession
board (see Figure 2) is used as the test board for all test and repeated for positive and negative voltages. For test configur-
configurations. A Keysight® N6705B four-quadrant power ations where the applied voltage is floating with respect to the test
supply analyzer supplies ±20 V to the test board for all test board ground, the source outputs are connected to the input
configurations except for the field power supply mode (FPSM) terminals at the same time. For test configurations where the
where ±15 V is used. A TTi® CPX200D power supply (current applied voltage is referenced to the test board ground, the test
limited to 4 A) applies the overvoltage condition to the input board RTD(−) terminal is connected first. The RTD(−) terminal is
terminals of the test board for all test configurations. For each connected to the test board AGND via a 100 Ω resistor (see
test configuration, three devices were tested at three Figure 3).
temperature points: −40°C, +25°C, and +105°C. After each AD4110-1 device is tested, the device production test
program runs to ensure that no data sheet specifications have
TEST METHOD
changed due to the result of the applied overvoltage condition.
The test method is based on what can happen during a system The AD4110-1 data sheet analog input overvoltage protection
installation where an analog input module is wired to a variety specification is determined from the worst case test result from
of industrial sensors when live system power cables are accessible. all test configurations with a 2 V margin applied. Table 1 summa-
The possibility of connecting the system power supply to the rizes the test result.
module input terminals due to a miswiring condition was also
tested. Typically, the system power supply is +24 V and can be
specified with a tolerance of ±20%, giving a possible overvoltage
range of ±19.2 V to ±28.8 V.

ANTIALIASING FILTER

10Ω, 0.25W 2 × 10nF

RTD(+)
0.1µF
47nF
30 29 25 24 13 +5V
ADR1

ADR0

CLKIO

35 RTD C(+) C(–)

10Ω, 0.25W IOVDD 20 0.1µF
AIN(+) 34 AIN(+)
47nF 33 EXRF IOVDD 21 1µF
32 EXRS DGND 22 +5V
5V
47nF 221Ω* 0.1µF
ADCDVDD 23 0.1µF
0.1µF
AIN(–) 31 AIN(–) 0V
10Ω, 0.25W 1µF
iREFF ERR 18
100Ω, 0.25W 25kΩ 3
RTD(–) DOUT
DOUT/RDY 14
4 iREFS DIN
DIN 15
SCLK 16 SCLK
AD4110-1 CS 17 CS

1.6kΩ 10nF SYNC 19

LV INPUT 1 27 AIN1(LV) ADR4525 +5V
REFIN(+) 2
0.1nF VREF
EXPOSED PAD 1µF 4.7µF
1.6kΩ VSS REFIN(–) 1
LV INPUT 2 28 AIN2(LV)
10nF REFOUT 5
26 AINCOM(LV) ADP7102 VDD
+5V
LDO
ADCAVDD

10
4.7µF 0.1µF
NIC
AVDD5

AVDD5
AGND

AGND

AGND
VDD

VDD
VSS
VSS

VPP

POWER SUPPLY ±12V TO ±20V

36 40 38 37 39 12 11 9 8 6 7 VDD
PROTECTION
DIODE
1µF
0.1µF 10µF 1µF VSS
0.1µF
10µF 0.1µF 0.1µF 0.1µF
10µF 10µF
VSS VDD +5V

*OPTIONAL COMPONENT, MUST BE 0Ω IF NOT USED.

14899-003

NOTES
1. NIC = NOT INTERNALLY CONNECTED.

Figure 3. Test Board Schematic Diagram of EVAL-AD4110-1SDZ

Rev. 0 | Page 3 of 13
AN-1417 Application Note

RESULTS SUMMARY
The AD4110-1 data sheet specification for analog input overvoltage in field power supply mode, as shown in Table 1. Note that the
protection on the AIN(+) and AIN(−) pins, specified at ±30 V, power supply is limited to ±15 V is this configuration and is
is determined from the worst case test result from all test config- therefore not the worst-case condition.
urations and with a 2 V margin applied. The overall test results The next lowest overvoltage condition applied where there was
summary is outlined in Table 1. The pass level of the applied no deviation from the AD4110-1 specifications is −33 V, config-
input voltage is the maximum overvoltage level at which the ured in 4-wire RTD mode. To verify this result, 30 additional
device meets the data sheet specifications after the test. See Figure 4 devices in this configuration were tested, which allows the data
through Figure 35 for the test configuration diagrams and test sheet specification for overvoltage protection to be specified at
results. ±30 V with a 3 V margin applied.
The lowest overvoltage condition applied where there was no
deviation from the AD4110-1 specifications is 32 V, configured
Table 1. Results Summary
Pass Level of Applied Input Voltage (V) 1
Test Configuration/Mode RTD(+) AIN(+) AIN(−) RTD(−)
Voltage Not applicable +40, −35 +40, −40 Not applicable
Current Not applicable +40, −35 +40, −40 Not applicable
2-Wire RTD Not applicable +40, −35 +40, −40 Not applicable
3-Wire RTD +40, −40 +40, −35 +40, −40 Not applicable
4-Wire RTD +40, −40 +40, −33 +40, −40 Not applicable
Field Power Supply Mode 2 Not applicable +40, −35 +32 Not applicable
No Power Supply Mode Not applicable 40 40 Not applicable
1
The pass level of the applied input voltage is the maximum overvoltage level at which the device meets data sheet specifications after the test.
2
The VDD or VSS power supply voltage is limited to ≤±15 V for this test configuration.

Rev. 0 | Page 4 of 13
Application Note AN-1417

TEST RESULTS
VOLTAGE MODE
VDD

RTD(+) 10Ω
35 RTD
47nF
IN1(+)
10Ω AIN(+) 1kΩ
AD4110-1
47nF C(+)
AIN(+) 10Ω
AGND 34 AIN(+)
RSENSE
47nF 33 EXRF
VSS ±V 32 EXRS
±10V EXRF PGA 47nF 221Ω
AIN(–)
31 AIN(–)
EXRS
REXT 10Ω
221Ω
IN1(–) 10Ω AIN(–) 1kΩ
RTD(–) 100Ω
47nF C(–)

14899-006
AGND VBIAS
14899-004 EVAL-AD4110-1SDZ
VSS AGND AD4110-1

Figure 4. Typical Application Diagram—Voltage Mode Figure 6. Voltage Mode, Test 3 and Test 4

RTD(+) 10Ω RTD(+) 10Ω

35 RTD 35 RTD
47nF 47nF

AD4110-1 AD4110-1
AIN(+) 10Ω AIN(+) 10Ω
34 AIN(+) 34 AIN(+)

47nF 33 EXRF 47nF 33 EXRF

±V 32 EXRS ±V 32 EXRS
47nF 221Ω 47nF 221Ω
AIN(–) AIN(–)
31 AIN(–) 31 AIN(–)
10Ω 10Ω

RTD(–) 100Ω RTD(–) 100Ω

14899-005

14899-007
EVAL-AD4110-1SDZ EVAL-AD4110-1SDZ

Figure 5. Voltage Mode, Test 1 and Test 2 Figure 7. Voltage Mode, Test 5 and Test 6

Table 2. Test Results for Voltage Mode Configurations

Pass Level of Applied Input Voltage (V) 1
Test Number Test Configuration RTD(+) AIN(+) AIN(−) RTD(−)
Test 1 See Figure 5 No connect 40 0 No connect
Test 2 See Figure 5 No connect 0 40 No connect
Test 3 See Figure 6 No connect 0 −40 0
Test 4 See Figure 6 No connect 0 40 0
Test 5 See Figure 7 No connect 40 0 0
Test 6 See Figure 7 No connect −35 0 0
1
The pass level of the applied input voltage is the maximum overvoltage level at which the device meets data sheet specifications after the test.

Rev. 0 | Page 5 of 13
AN-1417 Application Note
CURRENT MODE
VDD

RTD(+) 10Ω
35 RTD
47nF
IN1(+)
10Ω AIN(+) 1kΩ
AD4110-1
47nF C(+)
AIN(+) 10Ω
AGND 34 AIN(+)
RSENSE
47nF 33 EXRF
VSS ±V 32 EXRS
±20mA EXRF PGA 47nF 221Ω
AIN(–)
EXRS 31 AIN(–)
REXT 10Ω
221Ω
IN1(–) 10Ω AIN(–) 1kΩ
RTD(–) 100Ω
47nF C(–)

14899-010
AGND VBIAS
EVAL-AD4110-1SDZ
AD4110-1 14899-008
VSS AGND

Figure 8. Typical Application Diagram—Current Mode Figure 10. Current Mode, Test 3 and Test 4

RTD(+) 10Ω RTD(+) 10Ω

35 RTD 35 RTD
47nF 47nF

AD4110-1 AD4110-1
AIN(+) 10Ω AIN(+) 10Ω
34 AIN(+) 34 AIN(+)

47nF 33 EXRF 47nF 33 EXRF

±V 32 ±V 32
EXRS EXRS
47nF 47nF 221Ω
221Ω
AIN(–) AIN(–)
31 AIN(–) 31 AIN(–)
10Ω 10Ω

RTD(–) 100Ω RTD(–) 100Ω

14899-009

14899-011
EVAL-AD4110-1SDZ EVAL-AD4110-1SDZ

Figure 9. Current Mode, Test 1 and Test 2 Figure 11. Current Mode, Test 5 and Test 6

Table 3. Test Results for Current Mode Configurations

Pass Level of Applied Input Voltage (V)1
Test Number Test Configuration RTD(+) AIN(+) AIN(−) RTD(−)
Test 1 See Figure 9 No connect 40 0 No connect
Test 2 See Figure 9 No connect 0 40 No connect
Test 3 See Figure 10 No connect 0 −40 0
Test 4 See Figure 10 No connect 0 40 0
Test 5 See Figure 11 No connect 40 0 0
Test 6 See Figure 11 No connect −35 0 0
1
The pass level of the applied input voltage is the maximum overvoltage level at which the device meets data sheet specifications after the test.

Rev. 0 | Page 6 of 13
Application Note AN-1417
2-WIRE RTD MODE
IEXC VDD

RTD(+) 10Ω
RTD 35 RTD
IN1(+) 47nF
RL1 10Ω 1kΩ
AIN(+) AD4110-1
47nF C(+)
AIN(+) 10Ω
AGND 34 AIN(+)
RSENSE
47nF 33 EXRF
RTD VSS 32
EXRF PGA EXRS
SENSOR 47nF 221Ω
±V AIN(–)
EXRS 31 AIN(–)
REXT 10Ω
221Ω
IN1(–) 10Ω AIN(–)
RL2 1kΩ
RTD(–) 100Ω
47nF C(–)

14899-014
AGND VBIAS
OPTIONAL EVAL-AD4110-1SDZ
LINK WIRE ICOMP
100Ω VSS AGND AD4110-1

14899-012
RTD(–)
AGND

Figure 12. Typical Application Diagram—2-Wire RTD Mode Figure 14. 2-Wire RTD Mode, Test 3 and Test 4

RTD(+) 10Ω RTD(+) 10Ω

35 RTD 35 RTD
47nF 47nF

AD4110-1 AD4110-1
AIN(+) 10Ω AIN(+) 10Ω
34 AIN(+) 34 AIN(+)

47nF 33 EXRF 47nF 33 EXRF

±V 32 32
EXRS EXRS
47nF 221Ω 47nF 221Ω
AIN(–) AIN(–)
31 AIN(–) 31 AIN(–)
10Ω 10Ω
±V

RTD(–) 100Ω RTD(–) 100Ω

14899-013

14899-015
EVAL-AD4110-1SDZ EVAL-AD4110-1SDZ

Figure 13. 2-Wire RTD Mode, Test 1 and Test 2 Figure 15. 2-Wire RTD Mode, Test 5 and Test 6

Table 4. Test Results for 2-Wire RTD Configurations

Pass Level of Applied Input Voltage (V)1
Test Number Test Configuration RTD(+) AIN(+) AIN(−) RTD(−)
Test 1 See Figure 13 0 40 0 0
Test 2 See Figure 13 0 0 40 0
Test 3 See Figure 14 0 +40 0 0
Test 4 See Figure 14 0 −35 0 0
Test 5 See Figure 15 0 0 40 0
Test 6 See Figure 15 0 0 −40 0
1
The pass level of the applied input voltage is the maximum overvoltage level at which the device meets data sheet specifications after the test.

Rev. 0 | Page 7 of 13
AN-1417 Application Note
3-WIRE RTD MODE
IEXC VDD

RTD(+) 10Ω
RTD 35 RTD
47nF
IN1(+)
RL1 10Ω 1kΩ
AIN(+)
AD4110-1
47nF C(+)
AIN(+) 10Ω
AGND 34 AIN(+)
RSENSE
47nF 33 EXRF
RTD VSS 32 EXRS
SENSOR EXRF PGA 47nF 221Ω
±V AIN(–)
31 AIN(–)
EXRS
REXT 10Ω
221Ω
IN1(–) 10Ω AIN(–)
RL2 1kΩ
RTD(–) 100Ω
47nF C(–)

14899-018
AGND VBIAS
EVAL-AD4110-1SDZ
RTD(–) ICOMP
RL3 100Ω VSS AGND AD4110-1 14899-016

AGND

Figure 16. Typical Application Diagram—3-Wire RTD Mode Figure 18. 3-Wire RTD Mode, Test 3 and Test 7

RTD(+) 10Ω
35 RTD
47nF

AD4110-1
AIN(+) 10Ω
34 AIN(+)

47nF 33 EXRF
±V 32 EXRS
47nF 221Ω
AIN(–)
31 AIN(–)
10Ω

RTD(–) 100Ω
14899-017

EVAL-AD4110-1SDZ

Figure 17. 3-Wire RTD Mode, Test 1 and Test 2

Rev. 0 | Page 8 of 13
Application Note AN-1417

RTD(+) 10Ω RTD(+) 10Ω

35 RTD 35 RTD
47nF 47nF

AD4110-1 AD4110-1
AIN(+) 10Ω AIN(+) 10Ω
34 AIN(+) 34 AIN(+)

47nF 33 EXRF 47nF 33 EXRF

32
±V 32
EXRS EXRS
47nF 47nF 221Ω
221Ω
AIN(–) AIN(–)
31 AIN(–) 31 AIN(–)
10Ω 10Ω
±V

RTD(–) 100Ω RTD(–) 100Ω

14899-019

14899-020
EVAL-AD4110-1SDZ EVAL-AD4110-1SDZ

Figure 19. 3-Wire RTD Mode, Test 5 and Test 6 Figure 20. 3-Wire RTD Mode, Test 4 and Test 8

Table 5. Test Results for 3-Wire RTD Configurations

Pass Level of Applied Input Voltage (V) 1
Test Number Test Configuration RTD(+) AIN(+) AIN(−) RTD(−)
Test 1 See Figure 17 No connect 40 0 No connect
Test 2 See Figure 17 No connect 0 40 No connect
Test 3 See Figure 18 No connect 40 0 0
Test 4 See Figure 20 No connect 0 40 0
Test 5 See Figure 19 40 0 0 0
Test 6 See Figure 19 −40 0 0 0
Test 7 See Figure 18 No connect −35 0 0
Test 8 See Figure 20 No connect 0 −40 0
1
The pass level of the applied input voltage is the maximum overvoltage level at which the device meets data sheet specifications after the test.

Rev. 0 | Page 9 of 13
AN-1417 Application Note
4-WIRE RTD MODE
IEXC

RL1 RTD1 10Ω RTD VDD RTD(+) 10Ω

35 RTD
47nF 500Ω 47nF
AGND AD4110-1
IN1(+)
RL2 10Ω 1kΩ
AIN(+) 10Ω
47nF AIN(+) C(+) 34 AIN(+)

47nF 33 EXRF
AGND
RSENSE ±V 32 EXRS
47nF 221Ω
RTD VSS AIN(–)
SENSOR EXRF PGA 31 AIN(–)
10Ω
EXRS
REXT
221Ω
RTD(–) 100Ω
IN1(–) 10Ω AIN(–)
RL3 1kΩ

14899-023
47nF C(–)
EVAL-AD4110-1SDZ
AGND VBIAS
RTD(–)
RL4 100Ω ICOMP
VSS AGND AD4110-1
14899-021

AGND

Figure 21. Typical Application Diagram—4-Wire RTD Mode Figure 23. 4-Wire RTD Mode, Test 3 and Test 8

RTD(+) 10Ω RTD(+) 10Ω

35 RTD 35 RTD
500Ω 47nF 500Ω 47nF
AD4110-1 AD4110-1
AIN(+) 10Ω AIN(+) 10Ω
34 AIN(+) 34 AIN(+)

47nF 33 EXRF 33 EXRF

47nF
±V 32 ±V
EXRS 32 EXRS
47nF 221Ω 47nF
AIN(–) 221Ω
AIN(–)
31 AIN(–) 31 AIN(–)
10Ω 10Ω

RTD(–) 100Ω RTD(–) 100Ω

14899-022

14899-024
EVAL-AD4110-1SDZ EVAL-AD4110-1SDZ

Figure 22. 4-Wire RTD Mode, Test 1 and Test 2 Figure 24. 4-Wire RTD Mode, Test 4 and Test 9

Rev. 0 | Page 10 of 13
Application Note AN-1417

RTD(+) 10Ω RTD(+) 10Ω

35 RTD 35 RTD
47nF 47nF

AD4110-1 AD4110-1
AIN(+) 10Ω AIN(+) 10Ω
34 AIN(+) ±V 34 AIN(+)

47nF 33 EXRF 47nF 33 EXRF

±V 32 EXRS 32 EXRS
47nF 221Ω 47nF 221Ω
AIN(–) AIN(–)
31 AIN(–) 31 AIN(–)
10Ω 10Ω

RTD(–) 100Ω RTD(–) 100Ω

14899-025

14899-027
EVAL-AD4110-1SDZ EVAL-AD4110-1SDZ

Figure 25. 4-Wire RTD Mode, Test 5 and Test 10 Figure 27. 4-Wire RTD Mode, Test 7 and Test 11

RTD(+) 10Ω
35 RTD
47nF
±V
AD4110-1
AIN(+) 10Ω
34 AIN(+)

47nF 33 EXRF
32 EXRS
47nF 221Ω
AIN(–)
31 AIN(–)
10Ω

RTD(–) 100Ω
14899-026

EVAL-AD4110-1SDZ

Figure 26. 4-Wire RTD Mode, Test 6 and Test 12

Table 6. Test Results for 4-Wire RTD Configurations

Pass Level of Applied Input Voltage (V) 1
Test Number Test Configuration RTD(+) AIN(+) AIN(−) RTD(−)
Test 1 2 See Figure 22 0 40 0 0
Test 22 See Figure 22 0 0 40 0
Test 32 See Figure 23 0 −33 0 0
Test 42 See Figure 24 0 0 −40 0
Test 5 See Figure 25 −40 0 0 0
Test 6 See Figure 26 40 0 0 0
Test 7 See Figure 27 40 0 0 0
Test 82 See Figure 23 0 40 0 0
Test 92 See Figure 24 0 0 40 0
Test 10 See Figure 25 40 0 0 0
Test 11 See Figure 27 0 0 40 0
Test 12 See Figure 26 0 40 0 0
1
The pass level of the applied input voltage is the maximum overvoltage level at which the device meets data sheet specifications after the test.
2
RTD excitation current set to 600 µA; therefore, RTD(+) = 0.36 V and RTD(−) = 0.06 V.

Rev. 0 | Page 11 of 13
AN-1417 Application Note
FIELD POWER SUPPLY MODE
VDD

RTD(+) 10Ω
FIELD POWER 35 RTD
SUPPLY CONTROL
47nF
IN1(+)
10Ω AIN(+) 1kΩ
AD4110-1
47nF C(+)
AIN(+) 10Ω
AGND 34 AIN(+)
2.5V RSENSE
REG 47nF 33 EXRF
VSS ±V 32
4mA TO 20mA EXRS
FIELD PGA 47nF
EXRF 221Ω
TRANSMITTER AIN(–)
31 AIN(–)
EXRS 10Ω
REXT
221Ω
IN1(–) 10Ω
AIN(–) 1kΩ
RTD(–) 100Ω
47nF C(–)

14899-030
AGND VBIAS
EVAL-AD4110-1SDZ
14899-028
VSS AGND AD4110-1

Figure 28. Typical Application Diagram—Field Power Supply Mode Figure 30. Field Power Supply Mode, Test 3 and Test 5

RTD(+) 10Ω RTD(+) 10Ω

35 RTD 35 RTD
47nF 47nF

AD4110-1 AD4110-1
AIN(+) 10Ω AIN(+) 10Ω
34 AIN(+) 34 AIN(+)

47nF 33 EXRF 47nF 33 EXRF

±V 32 EXRS ±V 32 EXRS
47nF 221Ω 47nF
221Ω
AIN(–) AIN(–)
31 AIN(–) 31 AIN(–)
10Ω 10Ω

RTD(–) 100Ω RTD(–) 100Ω

14899-029

14899-031
EVAL-AD4110-1SDZ EVAL-AD4110-1SDZ

Figure 29. Field Power Supply Mode, Test 1 and Test 2 Figure 31. Field Power Supply Mode, Test 4 and Test 6

Test Results
The VDD and VSS power supply voltage is limited to ≤±15 V AIN(−) pins are current limited to ~ 40 mA when shorted to
for the test configurations described in Table 7. The default state AGND through the 100 Ω resistor connected to the RTD(−) pin.
is AIN(+) ≈ VSS + 2.5 V = −12.5 V. Both the AIN(+) and
Table 7. Test Results for Field Power Supply Mode Configurations
Pass Level of Applied Input Voltage (V)1
Test Number Test Configuration RTD(+) AIN(+) AIN(−) RTD(−)
Test 1 See Figure 29 No connect 40 0 No connect
Test 2 See Figure 29 No connect 0 32 No connect
Test 3 See Figure 30 No connect −35 0 0
Test 4 See Figure 31 No connect 0 40 0
Test 5 See Figure 30 No connect 40 0 0
Test 6 See Figure 31 No connect 0 40 0
1
The pass level of the applied input voltage is the maximum overvoltage level at which the device meets data sheet specifications after the test.

Rev. 0 | Page 12 of 13
Application Note AN-1417
NO POWER SUPPLY MODE (NPSM)

RTD(+) 10Ω
35 RTD

IN1(+) 47nF
10Ω AIN(+)
AD4110-1
47nF
+ AIN(+) 10Ω
AGND 3.2V 34 AIN(+)
–
47nF 33 EXRF
±V 32 EXRS
±20mA 47nF 221Ω
EXRF 24Ω AIN(–)
31 AIN(–)
EXRS 10Ω
REXT
221Ω
IN1(–) 10Ω
AIN(–)
RTD(–) 100Ω
47nF

AGND

14899-034
EVAL-AD4110-1SDZ
14899-032
AD4110-1

Figure 32. Typical Application Diagram—NPSM in Current Mode Figure 34. NPSM (Current Mode), Test 1 and Test 2

RTD(+) 10Ω
35 RTD
IN1(+) 47nF
10Ω AIN(+)
47nF AD4110-1
AIN(+) 10Ω
AGND 34 AIN(+)

47nF 33 EXRF

±V ±V 32 EXRS
≈30kΩ
47nF 221Ω
EXRF
AIN(–)
EXRS 31 AIN(–)
REXT 10Ω
221Ω
IN1(–) 10Ω
AIN(–)
RTD(–) 100Ω
47nF

AGND

14899-035
14899-033

EVAL-AD4110-1SDZ
AD4110-1

Figure 33. Typical Application Diagram—NPSM in Voltage Mode Figure 35. NPSM (Voltage Mode), Test 3 and Test 4

NPSM Test Results

The VDD and VSS power supply terminals are left open circuit.

Table 8. Test Results for NPSM Configurations

Pass Level of Applied Input Voltage (V)1
Test Number Test Configuration RTD(+) AIN(+) AIN(−) RTD(−)
Test 1 See Figure 34 No connect 40 0 No connect
Test 2 See Figure 34 No connect 0 40 No connect
Test 3 See Figure 35 No connect 40 0 No connect
Test 4 See Figure 35 No connect 0 40 No connect
1
The pass level of the applied input voltage is the maximum overvoltage level at which the device meets data sheet specifications after the test.

©2019 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
AN14899-0-3/19(0)

Rev. 0 | Page 13 of 13