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Avr 550 SD
Avr 550 SD
Avr 550 SD
Ver. 1
SERVICE MANUAL
MODEL AVR-550SD
AV SURROUND RECEIVER
注 意
サービスをおこなう前に、このサービスマニュアルを
必ずお読みください。本機は、火災、感電、けがなど
に対する安全性を確保するために、さまざまな配慮を
おこなっており、また法的には「電気用品安全法」に
もとづき、所定の許可を得て製造されております。
従ってサービスをおこなう際は、これらの安全性が維
持されるよう、このサービスマニュアルに記載されて
いる注意事項を必ずお守りください。
TOKYO , JAPAN
SAFETY PRECAUTIONS
The following check should be performed for the continued protection of the customer and service technician.
500V
1M
(1)
(2)
(1)
(2)
2
AVR-550SD
LEVEL DIAGRAM
3
AVR-550SD
4
BLOCK DIAGRAM AVR-550SD
5
AVR-550SD
SEMICONDUCTORS
Only major semiconductors are shown, general semiconductors etc. are omitted to list.
主な半導体を記載しています。汎用の半導体は記載を省略しています。
1. IC’s
Note: Abbreviation ahead of IC No. indicates the name of P.W.B., etc.
注 ): IC No. の前の記号は、基板の名称を表します。
MAIN: AUDIO DIGITAL P.W.B.
FRONT: FRONT P.W.B.
SMPS: SMPS P.W.B.
VIDEO: VIDEO P.W.B.
I/O: INPUT/OUT PUT P.W.B.
ICE1QS01 (SMPS:IC1)
Pin Assignmen
1 N.C. VCC 8
2 PCS OUT 7
3 RZI GND 6
4 SRC OFC 5
Block Diagram
VCC
20V Overvoltage
Foldback - Protection
Point Corr. +
PCS UVLO
+ -
- 1.5V
Burst-Mode
+
Reference
Voltage and
SRC + + Current
- 5V
-
2V +
Ringing 5V
+ 4.8V -
Suppression
-
1V Time 20k
+
4.4V
-
Start
5V
+
3.5V
-
RZI -
Digital Processing
5.7V ZC-Counter
UP/DO-Counter Power
Driver
S
SET
Q OUT
-
R CLR
Q
+
1V
OFC +
D
SET
Q
1V -
L CLR
Q
GND
6
Block Diagram
Pin Assignmen
ICE2B265 (SMPS:IC2)
ICE2B0565 (SMPS:IC3)
VCC Drain
Power Management
Undervoltage Internal
Lockout Bias
13.5V
C1
8.5V
16.5V
Power-Down 6.5V 0.72
Reset 5.3V Oscillator
Voltage Duty Cycle
6.5V 4.8V
Reference max
4.0V
C2 Power-Up 4.0V
G1
Reset Clock
FB
Drain
Isense
SoftS
21.5-100kHz
RSoft-Start
Soft Start Soft-Start
SoftS Comparator PWM-Latch CoolMOS™
S Q
4
3
2
1
5.6V
C4 Spike R Q
S Q
CSoft-Start
G3 Blanking Gate
G2 5 s G4
T1 Driver
6.5V
R Q
PWM
7
5.3V 4.8V
C3 Comparator
Error-Latch
RFB
0.3V
C5
5
6
7
8
Current-Limit 10k
FB
RSense
Vcsth
200ns
D1
Tj >140°C 21.5kHz 0.8V
UFB
Propagation-Delay
N.C
Compensation
Drain
x3.65
PWM OP
Improved Current Mode Current Limiting
CoolSET™-F2
GND
AVR-550SD
AVR-550SD
Pin Assignment
PWM_AM_1
PWM_BM_1
PWM_AM_2
PWM_BM_2
PWM_AM_3
PWM_BM_3
PWM_BP_1
PWM_AP_2
PWM_BP_2
PWM_AP_3
PWM_BP_3
AVDD_OSC
AVSS_OSC
PWM_AP1
XTL_OUT
VALID_1
VALID_2
VALID_3
XTL_IN
DVSS
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
NC 1 60 VREGB_CAP
NC 2 59 DVDD_RCL
MCLK_IN 3 58 DVSS_RCL
AVDD_PLL 4 57 DVDD_PWM
PLL_FLT_OUT 5 56 DVSS_PWM
PLL_FLT_RET 6 55 PWM_AP_4
AVSS_PLL 7 54 PWM_AM_4
NC 8 53 VALID_4
VREGA_CAP 9 52 PWM_BM_4
DVSS1 10 51 PWM_BP_4
NC 11 50 PWM_AP_5
RESET 12 49 PWM_AM_5
ERR_RCVRY 13 48 VALID_5
MUTE 14 47 PWM_BM_5
PDN 15 46 PWM_BP_5
SDA 16 45 PWM_AP_6
SCL 17 44 PWM_AM_6
CS0 18 43 VALID_6
NC 19 42 PWM_BM_6
NC 20 41 PWM_BP_6
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
M_S
CLIP
NC
NC
NC
SDIN1
SDIN2
SDIN3
SCLK
DVSS
DEM_SEL2
DEM_SEL1
NC
LRCLK
DVDD
MCLK_OUT
DVSS1
DVSS1
DBSPD
VREGC_CAP
NC − No internal connection
Block Diagram
VREGA_CAP
VREGB_CAP
VREGC_CAP
DVDD_PWM
DVSS_PWM
DVDD_RCL
DVSS_RCL
AVDD_PLL
AVSS_PLL
Power Supply
PWM
Section
MCLK_IN
XTAL_OUT
XTAL_IN PWM_AP_1
PWM_AM_1
DBSPD
PWM Ch. PWM_BP_1
M_S
PWM_BM_1
PLL_FLT_OUT Clock,
VALID_1
PLL Signal
PLL_FLT_RET PWM_AP_2
and Processing
SCLK Serial PWM_AM_2
LRCLK Data PWM Ch. PWM_BP_2
I/F PWM_BM_2
MCLKOUT
VALID_2
SDIN1
PWM_AP_3
SDIN2
PWM_AM_3
Output Control
SDIN3
PWM Ch. PWM_BP_3
DM_SEL1 Auto Mute PWM_BM_3
DM_SEL2 De-emphasis VALID_3
Soft Volume PWM_AP_4
Error Recovery PWM_AM_4
Soft Mute PWM_BP_4
SDA Serial Clip Detect PWM Ch.
SCL Control PWM_BM_4
CSO I/F VALID_4
PWM_AP_5
PWM_AM_5
PWM Ch. PWM_BP_5
Reset, PWM_BM_5
RESET Pwr Dwn VALID_5
PDN and PWM_AP_6
Status PWM_AM_6
PWM Ch. PWM_BP_6
CLIP PWM_BM_6
MUTE VALID_6
ERR_RCVY
8
AVR-550SD
Pin assignments
NC 1 56 GVSS
NC 2 55 GVDD
DVDD 3 54 GLS_A
DVSS 4 53 SLS_A
NC 5 52 SHS_A
DTC_HS 6 51 GHS_A
DTC_LS 7 50 BST_A
OC_HIGH 8 49 DHS_A
VRFILT 9 48 GLS_B
AP 10 47 SLS_B
AM 11 46 SHS_B
RESET_AB 12 45 GHS_B
BM 13 44 BST_B
BP 14 43 DHS_B
CP 15 42 GLS_C
CM 16 41 SLS_C
RESET_CD 17 40 SHS_C
DM 18 39 GHS_C
DP 19 38 BST_C
SHUTDOWN 20 37 DHS_C
ERR0 21 36 GLS_D
ERR1 22 35 SLS_D
LOW/HIZ 23 34 SHS_D
DVSS 24 33 GHS_D
NC 25 32 BST_D
NC 26 31 DHS_D
OC_LOW 27 30 GVDD
TEMP 28 29 GVSS
Block Diagram
LOW/HIZ
OC_HIGH SHUTDOWN
OC_LOW Protection Circuitry
Status ERR0
TEMP ERR1
Bandgap
VRFILT Reference A – Half-Bridge Driver GVDD
BST_A
DTC_HS
DTC_LS HS DHS_A
Gate GHS_A
Timing Drive SHS_A
AP PWM
and
Receiver Control
AM LS GVDD
Gate GLS_A
Drive SLS_A
HS DHS_B
Gate GHS_B
Timing Drive
BP PWM SHS_B
and
Receiver Control
BM LS GVDD
Gate GLS_B
Drive
SLS_B
HS DHS_C
Gate GHS_C
Timing Drive SHS_C
CP PWM
and
Receiver Control
CM GVDD
LS
Gate GLS_C
Drive SLS_C
HS DHS_D
Gate GHS_D
Timing Drive SHS_D
DP PWM
and
Receiver Control
DM LS GVDD
Gate GLS_D
DVDD Drive SLS_D
DVSS
GVSS
9
AVR-550SD
Pin assignments
DAUX2
TEST2
PVDD
MCLK
CAD1
CAD0
PVSS
INT0
RX7
RX6
RX5
RX4
RX3
RX2
TX1
TX0
VIN
I2C
NC
R
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
80
79
INT1 1 60 TEST1
BOUT 2 59 RX1
TVDD 3 58 NC
DVDD 4 57 RX0
DVSS 5 56 AVSS
XTO 6 55 AVDD
XTI 7 54 VREFH
53 VCOM
TEST3
MCKO2
8
9 (Top View) 52 RIN
MCKO1 10 51 LIN
COUT 11 50 NC
UOUT 12 49 ROUT1
VOUT 13 48 NC
SDTO2 14 47 LOUT1
BICK2 15 46 NC
LRCK2 16 45 ROUT2
SDTO1 17 44 NC
BICK1 18 43 LOUT2
LRCK1 19 42 NC
CDTO 20 41 ROUT3
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
CSN
PDN
MASTER
NC
NC
NC
DAUX1
SDTI4
SDTI3
SDTI2
SDTI1
XTL1
XTL0
DZF2
DZF1
ROUT4
LOUT4
LOUT3
CCLK/SCL
CDTI/SDA
Block Diagram
RX0 X'tal
RX1 Clock Oscillator
RX2 8 to 3
Recovery Clock MCKO1
RX3 Input Generator MCKO2
RX4
Selector
RX5
DEM
RX6
DAIF LRCK2
RX7 Audio
BICK2
Decoder I/F
SDTO2
TX0
DAUX2
PDN
TX1
I2C
AVDD DIT
AVSS
DVDD CSN
Error & Q-subcode CCLK
DVSS AC-3/MPEG PP I/F
STATUS buffer CDTO
TVDD Detect Detect CDTI
VIN
B,C,U, INT0
VOUT INT1
10
AVR-550SD
Functions
11
AVR-550SD
12
AVR-550SD
Pin Assignment
VREFL 1 28 VREFR
AGNDL 2 27 AGNDR
VCOML 3 26 VCOMR
VINL+ 4 25 VINR+
VINL– 5 24 VINR–
FMT0 6 23 AGND
FMT1 7 22 VCC
S/M 8 21 OVFL
OSR0 9 20 OVFR
OSR1 10 19 RST
OSR2 11 18 SCKI
BYPAS 12 17 LRCK/DSDBCK
DGND 13 16 BCK/DSDL
VDD 14 15 DATA/DSDR
Block Diagram
OSR0
CLK
SCKI OSR1
Control
OSR2
VINL+
Delta-Sigma Decimation
Modulator (L) HPF S/M
VINL– Filter (L)
FMT0
VCOML
FMT1
AGNDL
VREFL
VREFL LRCK/DSDBCK
Serial
Output
Interface BCK/DSDL
VREFR
VREFR
AGNDR DATA/DSDR
VCOMR
VINR+ Decimation
Delta-Sigma HPF OVFL
Modulator (R) Filter (R)
VINR– OVFR
BYPAS
Power Supply RST
13
AVR-550SD
Pin Assignment
VCC 1 50 GND
I/O0 2 49 I/O15
I/O1 3 48 I/O14
GNDQ 4 47 GNDQ
I/O2 5 46 I/O13
I/O3 6 45 I/O12
VCCQ 7 44 VCCQ
I/O4 8 43 I/O11
I/O5 9 42 I/O10
GNDQ 10 41 GNDQ
I/O6 11 40 I/O9
I/O7 12 39 I/O8
VCCQ 13 38 VCCQ
LDQM 14 37 NC
WE 15 36 UDQM
CAS 16 35 CLK
RAS 17 34 CKE
CS 18 33 NC
A11 19 32 A9
A10 20 31 A8
A0 21 30 A7
A1 22 29 A6
A2 23 28 A5
A3 24 27 A4
VCC 25 26 GND
Block Diagram
CLK
CKE
ROW DECODER
CS COMMAND
RAS DECODER MEMORY CELL
ROW
CAS & ARRAY
ADDRESS 2048
WE CLOCK
BUFFER
A11 GENERATOR MODE 11 11 BANK 0
REGISTER DQM
11 DATA IN
SENSE AMP I/O GATE
BUFFER
ADDRESS BUFFER
BURST COUNTER
ADDRESS LATCH
A10 256 16 16
COLUMN
COLUMN
8
A9 REFRESH SELF COLUMN DECODER I/O 0-15
A8 CONTROLLER REFRESH
CONTROLLER 8
A7 256
A6 DATA OUT
REFRESH SENSE AMP I/O GATE
A5 BUFFER
COUNTER
A4 16 16
ROW DECODER
A3
MEMORY CELL
A2
MULTIPLEXER
ARRAY Vcc/VccQ
A1 ROW 2048
GND/GNDQ
A0 ADDRESS
ROW BANK 1
11 BUFFER 11
ADDRESS
11
LATCH
14
AVR-550SD
Q4 9 10 Q5
1N4007 ( : IC ) SMAB36 ( : IC )
2 1
1:ANODE
2:CATHODE
15
AVR-550SD
BLOCK DIAGRAM
Display code RAM
Bank 1 : 8bit x 16
Bank 2 : 8bit x 64
. CGROM
(35bit x 160)
. Segment
... 59... ...
SEG00
33 SEG26
.
output
code
write circuit ... 31... ...
SEG27
CGRAM 24 SEG34
dot data
write (35bit x 16)
CS 14 Serial
data Code/
SCK 15 receive 23 SEG35
command
DIG12/
..
SDAT A 16 circuit control Segment/ 64 SEG36
circuit Digit 63
DIG13/
SEG37
select/
.
code 62 DIG14/
select output SEG38
DIG15/
circuit 61 SEG39
XIN 21
. .
Clock timing
clock Display
generator
XOUT 20 controller scan pulse
12 DIG00
Digit
.. .. ..
RESET 13
Vcc1 19
. . output
circuit
. . .
1 DIG11
Vcc2 60 2
18 P0
Vss 22
17 P1
Vp 32
16
AVR-550SD
74LCX244 (IC809~811)
TOP VIEW
1 20
OE VCC
2 19 1 20
I0 OE2 1G VCC
3 18 1A0 2 19 2G
O4 O0
# 4 17 2Y0 3 18 1Y 0
I1 I4
5 16 1A1 4 17 2A0
O5 O1 2Y1 5 16 1Y1
$ 6 15
6 15 2A1
I2 I5 1A2
7 14
O6 O2 2Y2 7 14 1Y2
8 13 1A3 8 13 2A2
I3 I6
9 12 2Y3 9 12 1Y3
O7 O3
10 11 GND 10 11 2A3
GND I7
PIN DESCRIPTION
VCC
A15 1 48 A16 Symbol Pin Name
A14 BYTE
A13 VSS A0-A18 Address Inputs
A12 DQ15A-1 DQ0-DQ7 Data Input/Outputs, Command Inputs
19 15
A11 DQ7
A10 DQ14 A0-A18 DQ0-DQ14 DQ8-DQ14 Data Input/Outputs
A9 DQ6
A8 DQ13 DQ15A-1 Data Input/Output or Address Input
NC DQ5 E Chip Enable
NC DQ12 W DQ15A-1
W DQ4 G Output Enable
RP 12 M29W800T 37 VCC E BYTE
M29W800AT W Write Enable
NC 13 M29W800T 36 DQ11
NC DQ3 RP Reset/Block Temporary Unprotect
RB DQ10 G RB
A18 DQ2 RB Ready/Busy Output
A17 DQ9
A7 DQ1
RP BYTE Byte/Word Organization
A6 DQ8
A5 DQ0
VCC Supply Voltage
A4 G VSS Ground
A3 VSS
A2 E NC No Connected Internally
A1 A0
24 25 Vss DU Don’t Use as Internally Connected
17
AVR-550SD
Block Diagram
18
AVR-550SD
A B E MONITOR OUT
Monitor OUT 16 IN1
L L * IN 1
GND 6dB 15 CTL A H L * IN 2
IN5 LOGIC 14 V OUT1 L H * IN 3
GND 13 Vcc
H H L IN 4
H H H IN 5
IN4 12 IN2
6dB C D E V OUT 1
CTL E 11 CTL B
L L *
IN3 7 LOGIC 10 V OUT2
H L * IN 2 T
CTL D 8 9 CTL C L H * IN 3
H H L IN 4
H H H IN 5
Note 1: * mark means that T
feasible for either H or L. C D E V OUT 2
L L * IN 1
Note 2: Each input terminal is
H L *
provided with sink chip
clamp (BA7625). L H * IN 3
Each input terminal takes H H L IN 4
20kohm at the end (BA7626). H H H IN 5
Truth Table
Y1 1 16 Vcc Control Inputs
Y0 2 15 Y Select
Enable C B A ONSwitches
Z1 3 14 X1
L L L L Z0 Y0 X0
Z 4 13 X
L L L H Z0 Y0 X1
Z0 5 12 X0 L L H L Z0 Y1 X0
Enable 6 11 C L L H H Z0 Y1 X1
VEE 7 10 A L H L L Z1 Y0 X0
GND 8 9 B L H L H Z1 Y0 X1
L H H L Z1 Y1 X0
L H H H Z1 Y1 X1
H X X X None
X = Don’t Care
Vcc
Power Save
6 5
Vref.
Yin 1 Clamp
3 Vout
Disc.
750Ω
4 Vsag
Cin 8 Bias
7 2
C mute GND
19
AVR-550SD
20
AVR-550SD
TRANSISTORS
KRC107M
KRA102M KRA102S KRA Series DTC Series
KRA104M KRC102S C KRC Series C
KTC3198 KRC107S
2SA933 KTA3875S R1 R1
B B
KTA1266 KTA1504S
R2 R2
KSA916 KRC234S
KSC2383(Q3) KTC2875 E
E
KSR1004(Q4,Q5)
R1 R2 R1 R2
B
FRONT TOP KRA102M/S 10Kohm 10Kohm KRC107M/S 10Kohm 47Kohm
VIEW VIEW C
KRA104M 47Kohm 47Kohm KRC102S 10Kohm 10Kohm
E
KRC2345S 4.7Kohm
E C B
2SA708 SPP20N60S5
2SC1008
KSP2222A(Q1,Q2)
FRONT
VIEW
FRONT
VIEW
GDS
mon
ut
E B C
FRONT
VIEW
G
S
G D S
KIA79151PI FQD5P10
D
S
FRONT
VIEW
D
G
G
Common
Ou tpu t
S
Input
H11A817(PC1~6)
CATHODE (K)
ANODE 1 4 COLLECTOR
REFERENCE (R)
CATHODE 2 3 EMITTER
ANODE(A)
21
AVR-550SD
DIODE
SF3006PT(D11)
FRONT
VIEW
1 2 3
SFAF808G(G5)
FRONT
VIEW
1 3
1 3
22
AVR-550SD
2. FL DISPLAY
15-ST-43GN
90 46
1 45
PIN CONNECTION
GRID ASSINMENT
23
AVR-550SD
ANODE CONNECTION
24
AVR-550SD
COMPONENT SIDE
25
AVR-550SD
FOIL SIDE
26
AVR-550SD
COMPONENT SIDE
27
AVR-550SD
FOIL SIDE
28
AVR-550SD
COMPONENT SIDE
29
AVR-550SD
FOIL SIDE
FOIL SIDE
30
AVR-550SD
31
AVR-550SD
l Resistors
Ex.: RN 14K 2E 182 G FR
RN 14K 2E 182 G FR
Type Shape Power Resist- Allowable Others
and per- ance error
formance
l Capacitors
Ex.: CE 04W 1H 2R2 M BP
CE 04W 1H 2R2 M BP
Type Shape Dielectric Capacity Allowable Others
and per- strength error
formance
CE : 0J : 6.3 V F ±1%
: HS :
CE : Aluminum foil 0J : 6.3V F : ±1% HS : High stability type CA : 1A : 10 V G ±2%
: BP :
electrolytic CS : 1C : 16 V J ±5%
: HR :
CA : Aluminum solid 1A : 10V G : ±2% BP : Non-polar type
electrolytic CQ : 1E : 25 V K ±10%
: DL :
CS : Tantalum electrolytic 1C : 16V J : ±5% HR : Ripple-resistant type CK : 1V : 35 V M ±20%
: HF :
CQ : Film 1E : 25V K : ±10% DL : For change and discharge CC : 1H : 50 V Z +80%
: U : UL
CK : Ceramic 1V : 35V M : ±20% HF : For assuring high
requency CP : 2A : 100 V −20% C : CSA
CC : Ceramic 1H : 50V Z : +80% U : UL part CM : 2B : 125 V P : +100% W : UL-CSA
CP : Oil 2A : 100V –20% C : CSA part CF : 2C : 160 V − 0% F :
CM : Mica 2B : 125V P : +100% W : UL-CSA type
CF : Metallized 2C : 160V –0% F : Lead wire forming CH : 2D : 200 V C : ±0.25pF
CH : Metallized 2D : 200V C : ±0.25pF 2E : 250 V D : ±0.5pF
2E : 250V D : ±0.5pF 2H : 500 V = :
2H : 500V = : Others
2J : 630V 2J : 630 V
• When the dielectric strength is indicated in AC, "AC" is included after the dieelectric
strength value.
32
AVR-550SD
33
AVR-550SD
34
AVR-550SD
35
AVR-550SD
36
AVR-550SD
37
AVR-550SD
38
AVR-550SD
39
AVR-550SD
40
AVR-550SD
41
AVR-550SD
42
AVR-550SD
43
AVR-550SD
44
AVR-550SD
45
AVR-550SD
46
AVR-550SD
47
AVR-550SD
48
AVR-550SD
49
AVR-550SD
50
AVR-550SD
51
AVR-550SD
52
AVR-550SD
53
AVR-550SD
54
AVR-550SD
55
AVR-550SD
EXPLODED VIEW
WARNING:
Parts List Parts marked with this symbol
characteristics.
have critical
S1
印の部分は安全を維持するために重要
S1
な部品です。従って交換時は必ず指定の
部品を使用して下さい。
S11
53
53
S12 S6 53
39
S10
!
S12 S9 S6 S9
36 S1 39
40
35 !
S10 S12
S9 50
49
S5 40
35 38
S8 51
S12 53
S5 52
34 S8
S5 33
S12
S12
33 37
33
32
33 33 54
S8 S8
33 31
30
30
30
44 S8
20
S4 30
30 48 46
19
S3 11 S8
21 45
13
14 22 42
10 S4 43
S2 15
16 23
9 7 12 47
31
8 24
17 18 S4 24 CAUTION. ご注意。
6 19 S4 27 バックパネルの分解・組み立てを行なうときは インプット基板をはずして作業してください。
(インプット基板のコンデンサーC813がメインシャーシに接触して破損する危険があります。)
41 S4 29
28 When you perform disassembly of a BACK PANEL, and an assembly,
S7 please work removing an INPUT B.D.
5 25
S2 S4 (There is a risk of the capacitor C813 of an INPUT B.D. being contacted
26
41
S1 and damaged on a main chassis.)
27
S3
C813 38 CHASSIS
29
S7 (BACK PANEL)
S2
4
S1
S1
1
3
2
S1
INPUT B.D.
56
AVR-550SD
57
AVR-550SD
58
AVR-550SD
PACKING VIEW
4 2 3
5 9
1
10
6
13
7 16
6
15
14
12 11
12
16
8
59
AVR-550SD
LEVEL DIAGRAM
60
AVR-550SD
WARNING: ! 印の部品は安全を維持するために重要な部品です。
Parts marked with this symbol ! have critical characteristics. 従って交換時は必ず指定の部品を使用してください。
Use ONLY replacement parts recommended by the manufactur-
er.
注)
CAUTION: (1) 指定なき抵抗値は Ω、k は kΩ、M は MΩ を示す。
Before returning the unit to the customer, make sure you make (2) 指定なきコンデンサーの値は µF、p は pF を示す。
either (1) a leakage current check or (2) a line to chassis resis-
tance check. If the leakage current exceeds 0.5 milliamps, or if (3) 各部の電圧は無信号の値を示す。
the resistance from chassis to either side of the power cord is (4) この配線図は基本配線図です。改良等のため変更する
less than 460 kohms, the unit is defective. ことがありますのでご了承ください。
WARNING:
DO NOT return the unit to the customer until the problem is lo-
cated and corrected. SIGNAL LINE
NOTICE:
ALL RESISTANCE VALUES IN OHM. k=1,000 OHM
M=1,000,000 OHM
ALL CAPACITANCE VALUES IN MICRO FARAD.
P=MICRO-MICRO FARAD
EACH VOLTAGE AND CURRENT ARE MEASURED AT
NO SIGNAL INPUT CONDITION.
CIRCUIT AND PARTS ARE SUBJECT TO CHANGE
WITHOUT PRIOR NOTICE.
SIGNAL LINE
61
SCHEMATIC DIAGRAM DSP1 UNIT AVR-550SD
1 2 3 4 5 6 7 8 9 10 11
SCHEMATIC DIAGRAMS
H
DSP1 UNIT
62
SCHEMATIC DIAGRAM DSP2 UNIT AVR-550SD
1 2 3 4 5 6 7 8 9 10 11
SCHEMATIC DIAGRAMS
H
DSP2 UNIT
63
SCHEMATIC DIAGRAM INPUT UNIT AVR-550SD
1 2 3 4 5 6 7 8 9 10 11
DIGITAL
E
ANALOG
SCHEMATIC DIAGRAMS
H
INPUT UNIT
64
SCHEMATIC DIAGRAM AMP UNIT AVR-550SD
1 2 3 4 5 6 7 8 9 10 11
SCHEMATIC DIAGRAMS
H
AMP UNIT
65
SCHEMATIC DIAGRAM CPU UNIT AVR-550SD
1 2 3 4 5 6 7 8 9 10 11
SCHEMATIC DIAGRAMS
H
CPU UNIT
66
SCHEMATIC DIAGRAM VIDEO UNIT AVR-550SD
1 2 3 4 5 6 7 8 9 10 11
C
VIDEO INPUT SWITCHING (BA7626)
SCHEMATIC DIAGRAMS
H
VIDEO UNIT
67
SCHEMATIC DIAGRAM SPK UNIT AVR-550SD
1 2 3 4 5 6 7 8 9 10 11
SCHEMATIC DIAGRAMS
H
SPK UNIT
68
SCHEMATIC DIAGRAM FRONT UNIT AVR-550SD
1 2 3 4 5 6 7 8 9 10 11
SCHEMATIC DIAGRAMS
H
FRONT UNIT
69
SCHEMATIC DIAGRAM SMPS UNIT (For JP model) AVR-550SD
1 2 3 4 5 6 7 8 9 10 11
SCHEMATIC DIAGRAMS
H
SMPS UNIT (For JP model)
70
SCHEMATIC DIAGRAM SMPS UNIT (For E2 model) AVR-550SD
1 2 3 4 5 6 7 8 9 10 11
SCHEMATIC DIAGRAMS
H
SMPS UNIT (For E2 model)
71