Department of Electronic Engineering

Faculty of Engineering and Technology University

of Sindh, Jamshoro

Electronic Devices and Circuits (EE-123)

LAB # 15
Name: ______________________________________________________ Roll No: ________________

Score ________________Signature of the Lab Tutor: ______________________ Date: _____________

Dr. Mudasir Ahmed Memon

Selection of Utilization of Experimental Experimental Lab Safety Teamwork Technical
Equipment Lab Tools & Data Collection Data Analysis Precautions During Lab cleanliness and 𝒔𝒄𝒐𝒓𝒆 = 𝟐
×𝐎𝐛𝐭𝐚𝐢𝐧ed marks
(0 to 5) Calibration (0 to 5) (0 to 5) (0 to 5) Task Organization 𝟑𝟓
(0 to 5) (0 to 5) (0 to 5)

Object: To study the transfer and output characteristics of an n-channel Junction field-effect Transistor
(JFET) in Common-source configuration.

Apparatus Required:
1. Regulated Power supply, Breadboard and Connecting wires
2. N-channel JFET
3. Oscilloscope and Multimeter (MM)

Theory: [30 minutes]

The BJT transistor is a current-controlled device, whereas the JFET transistor is a voltage-controlled
device as shown in Fig 15.1. The current IC in BJT is a direct function of the level of IB. For the FET, the
current ID will be a function of the voltage VGS applied to the input circuit. In each case, the current of the
output circuit is controlled by a parameter of the input circuit—in one case a current level and in the other
an applied voltage. Just as there are npn and pnp bipolar transistors, there are n-channel and p-channel
fieldeffect transistors and their symbols are shown in Fig 15.2. However, the BJT transistor is a bipolar
device—the prefix bi indicates that the conduction level is a function of two charge carriers, electrons and
holes. The FET is a unipolar device depending solely on either electron (n-channel) or hole (p-channel)
conduction. For the FET, an electric field is established by the charges present, which controls the
conduction path of the output circuit without the need for direct contact between the controlling and
controlled quantities. One of the most important characteristics of the FET is its high input impedance.
However, typical ac voltage gains for BJT amplifiers are a great deal more than for FETs. FETs are more
temperature stable than BJTs, and FETs are usually smaller than BJTs, making them particularly useful in
integrated-circuit (IC) chips.

1
 Department of Electronic Engineering
Faculty of Engineering and Technology University
of Sindh, Jamshoro

Electronic Devices and Circuits (EE-123)

(a) Current controlled (b) voltage controlled

Figure 15.1: BJT and FET

(a) N-Channel (b) P-Channel Fig.

15.2: Symbols of JFET.
The major part of the structure is the n-type material in n -channel JFET as shown in Fig. 15.3, which
forms the channel between the embedded layers of p-type material. The top of the n-type channel is
referred to as the drain (D), whereas the lower end of the same material is referred to as the source (S).
The two ptype materials are connected and to the gate (G) terminal. In essence, therefore, the drain and
the source are connected to the ends of the n-type channel and the gate to the two layers of p-type
material.

Fig. 15.3: N-channel Junction field-effect transistor (JFET).

As the voltage VDS is increased from 0V to a few volts, the current will increase as determined by Ohm’s
law and the plot of ID versus VDS will appear as shown in Fig. 15.4. The relative straightness of the plot
reveals that for the region of low values of VDS, the resistance is essentially constant. As VDS increases and
2
 Department of Electronic Engineering
Faculty of Engineering and Technology University
of Sindh, Jamshoro

Electronic Devices and Circuits (EE-123)

approaches a level referred to as VP in Fig. 15.4, the depletion regions will widen, causing a noticeable
reduction in the channel width. The reduced path of conduction causes the resistance to increase and the
curve in the graph of Fig. 15.4 to occur. The more horizontal the curve, the higher the resistance,
suggesting that the resistance is approaching “infinite” ohms in the horizontal region. If VDS is increased
to a level where it appears that the two depletion regions would “touch” as shown in Fig. 15.5, a
condition referred to as pinch-off will result. The level of VDS that establishes this condition is referred to
as the pinch-off voltage and is denoted by VP, as shown in Fig. 15.4. In actuality, the term pinch-off is a
misnomer in that it suggests the current ID is pinched off and drops to 0 A. As shown in Fig. 15.4,
however, this is hardly the case— ID maintains a saturation level defined as IDSS in Fig. 15.4. In reality, a
very small channel still exists, with a current of very high density. The fact that ID does not drop off at
pinch-off and maintains the saturation level indicated in Fig. 15.4 is verified by the following fact: The
absence of a drain current would remove the possibility of different potential levels through the n -
channel material to establish the varying levels of reverse bias along with the p – n junction. The result
would be a loss of the depletion region distribution that caused pinch-off in the first place.

Fig. 15.4: ID versus VDS for VGS = 0 V

3
 Department of Electronic Engineering
Faculty of Engineering and Technology University
of Sindh, Jamshoro

Electronic Devices and Circuits (EE-123)

Fig. 15.5: Pinch-off (VGS = 0 V, VDS = VP).

As VDS is increased beyond VP, the region of close encounter between the two depletion regions increases
in length along the channel, but the level of I D remains essentially the same. In essence, therefore, once
VDS > VP, the JFET has the characteristics of a current source. As shown in Fig. 15.6, the current is fixed
at ID=IDSS, but the voltage VDS (for levels > VP) is determined by the applied load.

Fig. 15.6: Current source equivalent for VGS = 0 V, VDS > VP.

IDSS is the maximum drain current for a JFET and is defined by the conditions VGS= 0 V and VDS > VP.
The relationship between ID and VGS is defined by Shockley’s equation.

𝑉𝐺𝑆 2
𝐼𝐷 = 𝐼𝐷𝑆(1− )
𝑉𝑃

The squared term in the equation results in a nonlinear relationship between ID and VGS, producing a curve
that grows exponentially with decreasing magnitude of VGS. The level of 𝑉𝐺𝑆 that results in ID =0 mA is
defined by VGS = VP, with VP being a negative voltage for n-channel devices and a positive voltage for
pchannel JFETs. The transfer curve obtaining from the drain characteristics is shown in Fig 15.7.

4
 Department of Electronic Engineering
Faculty of Engineering and Technology University
of Sindh, Jamshoro

Electronic Devices and Circuits (EE-123)

Fig. 15.7: Obtaining the transfer curve from the drain characteristics

Procedure [150 minutes]

1. Make the circuit connections as show in the figure 15.8.

2. Keep VGS = 0V, increase VDS in steps shown in table 15.1 and note down the corresponding value
of ID for each value of the VDS.
3. Tabulate the readings and plot a graph of V DS v/s ID for VGS =0, VGS = -1V, VGS = -2V. VGS = -3V,
VGS = -4V.
4. Plot the (Drain characteristics) graph of VDS versus ID for different constants values of VGS. Taking
VDS on X-axis and ID on Y-axis.

Fig. 15.8: n-channel Junction field effect Transistor (JFET) in Common-source configuration Table
15.1

5
 Department of Electronic Engineering
Faculty of Engineering and Technology University
of Sindh, Jamshoro

Electronic Devices and Circuits (EE-123)

VGS =0V VGS =-1V VGS =-2V VGS =-3V VGS =-4V
S.No VDS
ID ID ID ID ID
1 1
2 3
3 5
4 8
5 10
6 12
7 15
8 20

Graph

Transconductance characteristics

1. Make the circuit on the breadboard as shown in the figure 15.8.

2. Keep VDS = 10 V constant.
3. Increase VGS in the steps shown in table 15.2 and note the corresponding value of ID till ID =0.
4. Tabulate the readings and plot the graph ID v/s VGS. Taking VGS on X-axis and ID on Y-axis. Table
15.2
S.No VGS (V) ID (mA)
1 0
6
 Department of Electronic Engineering
Faculty of Engineering and Technology University
of Sindh, Jamshoro

Electronic Devices and Circuits (EE-123)

2 0.5
3 1.0
4 1.5
5 2.0
6 3.0
7 4.0
8 5.0
9 6.0

Graph