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Compal La-1012 r1b Schematics
Compal La-1012 r1b Schematics
1 1
2
32N101 LA-1012 Rev1.0 Schematics Doc. 2
4 4
Title
Compal Electronics, inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1012
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Custom 401200 1B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date: Friday, October 19, 2001 Sheet 1 of 45
A B C D E
A B C D E
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
BLOCK DIAGRAM
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
Model Name :
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
N32N101
PCB No : LA-1012 Mobile Tualatin
Date : 2001/09/01
4 4
or
Coppermine-T Thermal Sensor CK TITAN CPU VID & All
Revision : 1.0 (uFCBGA/uFCPGA) MAX1617MEE ICS9250-38 reference voltage
PAGE 4,5 PAGE 5 PAGE 8 PAGE 7
PSB
CRT
Conn. PAGE 16
Interface
HUB
LAN EXT. MIC IN
82562ET
CRT CONN.
PAGE 25
PS/2 CONN. PAGE 37
2
421 BGA Mini PCI 2
PCI BUS DC/DC Interface
USB & BlueTooth USB Socket
PAGE 17,18 PAGE 38
RTC Battery
PAGE 20
PAGE 39
LPC
CardBus
OZ6933T Slot 0/1
PAGE 24 BATTERY
PAGE 23
Super I/O Embedded Charger
PAGE 42
NS PC87391 Controller
PAGE 32 NS PC87591 Audio
PAGE 30 Controller EQ Circuit
ES1988 POWER
PAGE 27 PAGE 29
Interface
1 PAGE 40,41,42,44 1
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
3
IEEE-1394 Controller AD16 0 PIRQA 3
+VCC_H_CORE
1 1
AC21
AC19
AC17
AC15
AC13
AC11
AB22
AA21
AB20
AA19
AB18
AA17
AB16
AA15
AB14
AA13
AB12
AA11
AB10
W21
AC9
AC7
M22
AA9
AB8
AA7
G21
D22
H22
N21
R21
U21
D20
D18
D16
D14
D12
D10
E21
K22
P22
V22
Y22
E19
E17
E15
E13
E11
F22
T22
F20
F18
F16
F14
F12
F10
L21
J21
G5
D8
D6
H6
N5
E9
E7
E5
K6
V6
F8
F6
T6
J5
H_A#[3..31] U4A H_D#[0..63]
9 H_A#[3..31] H_D#[0..63] 9
VCC_0
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
H_A#3 K1 A16 H_D#0
H_A#4 A#3 D#0 H_D#1
J1 A#4 D#1 B17
H_A#5 G2 A17 H_D#2
H_A#6 A#5 D#2 H_D#3
K3 A#6 D#3 D23
H_A#7 J2 B19 H_D#4
H_A#8 A#7 D#4 H_D#5
H3 A#8 D#5 C20
H_A#9 G1 VCC C16 H_D#6
H_A#10 A#9 D#6 H_D#7
A3 A#10 D#7 A20
H_A#11 J3 A22 H_D#8
H_A#12 A#11 D#8 H_D#9
H1 A#12 D#9 A19
H_A#13 D3 A23 H_D#10
H_A#14 A#13 D#10 H_D#11
F3 A#14 D#11 A24
H_A#15 G3 C18 H_D#12
H_A#16 A#15 D#12 H_D#13
C2 A#16 D#13 D24
H_A#17 B5 B24 H_D#14
H_A#18 A#17 D#14 H_D#15
B11 A#18 D#15 A18
H_A#19 C6 E23 H_D#16
H_A#20 A#19 D#16 H_D#17
B9 A#20 D#17 B21
H_A#21 B7 B23 H_D#18
H_A#22 A#21 D#18 H_D#19
C8 A#22 D#19 E26
H_A#23 A8 C24 H_D#20
2 H_A#24 A#23 D#20 H_D#21 2
A10 A#24 Address D#21 F24
H_A#25 B3 Lines D25 H_D#22
H_A#26 A#25 D#22 H_D#23
A13 A#26 D#23 E24
H_A#27 A9 B25 H_D#24
H_A#28 A#27 D#24 H_D#25
C3 A#28 D#25 G24
H_A#29 C12 H24 H_D#26
H_A#30 A#29 D#26 H_D#27
C10 A#30 D#27 F26
H_A#31 A6 L24 H_D#28
A#31 D#28 H_D#29
A15 H25
A14
B13
A12
A#32
A#33
A#34
Mobile Data
Signals
D#29
D#30
D#31
C26
K24
G26
H_D#30
H_D#31
H_D#32
9 H_REQ#[0..4]
H_REQ#[0..4]
H_REQ#0 R1
A#35
REQ#0
Tualatin D#32
D#33
D#34
D#35
K25
J24
K26
H_D#33
H_D#34
H_D#35
H_REQ#1 L3 F25 H_D#36
H_REQ#2 REQ#1 D#36 H_D#37
T1 REQ#2 Request D#37 N26
H_REQ#3 U1 Signals J26 H_D#38
H_REQ#4 REQ#3 D#38 H_D#39
L1 REQ#4 D#39 M24
T4 U26 H_D#40
RP# D#40 H_D#41
9 H_ADS# AA3 ADS# D#41 P25
L26 H_D#42
D#42 H_D#43
D#43 R24
W2 R26 H_D#44
AERR# D#44 H_D#45
AB3 AP#0 D#45 M25
P3 Error V25 H_D#46
+1.5V_SW AP#1 D#46 H_D#47
C14 BERR# Interface D#47 T24
R19 1.5K AF23 M26 H_D#48
BINIT# D#48 H_D#49
1 2 AF4 IERR# D#49 P24
3 H_D#50 3
D#50 AA26
R28 10 T26 H_D#51
D#51 H_D#52
1 2 A7 BREQ0# D#52 U24
C4 Arbitration Y25 H_D#53
NC D#53 H_D#54
C22 NC Signals D#54 W26
AD23 V26 H_D#55
NC D#55 H_D#56
9 H_BPRI# R2 BPRI# D#56 AB25
L2 T25 H_D#57
9 H_BNR# BNR# D#57
V3 Snoop VSS VCC Y24 H_D#58
9 H_LOCK# LOCK# D#58
Signals W24 H_D#59
D#59 H_D#60
D#60 Y26
AA2 AB24 H_D#61
9 H_HIT# HIT# D#61
U2 AA24 H_D#62
9 H_HITM# HITM# D#62
T3 V24 H_D#63
9 H_DEFER# DEFER# D#63
VCC_80
VCC_79
VCC_78
VCC_77
VCC_76
VCC_75
VCC_74
VCC_73
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
B18 VSS_53
D17 VSS_54
F17 VSS_55
E18 VSS_56
AB17VSS_57
VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
AC25
AC22
AC20
AA25
AE26
AB23
AE23
AB21
AA22
AE21
AB19
AA20
AE19
AF25
W25
W22
AC5
M23
M21
AA5
AB6
G25
G22
N25
R25
U25
C23
H23
D21
H21
N22
R22
U22
D19
E16
E25
K23
P23
V23
Y23
B22
E22
K21
P21
V21
Y21
B20
F23
T23
F21
T21
TUALATIN
L25
L22
J25
J22
W5
M6
R4
U5
P6
Y6
+VCC_H_CORE
4 4
Title
Compal Electronics, inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL SCHEMATIC, M/B LA-1012
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE 401200
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date: Friday, October 19, 2001 Sheet 4 of 45
A B C D E
A B C D E
+VTT
AC18
AC16
AC14
AC12
AC10
AA18
AE17
AB15
AA16
AE15
AB13
AA14
AE13
AB11
AA12
AE11
AA10
AC8
AC6
AB9
AE9
AB7
AA8
AE7
AB5
AA6
AE5
D15
D13
D11
B16
B14
E14
B12
E12
B10
E10
F15
F13
F11
W6
W4
M3
G6
D9
D7
H5
N6
R6
U6
D4
H4
U4
D2
H2
B8
E8
B6
K5
V5
Y5
B4
K4
B2
F9
F7
F5
T5
F4
F2
L6
J6
+1.8V_SW U4B
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
+1.5V_SW
+1.5V_SW
RP1
Y3 AE24 1 8 TESTLO1
9 H_RS#0 RS#0 DEP#0
1
V1 AD25 2 7 TESTLO2
9 H_RS#1 RS#1 DEP#1
1 Place H_RESET# R267 R13 R21 R22 U3 AE25 3 6 TESTHI2 1
9 H_RS#2 RS#2 DEP#2
R272<0.1" from 56.2_1% 3K M5 RSP# Request DEP#3 AC24
+VTT
4 5 TESTHI1
U6
1.5K 1.5K
9 H_TRDY# W1 TRDY# Signals GND DEP#4 AF24
8P4R_1K
DEP#5 AD26
2
Data DEP#6 AC26
H_A20M# AC3 Signals AD24
17 H_A20M# A20M# DEP#7
17 H_FERR# AF6 FERR#
H_FLUSH# AF5
H_IGNNE# FLUSH#
17 H_IGNNE# AD9 IGNNE# VREF_1 AF21
AD3 AB26 +V_AGTLREF
17 H_SMI# SMI# VREF_2 +VCC_H_CORE
17 H_PWRGD AB4 PWRGOOD VREF_3 H26
+VTT
17 H_STPCLK# AE4 STPCLK# VTT Ref VREF_4 A21
17,42 H_DPSLP#
H_INTR
AF8 DPSLP# Compatibility VREF_5 AF9
17 H_INTR AD15 INTR/LINT0 VREF_6 A4
H_NMI AE14 N1
17 H_NMI NMI/LINT1 VREF_7
17 H_INIT# AE6 INIT# VREF_8 AA1
9 H_RESET# B15 RESET#
Y4 TESTLO1
TESTLO
9 H_DBSY# W3 DBSY# VCC R5
Y1 N3 VCPU_PLL1 1 2
+1.5V_SW 9 H_DRDY# DRDY# PLL1
Analog N2 VCPU_PLL2 L10 4.7UH
PLL2
NC P1
+1.5V_SW H_THERMDA AF13 THERMDA NC P5
H_THERMDC AF14 E1 C27
THERMDC NC 33UF_D2_16V
F1
Mobile NC
1
+
R40 R42 AE12
8,11 H_BSEL0 SELFSB0
150 150 AF10 AC1 CLK_HCLK
Tualatin
8 H_BSEL1 SELFSB1 CLK0 CLK_HCLK 8
2 1 2 AF16 AD1 CLK_HCLK# 2
EDGECTRLP CLK0# CLK_HCLK# 8
R35 110_1% M1 TESTLO2
TESTLO
2
AD19 +VTT
PICD0 R41 14_1%
AD17 PICD1 NC AF18
R284 1 2 26.7_1% PIC_CLK AF20 APIC AD16 NCHCTRLP 1 2
8 CLK_CPU_APIC PICCLK NCHCTRLP
C449 AF11 TESTHI1
TESTHI
1
1 R285 2 AE8
R286 NC
@33 AF22 RP2# NC N24
137_1% @10PF AE20 Debug AE10
RP3# NC TESTHI2
AD22 BPM0# Break TESTHI E2
AD21 BPM1# Point
CLK_HCLK CLK_HCLK#
2
NC P4
2
ITP_TCK AD10
7 ITP_TCK TCK
ITP_TDI AD7 Test R262 R261
7 ITP_TDI TDI
ITP_TDO AD11 Access AD4 @33 @33
7 ITP_TDO TDO NC_1
ITP_TMS AF7 PORT A5
7 ITP_TMS TMS NC_2
ITP_TRST# AF15 D1
7 ITP_TRST# TRST# NC_3
ITP_PREQ#
1
7 ITP_PREQ# AF19 PREQ# ( ITP ) NC_4 AD13
ITP_PRDY# AE22 B1 C378 C377
+VS_CMOSREF 7 ITP_PRDY# PRDY# NC_5
P26 @10PF @10PF
NC_6
NC_7 A11
AF12 CMOSREF_1
AD5 CMOSREF_0
Note : 1 2 AE16 VCCT VID E3 VTT_PWRGD
R38 56.2_1% RTTIMPDEP VTTPWRGOOD
GHI# Pull-Up internally
VSS_142
VSS_141
VSS_140
VSS_139
VSS_138
VSS_137
VSS_136
VSS_135
VSS_134
VSS_133
VSS_132
VSS_131
VSS_130
VCCT_1
VCCT_2
VCCT_3
VCCT_4
VCCT_5
VCCT_6
VCCT_7
VCCT_8
VCCT_9
VID0
VID1
VID2
VID3
VID4
VSS
VSS
VSS
NC
NC
N4 NC
+5V_ALW
AD20
AD18
AD14
AD12
AC23
AA23
AE18
AF26
AF17
W23
AD8
AD6
AC4
AC2
AD2
AA4
AE3
AB1
AE2
AE1
AB2
G23
AF2
AF1
AF3
N23
R23
U23
C21
C19
C17
C15
C13
C11
C25
A26
B26
E20
A25
F19
W=40mil TUALATIN
L23
J23
M4
M2
G4
C9
C7
C5
D5
R3
C1
E4
V4
E6
Y2
V2
P2
K2
T2
L4
J4
+VTT
1
R274
200
2
C422 +VTT
CPU_VR_VID2 7
CPU_VR_VID1 7
1
.1UF
CPU_VR_VID0 7
R18
1
1
R17 10K
15
Thermal Sensor
2
MAX1617 U6
MAX1617/NE1617 2K
2
16 NC
STBY#
VCC
VTT_PWRGD# 8,29
13 NC
2
9 NC SMBC 14 EC_SMC_2 29,33,36 1
5 NC 12 VTT_PWRGD 1 R16 2 2 Q8
SMBD EC_SMD_2 29,33,36 42 VTT_PWRGD
1 11 18K 3 3904
H_THERMDA 3 NC ALERT#
1
4
C758 4
DXP
ADD0
ADD1
From 87591
GND
GND
1
H_THERMDC 4 @2.2UF_16V_0805
C58 DXN R273
2
2200PF
10
100K
2
8
7
1K
1 2 Title
+5V_ALW
+5V_ALW
R36 1K THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL SCHEMATIC, M/B LA-1012
1 2 Address:1001_110X AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE 401200
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date: Saturday, October 20, 2001 Sheet 5 of 45
A B C D E
A B C D E
Layout note :
Place close to CPU, Use 2~3 vias per PAD.
1 Place .47uF caps underneath balls on solder side. Layout note : 1
Place 10uF caps on the peripheral near balls.
Use 2~3 vias per PAD. Place close to CPU,
Use 2 vias per PAD.
+VCC_H_CORE +VTT
1
1
C399 C398 C396 C411 C437 C401 C404 C413 C440 C434 C426 C428 + C42 + C75 + C105 + C47 + C51 + C392
.22UF_0603 .22UF_0603 .22UF_0603 .22UF_0603 .22UF_0603 .22UF_0603 150UF_D2_6.3V 150UF_D2_6.3V 150UF_D2_6.3V 150UF_D2_6.3V 150UF_D2_6.3V 150UF_D2_6.3V
2
2
.22UF_0603 .22UF_0603 .22UF_0603 .22UF_0603 .22UF_0603 .22UF_0603
2
+VCC_H_CORE
+VTT
1
1
C397 C412 C427 C435 C403 C433 C402 C410 C425 C432 C438 C439
.22UF_0603 .22UF_0603 .22UF_0603 .22UF_0603 .22UF_0603 .22UF_0603 C91 C436 C56 C29 C43 C41 C63 C55 C101 C102
1UF_0603 1UF_0603 1UF_0603 1UF_0603 1UF_0603 1UF_0603 1UF_0603 1UF_0603 1UF_0603 1UF_0603
2
2
.22UF_0603 .22UF_0603 .22UF_0603 .22UF_0603 .22UF_0603 .22UF_0603
2
2 2
+VCC_H_CORE
1
1
C98 C62 C407 C17 C406
10UF_10V_1206 10UF_10V_1206 10UF_10V_1206 10UF_10V_1206 10UF_10V_1206
Tualatin
2
2
-------------------------------------------------------
D4 D3 D2 D1 D0 CPU_Core(V) QS( MP)
+VCC_H_CORE -------------------------------------------------------
0 1 0 0 1 1.40V
0 1 1 0 0 1.15V
1
+VCC_H_CORE
3 3
Coppermine-T
1
0 0 0 0 1 1.70V
0 1 0 0 0 1.35V
-------------------------------------------------------
+VCC_H_CORE
D4 D3 D2 D1 D0 CPU_Core(V) QS( MP)
-------------------------------------------------------
1
0 0 0 0 1 1.70V
+ C24 + C424 + C469 + C444 + C471 + C52
150UF_D2_6.3V 150UF_D2_6.3V 150UF_D2_6.3V 150UF_D2_6.3V 150UF_D2_6.3V 150UF_D2_6.3V 0 1 0 0 0 1.35V
-------------------------------------------------------
2
4 4
Title
Compal Electronics, inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL SCHEMATIC, M/B LA-1012
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE 401200
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date: Friday, October 19, 2001 Sheet 6 of 45
A B C D E
A B C D E
1
1 1
1
2
3
4
R133 R62 Layout note :
R333 RP16 249_1% 249.9_1% 1K_1%
1K 8P4R_1K 1. Place R70 and R75 between and GMCH and CPU.
2. Place decoupling caps near CPU.(Within 500mils)
2
U34 RP37 8P4R_0
Place capacitor close to GMCH.
8
7
6
5
+V_SMREF +V_AGTLREF
3 2 MUX_VID0 4 5 CPU_VID0
5 CPU_VR_VID0 A0 C0
1
7 6 MUX_VID1 3 6 CPU_VID1
5 CPU_VR_VID1 A1 C1
1
11 10 MUX_VID2 2 7 CPU_VID2 R126 C223 R64 C389 C388 C400 C443
5 CPU_VR_VID2 A2 C2
17 16 MUX_VID3 1 8 CPU_VID3 49.9_1% .1UF 2K_1% .1UF .1UF .1UF .1UF
5 CPU_VR_VID3 A3 C3
21 20 MUX_VID4
5 CPU_VR_VID4 A4 C4
1R553 0 2 CPU_VID4
2
2
2
18 AC_VID0 4 B0 D0 5
18 AC_VID1 8 B1 D1 9
18 AC_VID2 14 B2 D2 15
18 AC_VID3 18 B3 D3 19
22 23 +5V_SW
18 AC_VID4 B4 D4
PM_SSGMUXSEL = 0 : for low Voltage A-C 1 BE# VCC 24
1 : for high Voltage B-C
1
13 12 C515
17,42 PM_SSMUXSEL BX GND .01UF +1.8V_SW +1.5V_SW
HUB Interface Reference CMOS Reference Voltage
SN74CBT3383
1
+3V_SW
R152 R68 Layout note :
301_1% Layout note : 499_1%
U33
1. Place R81 and R76 between and GMCH and CPU.
2 MUX_VID0 3 2 CPU_VID0 1. Place R123 and R124 in middle of Bus. 2. Place decoupling caps near CPU. 2
A0 C0 CPU_VID0 42
1
1
2
3
4
MUX_VID1 CPU_VID1
2
7 A1 C1 6 CPU_VID1 42 2. Place capacitors near GMCH.
R100 RP2 MUX_VID2 11 10 CPU_VID2 +VS_HUBREF
A2 C2 CPU_VID2 42 +VS_CMOSREF
@8P4R_10K MUX_VID3 17 16 CPU_VID3
A3 C3 CPU_VID3 42
1
@10K MUX_VID4 21 20 CPU_VID4
A4 C4 CPU_VID4 42
1
R159 C256 R65 C430 C423
STRAP_VID0 301_1% .1UF 1K_1% .1UF .1UF
2
8
7
6
5
4 B0 D0 5
STRAP_VID1 8 9
STRAP_VID2 B1 D1
2
14 B2 D2 15
STRAP_VID3
2
18 B3 D3 19
Default for Resistors Should STRAP_VID4 22 23 +5V_SW
B4 D4
be +VCC_CPU = 0.7V, for
1 BE# VCC 24
Deeper Sleep Only.
1
1
1
1
1
1
13 12 C516
17,42 PM_DPRSLPVR BX GND
R101 R103 R102 R107 R108 @.01UF
@0 @0 @0
@SN74CBT3383
@0 @0
2
+1.8V_SW Place Reference Circuit near GMCH
HUB Interface VSwing Voltage +1.5V_SW
2
2
2
2
2
1
C229 1 2 470PF
R435
1
301_1%
R127 R134
1. Place R360 and R361 in middle of 1K_1% 82.5_1%
2
Bus.
+1.5V_SW +3V_ALW +VS_HUBVSWING
2
In-Target Probe +VAGP_CRDREF
1
3 3
1
1
+VTT R438 C643
R328 301_1% .1UF R113 R119
+VTT +VTT 240 +1.5V_SW +VTT 1K_1% 82.5_1%
2
2
1
2
R313
1
1
14 GND BSEN# 13
16 15 R296
GND PREQ0# ITP_PREQ# 5
1
18 17 1 2 576_1%
GND PRDY0# ITP_PRDY# 5
20 19 R43 240
R270 GND PREQ1# R34 510
22 GND PRDY1# 21 1. Place R255 and R253 near GMCH.
39
2
24 GND NC 23 1 2
26 GND NC 25 +VS_RIMMREF
2
28 GND NC 27
1
4 4
R317 R332
2
@10 @10
12
12
C496 C512
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL SCHEMATIC, M/B LA-1012
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE 401200
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date: Friday, October 19, 2001 Sheet 7 of 45
A B C D E
A B C D E
1
1 2
1
+
L52 BLM21A601SPT C626 C289 C288 C287 C286 C313 C314 C315 C316 C615
22UF_1206_10V .01UF .01UF .01UF .01UF .01UF .01UF .01UF .01UF .01UF
2
1 1
14
19
32
37
46
50
1
8
U41
+3V_SW Place Crystal within 500 mils of CK_Titan
VDD_3V66
VDD_3V66
VDD_PCI
VDD_PCI
VDD_CPU
VDD_CPU
VDD_48MHZ
VDD_REF
L50 +3V_SW
+3V_SW BLM21A601SPT
2 1 2 XTAL_IN VDD_CORE 26 1 2
+3V_SW C629 10PF
1
1
caps are internal Y3 +
1
1
to CK_TITAN 14.318MHZ C664 C335
R365 R386 R380 .01UF 22UF_1206_10V
100K 1K
2
1K 2 1 3 27
C647 10PF XTAL_OUT GND_CORE
HOST_CPU R396 2 CLK_BCLK
2
2 45 1 1 2
CPUCLKT2 CLK_HCLK 5
40 0 R9 1 2 33
SEL2
1
SEL1 55 R5 60.4_1%
5 H_BSEL1 SEL1
SEL0 54 Place all these Block's
5,11 H_BSEL0 SEL0 R8
475_1%
Components near CPU (U6)
R6 1 2 60.4_1%
HOST_CPU# R397 CLK_BCLK# R10 1 2 33
2
17,29 PM_SLP_S1# 25 PWR_DWN# CPU_CLKC2 44 1 2 CLK_HCLK# 5
17 PM_STPPCI# 34 PCI_STOP# 0
R403 1 2 0 53 49 GMCH_CPU 1 R394 2 CLK_HT 1 2
17 PM_STPCPU# CPU_STOP# CPUCLKT1 CLK_GHT 9
0 R2781 2 33
1
R282 60.4_1%
2 +12V_SW Place all these Block's 2
+12V_SW 28 R281
5,29 VTT_PWRGD# VTT_PWRGD# Components near GMCH (U23)
1
2
CPUCLKC1 48 1 2 CLK_GHT# 9
R229 R230 R232 R364 1 2 10K 43 0
100K 10K 10K MULT0 CLK_ITP
CPUCLKT0 52 1 2 CLK_ITPP 7
22
Q31 R3181 2 33
G
1
2N7002 R320 60.4_1%
2
Q29 475_1%
G
R3301 2 60.4_1%
CLK_ITP# R3241 2 @33
2
14,17,19 SMB_CLK 1 3 CPUCLKC0 51 CLK_ITPP# 7
33
D
R390 1 2 22 DOT_48M 38
9 CLK_DREF 48MHZ_DOT
18 CB_33M R432 1 2 33
3 PCICLK6 CLK_PCI_CB 23 3
17 AUD_33M R431 1 2 33
PCICLK5 CLK_PCI_AUD 26
16 SIO_33M R430 1 2 33
PCICLK4 CLK_LPC_SIO 31
R400 1 2 33 REF_14M 56 13 1394_33M R429 1 2 33
17 CLK_ICH14 REF PCICLK3 CLK_1394 22
31 CLK_SIO14 1 2 PCICLK2 12
GND_48MHZ
R399 33 11 EC_33M R427 1 2 33 CLK_LPC_EC 29
GND_3V66
GND_3V66 PCICLK1
GND_IREF
GND_CPU
GND_REF
10 MINI_33M R426 1 2 33
GND_PCI
GND_PCI
PCICLK0 CLK_MINIPCI 37
1
C654 C652
1
2
@10PF @10PF
CK_Titan (U31)
2
4 4
Title
Compal Electronics, inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL SCHEMATIC, M/B LA-1012
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE 401200
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date: Friday, October 19, 2001 Sheet 8 of 45
A B C D E
A B C D E
AC5
AH2
AC7
M12
M13
M17
M18
AE2
AB2
N12
N13
N14
N15
N16
N17
N18
R13
R14
R15
R16
R17
U12
U13
U14
U15
U16
U17
U18
P13
P14
P15
P16
P17
V12
V13
V17
V18
T13
T14
T15
T16
T17
AJ5
W2
G2
D2
U5
H5
N2
Y5
P5
K2
T2
L5
H_D#[0..63] U30A H_A#[3..31]
4 H_D#[0..63] H_A#[3..31] 4
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS_H0
VSS_H1
VSS_H2
VSS_H3
VSS_H4
VSS_H5
VSS_H6
VSS_H7
VSS_H8
VSS_H9
VSS_H10
VSS_H11
VSS_H12
VSS_H13
VSS_H14
VSS_H15
VSS_H16
1 1
H_D#0 U4 H2 H_A#3
H_D#1 H_D#0 H_A#3 H_A#4
P1 H_D#1 H_A#4 E3
H_D#2 W6 G3 H_A#5
H_D#3 H_D#2 H_A#5 H_A#6
U2 H_D#3 H_A#6 N4
H_D#4 U6 M6 H_A#7
H_D#5 H_D#4 H_A#7 H_A#8
R1 H_D#5 VSS H_A#8 F1
H_D#6 N3 F2 H_A#9
H_D#7 H_D#6 H_A#9 H_A#10
W5 H_D#7 H_A#10 J3
H_D#8 V4 F3 H_A#11
H_D#9 H_D#8 H_A#11 H_A#12
P3 H_D#9 H_A#12 P6
H_D#10 R3 G1 H_A#13
H_D#11 H_D#10 H_A#13 H_A#14
U1 H_D#11 H_A#14 N5
H_D#12 V6 H1 H_A#15
H_D#13 H_D#12 H_A#15 H_A#16
W4 H_D#13 H_A#16 P4
H_D#14 T3 T4 H_A#17
H_D#15 H_D#14 H_A#17 H_A#18
P2 H_D#15 H_A#18 M2
H_D#16 V3 J2 H_A#19
H_D#17 H_D#16 H_A#19 H_A#20
R2 H_D#17 H_A#20 L2
H_D#18 T1 R4 H_A#21
H_D#19 H_D#18 H_A#21 H_A#22
W3 H_D#19 H_A#22 K1
H_D#20 U3 L3 H_A#23
H_D#21 H_D#20 H_A#23 H_A#24
Y4 H_D#21 H_A#24 L1
H_D#22 AA3 J1 H_A#25
H_D#23 H_D#22 H_A#25 H_A#26
W1 H_D#23 H_A#26 N1
H_D#24 V1 T5 H_A#27
H_D#25 H_D#24 H_A#27 H_A#28
Y1 H_D#25 H_A#28 H3
2 H_D#26 Y6 M3 H_A#29 2
H_D#27 H_D#26 H_A#29 H_A#30
AD3 H_D#27 Host H_A#30 M1
H_D#28 AB4 Interface K3 H_A#31
H_D#29 H_D#28 H_A#31
AB5
H_D#30
H_D#31
H_D#32
V2
Y3
Y2
H_D#29
H_D#30
H_D#31
H_D#32
Host
Interface Almador-M H_CPURST#
H_ADS#
R6
C1
1
R96
2
@0
H_RESETX# 7
H_RESET# 5
H_ADS# 4
H_D#33
H_D#34
H_D#35
AA4
AA1
AA6
H_D#33
H_D#34
H_D#35
GMCH H_BNR#
H_BPRI#
H_DBSY#
E1
L4
G5
H_BNR# 4
H_BPRI# 4
H_DBSY# 5
H_D#36 AB1 J4
H_D#36 H_DEFER# H_DEFER# 4
H_D#37 AC4 F4
H_D#37 H_DRDY# H_DRDY# 5
H_D#38 AA2 D3
H_D#38 H_HIT# H_HIT# 4
H_D#39 AB3 D1
H_D#39 H_HITM# H_HITM# 4
H_D#40 AD2 J6
H_D#40 H_LOCK# H_LOCK# 4
H_D#41 AD1 G4
H_D#41 H_TRDY# H_TRDY# 5
H_D#42 AC2 H_REQ#[0..4]
H_D#42 H_REQ#[0..4] 4
H_D#43 AB6
H_D#44 H_D#43 H_REQ#0
AC6 H_D#44 H_REQ#0 K6
H_D#45 AC1 M4 H_REQ#1
H_D#46 H_D#45 H_REQ#1 H_REQ#2
AF3 H_D#46 H_REQ#2 K5
H_D#47 AD4 K4 H_REQ#3
H_D#48 H_D#47 H_REQ#3 H_REQ#4
AD6 H_D#48 H_REQ#4 L6
H_D#49 AC3 H_RS#[0..2]
H_D#49 H_RS#[0..2] 5
H_D#50 AH3
H_D#51 H_D#50 H_RS#0
AE5 H_D#51 H_RS#0 H6
H_D#52 AE3 H4 H_RS#1
H_D#53 H_D#52 H_RS#1 H_RS#2
AG2 H_D#53 H_RS#2 G6
AGP_RCOMP/DVOBC_RCOMP
H_D#54 AF4
3 H_D#55 H_D#54 3
AF2 H_D#55
H_D#56 AJ3 AJ4
H_D#56 CLK_HT CLK_GHT 8
H_D#57 AE4 AH5
H_D#58 H_D#57 CLK_HT# CLK_GHT# 8
AG1 H_D#58
H_D#59 AE1 H_D#59
VSSPCMOS_LM0
VSSPCMOS_LM1
VSSPCMOS_LM2
H_D#60 AG4 AC19
H_D#60 CLK_DREF CLK_DREF 8
H_GTLRCOMP
H_D#61 AH4 AG26
HUB_PSTRB#
DVO_RCOMP
HUB_RCOMP
H_D#61 CLK_GBIN CLK_GBIN 8
HUB_PSTRB
VSSP_DVO0
VSSP_DVO1
VSSP_DVO2
VSSP_HUB0
VSSP_HUB1
H_GTLREF1
H_GTLREF0
SM_RCOMP
G8 VSSA_CPLL
AD7 VSSA_HPLL
H_D#62 AG3 AD24GBOUT_GMCH 1 2 GBOUT_ISO
VSSA_DAC
CLK_GBOUT 8
HUB_PD10
H_D#62 CLK_GBOUT
VSSP_IO0
VSSP_IO1
VSSP_IO2
HUB_REF
AGP_REF
H_D#63 R60 47
HUB_PD0
HUB_PD1
HUB_PD2
HUB_PD3
HUB_PD4
HUB_PD5
HUB_PD6
HUB_PD7
HUB_PD8
HUB_PD9
AF1 H_D#63
RESET#
C79 .01UF
2
VSS
VSS
R288 R297R298 R82
@33
AC22
AC23
AH19
AH20
AC26
AD22
AH24
AH26
AB24
AB23
AE28
AF25
AF27
@33
AA7
G26
G25
G27
G29
G28
AF5
H28
H29
H27
H26
H24
H25
E29
E28
K24
F29
F27
F28
82830 240K
J23
J25
C2
F6
J7 @33
1
C455 C456 C124
HUB_PD10
HUB_PD0
HUB_PD1
HUB_PD2
HUB_PD3
HUB_PD4
HUB_PD5
HUB_PD6
HUB_PD7
HUB_PD8
HUB_PD9
+VS_HUBREF @10PF
1
1 2 @10PF
R361 80.6_1%
+V_AGTLREF
@10PF
1
17 HUB_PD[0..10]
C532 C527
2
17 HUB_PSTRB
.1UF .1UF
17 HUB_PSTRB#
R81
2
54.9_1%
1
C198
.1UF
+VAGP_CRDREF
Compal Electronics, inc.
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL SCHEMATIC, M/B LA-1012
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE 401200
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date: Friday, October 19, 2001 Sheet 9 of 45
A B C D E
A B C D E
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
AG15
AG16
AG21
AD10
AH21
AH11
AH12
AH14
AH17
AH18
AE10
AE11
AE12
AE13
AE17
AE19
AB28
AE20
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AJ21
W28
AG7
AD8
AD9
AH6
AH8
AH9
AE8
AE9
G24
AF8
AF9
N28
U25
K28
P25
Y25
T28
L25
U30B SM_D_MA[0..12]
SM_D_MA[0..12] 13
VSSP_AGP0
VSSP_AGP1
VSSP_AGP2
VSSP_AGP3
VSSP_AGP4
VSSP_AGP5
VSSP_AGP6
VSSP_AGP7
VSSP_AGP8
VSSA_DPLL0
VSSA_DPLL1
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
VSS_LM
SM_DQ0 D29 A20 SM_D_MA0
SM_DQ1 SM_DQ0 SM_MA0 SM_D_MA1
C29 SM_DQ1 SM_MA1 B20
1 SM_DQ2 D27 B19 SM_D_MA2 1
SM_DQ3 SM_DQ2 SM_MA2 SM_D_MA3
C27 SM_DQ3 SM_MA3 C19
SM_DQ4 A27 A18 SM_D_MA4
SM_DQ5 SM_DQ4 SM_MA4 SM_D_MA5
B26 SM_DQ5 VSS SM_MA5 A19
SM_DQ6 E24 C17 SM_D_MA6
SM_DQ7 SM_DQ6 SM_MA6 SM_D_MA7
C25 SM_DQ7 SM_MA7 C18
SM_DQ8 E23 B17 SM_D_MA8
SM_DQ9 SM_DQ8 SM_MA8 SM_D_MA9
B25 SM_DQ9 SM_MA9 A17
SM_DQ10 C23 A16 SM_D_MA10
SM_DQ11 SM_DQ10 SM_MA10 SM_D_MA11
F22 SM_DQ11 SM_MA11 C15
SM_DQ12 B23 C14 SM_D_MA12
SM_DQ13 SM_DQ12 SM_MA12
C22 SM_DQ13
SM_DQ14 E21
SM_DQ15 SM_DQ14
B22 SM_DQ15 NC F20
SM_DQ16 C12 E20
SM_DQ17 SM_DQ16 NC
D10 SM_DQ17 NC F12
SM_DQ18 C11 E11
SM_DQ19 SM_DQ18 NC +3V
A10 SM_DQ19 VSS C21
SM_DQ20 C10 F19
SM_DQ21 SM_DQ20 VSS
C8 SM_DQ21 VCC_SM E12
SM_DQ22 A7 A12
SM_DQ23 SM_DQ22 VCC_SM C248 1
E9 SM_DQ23 2 .1UF
SM_DQ24 C7
SM_DQ25 SM_DQ24
E8 SM_DQ25 SM_BA0 B16 SM_BA0 14
SM_DQ26 A5 C16
SM_DQ26 SM_BA1 SM_BA1 14
SM_DQ27 F8 SM_DQ27 SM_DQM[0..7] 14
SM_DQ28 C5
SM_DQ29 SM_DQ28 SM_DQM0
D6 F18
2
SM_DQ30
SM_DQ31
SM_DQ32
B4
C4
E27
SM_DQ29
SM_DQ30
SM_DQ31
SM_DQ32
SDRAM
System Almador-M SDRAM
System
SM_DQM0
SM_DQM1
SM_DQM2
SM_DQM3
D18
D13
D12
SM_DQM1
SM_DQM2
SM_DQM3
2
SM_DQ33
SM_DQ34
SM_DQ35
C28
B28
E26
SM_DQ33
SM_DQ34
SM_DQ35
Memory
GMCH Memory SM_DQM4
SM_DQM5
SM_DQM6
E18
F17
F14
SM_DQM4
SM_DQM5
SM_DQM6
SM_DQ36 C26 F13 SM_DQM7
SM_DQ37 SM_DQ36 SM_DQM7
D25 SM_DQ37
SM_DQ38 A26
SM_DQ39 SM_DQ38 SM_CS#0
D24 SM_DQ39 SM_CS#0 E17 SM_CS#0 14
SM_DQ40 F23 F16 SM_CS#1
SM_DQ40 SM_CS#1 SM_CS#1 14
SM_DQ41 A25 D16 SM_CS#2
SM_DQ41 SM_CS#2 SM_CS#2 14
SM_DQ42 G22 D15 SM_CS#3
SM_DQ42 SM_CS#3 SM_CS#3 14
SM_DQ43 D22 E15 +3V
SM_DQ44 SM_DQ43 VCCQ_SM
A23 SM_DQ44 VSS E14
SM_DQ45 F21
SM_DQ46 SM_DQ45
D21 SM_DQ46
SM_DQ47 A22 A15 SM_D_CLK0
SM_DQ48 SM_DQ47 SM_CLK0 SM_D_CLK1
F11 SM_DQ48 SM_CLK1 B2
SM_DQ49 A11 B14 SM_D_CLK2
SM_DQ50 SM_DQ49 SM_CLK2 SM_D_CLK3
B11 SM_DQ50 SM_CLK3 A3
SM_DQ51 F10 A14
SM_DQ52 SM_DQ51 VSS
B10 SM_DQ52 VSS C3
SM_DQ53 B8
SM_DQ54 SM_DQ53
D9 SM_DQ54
SM_DQ55 B7 A13 SM_CKE0
SM_DQ55 SM_CKE0 SM_CKE0 14
SM_DQ56 F9 C9 SM_CKE1
SM_DQ56 SM_CKE1 SM_CKE1 14
SM_DQ57 A6 C13 SM_CKE2
SM_DQ57 SM_CKE2 SM_CKE2 14
SM_DQ58 C6 A9 SM_CKE3
SM_DQ58 SM_CKE3 SM_CKE3 14
SM_DQ59 D7 VSS Power B13
3 SM_DQ60 SM_DQ59 VSS 3
B5 SM_DQ60 VCC_SM A8
SM_DQ61 E6 C253 1 2 .1UF
SM_DQ61
VSSP_SM10
VSSP_SM11
VSSP_SM12
VSSP_SM13
VSSP_SM14
VSSP_SM15
VSSP_SM16
VSSP_SM17
VSSP_SM18
VSSP_SM19
SM_DQ62 A4
SM_VREF1
SM_VREF0
VSSP_SM0
VSSP_SM1
VSSP_SM2
VSSP_SM3
VSSP_SM4
VSSP_SM5
VSSP_SM6
VSSP_SM7
VSSP_SM8
VSSP_SM9
SM_DQ62 +3V
SM_OCLK
SM_RCLK
SM_CAS#
SM_RAS#
SM_DQ63 D4
SM_WE#
SM_DQ63
Layout note :
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
M14
M15
M16
AB7
G21
D28
H23
R12
R18
C24
D19
C20
B12
B15
B18
B21
B24
B27
E10
E13
E16
E19
E22
E25
K23
P24
V24
Y23
P12
P18
A24
A21
T24
T12
T18
F24
82830
W7
G9
H7
N6
E7
E4
K7
Y7
E5
T6
L7
SM_DQ[0..63] die.
SM_DQ[0..63] 14
GMCH_RAS# R150 1 2 10
SM_RAS# 14
GMCH_CAS# R149 1 2 10
SM_CAS# 14
GMCH_WE# R151 1 2 10
+VTT SM_WE# 14
SM_OCLK
+V_SMREF
1
C230 C217
1
Layout note :
2
1
C96 C95 2 1
+1.8V_SW C103 .1UF +3V L17 .1UH_0805 DVOA_D5 Desktop Mobile
Layout note : 2 1 .01UF .1UF
1
+VTT +3V +1.8V_SW
VCCA_DAC
C92 C93 DVOA_D6 Dual Ended Term Single Ended Term
+VCCA_DPLL0
+VCCA_DPLL1
Place close to AE16, 2 1 + +1.5V_SW
1
C205 .1UF +VTT C227 .1UF
VCCA_PLL
AE15 of GMCH C210 100UF_D2_6.3V
2
+
+1.5V_SW .1UF R289 1 2 @2.2K DVOA_D6
2
100UF_D2_6.3V R290 1 2 2.2K DVOA_D5
2
1 1
1
C127 R292 1 2 @2.2K DVOA_D1
R59
AG27
AD15
AD16
AD23
AC20
AC21
AE16
AE15
AE25
AA26
AA23
AF26
AF21
AF24
68PF R293 1 2 10K DVOA_D0 1 2
W23
AG5
AC9
AC8
AD5
M26
AE6
AE7
AA5
G10
G20
N24
R26
U24
AF6
V14
V15
V16
V26
F26
F25
H_BSEL0 5,8
L23
J24
J26
M5
G7
R5
V5
E2
F5
J5
U30C 680
VCCP_IO
VCCP_IO
VDD_LM
VDD_LM
VDD_LM
VDD_LM
VDD_LM
VDD_LM
VDD_LM
VCCQ_SM
VCCQ_SM
VCCPCMOS_LM
VCCPCMOS_LM
VCCPCMOS_LM
VCCPCMOS_LM
VCCP_DVO
VCCP_DVO
VCCP_DVO
VCCA_DPLL0
VCCA_DPLL1
VCCA_HPLL
VCCA_CPLL
VCCP_HUB
VCCP_HUB
VCCQ_AGP
VCCQ_AGP
VCCP_AGP
VCCP_AGP
VCCP_AGP
VCCP_AGP
VCCP_AGP
VCCP_AGP
VCCP_AGP
VCCP_AGP
VCCA_DAC
VCCA_DAC
VCC_H
VCC_H
VCC_H
VCC_H
VCC_H
VCC_H
VCC_H
VCC_H
VCC_H
Place R8, R234, R278
AA29 AGP_SBA0/ZV_D8 AE29 DAC_VSYNC DAC_VSYNC 16,36 near VGA Connector.
DAC_VSYNC
AA24 AD28 DAC_HSYNC DAC_HSYNC 16,36
AGP_SBA1/ZV_D7 DAC_HSYNC
AA25 AF28 DAC_RED# R72 1 2 37.4_1%
AGP_SBA2/ZV_D6 DAC_RED#
Y24 AG28 DAC_GREEN# R63 1 2 37.4_1%
AGP_PAR : Strapping option AGP_SBA3/ZV_D5 DAC_GREEN#
Y27 AH27 DAC_BLUE# R61 1 2 37.4_1%
AGP_SBA4/ZV_D2 DAC_BLUE#
for SW detection of AGP or Y26 AF29 DAC_RED 16,36
AGP_SBA5/ZV_D1 DAC_RED
DVO device. W24
AGP_SBA6/ZV_D0 Power DAC_GREEN
AG29 DAC_GREEN 16,36
0 -> DVO B/C device Y28
AGP_SBA7/ZV_HREF Interface DAC_BLUE
AH28 DAC_BLUE 16,36
AE27 IO_DDC1CLK 16
1 -> AGP device IO_DDC1CLK
AD27 IO_DDC1DATA 16
IO_DDC1DATA R53 1
L27 AJ27 2 255_1%
AGP_CBE#0/DVOB_D7 DAC_REFSET
P29
AGP_CBE#1/DVOB_BLANK#
R27
DVOC_D5 AGP_CBE#2/ZV_VSYNC DVOA_CLKINT DAC_VSYNC
T25 AD20
AGP_CBE#3/DVOC_D5 DVO_CLKIN
AD21
DVO_BLANK# DVOA_BLANK# 15
AF23
DVO_VSYNC DVOA_VSYNC 15 DAC_HSYNC
L29 AF22
AGP_ADSTB0/DVOB_CLK DVO_HSYNC DVOA_HSYNC 15
1
L28 AD25 DVOA_I2CCLK
AGP_ADSTB#0/DVOB_CLK# IO_I2CCLK DVOA_I2CCLK 15
1
R307 1 2 22 DVCCLK U29 AC25 DVOA_I2CDATA C764
15 DVOC_CLK AGP_ADSTB1/DVOC_CLK IO_I2CDATA DVOA_I2CDATA 15
R310 1 2 22 DVCCLK# U28 AG24 DVCLK# R50 1 2 22 C765 10PF
15 DVOC_CLK# AGP_ADSTB#1/DVOC_CLK# DVO_CLK# R52 DVOA_CLK# 15
DVCLK 2 22 10PF
2
AA27 AJ24 1
+1.5V_SW AGP_SBSTB/ZV_D4 DVO_CLK DVOA_CLK 15
2
AA28
M_DDC1_DATA AGP_SBSTB#/ZV_D3 RP13 16P8R_22
R29 DVOA_D[0..11] 15
AGP_FRAME#/M_DDC1_DATA DVOD0 1
1 2 M_I2CCLK P26 AJ22 16 DVOA_D0
2
R369 100K AGP_IRDY#/M_I2C_CLK DVO_D0 DVOD1 2 2
M_DDC1_CLK P27 Display AH22 15 DVOA_D1
AGP_TRDY#/M_DDC1_CLK DVO_D1 DVOD2 3
M_DDC2_DATA N25 Interface AG22 14 DVOA_D2
M_I2CDATA AGP_STOP#/M_DDC2_DATA DVO_D2 DVOD3 4
1 2 R28 AJ23 13 DVOA_D3
R363 100K AGP_DEVSEL#/M_I2C_DATA DVO_D3 DVOD4 5
AC27 (DVOA port) AH23 12 DVOA_D4
AGP_REQ#/ZV_CLK DVO_D4 DVOD5 6
AD29 AGP AG23 11 DVOA_D5
AGP_PAR AGP_GNT#/ZV_D15 DVO_D5 DVOD6 7
2 1 P28 Interface AE23 10 DVOA_D6
R104 330
J29
AGP_PAR
AGP_AD0/DVOB_HSYNC
(DVOB/DVOC & ZV port) Almador-M DVO_D6
DVO_D7
DVO_D8
DVO_D9
AE24
AJ25
AH25
DVOD7 8
DVOD8 4
DVOD9 3
9
5
6
DVOA_D7
DVOA_D8
DVOA_D9
J28
K26
K25
AGP_AD1/DVOB_VSYNC
AGP_AD2/DVOB_D1
AGP_AD3/DVOB_D0
GMCH DVO_D10
DVO_D11
AG25
AJ26
DVOD10 2
DVOD11 1
7
8
DVOA_D10
DVOA_D11
1
L24 C756
AGP_AD10/DVOB_D8
1
M27 AG17 R46 C757
AGP_AD11/DVOB_D11 LM_DQA0 @33 27PF
N29 AJ17
15 DVOC_FLD AGP_AD12/DVOB_D10 LM_DQA1 27PF +3V_SW
2
M25 AG18
AGP_AD13/DVOBC_CLKINT# LM_DQA2
2
2 1 N26 AJ18 R91 10K
R90 100K M_DDC2_CLK AGP_AD14/DVOB_FLD/STL LM_DQA3 DVOA_I2CDATA1
1
N27 AG19 2
AGP_AD15/M_DDC2_CLK LM_DQA4 C77
15 DVOC_VSYNC R25
AGP_AD16/DVOC_VSYNC Local Memory LM_DQA5
AJ19
R24 AG20 @10PF DVOA_I2CCLK 1 2
15 DVOC_HSYNC AGP_AD17/DVOC_HSYNC Interface LM_DQA6 R89 10K
T29 AJ20
DVOC_D0 AGP_AD18/DVOC_BLANK# LM_DQA7
T27
DVOC_D1 AGP_AD19/DVOC_D0 +1.5V_SW
T26
DVOC_D2 AGP_AD20/DVOC_D1
U27 AJ11 R56 100K
DVOC_D3 AGP_AD21/DVOC_D2 LM_DQB0 +3V_SW DVOA_CLKINT 1
V27 AH10 2
3 DVOC_D4 AGP_AD22/DVOC_D3 LM_DQB1 3
15 DVOC_D[0..11] V28 AJ10
DVOC_D7 AGP_AD23/DVOC_D4 LM_DQB2 DVO_INTR#
U26 AG10 1 2
DVOC_D6 AGP_AD24/DVOC_D7 LM_DQB3 R57 100K
V29
AGP_AD25/DVOC_D6 Local Memory LM_DQB4
AJ9
1
DVOC_D9 W29 AG9
AGP_AD26/DVOC_D9 Interface LM_DQB5
AGP_PIPE#/ZV_D10
AGP_RBF#/ZV_D11
AGP_AD27/DVOC_D8 LM_DQB6
AC28AGP_ST0/ZV_D14
AGP_ST1/ZV_D13
AGP_ST2/ZV_D12
VCCP_SM
VCCP_SM
VCCP_SM
VCCP_SM
VCCP_SM
VCCP_SM
VCCP_SM
VCCP_SM
VCCP_SM
VCCP_SM
VCCP_SM
VCCP_SM
VCCP_SM
2
LM_CTM#
LM_CFM#
LM_GCLK
LM_RCLK
1 2 Y29 AC24
LM_CMD
AGP_BUSY# AGP_BUSY# 17
AH15LM_CTM
LM_CFM
AGP_AD31/DVOC_FLD/STL
VCC_LM
VCC_LM
VCC_LM
VCC_LM
VCC_LM
VCC_LM
VCC_LM
VCC_LM
VCC_LM
LM_SCK
LM_RQ0
LM_RQ1
LM_RQ2
LM_RQ3
LM_RQ4
LM_RQ5
LM_RQ6
LM_RQ7
LM_SIO
TV_I2CCLK 1 2
R555 4.7K
AG11
AG12
AG13
AG14
AC29
AH13
AD14
AH16
AC10
AC11
AD11
AD12
AD13
AD17
AD18
AD19
AB26
AB29
AB25
AB27
AE14
AE18
AJ12
AJ13
AJ14
AJ15
AJ16
AG6
AH7
G11
G19
G23
AF7
D11
D14
D17
D20
D23
D26
AJ7
AJ6
F15
+1.5V_SW 82830
D5
D8
F7
+1.8V_SW
M_DDC2_CLK 4 5
M_DDC2_DATA 3 6
1
M_DDC1_CLK 2 7 +3V
M_DDC1_DATA 1 8 C108
68PF
RP36 8P4R_100K
2
+3V_SW
U60 R295 1 2 10K
1
NC
1.5V level clock R55 1 2 10K
VCC 5
17,23,24 RTCCLK 2
A DPMS_CLK
4
Y 4 2 1 4
3 R568
GND
2
732_1%_0603 +VS_RIMMREF
NC7S14
R569 VS_RIMMREF 1 2
604_1%_0603 R294 100_1%_0603
1
1
1
C454
.1UF
C452
.1UF Title
Compal Electronics, inc.
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL SCHEMATIC, M/B LA-1012
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE 401200
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date: Friday, October 19, 2001 Sheet 11 of 45
A B C D E
A B C D E
+1.8V_SW
+VTT
1 1
1
1
1
+ C74 C224 C120 C121 C122
C100 C87 C537 C547 C84 C142 C132 C106 C114 C136 22UF_1206_10V .1UF .1UF .01UF .01UF
.1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF
2
2
2
+VTT
Layout note :
1
1
Distribute as close as possible
C109 C86 C89 C111 C113 C88 C85 C112 C151 C148
.1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF
to GMCH Local Memory Quadrant .
2
2
+1.8V_SW
+VTT
1
1
1
+
+ C65 + C414 + C212 C133 C82 C135 C131 C137 C118 C197
150UF_D2_6.3V 150UF_D2_6.3V 150UF_D2_6.3V 82PF 22UF_1206_10V .1UF .1UF 82PF .1UF .1UF
2
2
2 +VTT 2
Layout note :
Distribute as close as possible
1
1
+ C211
150UF_D2_6.3V C128 C115 C116 C117 C143 C147 C154 C161 C174 C183
.1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF
+1.5V_SW
2
2
+VTT
1
+
C165 C97 C157 C168 C123 C141 C193 C175 C126 C185 C181 C125 C180 C186
1
.1UF .1UF 82PF .1UF .1UF 82PF .1UF .1UF 82PF .1UF .1UF 82PF .1UF
1
1
C64
2
+
150UF_D2_6.3V C192 C194 C199 C204 C94 C172 C162 C155 C140 C139 22UF_1206_10V
.1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF
2
2
+VTT
Layout note :
Distribute as close as possible
to GMCH System Memory Quadrant .
1
+ C50
150UF_D2_6.3V C138 C153 C159 C171 C190 C189 C188 C110 C134 C146 +3V
3 .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF 3
2
1
+VTT +
C221 C202 C203 C201 C214 C236 C213 C240 C209 C208 C220 C239 C215 C238 C244 C237 C242
22UF_1206_10V .1UF .1UF 82PF .1UF .1UF 82PF .1UF .1UF 82PF .1UF .1UF 82PF .1UF .1UF .1UF .1UF
2
1
C156 C173 C184 C195 C206 C187 C191 C130 C145 C226
.1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF
2
Layout note :
Distribute as close as possible
+VTT
to IO Quadrant .
1
+3V
+ C66 + C49 + C67 + C415
150UF_D2_6.3V 150UF_D2_6.3V 150UF_D2_6.3V 150UF_D2_6.3V
1
1
2
2
2
4 4
Title
Compal Electronics, inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1012
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Custom 401200 1B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date: Friday, October 19, 2001 Sheet 12 of 45
A B C D E
A B C D E
Layout note :
1 1
One .1uF cap per power pin .
Place each cap close to SODIMM(DIMM 0) pin .
+3V
1
C462 C465 C475 C491 C566 C579 C592 C602 C494 C613 C598 C584 C556 C528 C540 C492 C479 C464
.1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF
2
10 SM_D_MA[0..12] SM_MA[0..12] 14
+3V
RP3
1
SM_D_MA3 1 8 SM_MA3
SM_D_MA2 2 7 SM_MA2 + C417
SM_D_MA1 3 6 SM_MA1 22UF_1206_10V
SM_D_MA0 4 5 SM_MA0
2
8P4R_10
RP5
SM_D_MA5 1 8 SM_MA5
2 SM_D_MA4 2 7 SM_MA4 2
SM_D_MA7 3 6 SM_MA7
SM_D_MA6 4 5 SM_MA6
Layout note :
8P4R_10
RP4 One .1uF cap per power pin .
SM_D_MA9 1 8 SM_MA9
SM_D_MA8 SM_MA8
Place each cap close to SODIMM(DIMM 1) pin .
2 7
SM_D_MA10 3 6 SM_MA10
SM_D_MA11 4 5 SM_MA11
8P4R_10 +3V
SM_D_MA12 1 2 SM_MA12
R147 10
1
C461 C489 C521 C574 C586 C593 C606 C481 C495 C543 C553 C591 C601 C619 C611 C575 C467 C470
.1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF
2
+3V
1
+ C416
22UF_1206_10V
3 3
4 4
Title
Compal Electronics, inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1012
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Custom 401200 1B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date: Friday, October 19, 2001 Sheet 13 of 45
A B C D E
A B C D E
SM_DQ[0..63] 10
+3V +3V +3V +3V
JP28 JP29
1 2 1 2
SM_DQ0 VSS VSS SM_DQ32 SM_DQ0 VSS VSS SM_DQ32
3 DQ0 4 3 DQ0 4
SM_DQ1 DQ32 SM_DQ33 SM_DQ1 DQ32 SM_DQ33
5 6 5 6
SM_DQ2 DQ1 DQ33 SM_DQ34 SM_DQ2 DQ1 DQ33 SM_DQ34
7 8 7 8
SM_DQ3 DQ2 DQ34 SM_DQ35 SM_DQ3 DQ2 DQ34 SM_DQ35
9 10 9 10
DQ3 DQ35 DQ3 DQ35
11 12 11 12
SM_DQ4 VCC VCC SM_DQ36 SM_DQ4 VCC VCC SM_DQ36
13 14 13 14
SM_DQ5 DQ4 DQ36 SM_DQ37 SM_DQ5 DQ4 DQ36 SM_DQ37
15 16 15 16
SM_DQ6 DQ5 DQ37 SM_DQ38 SM_DQ6 DQ5 DQ37 SM_DQ38
17 18 17 18
SM_DQ7 DQ6 DQ38 SM_DQ39 SM_DQ7 DQ6 DQ38 SM_DQ39
1 19 20 19 20 1
DQ7 DQ39 DQ7 DQ39
21 22 21 22
SM_DQM0 VSS VSS SM_DQM4 SM_DQM0 VSS VSS SM_DQM4
10 SM_DQM0 23 24 23 24
SM_DQM1 CKE0#DQMB0 DQMB4/CE4# SM_DQM5 SM_DQM4 10 SM_DQM1 CKE0#DQMB0 DQMB4/CE4# SM_DQM5
10 SM_DQM1 25 26 25 26
CKE1#/DQMB1 DQMB5/CE5# SM_DQM5 10 CKE1#/DQMB1 DQMB5/CE5#
27 28 27 28
SM_MA0 VCC VCC SM_MA3 SM_MA0 VCC VCC SM_MA3
13 SM_MA0 29 30 SM_MA3 13 29 30
SM_MA1 A0 A3 SM_MA4 SM_MA1 A0 A3 SM_MA4
13 SM_MA1 31 32 SM_MA4 13 31 32
SM_MA2 A1 A4 SM_MA5 SM_MA2 A1 A4 SM_MA5
13 SM_MA2 33 34 SM_MA5 13 33 34
A2 A5 A2 A5
35 36 35 36
SM_DQ8 VSS VSS SM_DQ40 SM_DQ8 VSS VSS SM_DQ40
37 38 37 38
SM_DQ9 DQ8 DQ40 SM_DQ41 SM_DQ9 DQ8 DQ40 SM_DQ41
39 40 39 40
SM_DQ10 DQ9 DQ41 SM_DQ42 SM_DQ10 DQ9 DQ41 SM_DQ42
41 42 41 42
SM_DQ11 DQ10 DQ42 SM_DQ43 SM_DQ11 DQ10 DQ42 SM_DQ43
43 44 43 44
DQ11 DQ43 DQ11 DQ43
45 46 45 46
SM_DQ12 VCC VCC SM_DQ44 SM_DQ12 VCC VCC SM_DQ44
47 48 47 48
SM_DQ13 DQ12 DQ44 SM_DQ45 SM_DQ13 DQ12 DQ44 SM_DQ45
49 50 49 50
SM_DQ14 DQ13 DQ45 SM_DQ46 SM_DQ14 DQ13 DQ45 SM_DQ46
51 52 51 52
SM_DQ15 DQ14 DQ46 SM_DQ47 SM_DQ15 DQ14 DQ46 SM_DQ47
53 54 53 54
DQ15 DQ47 DQ15 DQ47
55 56 55 56
VSS VSS VSS VSS
57 58 57 58
RFU/DQ64 DQ68/RFU RFU/DQ64 DQ68/RFU
59 60 59 60
RFU/DQ65 DQ69/RFU RFU/DQ65 DQ69/RFU
DIMM0 +3V
+3V DIMM1
+12V_SW
8
7
6
5
1
R551 8P4R_10K
2
U17
16
D45 6 1 SODIMM0_SMCLK 10 10 10 10
VCC
INH X0 SODIMM1_SMCLK
17 SM_SEL0 1 2 10 5
A X1
2
G
Q24 2N7002
12
12
12
12
9 2
B X2 C533 C559 C511 C546
4
RB751V X3
8,17,19 SMB_CLK 1 3
3 10PF 10PF 10PF 10PF
D
X SODIMM0_SMDAT
2
2
12
Y0 SODIMM1_SMDAT
13 14
Y Y1
1 3 15
D
GND
GND
8,17,19 SMB_DATA Y2
11
Q22 2N7002 Y3
74HC4052
G
2
7
8
4 4
R194
100K
B A Output
0 0 X0, Y0
0 1 X1, Y1
Title
Compal Electronics, inc.
1 0 X2, Y2 System SMBus Selector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1012
1 1 X3, Y3 AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Custom 401200 1B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date: Friday, October 19, 2001 Sheet 14 of 45
A B C D E
5 4 3 2 1
+3V_SW
+1.8V_SW
1
C441
1
C447 +12V_ALW +LCDVDD
1
10UF_10V_1206 .1UF L44 + +3V
C442 C450 C451 +LCDVDD
2
L0805 22UF_1206_10V .1UF 1000PF SI2302DS
+12V_ALW R32
2
3 1
1
+3V_SW +1.8V_SW 100K
1
1.8VS_VCH R26
Q35 + C418 C419
100
1
R302 10K R31 C420 .1UF 1000PF
2
C448 100K 22UF_1206_10V
2
2 1
.1UF C421
2
Q11 1 R33 C409 C405 +
2
1
M14
M13
G11
G14
G13
G12
D10
H11
N13
C10
H14
H13
H12
A13
E11
K11
K14
K13
K12
F11
F14
L10
L14
L13
L12
J11
J14
J13
J12
D D
G4
C9
D4
D6
D9
H4
C6
C5
D5
C7
A2
E4
K4
E8
+
F4
L6
L5
L7
L8
L9
2 2
J4
U28 +1.8V_SW 3 3
Q10 150K 4.7UF_16V_1206
TV_DATA0
TV_DATA1
TV_DATA2
TV_DATA3
TV_DATA4
TV_DATA5
TV_DATA6
TV_DATA7
TV_DATA8
TV_DATA9
TV_DATA10
TV_DATA11
TV_BLANK#
VCC_3V1
VCC_3V2
VCC_3V3
VCC3_3V4
VCC3_3V5
VCC3_3V6
VCC3_3V7
VCC3_3V8
VCC3_3V9
VCC3_3V10
VCC3_3V11
VCC3_3V12
VCC3_3V13
VCC3_3V14
VCC1_8V16
VCC1_8V1
VCC1_8V2
VCC1_8V3
VCC1_8V5
VCC1_8V7
VCC1_8V6
VCC1_8V8
VCC1_8V9
VCC1_8V10
VCC1_8V11
VCC1_8V12
VCC1_8V13
VCC1_8V14
VCC1_8V15
TV_VSYNC
TV_HSYNC
TV_CLKOUT#
TV_CLKIN
TV_CLKOUT
VCCA
VCCBA
VCCDA
2N7002 2N7002
D8 VCH_VREFHI 2R279 1 150
11 DVOA_D[0..11] VREF_HI
1
DVOA_D0 M11 D7 VCH_VREFLO 1 2 150
DVOA_D1 DVODATA0 VREF_LO R283
P10
DVOA_D2 DVODATA1
N10
DVOA_D3 DVODATA2 4.7UF_16V_1206
M10 E3
DVOA_D4 DVODATA3 P0 ENVDD 22K Q12 @1000PF
P9 E2 2
DVOA_D5 DVODATA4 P1
M9 E1
DVOA_D6 DVODATA5 P2 DTC124EK
P8 F3
DVOA_D7 DVODATA6 P3 22K
P7 F2
DVOA_D8 DVODATA7 P4
N7 F1
DVOA_D9 DVODATA8 P5
3
11 DVOA_STALL M7 G3
DVOA_D10 DVODATA9 P6
P6 G2
DVOA_D11 DVODATA10 P7
N6 G1
DVODATA11 P8
H3
P9
11 DVOA_CLK M8 H2
CLKIN P10
11 DVOA_CLK# N8 H1
CLKIN# P11 +3V_SW
11 DVOA_BLANK# N11 J3
R322 15_1%P12 BLANK# P12
2 1 J2
DVOA_HSYNC CLKOUT P13
11 DVOA_HSYNC P11 J1
1
E14 L1 1 2 DISPOFF# 33
+3V_SW GPIO7 P20 29 BKOFF#
F12 M3
PID3 GPIO6 P21
E13 M2
PID2 GPIO5 P22 D19 LCDVDD
E12 M1 RB751V
PID1 GPIO4 P23
C13 N1
PID0 GPIO3 P24 ENBLT 1
B13 N2 2
GPIO2 P25 29 ENBLT
C14 P2
GPIO1 P26 C395
C12 N3
GPIO0 P27
2
P3 C53 C54 +
P28
C M4 C
P29 1000PF .1UF 10UF_10V_1206
11 DVOA_I2CDATA D13 N4
I2C_DATA P30
1
11 DVOA_I2CCLK D12 P4
I2C_CLK P31
M5
+1.8V_SW R326 36.5_1% P32
N5
P33
1 2 N9 P5
R299 2 DVOrCOMP P34
1 2.2K B14 M6
TESTIN P35 L53 @0_0805
C1 1 2
FLM
9,17,21,22,23,26,29,31,37 PCI_RST# D14 B2
PCIRST# LP L13 JP10
D2
DE LCDVDD TXOUT2-
D3 +LCDVDD 1 2 1 11
SHFCLK FBM-l11-201209-221LMAT 1 11 TXOUT2+
8 CLK_VCH M12 2 12
OSC ENBLT 2 12
C2 3 13
ENABKL ENVDD 3 13 TXCLK0-
C3 4 14
ENAVDD ENEXBUF TXOUT0- 4 14 TXCLK0+
D1 1 5 15
DVOA_CLK ENEXBUF TP1 TXOUT0+ 5 15
6 16
CLKAM
CLKBM
C8 VSSDA
C11 VSSBA
CLKAP
CLKBP
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS40
VSS38
VSS39
VSS41
VSS42
VSS43
VSS44
6 16
YA0M
YA1M
YA2M
YA3M
YA4M
YA5M
YA6M
YA7M
L11 VSSA
VSS1
VSS2
VSS3
VSS4
VSS7
VSS8
VSS9
VSS5
VSS6
YA0P
YA1P
YA2P
YA3P
YA4P
YA5P
YA6P
YA7P
DVOA_CLK# TP 7 17
TXOUT1- 7 17
8 18
8 18
2
TXOUT1+ 9 19
9 19
G10
D11
H10
N14
A14
E10
K10
P14
A10
B10
A11
B11
A12
B12
F10
R51 R49
J10
10 20
G5
G6
G7
G8
G9
C4
H5
H6
H7
H8
H9
A1
B1
E5
E6
E7
E9
K5
K6
K7
K8
K9
P1
A3
B3
A4
B4
A5
B5
A7
B7
A6
B6
A8
B8
A9
B9
F5
F6
F7
F8
F9
L4
J5
J6
J7
J8
J9
@33 @33 10 20
82807
JST BM20B-SRDS
TXOUT0+
TXOUT1+
TXOUT2+
TXOUT5+
TXOUT6+
TXOUT4+
TXCLK0+
TXCLK1+
TXOUT0-
TXOUT1-
TXOUT2-
TXOUT4-
TXOUT5-
TXOUT6-
TXCLK0-
TXCLK1-
1
C78 C80
@10PF @10PF
+3V_SW JP11
LCDVDD 1 16 TXOUT2-
1 16 TXOUT2+
2 17
+1.5V_SW 2 17
3 18
3 18
1
2
3
4
CLK_VCH 4 19 TXCLK0-
11 DVOC_D[0..11] 4 19
RP15 TXOUT0- 5 20 TXCLK0+
2
TXOUT0+ 5 20
6 21
6 21
1
12 9 24
2K_1% SW1 DVOC_D9 D10 R5341 9 24
11 35 2 @75_1% 10 25
PID3 DVOC_D8 D9 DS/BCO TXOUT5- 10 25 TXOUT6-
1
4 5 10 COMPS 16,36 11 26
C330 LCD_VREF PID2 DVOC_D7 D8 R5351 11 26
2 75_1% TXOUT5+ TXOUT6+
2
3 6 9 17 12 27
D7 CSYNC 12 27
1
@10PF PID1 2 7 DVOC_D6 7 13 28
D6 13 28
1
2
1 21
DVOC_D0 D1 C
2
44
+1.8V_SW D0 +3V_SW
41
11 DVOC_CLK# XCLK*
11 DVOC_CLK 40 5
XCLK DVDD[0]
16
DVDD[1]
30
DVDD[2]
1
1
C486 C562
C499 C498 C476 C473 R351 2 1 0 SL_STALL 37 8 C541 C570 C510
11 DVOC_FLD POUT DGND[0]
10UF_10V_1206 .1UF .1UF .1UF .1UF 18 1000PF .1UF .1UF 10UF_10V_1206
DGND[1]
1
2
2
11 DVOC_HSYNC 42 28
R353 H DGND[2] +1.5V_SW
11 DVOC_VSYNC 43
V
@75_1% PCI_RST# 29 38
+3V_SW RESET* DVDD2
36
DGND[3]
1
1
C545
2
11 TV_DDCDATA 26
C446 C478 C445 C474 SD C542
11 TV_DDCCLK 27
.1UF .1UF .1UF .1UF SC .1UF 10UF_10V_1206
31
AVDD
2
2
15 34
R336 1 GPIO[1] AGND
2 100K 14 +5V_SW
GPIO[0]
2
1 2 25 +5V_SW
+3V_SW 17 PAL/NTSC# VDD
R337 19
D46 RB751V R362 2 GND[0]
1 360_1% 24 23
ISET GND[1]
1
100K
1
C567 C573 C577
1
XI/FIN
XO
A + 39 A
C485 C463 C497 +1.5V_SW VREF
2
22UF_1206_10V .1UF 1000PF DVOC_CLK CH7007
33
32
DVOC_CLK#
2
Y2
1
10K
1
CRTVCC
CRT Connector
D47
2 1
+5V_SW
F1
RB491D
POLYSWITCH_0.5A
1 1
1
D1 D16 D15 +1.8V_SW C5 Q60
DAN217 DAN217 DAN217 .1UF
2
2N7002
1
1 3 5VDDCDA
S
1
C16 2N7002 Q61
.1UF
G
5VDDCCL
2
1 3
S
2
3
6
G
L7 JP2
2
30,36 M_SEN# 11
DAC_RED 1 2 DAC_R 1
11,36 DAC_RED
FCM2012C-800(0805) 7
L35 12 CRTGATE
DAC_GREEN 1 2 DAC_G 2
11,36 DAC_GREEN
FCM2012C-800(0805) 8
L36 13
DAC_BLUE 1 2 DAC_B 3
11,36 DAC_BLUE
FCM2012C-800(0805) 9
1
R256 R4 14
1
R250 C360 C18 4
C365 75_1% C8 C357 C361 10
75_1% 18PF 75_1% 18PF 18PF 18PF_0603 18PF_0603 18PF_0603 15
CRT-15P
2
2
5
2
2
2 2
18
19
L2
DAC_HSYNC R135 33 DAC_H
D
11,36 DAC_HSYNC 3 1 1 2 1 2
Q3 FBM-L10-160808-301
2N7002
L33
G
DAC_VSYNC S R142 33 DAC_V
2
11,36 DAC_VSYNC 3 1 1 2 1 2
Q33 FBM-L10-160808-301
2N7002
1
G
2
1 2
R254 100K
+5V_SW
GMBus switch
2
D5
+3V_SW
RB751V
TV Out CONN. D39
1
3 3
1
3
Output filter network R73 R74
1
1
1
C163 R99 2.2K 2.2K
C20 2
33PF_0603 U10 .1UF 10K
2
2
1 2
DAN217
2
VCC 24
L9 3 2
21 CDLED_CON# 1A1 1B1 CDLED# 33
1.8UH_0603 4 5
21 HDDLED_CON# 1A2 1B2 HDDLED# 33
1 2 COMPS_CON 1 JP6 7 6 5VDDCDA
15,36 COMPS 11 IO_DDC1DATA 1A3 1B3 5VDDCDA 36
RCA JACK 8 9 5VDDCCL
11 IO_DDC1CLK 1A4 1B4 5VDDCCL 36
11 1A5 1B5 10
2
2
1 OE1#
13 OE2# GND 12
CBTD_3384
4 4
Title
Compal Electronics, inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1012
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Custom 401200 1B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date: Friday, October 19, 2001 Sheet 16 of 45
A B C D E
A B C D
+3V_SW
34,42 VGATE LPC_AD0 29,31
EC_SMI# +3V_SW
29 EC_SMI# 5 PM_CPUPERF# LPC_AD1 29,31
EC_SCI# RP18 LAN_DET 1 2
29 EC_SCI# 7,42 PM_SSMUXSEL LPC_AD2 29,31
EC_LID_OUT# 1 8 R577 100K
29 EC_LID_OUT# 29 PM_THRM# LPC_AD3 29,31
IDE_PATADET 2 7
21 IDE_PATADET 29,31 PM_SUS_STAT#
S_GPIO4 3 6 R578 1 2 LAN@100K
11,23,24 RTCCLK +3V_SW LPC_DRQ#1 31
S_GPIO5 4 5
8 PM_STPPCI# LPC_FRAME# 29,31
8 PM_STPCPU# WARM_RST# 34
LAN enable: Mount R577, del R578.
29 PM_SLP_S5# SM_SEL0 14
8P4R_100K LAN disable: Mount R578, del R577.
+3V_SW
29 PM_SLP_S3# PAL/NTSC# 15
1
8,29 PM_SLP_S1#
PM_RSMRST# R401 R225 2 1 0 IR_DET 1 2
19 PM_RSMRST#
R224 2 1 10K R579 @100K
19,29 ICH_SWI#
1 @4.7K R213 2 1 10K 1
34 PM_PWROK
R580 1 2 100K
IDE_PATADET
29 PBTN_OUT#
CLK_ICHAPIC
EC_LID_OUT#
2
INT_PIRQC#
INT_PIRQD#
INT_PIRQA#
INT_PIRQB#
7,42 PM_DPRSLPVR
19,22,23,29,31,37 PM_CLKRUN# INT_IRQ14 19,21
IR enable: Mount R579, del R580.
LAN_DET
EC_SMI#
H_PICD0
H_PICD1
EC_SCI#
S_GPIO5
IR disable: Mount R580, del R579.
S_GPIO4
IR_DET
INT_IRQ15 19,21
19,29 PM_BATLOW# INT_SERIRQ 19,23,29,31
+3V_ALW
25,29 PM_LANPWROK
11 AGP_BUSY#
PM_RSMRST# 1 R474 2 ICH3_PME# 1 2
AB21
AB14
0
W20
W19
AC2
AB3
AB1
AA6
AA1
AA7
AA5
AA2
AA4
AB4
U21
U20
D11
C11
H22
V21
Y20
V19
B11
J19
J20
J21
W2
W3
W4
U5
C7
U3
U2
U4
U1
C1
C5
V4
Y5
V5
B7
A7
V1
V2
Y4
Y2
Y3
B1
B2
A2
A6
B5
A5
INT_PIRQA# R525 100K
T3
T2
U16A 19,22,23 INT_PIRQA#
INT_PIRQB#
22,23,26,37 PCI_AD[0..31] 19,23 INT_PIRQB#
INT_PIRQC#
INT_IRQ14
INT_IRQ15
INT_APICD0
INT_APICD1
INT_PIRQA#
INT_PIRQB#
PM_GMUXSEL/GPIO23
PM_CPUPREF#/GPIO22
AC_RST#
AC_SDATAIN0
AC_SDATAIN1
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_DRQ#0
LPC_DRQ#1
LPC_FRAME#
GPIO_7
GPIO_8
GPIO_12
GPIO_13
GPIO_25
GPIO_27
GPIO_28
INT_PIRQC#
INT_PIRQD#
INT_PIRQE#/GPIO2
INT_PIRQF#/GPIO3
INT_PIRQG#/GPIO4
PM_AGPBUSY#/GPIO6
PM_BATLOW#
PM_C3_STAT#/GPIO21
PM_CLKRUN#/GPIO24
PM_RI#
PM_RSMRST#
PM_SLP_S1#/GPIO19
PM_SLP_S3#
PM_SLP_S5#
PM_STPCPU#/GPIO20
PM_STPPCI#/GPIO18
PM_SUS_STAT#
PM_THRM#
INT_PIRQH#/GPIO5
PM_PWRBTN#
INT_SERIRQ
PM_AUXPWROK
PM_DPRSLPVR
AC_SYNC
INT_APICCLK
PM_PWROK
PM_SUS_CLK
PM_VGATE/VRMPWRGD
AC_BITCLK
AC_SDATAOUT
19,37 INT_PIRQC#
INT_PIRQD#
19,26,37 INT_PIRQD#
Place closely to
ICH3-M
PCI_AD0 J2 T5 CLK_ICHPCI CLK_ICHPCI
PCI_AD0 PCI_CLK CLK_ICHPCI 8
PCI_AD1 K1 M3
PCI_AD1 PCI_DEVSEL# PCI_DEVSEL# 19,22,23,26,37
1
PCI_AD2 J4 F1
PCI_AD2 PCI_FRAME# PCI_FRAME# 19,22,23,26,37
PCI_AD3 K3 C4 R222
PCI_AD3 PCI_GPIO0/REQA# PCI_REQA# 19
PCI_AD4 H5 D4
PCI_AD4 PCI_GPIO1/REQB#/REQ5# PCI_REQB# 19
PCI_AD5 K4 AC'97 LPC unMUX Interrupt B6 @10
PCI_AD6 PCI_AD5 PCI_GPIO16/GNTA#
H3 PCI_AD6 Power Management Geyserville Interface Interface GPIO Interface PCI_GPIO17/GNTB#/GNT5# B3
PCI_AD7
12
L1 PCI_AD7 PCI_IRDY# N3 PCI_IRDY# 19,22,23,26,37
PCI_AD8 L2 G5 C328
PCI_AD8 PCI_PAR PCI_PAR 19,22,23,26,37
PCI_AD9 G2 M2
PCI_AD9 PCI_PERR# PCI_PERR# 19,22,23,37
PCI_AD10 L4 M1 @15PF
PCI_AD10 PCI_LOCK# PCI_LOCK# 19,23
PCI_AD11 ICH3_PME#
2
H4 PCI_AD11 PCI PCI_PME# W1
2 PCI_AD12 M4 Interface Y1 2
PCI_AD13 PCI_AD12 PCI_RST# PCI_RST# 9,15,21,22,23,26,29,31,37
J3 PCI_AD13 PCI_SERR# L5 PCI_SERR# 19,22,23,37
PCI_AD14 M5 H2
PCI_AD14 STOP# PCI_STOP# 19,22,23,26,37
PCI_AD15 J1 H1
PCI_AD15 PCI_TRDY# PCI_TRDY# 19,22,23,26,37
PCI_AD16 F5
PCI_AD17 PCI_AD16 +1.5V_SW
N2 PCI_AD17
PCI_AD18 G4 Y6
PCI_AD18 SM_INTRUDER# SM_INTRUDER# 19
PCI_AD19 P2 AC3
PCI_AD19 SMLINK0 SMLINK0 19
PCI_AD20 G1 AB2
PCI_AD20 System SMLINK1 SMLINK1 19
1
PCI_AD21 P1 Managment SMB_CLK AC4
Place closely to ICH3-M PCI_AD21 SMB_CLK 8,14,19
PCI_AD22 F2 AB5 R234 (for use if CPU unable
PCI_AD23 PCI_AD22 Interface SMB_DATA SMB_DATA 8,14,19
@10K to support DPSLP#)
P3 PCI_AD23 SMB_ALERT#/GPIO11 AC5 SMB_ALERT# 19
CLK_ICH14 PCI_AD24 F3 PCI
PCI_AD25 R1
PCI_AD24
PCI_AD25 Interface
ICH3-M (1/2)
1
PCI_AD26
2
E2 PCI_AD26 CPU_A20GATE Y22 GATE20 29
R212 PCI_AD27 N4 V23
PCI_AD27 CPU_A20M# H_A20M# 5
PCI_AD28 D1 AB22 R233 1 2 0
@10 PCI_AD29 PCI_AD28 CPU_DPSLP#
P4 PCI_AD29 CPU_FERR# J22 H_FERR# 5
PCI_AD30 E1 AA21
PCI_AD30 CPU_IGNNE# H_IGNNE# 5 5,42 H_DPSLP#
PCI_AD31
12
A4 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
3 22 PCI_GNT#0 PCI_GNT#0 3
R188 E3 AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D L22 HUB_PD0
37 PCI_GNT#1 PCI_GNT#1 HUB_PD0
D2 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE M21 HUB_PD1 H_PICD0
23 PCI_GNT#2 PCI_GNT#2 HUB_PD1
@10 D5 M23 HUB_PD2 H_PICD1
26 PCI_GNT#3 PCI_GNT#3 USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC. HUB_PD2
B4 N20 HUB_PD3
37 PCI_GNT#4 PCI_GNT#4 HUB_PD3
1
HUB_PD4
12
HUB_PD4 P21
C290 R22 HUB_PD5
HUB_PD5 HUB_PD6 R211 R220
19,22 PCI_REQ#0 D3 PCI_REQ#0 HUB_PD6 R20
@15PF F4 VSS Clocks LAN EEPROM HubLink T23 HUB_PD7 1K 1K
19,37 PCI_REQ#1 PCI_REQ#1 HUB_PD7 HUB_PD8
2
2
19,26 PCI_REQ#3 R4 PCI_REQ#3 HUB_PD9 P19
E4 N19 HUB_PD10
LAN_RSTSYNC
19,37 PCI_REQ#4 PCI_REQ#4 HUB_PD10
HUB_VSWING
HUB_PSTRB#
HUB_RCOMP
CLK_RTEST#
HUB_PSTRB
EEP_SHCLK
CLK_RTCX1
CLK_RTCX2 HUB_PD[0..10]
CLK_VBIAS
EEP_DOUT
HUB_VREF
LAN_RXD2
LAN_RXD1
LAN_RXD0
HUB_PD[0..10] 9
LAN_TXD2
LAN_TXD1
LAN_TXD0
LAN_JCLK
HUB_PAR
HUB_CLK
EEP_DIN
EEP_CS
CLK_14
CLK_48
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
CLK_ICHHUB
+VS_HUBREF
2
AC7
AC6
+VS_HUBVSWING
RTC_VBIASAB7
C14
C15
C16
C17
C18
C19
C20
C21
C22
D13
D16
D17
D20
D21
D22
C10
D10
N22
R19
A13
A16
A17
A20
A23
B10
B13
B14
B15
B18
B19
B20
B22
A10
K19
P23
F19
F20
T19
R456
L19
L20
J23
C3
C6
D9
D7
C9
C8
D8
A1
B8
E5
RTC_RST# Y7
B9
A9
A8
E8
E9
82801 @33
CLK_ICHHUB
RTC_X1
RTC_X2
+RTCVCC CLK_ICHHUB 8
1
HUB_PSTRB 9
LAN_CLK_ICH
CLK_ICH14 C686
8 CLK_ICH14 HUB_PSTRB# 9
C702 .047UF CLK_ICH48 HUB_ICH_RCOMP 1 2 @10PF
8 CLK_ICH48
1 2 1 2 RTC_VBIAS R227 36.5_1%
R495 1K 1 2
+RTCVCC
R475 RTC_X1
EEP_CS 25
1
RTC_X2 R472 15K
1
4 2 1 1 2 1 2 4
10M_0603 R491 10M_0603 EEP_DIN 25 C334 C666
C690 J1 EEP_DOUT 25
R566 22M_0603 .01UF .01UF
1UF_0603 JOPEN EEP_SHCLK 25
2
X3 Close to ICH3-M.
2
LAN_RXD0 25
2
12
1
R567
LAN_RXD1 25
R186
R482 LAN_RXD2 25
1
R5291 LAN_TXD2 25
2 22
2
2
SCHEMATIC, M/B LA-1012
2
LAN_JCLK 25
LAN_RSTSYNC 25 Size Document Number Rev
Custom 401200 1B
2
USB_D_PP0
USB_PP0 20
R493 D27 USB_D_PN0
USB_PN0 20
1K 1SS355 USB_D_PP1
USB_PP1 20
USB_D_PN1
+3V_ALW USB_PN1 20
USB_D_PP2 L27 1 2 FBM-L10-160808-301
USB_PP2 36
USB_D_PN2 L26 FBM-L10-160808-301
1
1 2 USB_PN2 36
1 USB_D_PP3 L19 1 2 FBM-L10-160808-301 1
USB_PP3 36
VCC5REF USB_D_PN3 L18 1 2 FBM-L10-160808-301
USB_PN3 36
USB_D_PP4 L25 1 2 FBM-L10-160808-301
USB_PP4 20
1
USB_D_PN4 L24 1 2 FBM-L10-160808-301
USB_PN4 20
C709 C714 C599
.1UF @1UF_0603 .1UF
+RTCVCC
2
+1.8V_ALW +V1.8_ICHLAN +3V_ALW +1.8V_ALW
L47 +1.5V_SW
1
1 2
VCCP_AUX
C705
VPLL_USB
BLM21A601SPT +3V_SW +1.8V_SW
1UF_0603
2
+1.8V_ALW
M10
M14
AB6
G18
C13
U18
C23
H18
R18
E13
K12
P10
K10
P14
V22
B23
A21
A22
P12
V15
V16
V17
V18
E11
K18
P18
V10
V14
F14
F15
F16
F10
T21
T18
J18
W8
W5
G6
D6
C2
H6
R6
U6
V6
V7
E6
E7
K6
P6
F7
F8
F9
T1
F6
T6
J6
U16B
VCC_SUS0
VCC_SUS1
VCC_SUS2
VCC_SUS3
VCC_SUS4
VCC_SUS5
VCC_USB0/VCC_SUS6
VCC_USB1/VCC_SUS7
VCCPAUX0/VCCLAN3_3
VCCPAUX1/VCCLAN3_3
VCC_AUX0/VCCLAN1_8
VCC_AUX1/VCCLAN1_8
VCC_AUX2/VCCLAN1_8
VCC5REF1
VCC5REF2
N/C0
N/C1
N/C2
N/C3
N/C4
VSS102
VSS103
VCCPPCI0
VCCPPCI1
VCCPPCI2
VCCPPCI3
VCCPPCI4
VCCPPCI5
VCCPPCI6
VCCPPCI7
VCCP0
VCCP1
VCCPIDE0
VCCPIDE1
VCCPIDE2
VCCPIDE3
VCCPIDE4
VCC5REFSUS1
VCC5REFSUS2
VCCPCPU0
VCCPCPU1
VCCPCPU2
VCCUSBBG/VCC_SUS8
VCCUSBPLL/VCC_SUS9
VCCPHL0
VCCPHL1
VCCPHL2
VCCPHL3
VCCCORE0
VCCCORE1
VCCCORE2
VCCCORE3
VCCCORE4
VCCCORE5
VCCCORE6
VCC_RTC
IDE_PDCS1# AC15
+3V_ALW RP19 IDE_PDCS1# 21
IDE_PDCS3# AB15 IDE_PDCS3# 21
8P4R_100K USB_D_PP0 D19 AC21
2 USB_D_PP1 USB_PP0 IDE_SDCS1# IDE_SDCS1# 21 2
A19 USB_PP1 IDE_SDCS3# AC22 IDE_SDCS3# 21
1 8 USB_OC#2 USB_D_PP2 E17
USB_OC#3 USB_D_PP3 USB_PP2
2 7 B17 USB_PP3 IDE_PDA0 AA14
USB_OC#4 USB_D_PP4 IDE_PDA0 21
3 6 D15 USB_PP4 Power IDE_PDA1 AC14 IDE_PDA1 21
4 5 USB_OC#5 A15 AA15
USB_D_PN0 USB_PP5 IDE_PDA2 IDE_PDA2 21
D18 USB_PN#0 IDE_SDA0 AC20 IDE_SDA0 21
USB_D_PN1 A18 AA19
USB_D_PN2 USB_PN#1 IDE_SDA1 IDE_SDA1 21
E16 USB_PN#2 IDE_SDA2 AB20
USB_D_PN3 IDE_SDA2 21
B16 USB_PN#3 IDE_PDD[0..15] 21
USB_D_PN4 D14 W12 IDE_PDD0
USB_PN#4 IDE_PDD0 IDE_PDD1
A14 USB_PN#5 IDE_PDD1 AB11
AA10 IDE_PDD2
IDE_PDD2 IDE_PDD3
IDE_PDD3 AC10
USB_OC#0 E12 W11 IDE_PDD4
20 USB_OC#0 USB_OC#0 IDE_PDD4
USB_OC#1 D12 Y9 IDE_PDD5
20 USB_OC#1 USB_OC#1 IDE_PDD5
USB_OC#2 C12 AB9 IDE_PDD6
36 USB_OC#2 USB_OC#2 IDE_PDD6
USB_OC#3 B12 AA9 IDE_PDD7
36 USB_OC#3 USB_OC#3 IDE_PDD7
USB_OC#4 A12 USB AC9 IDE_PDD8
USB_OC#5 USB_OC#4 IDE_PDD8 IDE_PDD9
A11 USB_OC#5 Interface IDE_PDD9 Y10
W9 IDE_PDD10
IDE_PDD10 IDE_PDD11
IDE_PDD11 Y11
H20 AB10 IDE_PDD12
21 ICH_IDE_PRST# GPIO32 IDE_PDD12
G22 AC11 IDE_PDD13
21 ICH_IDE_SRST# GPIO33 IDE_PDD13
F21 AA11 IDE_PDD14
7 AC_VID0 GPIO34 IDE_PDD14
G19 AC12 IDE_PDD15
ICH3-M (2/2)
7 AC_VID1 GPIO35 IDE_PDD15 IDE_SDD[0..15] 21
7 AC_VID2 E22 GPIO36 IDE
E21 Interface Y17 IDE_SDD0
7 AC_VID3 GPIO37 IDE_SDD0
H21 W17 IDE_SDD1
7 AC_VID4 GPIO38 IDE_SDD1
G23 AC17 IDE_SDD2
3 19 FWH_WP# GPIO39 IDE_SDD2 3
F23 AB16 IDE_SDD3
19 FWH_TBL# GPIO40 IDE_SDD3
G21 W16 IDE_SDD4
30 EC_FLASH# GPIO41 IDE_SDD4
ICH_ACIN D23 Y14 IDE_SDD5
GPIO42 IDE_SDD5 IDE_SDD6
19 GPIO43 E23 GPIO43 IDE_SDD6 AA13
W15 IDE_SDD7
IDE_SDD7 IDE_SDD8
IDE_SDD8 W13
USB_BIAS B21 Y16 IDE_SDD9
R196 USB_RBIAS IDE_SDD9
+3V_SW 1 2 @1K IDE_SDD10 Y15 IDE_SDD10
1
AC16 IDE_SDD11
R154 IDE_SDD11 IDE_SDD12
27 ICH_SPKR H23 SPKR Misc IDE_SDD12 AB17
18.2_1% AA17 IDE_SDD13
IDE_SDD13 IDE_SDD14
IDE_SDD14 Y18
U19 AC18 IDE_SDD15
+1.8V_SW VCCA IDE_SDD15
2
Power
IDE_PDDACK# Y13 IDE_PDDACK# 21
+3V_ALW F17 VCCPSUS3/VCCPUSB0 IDE_SDDACK# Y19 IDE_SDDACK# 21
F18 VCCPSUS4/VCCPUSB1 IDE_PDDREQ AB12 IDE_PDDREQ 21
V3ALW_ICH
VSS100
VSS101
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
1
AC23
AA22
AA12
AA16
AA20
4 4
W10
W14
W18
W22
AC1
AC8
M11
M12
M13
M20
M22
AA3
AA8
AB8
G20
H19
N10
N11
N12
N13
N14
N21
N23
R21
R23
E14
E15
E18
E19
E20
K11
K13
K20
K21
K22
K23
P11
P13
P20
P22
V20
F22
T20
T22
R181
L10
L11
L12
L13
L14
L21
L23
W6
W7
G3
N5
R3
R5
82801 V3
Y8
T4
L3
J5
100K
2
29,38,40 ACIN
1
D13
2
RB751V
ICH_ACIN
Title
Compal Electronics, inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1012
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Custom 401200 1B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date: Friday, October 19, 2001 Sheet 18 of 45
A B C D E
A B C D E
+3V_SW
RP8
1 8 R200 1 2 100
18 FWH_WP# 17,22,23,26,37 PCI_PAR
18 FWH_TBL# 2 7
+3V_SW +3V_SW
17,22,23,29,31,37 PM_CLKRUN# 3 6
4 5
RP6
1 10 8P4R_10K
17,22,23,26,37 PCI_FRAME#
17,22,23,26,37 PCI_IRDY# 2 9 PCI_SERR# 17,22,23,37
17,22,23,26,37 PCI_TRDY# 3 8 PCI_DEVSEL# 17,22,23,26,37 +3V_ALW +3V_ALW
1 17,22,23,26,37 PCI_STOP# 4 7 PCI_PERR# 17,22,23,37 1
5 6 PCI_LOCK# 17,23
R461 1 2 100K R550 100K
17,29 ICH_SWI#
10P8R_8.2K 1 2
17,29 PM_BATLOW#
R466 1 2 100K
+3V_SW +3V_SW 17 SMB_ALERT#
17 PCI_REQA# 1 10
17 PCI_REQB# 2 9 PCI_REQ#2 17,23
17,22 PCI_REQ#0 3 8 PCI_REQ#3 17,26
1
17,37 PCI_REQ#1 4 7 PCI_REQ#4 17,37
1
5 6 INT_SERIRQ 17,23,29,31 + +
C338 C341 C340 C660 C678 C661
10P8R_8.2K 1UF_0603 .1UF .1UF 1UF_0603 .1UF .1UF
2
+3V_SW +3V_SW
RP17
18 GPIO43 1 10
2 9 INT_IRQ15 17,21
17,26,37 INT_PIRQD# 3 8 INT_PIRQA# 17,22,23 +3V_SW
17,21 INT_IRQ14 4 7 INT_PIRQB# 17,23
5 6 INT_PIRQC# 17,37
10P8R_8.2K
1
2 + + 2
C337 C336 C645 C616 C625 C617 C622 C672 C673 C674 C662 C656 C657 C667 C624 C610 C621 C658 C675 C646
22UF_1206_10V 22UF_1206_10V .1UF .1UF 47PF .1UF .1UF 47PF .1UF .1UF 47PF .1UF .1UF .1UF 47PF .1UF .1UF 47PF .1UF .1UF
2
+3V_ALW
1
+
C249 C263 C261 C264 C262
22UF_1206_10V .1UF .1UF .1UF .1UF
2
+3V_ALW
+1.8V_SW +1.8V_ALW
R556 1 2 2.2K
8,14,17 SMB_DATA
R557 1 2 2.2K
8,14,17 SMB_CLK
R558 1 2 100K
17 SMLINK0
1
1
R559 1 2 100K
17 SMLINK1
1
+ +
C325 C639 C651 C644 C630 C604 C676 C677 C243 C246 C250 C251
100UF_D2_6.3V .1UF 33PF .1UF .1UF 33PF .1UF .1UF 22UF_10V_1206 .1UF .1UF .1UF
2
2
3 3
+RTCVCC
1 2 +3V_ALW
17 SM_INTRUDER# R538
R476 8.2K @0 R473 0
1 2 1 2 G_RST# 22,23,24,29
+3V_ALW +3V_ALW
1
R359 +3V_ALW
14
14
74LVC14 74LVC14
5
R549 0 U63
29,34 EC_RST# 1 2 9 8 11 10 1
4 PM_RSMRST# 17
2
1
7
.47UF_0603
3
2
4
330K 4
2
30 EC_GRST#
Title
Compal Electronics, inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1012
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Custom 401200 1B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date: Friday, October 19, 2001 Sheet 19 of 45
A B C D E
A B C D E
USBPWR_AS +3V_ALW
BlueTooth Interface USB Interface USBPWR_BS
1
+5V_ALW
R260 R263
+3V_ALW +5V_ALW 10K 10K
1 1
Bluetooth Connector U26
2
JP13 1 8
GND OC1# USB_OC#0 18
30 BT_DETACH 1 2 2 IN OUT1 7
BT_WAKE_UP 3 6
30 BT_WAKE_UP 3 4 EN1# OUT2
1
C380 4 5
5 6 BT_ON# 30 EN2# OC2# USB_OC#1 18
18 USB_PP4 7 8 BT_PRES# 30
18 USB_PN4 9 10
1
4.7UF_10V_0805 TPS2042 C374 C383
2
11 12
30 BT_RST# 13 14 1UF_0603 1UF_0603
15 16
2
17 18
19 20 18 USB_PN0
18 USB_PP0 USB_PN1 18
1
1
AXN420C530P
USBPWR_AS USB_PP1 18 USBPWR_BS
C61 C60
.1UF .1UF JP4
2
2
USB_AS 1 5 USB_BS
VCC VCC
1
1 2 USB_CPN0 2 D0- D1- 6 USB_CPN12 1
1
C39 + C35 L32 FBM-L10-160808-301 L30 FBM-L10-160808-301 C369+ C367
1 2 USB_CPP0 3 7 USB_CPP12 1
150UF_D2_16V 1000PF L31 FBM-L10-160808-301 D0+ D1+ L29 FBM-L10-160808-301 1000PF 150UF_D2_16V
2
4 VSS VSS 8
2 2
11 G3 G1 9
12 G4 G2 10
Molex-67300
USB Connector Stacked
USB_CPN0 USB_CPN1
USB_CPP0 USB_CPP1
1
C34 C762
C763 C370
15PF 15PF
15PF 15PF
2
3 3
4 4
Title
Compal Electronics, inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1012
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Custom 401200 1B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date: Friday, October 19, 2001 Sheet 20 of 45
A B C D E
A B C D E
+5V_SW
HDD Manual ATA Type Selection:
ATA33 : populate R224, de-populate R225.
ATA66/100 : populate R225, de-populate R224.
5
U24
1
18 ICH_IDE_PRST# HDD_RST# +3V_SW
4
2 +5V_SW
9,15,17,22,23,26,29,31,37 PCI_RST#
1 2 IDE_PIORDY 1 2 IDE_PDDREQ
7SH08 R243 4.7K R240 @5.6K
1
3
+5V_SW
1
R241 1
HDD Connector 1 2 IDE_SIORDY 1 2 IDE_SDDREQ @10K
R238 4.7K R239 @5.6K
IDE_PDD[0..15]
2
18 IDE_PDD[0..15] IDE_PATADET 17
1
JP22
1 2 R242
IDE_PDD7 1 2 IDE_PDD8 100K
3 4
IDE_PDD6 3 4 IDE_PDD9
5 6
IDE_PDD5 5 6 IDE_PDD10
7 8
IDE_PDD4 7 8 IDE_PDD11
2
9 10
IDE_PDD3 9 10 IDE_PDD12
11 12
IDE_PDD2 11 12 IDE_PDD13
13 14
IDE_PDD1 13 14 IDE_PDD14
15 16
IDE_PDD0 15 16 IDE_PDD15
17 18
17 18
19 20
IDE_PDDREQ 19 20
18 IDE_PDDREQ 21 22
IDE_PDIOW# 21 22
18 IDE_PDIOW# 23
23 24
24 Layout note : Layout note :
IDE_PDIOR# 25 26
18 IDE_PDIOR# 25 26
IDE_PIORDY 27 28 IDE_PD_CSEL Place capacitors near HDD connector . Place capacitors near CD-ROM connector .
18 IDE_PIORDY 27 28
IDE_PDDACK# 29 30
18 IDE_PDDACK# 29 30
INT_IRQ14 31 32
17,19 INT_IRQ14 31 32
IDE_PDA1 33 34
18 IDE_PDA1 33 34 +5V_SW +5V_SW
IDE_PDA0 35 36 IDE_PDA2
18 IDE_PDA0 35 36 IDE_PDA2 18
IDE_PDCS1# 37 38 IDE_PDCS3#
18 IDE_PDCS1# 37 38 IDE_PDCS3# 18
16 HDDLED_CON# 39 40
39 40
+5V_SW 41 42 +5V_SW
41 42
1
43 44
43 44
1
+ +
HDD CONN C717 C349 C715 C347 C344 C343
22UF_1206_10V .1UF 1000PF 22UF_1206_10V .1UF 1000PF
2
2 2
+5V_SW
5
U8
18 ICH_IDE_SRST# 1
4 CDR_RST#
9,15,17,22,23,26,29,31,37 PCI_RST# 2
7SH08
3
+5V_SW
CD-ROM Connector
3 18 IDE_SDD[0..15] 3
JP23
26 INT_CD_L 1 2 INT_CD_R 26
26 CD_AGND 3 4
CDR_RST# IDE_SDD8
IDE_SDD7 5 6 IDE_SDD9
7 8
1
IDE_SDD2 15 16 IDE_SDD14
+5V_SW IDE_SDD1 17 18 IDE_SDD15
IDE_SDD0 19 20
21 22 IDE_SDDREQ 18
23 24 IDE_SDIOR# 18
18 IDE_SDIOW# 25 26
18 IDE_SIORDY 27 28 IDE_SDDACK# 18
17,19 INT_IRQ15 29 30 R237 1 2 100K
18 IDE_SDA1 31 32
18 IDE_SDA0 33 34 IDE_SDA2 18
18 IDE_SDCS1# 35 36 IDE_SDCS3# 18
W=80mils
16 CDLED_CON# 37 38
39 40
41 42
43 44
1
45 46 C345
2 1 SEC_CSEL
R235 470 47 48 .1UF
49 50 2
CD-ROM CONN.
4 4
Title
Compal Electronics, inc.
SCHEMATIC, M/B LA-1012
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Custom 401200 1B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date: Friday, October 19, 2001 Sheet 21 of 45
A B C D E
5 4 3 2 1
+3V_ALW R116
1
1
1
R130 R136 R197 R198
2
2
2
D D
+3V_ALW
20
35
48
62
78
87
86
96
10
11
TEST17
TEST16
CYCLEIN
VDDP
VDDP
VDDP
VDDP
VDDP
CNA
CYCLEOUT
15 L28 1 2 @0_0805
17,23,26,37 PCI_AD[0..31] DVDD
PCI_AD31 22 27
PCI_AD30 PCI_AD31 DVDD
24 PCI_AD30 DVDD 39
PCI_AD29 25 51
PCI_AD28 PCI_AD29 DVDD VPLL_1394
26 PCI_AD28 DVDD 59
PCI_AD27 28 72
PCI_AD26 PCI_AD27 DVDD
29 PCI_AD26 DVDD 88
PCI_AD25 31 100
PCI_AD25 DVDD
1
PCI_AD24 32 7 C306 C320
PCI_AD23
PCI_AD22
37
38
PCI_AD24
PCI_AD23
TSB43AB22 PLLVDD
AVDD 1
2 @.01UF @4.7UF_10V_0805
PCI_AD21 PCI_AD22 AVDD
2
40 PCI_AD21 AVDD 107
PCI_AD20 41 108
PCI_AD19 PCI_AD20 AVDD +3V_ALW
42 PCI_AD19 AVDD 120
PCI_AD18 43 PCI_AD18
PCI_AD17 45 PCI_AD17
PCI BUS INTERFACE
CLK_1394 PCI_AD16 46 106 R167 1 2 @1K
PCI_AD15 PCI_AD16 CPS
61 PCI_AD15
1
PCI_AD14 63 C281 C303 C304 C307 C308 C301 C295 C284
PCI_AD14
1
2
67 PCI_AD11 TPA1- 123
@10 PCI_AD10 69 122 R190 1 2 @1K
PCI_AD9 PCI_AD10 TPB1+ R185 1
70 PCI_AD9 TPB1- 121 2 @1K
PCI_AD8
12
71 PCI_AD8
1
C C319 PCI_AD7 74 118 1 2 @6.34K_1% C268 C272 C233 C234 C232 C
PCI_AD6 PCI_AD7 BIAS CURRENT R0 R179
76 PCI_AD6
@15PF PCI_AD5 77 @1000PF @1000PF @1000PF @1000PF @1000PF
PCI_AD4 PCI_AD5
2
2
79 PCI_AD4
PCI_AD3 80 Near 1394 IC
PCI_AD2 PCI_AD3
81 PCI_AD2 R1 119
PCI_AD1 82 C312 1 2 @15PF
PCI_AD0 PCI_AD1
84 PCI_AD0 OSCILLATOR X0 6
17,23,26,37 PCI_C/BE#3 34 PCI_C/BE3
47 X1
17,23,26,37 PCI_C/BE#2 PCI_C/BE2
17,23,26,37 PCI_C/BE#1 60 PCI_C/BE1
73 5 @24.576MHz
17,23,26,37 PCI_C/BE#0 PCI_C/BE0 X1
16 C311 1 2 @15PF
8 CLK_1394 PCI_CLK
17 PCI_GNT#0 18 PCI_GNT
19 3 C305 1 2 @.1UF
17,19 PCI_REQ#0
PCI_AD16 PCI_REQ FILTER FILTER0
1R187 2@100 36
ID: AD16 49
PCI_IDSEL
4
17,19,23,26,37 PCI_FRAME# PCI_FRAME FILTER1
17,19,23,26,37 PCI_IRDY# 50 PCI_IRDY
52 92 SDA_1395 R131 1 2 @220
17,19,23,26,37 PCI_TRDY#
53
PCI_TRDY EEPROM 2 WIRE BUS SDA
17,19,23,26,37 PCI_DEVSEL# PCI_DEVSEL SCL_1394 R123 1
17,19,23,26,37 PCI_STOP# 54 PCI_STOP SCL 91 2 @220
17,19,23,37 PCI_PERR# 56 PCI_PERR
17,19,23 INT_PIRQA# 13 PCI_INTA POWER CLASS PC0 99
30 1394_PME# 21 PCI_PME PC1 98
17,19,23,37 PCI_SERR# 57 PCI_SERR PC2 97
17,19,23,26,37 PCI_PAR 58 PCI_PAR
12 116 XTPBIAS0
17,19,23,29,31,37 PM_CLKRUN# PCI_CLKRUN PHY PORT 1 TPBIAS0 XTPA0+
9,15,17,21,23,26,29,31,37 PCI_RST# 85 PCI_RST TPA0+ 115
114 XTPA0-
B TPA0- XTPB0+ B
TPB0 + 113
112 XTPB0-
TPB0 -
TEST9 94
1
95 C350
TEST8 R248 R247
19,23,24,29 G_RST# 14 G_RST
101 @56.2_1% @56.2_1% @1UF_25V_0805
TEST3
REG_EN#
PLLGND1
2
2 1 89 GPIO3 TEST2 102
R124 2 1 @220 90 104
REG18
REG18
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
GPIO2 TEST1
AGND
AGND
AGND
AGND
AGND
AGND
AGND
2
105 L1
TEST0 XTPA0+ PA0+_C
XTPA0- 1 8 PA0-_C 4 5
XTPB0+ 2 7 PB0+_C 3 6
109
110
111
117
126
127
128
103
30
93
17
23
33
44
55
64
68
75
83
4 5 1
@IEEE1394-COILS @1394_CONN 4PIN
1
R246 R244
@56.2_1% @56.2_1%
1
C302 C231
2
@.1UF @.1UF
1
2
1
C351 R245
@5.11K
@220PF
2
A A
2
Title
Compal Electronics, inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1012
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Custom 401200 1B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date: Friday, October 19, 2001 Sheet 22 of 45
5 4 3 2 1
A B C D E
S1_IOWR#
S1_IORD# S1_IOWR# 24
S1_IORD# 24
S1_OE# S1_A[0..25]
S1_OE# 24 S1_A[0..25] 24
S1_CE2# S1_D[0..15]
S1_CE2# 24 S1_D[0..15] 24
S1_IOWR#
S1_IORD#
S1_CE2#
S1_OE#
S1_D10
S1_D15
S1_D13
G_RST# 19,22,24,29
S1_D12
S1_D11
S1_A17
S1_A25
S1_A24
S1_A11
S1_A10
S1_D9
S1_D1
S1_D8
S1_D0
S1_D7
S1_D6
S1_D5
S1_D4
S1_D3
S1_A0
S1_A3
S1_A5
S1_A7
S1_A1
S1_A2
S1_A4
S1_A6
S1_A9
S1_VCC
1 1
127
134
180
124
122
121
120
119
116
113
111
109
107
105
103
102
100
21
37
50
79
99
83
81
80
78
77
75
74
73
71
68
67
66
65
64
63
62
59
17,22,26,37 PCI_AD[0..31]
6
U37 C580 C649 C659
A_D10/CAD31
A_D9/CAD30
A_D1/CAD29
A_D8/CAD28
A_D0/CAD27
A_A0/CAD26
A_A1/CAD25
A_A2/CAD24
A_A3/CAD23
A_A4/CAD22
A_A5/CAD21
A_A6/CAD20
A_A7/CAD18
A_IOWR/CAD15
A_A9/CAD14
A_IORD#/CAD13
A_OE#/CAD11
A_CE2#/CAD10
A_D15/CAD8
A_D12/CAD4
A_A25/CAD19
A_A24/CAD17
A_A17/CAD16
A_A10/CAD9
A_D7/CAD7
A_D13/CAD6
A_D6/CAD5
A_D5/CAD3
A_D11/CAD2
A_D4/CAD1
A_D3/CAD0
A_A11/CAD12
AUX_VCC
PCI_VCC
PCI_VCC
PCI_VCC
PCI_VCC
CORE_VCC
CORE_VCC
CORE_VCC
117 .1UF .1UF .1UF
PCI_AD31 GRST#
4 AD31 A_SKT_VCC 98
PCI_AD30 5 60
PCI_AD29 AD30 A_SKT_VCC
7 AD29
PCI_AD28 8 112
PCI_AD27 AD28 A_REG#/CCBE3# S1_A12 S1_REG# 24
9 AD27 A_A12/CCBE2# 97
PCI_AD26 10 82 S1_A8
PCI_AD25 AD26 A_A8/CCBE1#
11 AD25 A_CE1#/CCBE0# 70 S1_CE1# 24
PCI_AD24 12
PCI_AD23 AD24
16 AD23 A_A16/CCLK 93 R421 1 2 33 S1_A16
PCI_AD22 17 96 S1_A23
PCI_AD21 AD22 A_A23/CFRAME# S1_A15
18 AD21 A_A15/CIRDY# 95
PCI_AD20 19 94 S1_A22
PCI_AD19 AD20 A_A22/CTRDY# S1_A21
20 AD19 A_A21/CDEVSEL# 92
PCI_AD18 22 90 S1_A20
PCI_AD17 AD18 A_A20/CSTOP# S1_A13
23 AD17 A_A13/CPAR 84
PCI_AD16 24 86 S1_A14
PCI_AD15 AD16 A_A14/CPERR#
38 AD15 A_WAIT#/CSERR# 108 S1_WAIT# 24
PCI_AD14 39 110
PCI_AD13 AD14 A_INPACK#/CREQ# S1_INPACK# 24
40 AD13 A_WE#/CGNT# 89 S1_WE# 24
PCI_AD12 41 91
PCI_AD11 AD12 A_RDY_IRQ#/CINT# S1_A19 S1_RDY# 24
42 AD11 A_A19/CBLOCK# 88
PCI_AD10 43 125 S1_WP 24
PCI_AD9 AD10 A_WP/CCLKRUN#
45 AD9 A_RST/CRST# 106
2 PCI_AD8 S1_D2 S1_RST 24 2
46 AD8 A_R2_D2/RFU 123
PCI_AD7 48 69 S1_D14
PCI_AD6 AD7 A_R2_D14/RFU S1_A18
49 AD6 A_R2_A18/RFU 85
PCI_AD5 51 76
PCI_AD4 AD5 A_VS1/CVS1 S1_VS1 24
52 AD4 A_VS2/CVS2 104
PCI_AD3 S1_VS2 24
53 AD3 A_CD1#/CCD1# 61 S1_CD1# 24
PCI_AD2 54 126
PCI_AD1
PCI_AD0
55
56
AD2
AD1
AD0
CardBus Controller A_CD2#/CCD2#
A_BVD2/CAUDIO
A_BVD1/CSTSCHG
114
118
S1_CD2#
S1_BVD2
S1_BVD1
24
24
24
17,22,26,37
17,22,26,37
17,22,26,37
PCI_C/BE#3
PCI_C/BE#2
PCI_C/BE#1
13
25
36
C/BE3#
C/BE2#
C/BE1#
OZ6933T (TQFP) B_BVD1/CSTCHG
B_BVD2/CAUDIO
B_CD2#/CCD2#
192
190
202
S2_BVD1
S2_BVD2
S2_CD2#
24
24
24
17,22,26,37 PCI_C/BE#0 47 C/BE0# B_CD1#/CCD1# 136 S2_CD1# 24
R358 100 179
B_VS2/CVS2 S2_VS2 24
17,22,26,37 PCI_AD20 1 2 15 IDSEL B_VS1/CVS1 152 S2_VS1 24
CLK_PCI_CB CLK_PCI_CB 1 161 S2_A18
8 CLK_PCI_CB PCI_CLK B_R2_A18/RFU
31 145 S2_D14
17,19,22,26,37 PCI_DEVSEL# DEVSEL# B_R2_D14/RFU
2
27 198 S2_D2
17,19,22,26,37 PCI_FRAME# FRAME# B_R2_D2/RFU
R355 29 182
17,19,22,26,37 PCI_IRDY# IRDY# B_RST/CRST# S2_RST 24
@33 30 201
17,19,22,26,37 PCI_TRDY# TRDY# B_WP/CCLKRUN# S2_WP 24
32 164 S2_A19
17,19,22,26,37 PCI_STOP# STOP# B_A19/CBLOCK#
17,19,22,26,37 PCI_PAR 35 PAR B_RDY_IRQ#/CINT# 167
S2_RDY# 24
1
72 R418 33
32 PCM_RI# IRQ15/RI_OUT#
27 CB_SPK# 128 SPKR_OUT# B_CE1#/CCBE0# 147 S2_CE1# 24
133 157 S2_A8
SDATA/B_VCC_3#
LEDO#/SKTA_ACTV B_A8/CCBE1#
B_IOWR#/CAD15
SCLK/A_VCC_5#
S2_A12
B_IORD#/CAD13
193 173
IRQ3/A_VCC_3#
IRQ11/SKTB_ACTV B_A12/CCBE2#
B_CE2#/CAD10
B_OE#/CAD11
188
B_D10/CAD31
B_A25/CAD19
B_A24/CAD17
B_A17/CAD16
B_A11/CAD12
B_REG#/CCBE3# S2_REG# 24
B_D9/CAD30
B_D1/CAD29
B_D8/CAD28
B_D0/CAD27
B_D15/CAD8
B_D13/CAD6
B_D12/CAD4
B_D11/CAD2
B_A0/CAD26
B_A1/CAD25
B_A2/CAD24
B_A3/CAD23
B_A4/CAD22
B_A5/CAD21
B_A6/CAD20
B_A7/CAD18
B_A9/CAD14
B_A10/CAD9
205
B_D7/CAD7
B_D6/CAD5
B_D5/CAD3
B_D4/CAD1
B_D3/CAD0
17,19,29,31 INT_SERIRQ IRQ5/SERIRQ#
206 IRQ7/SIN#/B_VPP_PGM B_SKT_VCC 143 S2_VCC
B_SKT_VCC 160
200
GND
GND
GND
GND
GND
GND
GND
GND
B_SKT_VCC
C684 C650 C583
OZ6933TQFP
101
129
177
132
131
130
115
146
199
197
196
195
194
191
189
187
185
183
181
178
176
175
174
158
156
155
154
153
151
150
149
148
144
142
141
140
139
138
137
135
14
26
28
44
57
87
S2_D15
S2_D13
S2_D12
S2_D11
S2_A17
S2_A25
S2_A24
S2_A11
S2_A10
+3V_SW
S2_D9
S2_D1
S2_D8
S2_D0
S2_D7
S2_D6
S2_D5
S2_D4
S2_D3
S2_A0
S2_A3
S2_A5
S2_A7
S2_A1
S2_A2
S2_A4
S2_A6
S2_A9
1
+3V_ALW S2_CE2#
4 SLATCH 24 S2_CE2# 24 4
S2_OE#
+3V_SW SLDATA 24 S2_OE# 24
S2_IORD#
RTCCLK 11,17,24 S2_IORD# 24
C681 S2_IOWR#
C612 C561 C565 C564 S2_IOWR# 24
.1UF .1UF .1UF .1UF .1UF S2_A[0..25]
S2_A[0..25] 24
S2_D[0..15]
S2_D[0..15] 24
Title
Compal Electronics, inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1012
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Custom 401200 1B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date: Friday, October 19, 2001 Sheet 23 of 45
A B C D E
A B C D E
CARDBUS SOCKET
JP18
1 1
A77 a68 B77
b68
A76 a34 B76
S1_CD2# b34 S2_CD2#
A75 B75
23
23
S1_CD2#
S1_WP
S1_WP
S1_D10
A74
A73
A72
a67
a33
GND
b67
b33
GND
B74
B73
B72
S2_WP
S2_D10
S2_CD2# 23
S2_WP 23 23
23
S1_D[0..15]
S1_A[0..25]
S1_D[0..15]
S1_A[0..25]
S2_D[0..15]
PCMCIA POWER CTRL.
S1_D2 a66 b66 S2_D2 23 S2_D[0..15] S2_A[0..25]
A71 a32 B71
S1_D9 b32 S2_D9 23 S2_A[0..25]
A70 a65 B70
S1_D1 b65 S2_D1
A69 a31 B69
S1_D8 b31 S2_D8 +12V_ALW
A68 a64 B68
S1_D0 b64 S2_D0 S1_VPP
A67 a30 B67 S1_VPP
S1_BVD1 b30 S2_BVD1
23 S1_BVD1 A66 a63 B66 S2_BVD1 23
b63 +5V_ALW
A65 B65 U32 S1_VCC
S1_A0 GND GND S2_A0
A64 B64
1
S1_BVD2 a29 b29 S2_BVD2
23 S1_BVD2 A63 a62 B63 S2_BVD2 23 25 NC AVPP 8
S1_A1 b62 S2_A1 +3V_ALW C552
A62 a28 B62 AVCC 9
S1_REG# b28 S2_REG# 10UF_16V_1206
23 S1_REG# A61 a61 B61 S2_REG# 23 7 12V AVCC 10
S1_A2 b61 S2_A2 C502 2.2UF_16V_0805
2
A60 a27 B60 24 12V AVCC 11
S1_INPACK# b27 S2_INPACK#
23 S1_INPACK# A59 a60 B59 S2_INPACK# 23
S1_A3 b60 S2_A3 C501 .1UF S2_VPP
A58 a26 B58 1 5V BVPP 23 S2_VPP
b26
A57 GND B57 2 5V BVCC 20
S1_WAIT# GND S2_WAIT# C550 .1UF
23 S1_WAIT# A56 a59 B56 S2_WAIT# 23 30 5V BVCC 21 S2_VCC
S1_A4 b59 S2_A4
A55 a25 B55 BVCC 22
b25
1
S1_RST A54 B54 S2_RST C551 .1UF 15
23 S1_RST S1_A5 a58 b58 S2_A5 S2_RST 23 3.3V C513
A53 a24 B53 16 3.3V RESET 6
S1_VS2 b24 S2_VS2 C504 .1UF 10UF_16V_1206
A52 a57 B52 17 3.3V RESET# 14
23 S1_VS2 S1_A6 b57 S2_A6 S2_VS2 23
2
A51 a23 B51
S1_A25 b23 S2_A25 C503 .1UF SLDATA
A50 a56 B50 3 DATA NC 26
2 b56 23 SLDATA SLATCH 2
A49 B49 5 27 G_RST# 19,22,23,29
S1_A7 A48
GND GND
B48 S2_A7 C548 .1UF23 SLATCH
4
LATCH NC
28
S1_A24 a22 b22 S2_A24 11,17,23 RTCCLK CLOCK NC
A47 a55 B47 MODE 29
S1_A12 b55 S2_A12
A46 a21 B46 13 NC
S1_A23 b21 S2_A23
A45 a54 B45 19 STBY#
S1_A15 b54 S2_A15
A44 a20 B44 18 OC# GND 12
S1_A22 b20 S2_A22 +3V_ALW
A43 a53 B43
b53
A42 GND B42
S1_A16 GND S2_A16
A41 B41 TPS2216
a19 b19
A40 a52 B40 1 2 SLDATA
S1_VPP b52 S2_VPP R561 100K
A39 a18 b18 B39
S1_VCC A38 a51 b51 B38 S2_VCC 1 2 SLATCH
A37 B37 R562 100K
S1_A21 a17 b17 S2_A21
A36 a50 b50 B36
S1_RDY# A35 B35 S2_RDY#
23 S1_RDY# S1_A20 a16 b16 S2_A20 S2_RDY# 23
A34 a49 b49 B34
S1_WE# A33 B33 S2_WE# S1_VCC
23 S1_WE# a15 b15 S2_WE# 23 S2_VCC
S1_A19 A32 B32 S2_A19
a48 b48
1
S1_A14 A31 B31 S2_A14
S1_A18 a14 b14 S2_A18 C529 C530 C538 C523 C522 C505
A30 a47 b47 B30
S1_A13 A29 B29 S2_A13 .1UF .01UF 4.7UF_16V_1206 .1UF .01UF 4.7UF_16V_1206
a13 b13
2
A28 GND GND B28
S1_A17 A27 B27 S2_A17
S1_A8 a46 b46 S2_A8
A26 a12 b12 B26
S1_IOWR# A25 B25 S2_IOWR#
23 S1_IOWR# S1_A9 a45 b45 S2_A9 S2_IOWR# 23
A24 a11 b11 B24
S1_IORD# A23 B23 S2_IORD#
23 S1_IORD# a44 b44 S2_IORD# 23
A22 GND GND B22
S1_A11 A21 B21 S2_A11
3 S1_VS1 a10 b10 S2_VS1 3
A20 a43 b43 B20 S2_VS1 23
23 S1_VS1 S1_OE# S2_OE#
23 S1_OE# A19 a9 b9 B19 S2_OE# 23 S1_VPP
S1_CE2# A18 B18 S2_CE2#
23 S1_CE2# a42 S2_CE2# 23
1
S1_A10 b42 S2_A10
A17 a8 b8 B17
A16 B16 C531 C539
S1_D15 GND GND S2_D15 .01UF 4.7UF_25V_1206
A15 a41 b41 B15
S1_CE1# S2_CE1#
2
23 S1_CE1# A14 a7 b7 B14 S2_CE1# 23
S1_D14 A13 B13 S2_D14
S1_D7 a40 b40 S2_D7
A12 a6 b6 B12
S1_D13 A11 B11 S2_D13
S1_D6 a39 b39 S2_D6
A10 a5 b5 B10
A9 GND GND B9 S2_VPP
S1_D12 A8 B8 S2_D12
a38
1
S1_D5 b38 S2_D5
A7 a4 b4 B7
S1_D11 A6 B6 S2_D11 C526 C514
S1_D4 a37 b37 S2_D4 C582 .01UF 4.7UF_25V_1206
A5 a3 b3 B5
S1_CD1# S2_CD1# S1_CD1# 1
2
23 S1_CD1# A4 a36 b36 B4 S2_CD1# 23 2
S1_D3 A3 B3 S2_D3 1000PF
a2 b2
A2 a35 b35 B2
C680
A1 a1 b1 B1
S1_CD2# 1 2
78
79
80
81
1000PF
PCMC154PIN
78
79
80
81
C683
S2_CD1# 1 2
1000PF
C581
4
S2_CD2# 1 2 4
1000PF
Title
Compal Electronics, inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1012
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Custom 401200 1B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date: Friday, October 19, 2001 Sheet 24 of 45
A B C D E
A B C D E
+3V_ALW JP7
DL@22PF RJ45_TX+ L37 1 2 DL@0_0805 TX+_CON 1
R309 36 LAN_TX+ 1
2 1 LAN_X1 1 2 VCCR_LAN LAN_TD+ 1 2 LAN_TD- RJ45_TX- L38 1 2 DL@0_0805 TX-_CON 2
36 LAN_TX- 2
+ + L45 DL@4.7UH DL@100_1% 3 3
1
C457 + 4
X2 C517 C466 C490 C477 C468 C472 C488 C487 LAN_RD+ 1 R308 2 LAN_RD- RJ45_RX+ L41 4
36 LAN_RX+ 1 2 DL@0_0805 RX+_CON 5 5
DL@4.7UF_10V_0805 DL@4.7UF_10V_0805
DL@.1UFDL@.1UFDL@.1UFDL@.1UF DL@.1UF DL@4.7UF_10V_0805 DL@100_1% RJ45_RX- L42 1 2 DL@0_0805 RX-_CON 6
36 LAN_RX- 6
2
DL@25MHZ
C458 @HEADER 6
25
36
40
12
14
17
19
23
1
2
7
9
2 1 LAN_X2
C535 R339
VCCA2
1 1
VCC
VCC
VCCR
VCCR
VCCP
VCCP
VCCA
VCCT
VCCT
VCCT
VCCT
DL@22PF 2 1 2 1 JP12
MOD_RING
@10PF @33 MOD_TIP 1
KIN_CLK LAN_TD+ U27 2
17 LAN_JCLK 39 JCLK TDP 10
+3V_ALW KIN_RST 42 11 LAN_TD-
17 LAN_RSTSYNC JRSTSYNC TDN
1
KIN_TXD2 45 LAN_RD+ 1 16 RX+_CON HEADER 2
17 LAN_TXD2 JTXD[2] RD+ RX+
1
KIN_TXD1 44 15 LAN_RD+ LAN_RD- 2 15 RX-_CON C393 C394
17 LAN_TXD1 JTXD[1] RDP RD- RX-
TP_LAN_ADV 1 2 TP_LAN_TOUT R347 KIN_TXD0 43 16 LAN_RD- 3 14 1000PF_1206_2KV 1000PF_1206_2KV
17 LAN_TXD0 JTXD[0] RDN CT CT
DL@100K KIN_RXD2
2
R338 @0 17 LAN_RXD2 37 JRXD[2] 4 NC NC 13
KIN_RXD1 35 5 R306 1 2 DL@619_1% 5 12
17 LAN_RXD1 KIN_RXD0 JRXD[1] RBIAS100 R304 1 NC NC
34 JRXD[0] Kinnereth RBIAS10 4 2 DL@549_1% 6 CT CT 11
17 LAN_RXD0 LAN_TD+ TX+_CON
2
7 TD+ TX+ 10
If LAN is enable, 32 LAN_ACTLED# LAN_TD- 8 9 TX-_CON
LAN_TCK TP_LAN_ADV ACTLED# TD- TX-
PM_LANPWROK 41 ADV10 SPDLED# 31
1
LAN_TI LAN_TCK 30 27 LAN_LILED#
waits for PM_PWROK LAN_EX LAN_TI ISOL_TCK LILED# C459 C460 DL@H0013
28 ISOL_TI
to go high and stays high in S3 LAN_TESTEN LAN_EX 29 DL@1000PF @.01UF R272 R271
TP_LAN_TOUT ISOL_TEX LAN_X2 DL@75_1% DL@75_1%
2
26 TOUT X2 47
LAN_TESTEN 21 46 LAN_X1
TESTEN X1 LAN_GND
2
1
VSSA2
1
VSSR
VSSR
VSSP
VSSP
VSSA
2 Q42 C408
VSS
VSS
VSS
VSS
VSS
17,29 PM_LANPWROK
G DL@2N7002
= LAN_RST# S DL@1000PF_1206_2KV
DL@82562ET
3
2
13
18
24
48
33
38
20
22
U29
3
6
2 2
JP8
RJ45_TX+ 1 13
TX+ GND 0
Layout note :
RJ45_TX- 2 R30 LAN_LILED#
TX- GRN_LED_N
Cassis LANGND CATHODE1 15
RJ45_RX+ 3 LED1_GRNN
should cover part RX+ R39 @0
LED1_GRNN 37
of U22. 4
Green Led +3V_SW
N/C
5 16 GRN_LED_P +3V_ALW
N/C ANODE1 R257 330 GRN_LED_P R379 @100K
3 RJ45_RX- 3
6 RX- ORE_LED_P
7 R546 @100K
N/C R368 0 LAN_ACTLED#
8 17 ORE_LED_N
N/C CATHODE2 LED2_YELN
LED2_YELN 37
MOD_RING R387 @0
9
Orange Led
N/C
1
VH1 10 18 ORE_LED_P
1
11 TIP
MOD_TIP
2
12 N/C GND 14
R258 R259
75_1% 75_1%
RJ-45 & RJ-11
LAN_GND
GRN_LED_N
4
GRN_LED_P 4
ORE_LED_N
ORE_LED_P
1
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1012
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Custom 401200 1B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date: Friday, October 19, 2001 Sheet 25 of 45
A B C D E
A B C D E
+5V_ALW
5VAUD_GATE
U59
1
C291
2
1 2
22UF_10V_1206 1 7
16V Cnoise ERR# R592 30K_1%
1
C160 GD1 2 1 2 6 ADJ1 1 2
DELAY SEN/ADJ
1
1
C555 C170 C169 R563 10K
+
1
GD0 2 1 3 5 +5V_AMP
1000PF .1UF .1UF 4.7UF_10V_0805 R564 10K C299 GND VOUT
1
GD4 C296 C293
2
2
2 1 .1UF
R570 @10K R593 +
2
1 SI9181 1
Place component's .1UF
22UF_10V_1206
2
to ES1988 10K_1% 16V
U12
2
+5V_ALW R404 100K
1
C158 4 8 5VAUD_GATE 1 2
VIN SD# +5V_SW
.01UF 1 7
PCI_AD[0..31] Cnoise ERR# R594 @30K_1%
2
17,22,23,37 PCI_AD[0..31]
17,22,23,37 PCI_C/BE#[0..3] PCI_C/BE#[0..3] 2 6 ADJ2 1 2
DELAY SEN/ADJ
1
+3V_ALW C167 3 5
.1UF GND VOUT +5V_AMP R376 1K
1
C149 ESS_VOL_UP#
2
29 EC_VOL_UP# 1 2
2 1 SI9181 R595
R565 @100K R115 1 2 .1UF
100K R572 10K R377 1K
2
37 MD_SYNC
29 MIC_GAINLOW# @10K_1% 1 2 1 2 ESS_VOL_DW#
C182 10PF 29 EC_VOL_DW#
2
37 MD_BITCLK 2 1
1
NPO R114 22
37 MD_SDATAO MD_SDATAI 37
R110 ESS_VOL_UP#
MD_RST# 37
Y1 1M ESS_VOL_DW#
49.152 MHz +3V_SW
GD4
C219 R331 10K
GD1
GD0
2
2 1 2 1
C166 33PF R106 0 @33PF
1
NPO
2
L15 U15
46
45
44
43
42
49
48
47
63
62
61
60
56
53
52
51
50
59
85
84
39
2 ES1988 +5V_AMP +5V_AMP 2
LK1608-1R0K
GD0
GPIO10 / SCLK2
GPIO8 / SDI2
GPIO15 / GD7
GPIO14 / GD6
GPIO13 / GD5
GPIO9 / SDFS2
GPIO1 / RXD
GPIO11 / SDO2 / VauxD
GPIO2 / TXD
CLKRUN# / ECS
GD1 / EDOUT
57 OSCI VCC 90
2
58 OSCO VCC 41
C176 1500PF 12
NPO VCC
1
64 C525
27 MONO_IN PC_BEEP
2 1 72 C518
R128 6.8K2 AVDD1 .1UF
37 MOD_AUDIO_MON 1 1 2 65 PHONE AVDD2 83
R138 2 6.8K C218 1UF_0603 1 10UF_10V_1206
2
37 MOD_MIC 1 2 81 MONO_OUT
2 1 R175 6.8K C270 1UF_0603
R174 6.8K 2 1 69 74
27 MIC_OUT+ MIC VREF AUD_VREF
R371 0
CDROM_AGND 67
CD_L_R CD_GND
1 2 66 CD_L REQ# 92 2 1 PCI_REQ#3 17,19
CD_R_R C228 1UF_0603 1 2 68 91 2R172 0 1
C245 1UF_0603 CD_R GNT# R171 0 PCI_GNT#3 17 +5V_AMP
36 DOCK_LIN_L 2 R173 1 1 2 70 88 CLK_PCI_AUD CLK_PCI_AUD 8
R145 1 6.8K C273 1UF_0603 1 LINE_IN_L PCICLK
36 DOCK_LIN_R 2 2 71 LINE_IN_R
6.8K 2 R178 1 C247 1UF_0603 87 2 1 INT_PIRQD# 17,19,37
INT#
1
2 R160 1 6.8K 1 2 79 LINE_OUT_L RST# 86 R370 0
PCI_RST# 9,15,17,21,22,23,29,31,37
6.8K C597 1UF_0603 80 R95
28 LEFT_EQ LINE_OUT_R
28 RIGHT_EQ 1 2 C/BE3# 1 PCI_C/BE#3 17,22,23,37
C596 1UF_0603 13 100_0805
C/BE2# PCI_C/BE#2 17,22,23,37
75 AFILT1 C/BE1# 20 PCI_C/BE#1 17,22,23,37
2
76 AFILT2 C/BE0# 30 PCI_C/BE#0 17,22,23,37
77 VCM
1
1
C508 D Q17
78 VREFADC PME# / SPDIFO / VOLDN# 54 AUD_PME# 30
1
73 18 PCI_STOP# 17,19,22,23,37 S
1UF_0603 1000PF .1UF .1UF AVSS1 STOP#
2
3
82 AVSS2 DEVSEL# 17 PCI_DEVSEL# 17,19,22,23,37
89 GND TRDY# 16 PCI_TRDY# 17,19,22,23,37
C576 C585 40 15
GND IRDY# PCI_IRDY# 17,19,22,23,37
10UF_10V_1206 10UF_10V_1206 21 14
GND FRAME# PCI_FRAME# 17,19,22,23,37
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
R139 3 55
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
100
21 INT_CD_L 2 1
38
37
36
35
34
33
32
31
29
28
27
26
25
24
23
22
11
10
99
98
97
96
95
94
93
9
8
7
6
5
4
R129 6.8K
2 1
2 1 CD_R_R Place closely to ES1988 +3V_ALW AUD_VREF
21 INT_CD_R
R141 6.8K CLK_PCI_AUD
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
R143
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
6.8K
1
R169
+5V_SW C178 C179 C267 C274
@10 1UF_0603 .01UF 1UF_0603 .01UF
2
+3V_SW +3V_SW
12
C278
+ +
1
2
@20K @20K
4
C771 @10UF_16V_1206 C772 @10UF_16V_1206 4
2
2
+
16V 16V
1
R165
1 2 1 2 CDROM_AGND R575 R576
21 CD_AGND C252 .1UF_0603 @20K @20K
6.8K
Compal Electronics, inc.
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1012
6.8K
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 401200 1B
1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date: Friday, October 19, 2001 Sheet 26 of 45
A B C D E
A B C D E
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
+5V_AMP AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
3
S
G
2 Q25
30 EC_MUTE
+ + 2N7002 Layout note:
C506 C663 D
Trace width=15 mils.
1
150UF_TPB_6.3V U21 C635 C648 150UF_TPB_6.3V
1 R208 1.SPK_R+/-,SPK_L+/-
13
18
2 +12V_ALW
3
8
1000PF .1UF 100K 2.SPKR+/-,SPKL+/-
3.LINEOUT_L,LINEOUT_R
VDD1
VDD2
VDD3
VDD4
2
Q28
G
1 2N7002 1
R448 C665 12 SPK_R+ 1 3 SPKR+
ROUT+ SPKR+ 33
RIGHT 2 1 R_IN 1 2 17
S
28 RIGHT RLINEIN
0
+
LINEOUT_R 33,36
2.2UF_16V_0805 19 SPK_R- C333 150UF_TPB_6.3V
ROUT- SPKR- 33
R457 C679 Q26 2N7002
LEFT 2 1 L_IN 1 2 15 2 SPK_L+ 1 3 SPKL+
S
28 LEFT LLINEIN LOUT+ SPKL+ 33
0
1
2.2UF_16V_0805
+
LINEOUT_L 33,36
9 C317 150UF_TPB_6.3V
G
R447 R460 LOUT- SPK_L-
2
SPKL- 33
@10K @10K
+ C775
2
2
DIS_ADJVOL 30
10UF_16V_1206
16V +5V_ALW
HPS 4 6 1 R217 2
HPS R_UP/DOWN#
1K
1
5 U58
L_UP/DOWN# 7
4 2 ADJVOL_UP/DW# 30
R439 14
GAINSEL
30 EC_MUTE 1 2
74AHCT1G125GW
3
R228
GND1
GND2
GND3
GND4
100K 5 16 1 2
MODE SVR +5V_AMP
100K +3V_MIC
2 2
GAIN_SEL# 28
1
10
11
20
1
R440 1 TDA8552TS Q30 D
1
C634 C628 2 HPS
100K .1UF 2.2UF_16V_0805 2N7002 G
S +3V_MIC R590
2.2K
2
7
8
JP26
2
5
R20 4
2.2K
+5V_ALW
L43 FBM-L10-160808-301 3
1
2
2 6
U61
26 MIC_OUT+ 1 2 1 2 2
4.7UF_10V_0805 3 4 +3V_MIC L12 FBM-L10-160808-301 1
VIN VOUT 1UF_0603
2
1
5 MIC_BP C81 MIC
BP
1
C371 C48 C385
+5V_SW 2 1 MIC_SD# 1 SHDN# GND 2 .1UF FOXCONN JA6033L-101
1
R459 100K 10UF_10V_1206 330PF 330PF
2
C73
2
+3V_ALW +3V_ALW .01UF
@MAX8868_EUK30 2 U62
29 BEEP#
SI9183DT-33
1 5 +3V_MIC
+5V_ALW VIN VOUT
1
+5V_ALW
1
R342
VSS
100K_1% C519 MIC_SD# 3 4 MIC_BP
3 .1UF AVDD_AC97 SD# BP Q40 3
2N7002
2
1
C544
2
2
1
INT_MIC DOCK_MIC
D
14
33 INT_MIC 3 1
DOCK_MIC 36
1
G
MICOFF#
2
33,36 INTMICOFF# 1 2 1 2 +12V_SW
1
+3VALW POWER
+
3
U35
10UF_16V_1206
1
1
C534
R384 R383 R382
2
14
MONO_IN 26
U36B 100K 100K 100K
1
2
23 CB_SPK# 3 4 1 2 1 2 2 1
3 Q43 R346 3 HPS
HPS 28
1UF_0603 560 2SC2411EK 2.4K 2
1
D
+3VALW POWER Q45 R412
7
36 INTSPKOFF# 2 RB425D
G
2N7002 1M
S
+3V_ALW
3
4 4
2
33,36 LINE_OUT_PLUG
14
U36C
74LVC14 C568 R366 D42
5 6 1 2 1 2 1 2
18 ICH_SPKR
Compal Electronics, inc.
1
2
+5V_AMP
2
C620 R406 C309 R191
+5V_AMP
C642 R413
1500PF 560K_1% 470PF 220K_1% 330PF 200K_1%
C600 C595 C633
1
1 1
.1UF 4.7UF_10V_0805 C608 R405 C614 R192 C298 330PF
1
LEFTEQ L_EQ 1 2 1 2 OUT1_L L_EQ 1 2 1 2 OUT2_L L_EQ 1 2 1 2 OUT3_L
140K_1% 220K_1%
1UF_0603 R417
U39
2
1500PF 536HZ 470PF 2230HZ 200K_1% 3410HZ
2
5V
IN1 OUT1 140K_1% +6dB 200K_1% -6dB 200K_1% -6dB
R436 EQ_L_INPUT2 5 4 OUT2_L Q=1.41 Q=0.72 Q=0.707
2K_1% IN2 OUT2
EQ_L_INPUT3 OUT3_L
1
7 IN3 OUT3 6
1
EQ_L_INPUT4 10 11 OUT4_L
IN4 OUT4 EQ_L_INPUT4 EQ_L_INPUT5
EQ_L_INPUT5 12 13 OUT5_L
IN5 OUT5
2
2
2
14 15 C636 R414 C623 R407
IN6 OUT6
EQ1_VREF EQ_IN_L 82PF 301K_1% 220PF 301K_1%
8 9 14
GND
1
1 2 LEFT 27
2
1
7
1
13
R419 C627 C603 LMV801 U22A 75K_1% 127K_1%
2K_1% 1UF_0603 HPS_PLUG 74HCT4066
2
82PF 220PF
2
18299HZ 7646HZ
R422 R416
1
14
EQ_IN_L 11 10 75K_1% +6dB 39.2K_1% +1.45dB
7 Q=1.41 Q=1.59
10UF_10V_1206
12
R442 1 LEFTEQ U22B
1
2 2 2
26 LEFT_EQ 0 GAIN_SEL# 74HCT4066
2 R441 1
@33K
2 R454 1
@33K
2 R445 1 RIGHTEQ
26 RIGHT_EQ
0
2
2
2
C282 R189 C310 R193 C323 R202
1
C285 R184 C283 R210 C300 R214 C324
1
+5V_AMP RIGHTEQ R_EQ 1 OUT1_R R_EQ OUT2_R R_EQ OUT3_R
2 1 2 1 2 1 2 1 2 1 2
C292 C294 140K_1% 220K_1% 200K_1%
1UF_0603
2
.1UF 4.7UF_10V_0805 1500PF 536HZ 470PF 2230HZ 330PF 3410HZ
R183 R207 R215
140K_1% +6dB 200K_1% -6dB 200K_1% -6dB
U18 Q=1.41 Q=0.72 Q=0.707
2
2
EQ_R_INPUT1 OUT1_R
1
3 1
5V
2
EQ_R_INPUT4 10 11 OUT4_R
IN4 OUT4
2
C329 R216 C321 R203
EQ_R_INPUT5 12 13 OUT5_R +5V_AMP
IN5 OUT5 C332 82PF 301K_1% 220PF 301K_1%
1
14 IN6 OUT6 15
R219 C331 R205 C322
1
EQ2_VREF 8 9 EQ_IN_R R_EQ OUT4_R R_EQ OUT5_R
.1UF 14 1 2 1 2 1 2 1 2
GND
2
U22C 82PF 18299HZ 220PF 7646HZ
16
1
14
EQ_IN_R
1
1
8 9
7
U22D
10UF_10V_1206 74HCT4066
6
GAIN_SEL#
27 GAIN_SEL#
4 4
Title
Compal Electronics, inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1012
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Custom 401200 1B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date: Friday, October 19, 2001 Sheet 28 of 45
A B C D E
A B C D E
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
.1UF EC_AVCC AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
+3V_ALW +3V_ALW +RTCVCC
1 2 EC_3VDD DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
+3V_SW
2
C742 C734 C733 C732 R488 @0 C723
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
+3V_ALW 1 2
123
136
157
166
161
.1UF 1000PF C697 C695 1UF_0603 C640 .01UF
16
34
45
95
R489 0
U46 TEMP_GMCH ECAGND
1
1 2
22UF_10V_1206 22UF_10V_1206 .1UF
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VDD
AVCC
VBAT
C641 .01UF
2
L48
1 2 BATT_TEMP 1 2
+3V_ALW EC_AVCC
BLM11A20
1
C637 C632 7 81 BATT_TEMP
17,19,23,31 INT_SERIRQ SERIRQ AD0 BATT_TEMP 40
8 LDRQ AD1 82 I/O Address
L49 .1UF 1000PF
17,31 LPC_FRAME# 9 83 BADDR1-0 Index Data
LFRAME AD2
ECAGND TEMP_GMCH 0 0 2E 2F
2
1 1 2 17,31 LPC_AD0 15 LAD0 AD3 84 TEMP_GMCH 35 1
BLM11A20 14 Host interface 87 0 1 4E 4F
17,31 LPC_AD1 LAD1 IOPE0AD4 LI/NIMH# 40,41
17,31 LPC_AD2 13 88 * 1 0 (HCFGBAH, HCFGBAL) (HCFGBAH, HCFGBAL)+1
LAD2 IOPE1/AD5
19,34 EC_RST# 17,31 LPC_AD3 10 LAD3 IOPE2/AD6 89 1 1 Reserved
CLK_LPC_EC 18 AD Input 90
R458 8 CLK_LPC_EC LCLK IOPE3/AD7
+3V_ALW 19 LREST1 DP/AD8 93
@100K 22 SMI DN/AD9 94 ENV0 ENV1 TRIS
1
D
23 PWUREQ
R467 PC7 2 Q50 99 IRE 0 0 0
+3V_ALW DA0 DAC_BRIG 33
100K G 2N7002 100
DA output DA1 EC_EN_FAN 35
S 17 EC_SCI#
EC_SCI# 31 IOPD3/ECSCI DA2 101 EC_EN_FAN2 35 * OBD 0 1 0
For REV.A only
3
DA3 102
DEV 1 0 0
RB751V 5 32
GA20/IOPB5 IOPA0/PWM0 INVT_PWM 33
17 GATE20
GATE20 2 1 6 33 BEEP# 27
PROG 1 1 0
KBRST/IOPB6 IOPA1/PWM1
IOPA2/PWM2 36
D29 KSI[0..7] PWM 37
34 KSI[0..7] or IOPA3/PWM3 ACOFF 41
RB751V 34 KSO[0..15] KSO[0..15] KSI0 71 PORTA
IOPA4/PWM4 38 PM_BATLOW# 17,19
SHBM=1: Enable shared memory with host BIOS
KBSIN0
17 KBRST#
KBRST# 2 1 KSI1 72 KBSIN1 IOPA5/PWM5 39 EC_ON 34
TRIS=1: While in IRE and OBD, float all the
KSI2 73 40
KSI3 KBSIN2 IOPA6/PWM6 EC_LID_OUT# 17 signals for clip-on ISE use
D14 74 43 @0 R443
KBSIN3 IOPA7/PWM7 PM_LANPWROK 17,25
ADB[0..7] KSI4 77
ADB[0..7] 30 KBSIN4 +3V_ALW
CLK_LPC_EC KSI5 78 153
KBSIN5 IOPB0/URXD EC_VOL_UP# 26
KBA[0..18] KSI6 79 154
KBA[0..18] 30 KBSIN6 IOPB1/UTXD EC_VOL_DW# 26
1
KSI7 80 Key matrix scan 162
KBSIN7 IOPB2/USCLK EN_WOL# 37
R468 163 EC_SMC_1 10K R449
PORTB IOPB3/SCL1 EC_SMC_1 30,40
KSO0 49 164 EC_SMD_1 KBA1 (ENV1)
KBSOUT0 IOPB4/SDA1 EC_SMD_1 30,40
RP21 @10 KSO1 50 165 PCI_RST#
KBSOUT1 IOPB7/RING/PFAIL/LRESET2 PCI_RST# 9,15,17,21,22,23,26,31,37
10 1 KBD_DATA KSO2 51 @10K R507
+5V_SW KBSOUT2
KBD_CLK KSO3 KBA2 (BADDR0)
12
2 9 2 52 168 2
KBSOUT3 IOPC0 PBTN_OUT# 17
8 3 TP_DATA C688 KSO4 53 169 EC_SMC_2
KBSOUT4 IOPC1/SCL2 EC_SMC_2 5,33,36
PS2_DATA 7 4 TP_CLK KSO5 56 170 EC_SMD_2 EC_SMD_2 5,33,36
PS2_CLK @15PF KSO6 KBSOUT5 IOPC2/SDA2 KBA3
6 5 +5V_SW 57 KBSOUT6 IOPC3/TA1 171 FAN_SPEED 35 (BADDR1)10K R506
KSO7 PORTC PCI_WAKE_UP#
2
1
SELIO# 2 7 EC_SMC_2 2 7 PS2_CLK 114 128 KBA4 7SH08 C14
34,36 PS2_CLK PSCLK2/IOPF2 PORTH IOPH4/A4/TRIS
FRD# 3 6 EC_SMD_1 3 6 PS2_DATA 115 131 KBA5
34,36 PS2_DATA PSDAT2/IOPF3 PS2 interface IOPH5/A5/SHBM
EC_SMI# 4 5 EC_SMC_1 4 5 TP_CLK 116 132 KBA6 .1UF
33 TP_CLK PSCLK3/IOPF4 IOPH6/A6
TP_DATA KBA7
2
33 TP_DATA 117 PSDAT3/IOPF5 IOPH7/A7 133
8P4R-10K 8P4R-10K LID_SW# 118
30,33 LID_SW# PSCLK4/IOPF6
119 138 ADB0
26 MIC_GAINLOW# PSDAT4/IOPF7 IOPI0/D0 ADB1
IOPI1/D1 139
3 ADB2 3
IOPI2/D2 140
141 ADB3
CRY1 PORTI IOPI3/D3 ADB4
158 32KX1/32KCLKOUT IOPI4/D4 144
145 ADB5
CRY2 IOPI5/D5 ADB6
160 32KX2 IOPI6/D6 146
147 ADB7
IOPI7/D7
150 FRD#
PORTJ-1 IOPJ0/RD FRD# 30
151 FWR#
IOPJ1/WR0 FWR# 30
152 SELIO#
SELIO SELIO# 30
EC_SMI# 62 41
17 EC_SMI# IOPJ2/BST0 IOPD4 SCROLLED# 16
63 IOPJ3/BST1 IOPD5 42 NUMLED# 16
2 1 69 PORTD-2 54
19,22,23,24 G_RST# IOPJ4/BST2 PORTJ-2 IOPD6 CAPSLED# 16
R528 @0 70 55
17,19 ICH_SWI# IOPJ5/PFS IOPD7
75 IOPJ6/PLI
76 143 KBA8
8,17 PM_SLP_S1# IOPJ7/BRKL_RSTO IOPK0/A8 KBA9
IOPK1/A9 142
KBA10 JP30
38 SYSON 148 IOPM0/D8 IOPK2/A10 135
149 PORTK 134 KBA11 1
32,38,39 EC_SUSP# IOPM1/D9 IOPK3/A11 1 +3V_ALW
155 130 KBA12 2 EC_TINIT#
42 VR_ON IOPM2/D10 PORTM IOPK4/A12 2
156 129 KBA13 3 EC_TCK
41 TRICKLE IOPM3/D11 IOPK5/A13/BE0 3
3 121 KBA14 4 EC_TDO
42 VTT_ON IOPM4/D12 IOPK6/A14/BE1 4
4 120 KBA15 5 EC_TDI
5,8 VTT_PWRGD# IOPM5/D13 IOPK7/A15/CBRD 5
27 6 EC_TMS
15 ENBLT IOPM6/D14 6
28 113 KBA16 7
15 BKOFF# IOPM7/D15 IOPL0/A16 KBA17 7 EC_VOL_UP#
IOPL1/A17 112 8 8
FSEL# 173 PORTL 104 KBA18 9 EC_VOL_DW#
4 30 FSEL# SEL0 IOPL2/A18 9 4
CRY1 174 103 10 EN_WOL#
R498 20M SEL1 IOPL3/A19 10
47 CLK IOPL4/WR1 48 FSTCHG 41
1 2 CRY2
@96212-1011S
AGND
R501
GND1
GND2
GND3
GND4
GND5
GND6
GND7
NC10
2 1
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
120K
Compal Electronics, inc.
1
96
11
12
20
21
85
86
91
92
97
98
10PF 10PF
SCHEMATIC, M/B LA-1012
2
INPUT OUTPUT
+5V_ALW +5V_ALW
+3V_ALW ADB[0..7] C753
29 ADB[0..7]
C755 1 2
1
1 2 29 KBA[0..18] KBA[0..18]
R521 .1UF
100K .1UF
20
U51
PCMRST#
20
U53 ADB0 3 2
VCC
D0 Q0 EC_GRST# 19
ADB0 ADB1
2
2 18 4 5
VCC
+3V_ALW 1A1 1Y1 D1 Q1 BT_RST# 20
1 M_SEN# 4 16 ADB1 ADB2 7 6 1
16,36 M_SEN# 1A2 1Y2 +3V_ALW D2 Q2 BT_DETACH 20
CONA# 6 14 ADB2 ADB3 8 9
36 CONA# 1A3 1Y3 D3 Q3 BT_ON# 20
BT_PRES# 8 12 ADB3 C747 ADB4 13 12 1
20 BT_PRES# 1A4 1Y4 D4 Q4 TP2
R582 1 2 100K 11 9 ADB4 1 2 ADB5 14 15
2A1 2Y1 U57A D5 Q5 EC_MUTE 27
13 7 ADB5 ADB6 17 16 1
33 TPAD_ON/OFF# 2A2 2Y2 74LVC32 D6 Q6 TP3
1394_PME# 15 5 ADB6 .1UF 14 ADB7 18 19 1
22 1394_PME# 2A3 2Y3 D7 Q7 TP4
BT_WAKE_UP 17 3 ADB7 KBA2 1
20 BT_WAKE_UP 2A4 2Y4
3 11
GND
SELIO# LARST# CLK
1 2 1
GND
1G CLR
19 2G 7
+3V_ALW 74HCT273
10
74LVC244
10
U57B
74LVC32 C726
14
KBA1 R516
4 +3V_ALW 1 2 1 2
6 +3V_ALW 20K
SELIO# 5 RP34 1UF_0603
29 SELIO# M_SEN#
7 1 8
+3V_ALW CONA# +5V_ALW
2 7
C754 3 6 C748
29,33 LID_SW#
1 2 BT_PRES# 4 5 1 2
20
20
U54 U50
2 18 ADB0 +3V_ALW ADB0 3 Q0 2
VCC
VCC
33 USER_BTN1# 1A1 1Y1 D0 TPAD_LED# 33
4 16 ADB1 ADB1 4
+3V_ALW 33 USER_BTN2# 1A2 1Y2 ADB2 C685 ADB2 D1 Q1 5
33 USER_BTN3# 6 1A3 1Y3 14 7 D2 Q2 6 DIS_ADJVOL 27
8 12 ADB3 1 2 ADB3 8
2 33 USER_BTN4# 1A4 1Y4 ADB4 ADB4 D3 Q3 9 ADJVOL_UP/DW# 27 2
33,36 SUSPBTN# 11 2A1 2Y1 9 13 D4 Q4 12 1 TP5
R583 1 2 100K 13 7 ADB5 +3V_ALW .1UF ADB5 14
R584 1 2A2 2Y2 ADB6 U43A ADB6 D5 Q5 15 1 TP6
2 100K 15 2A3 2Y3 5 R548 100K 17 D6 Q6 16 1 TP7
R585 1 ADB7 1394_PME# 1 74LVC32 ADB7
2 100K 17 2A4 2Y4 3 2 14 18 D7 Q7 19 1 TP8
KBA4 1
1 3 11
GND
GND
+3V_ALW 1G +3V_ALW SELIO# LARST# CLK
19 2G 2 1 CLR
RP22 7
U57D 74LVC244 AUD_PME# 1 8 74HCT273
10
10
14 74LVC32 PCM_PME# 2 7
KBA3 12 MDM_PME# 3 6
11 LAN_PME# 4 5
SELIO# 13
7 8P4R-100K
R532 100K U42
+3V_ALW 1 2 BT_WAKE_UP
C749 VCC_FLASH 1 2 KBA11 1 32 FRD#
+5V_ALW A11 OE#
1 2 R499 @0 KBA9 2 31 KBA10
KBA8 A9 A10 FSEL#
U38 1 2 +3V_ALW 3 30
+3V_ALW .1UF R508 0 KBA13 A8 CE# ADB7
4 A13 DQ7 29
1
KBA18 KBA14 ADB6
20
2
U52 KBA16 2 31 FWE# C720 + C718 VCC_FLASH KBA17 6 27 ADB5
R586 100K ADB0 KBA15 A16 WE* KBA17 FWE# A17 DQ5 ADB4
1 2 2 18 3 30 7 26
VCC
R587 100K 1A1 1Y1 ADB1 KBA12 A15 A17 KBA14 .1UF WE# DQ4 ADB3
1 2 4 1A2 1Y2 16 4 A12 A14 29 8 VCC DQ3 25
R588 100K ADB2 KBA7 KBA13 KBA18
1
1 2 6 1A3 1Y3 14 5 A7 A13 28 9 A18 VSS 24
R589 1 2 100K 8 12 ADB3 KBA6 6 27 KBA8 4.7UF_10V_0805 KBA16 10 23 ADB2
AUD_PME# 1A4 1Y4 ADB4 KBA5 A6 A8 KBA9 KBA15 A16 DQ2 ADB1
26 AUD_PME# 11 2A1 2Y1 9 7 A5 A9 26 11 A15 DQ1 22
PCM_PME# 13 7 ADB5 KBA4 8 25 KBA11 KBA12 12 21 ADB0
23 PCM_PME# 2A2 2Y2 A4 A11 A12 DQ0
MDM_PME# 15 5 ADB6 KBA3 9 24 FRD# KBA7 13 20 KBA0
3 37 MDM_PME# 2A3 2Y3 A3 OE* A7 A0 3
LAN_PME# 17 3 ADB7 KBA2 10 23 KBA10 KBA6 14 19 KBA1
37 LAN_PME# 2A4 2Y4 A2 A10 A6 A1
KBA1 11 22 FSEL# KBA5 15 18 KBA2
+3V_ALW KBA0 A1 CE* ADB7 KBA4 A5 A2 KBA3
1 12 21 16 17
GND
1
U40 R206
1
KBA11 FRD# R209 100K
1 A11 OE# 32 FRD# 29
KBA9 2 31 KBA10 +3V_ALW
+5V_ALW +5V_ALW KBA8 A9 A10 FSEL# 100K
2
3 A8 CE# 30 FSEL# 29
KBA13 4 29 ADB7
A13 DQ7
2
VCC_FLASH KBA14 ADB6 U43B Q27
G
2
5 A14 DQ6 28
1
S
.1UF 100K KBA18 VCC DQ3
9 A18 VSS 24 5
U55 KBA16 ADB2
2
10 A16 DQ2 23 7
KBA15 ADB1
2
KBA4 16 17 KBA3
R526 NM24C164 R515 A4 A3
Title
Compal Electronics, inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1012
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Custom 401200 1B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date: Friday, October 19, 2001 Sheet 30 of 45
A B C D E
5 4 3 2 1
+3V_SW
14
39
63
88
U47
VDD
VDD
VDD
VDD
D +3V_SW D
LPC_AD0 15 52 LPD0
17,29 LPC_AD0 LAD0 PD0/INDEX# LPD0 32,36
LPC_AD1 16 50 LPD1
17,29 LPC_AD1 LAD1 PD1/TRK0# LPD1 32,36
LPC_AD2 17 48 LPD2
17,29
17,29
LPC_AD2
LPC_AD3
LPC_AD3 18
LAD2
LAD3
PC87391 PD2/WP#
PD3/RDATA# 46 LPD3
LPD2
LPD3
32,36
32,36
1
45 LPD4
PD4/DSKCHG# LPD4 32,36
R512 CLK_LPC_SIO 8 44 LPD5
8 CLK_LPC_SIO LCLK PD5/MSEN0 LPD5 32,36
PCI_RST# 9 43 LPD6
9,15,17,21,22,23,26,29,37 PCI_RST# LRESET# PD6/DRATE0 LPD6 32,36
100K LPC_FRAME# 12 42 LPD7
17,29 LPC_FRAME# LFRAME# PD7/MSEN1 LPD7 32,36
LPC_DRQ#1 11 R479 100K
17 LPC_DRQ#1 LDRQ#
2
17,29 PM_SUS_STAT# 1 2 7 LPCPD# PNF 35 2 1 +3V_SW
R511 @0 PM_CLKRUN# 6 36 LPTSLCT
17,19,22,23,29,37 PM_CLKRUN# CLKRUN# SLCT/WGATE# LPTSLCT 32,36
SERIRQ 10 37 LPTPE
VDD_391 17,19,23,29 INT_SERIRQ SERIRQ PE/WDATA# LPTPE 32,36
1 2 19 40 LPTBUSY
+3V_SW SMI# BUSY_WAIT#/MTR1# LPTBUSY 32,36
R509 @10K 41 LPTACK#
ACK#/DR1# LPTACK# 32,36
.1UF 4.7UF_10V_0805 CLK_SIO14 20 47 LPTSLCTIN #
8 CLK_SIO14 CLKIN SLIN#_ASTRB#/STEP# LPTSLCTIN # 32,36
49 LPTINIT#
INIT#/DIR# LPTINIT# 32,36
1
1
C668 C669 C670 C671 51 LPTERR #
ERR#/HDSEL# LPTERR# 32,36
DSKCHG# 21 53 LPTAFD #
33 DSKCHG# DSKCHG# AFD#_DSTRB#/DENSEL LPTAFD # 32,36
.1UF 1000PF_ 50V HDSEL# 22 54 LPTSTB#
33 HDSEL# HDSEL# STB#_WRITE# LPTSTB# 32,36
RDATA#
2
2 23
33 RDATA# RDATA#
WP # 24
33 WP # WP#
TRACK0 # 25 55 DCDA#
33 TRACK0 # TRK0# DCD1# DCDA# 32
WGATE# 26 56 DSRA#
33 WGATE# WGATE# DSR1# DSRA# 32
WDA TA# 27 57 RXDA
33 WDA TA# WDATA# SIN1 RXDA 32
STEP# 28 58 RTSA#
33 STEP# SETP# RTS1#/TEST RTSA# 32
FDDIR# 29 59 TXDA
33 FDDIR# DIR# SOUT1/XCNF0 TXDA 32
DRV0# 30 60 CTSA#
16 DRV0# DR0# CTS1# CTSA# 32
CLK_LPC_SIO CLK_SIO14 MTR0# 31 61 DTRA#
33 MTR0# MTR0# DTR1#_BOUT1/BADDR DTRA# 32
INDEX# 32 62 RIA#
33 INDEX# INDEX# RI1# RIA# 32
1
C 3MODE# C
33 3MODE# 33 DENSEL
34 RP24 8P4R_10 0K
R503 R504 DRATE0/IRSL2
72 DR1# DCD2# 74 8 1
@33 @33 73 75 7 2
MTR1#/DRATE0 DSR2# +3V_SW
84 MTR1# SIN2 76 6 3
2
RTS2# 77 5 4
1 NC SOUT2 78
1
C721 C722 2 79
NC CTS2#
3 NC DTR2#_BOUT2 80
@15PF @15PF 4 81 2 1
NC RI2# R469 100K
2
65 NC
82 NC
83 NC IRTX 70 IRTXOUT 32
85 NC IRRX1 69 IRRX 32
86 NC IRRX2_IRSL0 68 IRMODE 32
87 NC IRSL1 67
90 NC IRSL2/DR1# 71
91 NC IRSL3/PWUREQ# 66
92 NC
93 NC
94 NC WDO# 5
95 NC
96 NC
97 NC
98 NC
99
VSS
VSS
VSS
VSS
NC
100 NC
PC8739 1
13
38
64
89
B BADDR PULL-UP :4E B
Signal Pin # Description BADDR PULL-DOWN:2E
(DEFAULT) +3V_SW
BADDR 61 BASE Address Selection
"0": 2E~2F (Default) DTRA# 1 2
R450 @10K
"1": 4E~4F
Title
Compal Electronics, inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL SCHEMATIC, M/B LA-1012
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE 401200
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date: Friday, October 19, 2001 Sheet 31 of 45
5 4 3 2 1
A B C D E
PARALLEL
+5V_PRN
+5V_PRN
1 2 LPTINIT#_1
31,36 LPTINIT#
1 R249 33 D4 1
1
+5V_SW 2 1
1 2 LPTSLCTIN#_1 C364 C13
31,36 LPTSLCTIN#
1
R253 33 RB420D 4.7UF_10V_0805 .1UF
R2
2
+5V_SW 2.7K
RP12
LPTSLCTIN#_1 1 10 JP1
LPTINIT#_1 LPTACK# LPTCN-25
2
2 9
LPTERR# 3 8 LPTBUSY R3 33 CP12
AFD#/3M# 4 7 LPTPE LPTSTB# 1 2 w=10mils 1 AFD#/3M# 1 8
31,36 LPTSTB#
5 6 LPTSLCT LPTAFD# 1 2 AFD#/3M# 14 LPTERR# 2 7
+5V_SW 31,36 LPTAFD#
FD0 R252 33 2 LPTINIT#_1 3 6
10P8R_2.7K LPTERR# 15 LPTSLCTIN#_1 4 5
+5V_SW 31,36 LPTERR#
FD1 3
RP10 LPTINIT#_1 16 8P4C_220PF
FD0 1 10 FD2 4 CP10
FD1 2 9 FD7 LPTSLCTIN#_1 17 LPTACK# 1 8
FD2 3 8 FD6 FD3 5 LPTBUSY 2 7
FD3 4 7 FD5 18 LPTPE 3 6
5 6 FD4 FD4 6 LPTSLCT 4 5
+5V_SW
19
10P8R_2.7K FD5 7 8P4C_220PF
20 CP1
RP11 FD6 8 FD0 1 8
LPD3 9 8 FD3 21 FD1 2 7
LPD2 10 7 FD2 FD7 9 FD2 3 6
LPD1 11 6 FD1 22 FD3 4 5
LPD0 12 5 FD0 LPTACK# 10
31,36 LPTACK#
2 LPD7 13 4 FD7 23 8P4C_220PF 2
LPD6 14 3 FD6 LPTBUSY 11 CP11
31,36 LPTBUSY
LPD5 15 2 FD5 24 FD4 1 8
LPD4 16 1 FD4 LPTPE 12 FD5 2 7
31,36 LPTPE
25 FD6 3 6
16P8R_33 LPTSLCT 13 FD7 4 5
31,36 LPTSLCT
8P4C_220PF
28
29
LPD[0..7]
LPD[0..7] 31,36
+5V_ALW
SERIAL
+5V_SW
1
+3V_ALW C373
1
3 +3V_SW R1 3
@5.6_1206 + C9 D@.1UF
@10UF_10V_1206
2
1
C372 U25
26
T = 20mil FIR Module R251 D@.1UF D@MAX3243 C375
D@.47UF_16V_0805
2
1 2 28
VCC
100K C1+
T = 20mil V+ 27 1 2
1
C1 C4
2
+ + D3 24 3 1 2
@10UF_10V_1206 @22UF_10V_1206 C1- V-
23 PCM_RI# 1 2 1 2 1 C2+ C362
C363 D@.47UF_16V_0805
2
RB751V
D2 D@.47UF_16V_08052
U1 C2- DTR1#
T = 20mil 37 MODEM_RI# 1 2 31 DTRA# 14 TIN1 TOUT1 9 DTR1# 36
1 13 10 RTS1# CP2
LED_A 31 RTSA# TIN2 TOUT2 RTS1# 36
2 3 T = 12mil IRTXOUT RB751V 12 11 TXD1 TXD1 1 8
LED_C TXD IRTXOUT 31 31 TXDA TIN3 TOUT3 TXD1 36
C3 4 5 T = 12mil IRMODE 19 4 CTS1# CTS1# 2 7
RXD SD IRMODE 31 29 RING# 31 CTSA# ROUT1 RIN1 CTS1# 36
@.1UF 6 7 T = 12mil IRRX RIA# 18 5 RI1# DTR1# 3 6
VCC MODE IRRX 31 31 RIA# ROUT2 RIN2 RI1# 36
8 17 6 RXD1 RI1# 4 5
GND 31 RXDA ROUT3 RIN3 RXD1 36
16 7 DCD1#
31 DCDA# ROUT4 RIN4 DCD1# 36
1
GND 25 3 6
22 RTS1# 4 5
FORCEOFF#
1
D@8P4C_220PF
4
R581 4
100K
2
Title
Compal Electronics, inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1012
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Custom 401200 1B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date: Friday, October 19, 2001 Sheet 32 of 45
A B C D E
A B C D E
+5V_SW
JP17
1 1
2 2
3
FDD Connector 30 TPAD_ON/OFF#
4
3
+5V_SW +5V_SW 30 TPAD_LED# 4
5 5
29 TP_DATA 6 6
1 JP20 7 1
29 TP_CLK 7
1 1 27 27 8 8
INDEX# 2 28 INDEX#
31 INDEX# 2 28
1
3 29 C554 C558 HEADER 8
DRV05V# 4
3 29
30 DRV05V# Layout note :
16 DRV05V# 4 30
5 31 Place capacitors near Floppy connector . 22PF
DSKCHG# 5 31 DSKCHG# 22PF
2
31 DSKCHG# 6 6 32 32
7 7 33 33
8 8 34 34
9 35 +5V_SW
MTR0# 9 35 MTR0#
31 MTR0# 10 10 36 36
11 11 37 37
FDDIR# 12 38 FDDIR#
31 FDDIR# 12 38
1
3MODE# 13 39 3MODE#
31 3MODE# 13 39
STEP# 14 40 STEP# C342 C348 C339 C346
31 STEP# 14 40
15 41 1000PF 10UF_10V_1206 1UF_0603 .1UF
WDATA# 15 41 WDATA# JP19
2
31 WDATA# 16 16 42 42
17 17 43 43 27 SPKR+ 1 1
WGATE# 18 44 WGATE# 2
31 WGATE# 18 44 27 SPKR- 2
19 19 45 45 27 SPKL+ 3 3
TRACK0# 20 46 TRACK0# 4
31 TRACK0# 20 46 27 SPKL- 4
21 47 RP9
WP# 21 47 WP# 3MODE# HEADER 4
31 WP# 22 22 48 48 6 5 +5V_SW
1
23 49 DSKCHG# 7 4
RDATA# 23 49 RDATA# INDEX# RDATA# C279 C271 C266 C258
31 RDATA# 24 24 50 50 8 3
25 51 9 2 WP# 220PF 220PF 220PF 220PF
HDSEL# 25 51 HDSEL# TRACK0#
2
31 HDSEL# 26 26 52 52 +5V_SW 10 1
RP35
DRV05V# 6 5 +5V_SW
MTR0# 7 4 FDDIR#
STEP# 8 3 WDATA# JP24
WGATE# 9 2 HDSEL# 1
27,36 LINE_OUT_PLUG 1
+5V_SW 10 1 2 2
3 3
10P8R_1K 4
27,36 LINEOUT_R 4
27,36 LINEOUT_L 5 5
6 6
1
C735 C736 C737 HEADER 6
220PF 220PF 220PF
2
+5V_SW
+5V_ALW +5V_SW
1
JP9
1 21 C386
3 1 21 3
2 2 22 22
.1UF
2
3 3 23 23
4 4 24 24
5 5 25 25 ON/OFFBTN# 29,36
6 6 26 26 SUSPBTN# 30,36
16 SCRLED5V# 7 7 27 27 USER_BTN1# 30
16 NUMLED5V# 8 8 28 28 USER_BTN2# 30
9 29 D48 RB751V
16 CAPSLED5V# 9 29 USER_BTN3# 30
DRV05V# 10 30 1 2
FDDLED# 10 30 LID_SW_CON#
USER_BTN4# 30 LID_SW# 29,30
16 CDLED# 11 11 31 31
16 HDDLED# 12 12 32 32
13 33 D49 RB751V
13 33 EC_PWR_ON#
27 INT_MIC 14 14 34 34 EC_PWR_ON# 34,36,41 1 2 INTMICOFF# 27,36
15 15 35 35 EC_SMC_2 5,29,36
15 DISPOFF# 16 16 36 36 EC_SMD_2 5,29,36
29 DAC_BRIG 17 17 37 37
18 18 38 38
29 INVT_PWM 19 19 39 39
20 20 40 40
HEADER 40
4 4
Title
Compal Electronics, inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1012
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Custom 401200 1B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date: Friday, October 19, 2001 Sheet 33 of 45
A B C D E
A B C D E
+3V_SW
CP4
KSI1 1 8
INT_KBD CONN. KSI7 2 7
1
KSI6 3 6
R573 KSI5 4 5
+3V_SW KSI[0..7]
U64 +3V_SW KSI[0..7] 29
8P4C_220PF
@47K U65 JP21
1 NC KSI1 CP6
2
VCC 5 1 NC 1 1
2 5 2 KSI7 KSO9 1 8
A VCC KSI6 2 KSO0
Y 4 2 A 3 3 2 7
1 3 4 4 KSO9 KSO1 3 6 1
GND Y 4
1
1
3 KSI4 5 KSO5 4 5
R574 C770 GND 5 KSI5
@NC7S14 6 6
@NC7S14 KSO0 7 8P4C_220PF
2 @.47UF_0603 7 KSI2
8 8
@330K KSI3 9 9 KSO5 CP7
2
10 10
KSO1 11 KSI4 1 8
11 KSI0 KSI2
12 12 2 7
KSO2 13 KSI3 3 6
13 KSO4 KSI0
14 14 4 5
KSO7 15 15 KSO8 8P4C_220PF
16 16
+3V_SW KSO6 17 17 KSO3 CP8
18 18
KSO12 19 KSO2 1 8
19
1
+3V_SW 20 KSO13 KSO4 2 7
R111 KSO14 20 KSO7
21 21 3 6
U13 100K 22 KSO11 KSO8 4 5
D8 KSO10 22
23 23
RB751V 24 KSO15 8P4C_220PF
24
2
1 VCC RESET# 3 1 2 PM_PWROK 17
CP9
INT_KB_CONN.
KSO6 1 8
GND
1
KSO3 2 7
C196 KSO12 3 6
.1UF MAX809SEUR D9 RB751V KSO[0..15] KSO13 4 5
KSO[0..15] 29
SOT23
2
17,42 VGATE 1 2
8P4C_220PF
2 2
CP5
D40 RB751V KSO14 1 8
1 2 KSO11 2 7
17 WARM_RST#
KSO10 3 6
KSO15 4 5
8P4C_220PF
Reset Button
+3V_ALW
1
D36
PS2 CONN.
1N4148
SW2
2
3
1 2 1 R519 2
EC_RST# 19,29
33 Q2
1
3 4 @SM05
1
2
2
2
29,36 PS2_CLK 1 2
FCM1608C-121T
29,36 PS2_DATA 1 2
L5
KB_VCC KB_AS FCM1608C-121T JP3
F2 L34 KBD/PS2_6
W=40mils 1 2 W=40mils
+5V_SW 4 6
FBM-11-451616-800T 8
Power ON 2 8
1
POLYSWITCH_1A 4516 7
C355 C356 C358 1 7
1000PF 220PF 4.7UF_10V_0805 3 5
2
EC_PWR_ON# 33,36,41 L3
29,36 KBD_DATA 1 2
+3V_ALW FCM1608C-121T
29,36 KBD_CLK 1 2
L4
1
2
FCM1608C-121T
1
1
R316 C484 D22
1
C 1000PF RLZ20A Q1 C6 C7
4.7K
2
@SM05
220PF 220PF
2
2
22K
2
29 EC_ON 1 2 2
B
3
R314 E
4
22K Q38 22K 4
DTC124EK
3
1
D
Q39 2
@2N7002 G
S
Compal Electronics, inc.
3
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1012
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Custom 401200 1B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date: Friday, October 19, 2001 Sheet 34 of 45
A B C D E
5 4 3 2 1
2
VL
2
1
R140 R75
4
10UF_10V_1206 3.48K Q20 R510
1
FMMT619 100K_1%
2
2 - 1
2
100K
1
1 2
R117 100K D6 R69
1
+5V_SW 3 + 3 2 1
2
U14A 1SS355 R83
2
LMC6482IM D10 JP16 2.15K_1% 47K_1%
R118 1N4148 5V_FAN1
2
R125 +5V_SW 1
1
2
8
1M 100K C177
D7 3 R87 U11A
1
2 1 3 +
3 CON3 1 MAINPWON 39
Q21 1SS355 16.9K_1%
2
29 EC_EN_FAN 2 2 -
1 LM393
1
2SA1036K
1
R70 C107 R78
4
1
C129 0 .22UF_0805 100K_1%
10UF_10V_1206 .1UF
2
2
2
29 FAN_SPEED
2
R71
2 2
Thermistor_0805
1
Secondary FAN Connector Layout note :
C276 1UF_0603 Place a copper ground plan from CPU and place the
1 2 Thermistor upper this ground plan.
R164 3M
R162 10M_0603
+12V_SW
+5V_SW +3V_SW
2
1
1
C277 R153
4
6 - 1
R170 100K D17 100K
1
7 2
+5V_SW 5 + 3
2
U14B 1SS355
2
LMC6482IM D11 JP14 +3V_ALW
R168 5V_FAN2
8
1M 100K
3
1
1
3 D18 C431 3
GMCH.
1
3 CON3 R76
2 Q23 1SS355
29 EC_EN_FAN2
2.15K_1%
2
1
2SA1036K
2
2
TEMP_GMCH 29
10UF_10V_1206
1
R77
29 FAN_SPEED2
0
2
1
R80
Thermistor_0805
2
Layout note :
Place a copper ground plan from GMCH and place
4 the Thermistor upper this ground plan. 4
Title
Compal Electronics, inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1012
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Custom 401200 1B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date: Friday, October 19, 2001 Sheet 35 of 45
5 4 3 2 1
A B C D E
EMI Finger
14
8
U11B
PAD4 PAD5 PAD6 PAD7 5 + LM393
1 EMIPAD_PS-4 EMIPAD_PS-4 EMIPAD_PS-4 EMIPAD_PS-4 7 13 12 1
6 -
+12V_ALW U36F
74LVC14
7
+3V_ALW +3V_ALW
U43C U43D
74LVC32 74LVC32
14 14
9 12
8 11
10 13
7 7
+3V_ALW +3V_ALW
1
5 6 C30 C31
29,34 KBD_CLK 5 6
29,34 PS2_CLK 7 7 8 8
9 10 @100PF @1000PF
29,34 PS2_DATA 9 10
2
2 11 12 2
11 12
13 13 14 14
25 LAN_TX+ 15 15 16 16
25 LAN_TX- 17 17 18 18
19 19 20 20
25 LAN_RX+ 21 21 22 22 EC_SMD_2 5,29,33
25 LAN_RX- 23 23 24 24 EC_SMC_2 5,29,33
25 25 26 26 SUSPBTN# 30,33
27 27 28 28
DCD1# 29 30 DTR1#
32 DCD1# 29 30 DTR1# 32
DSR1# 31 32 CTS1#
32 DSR1# 31 32 CTS1# 32
TXD1 33 34 RTS1#
32 TXD1 33 34 RTS1# 32
RXD1 35 36 RI1# D12
32 RXD1 35 36 RI1# 32
37 37 38 38 1 ON/OFFBTN# 29,33
LPD1 39 40 SPR_ON/OFFBTN# 3
LPD3 39 40 LPD0
41 42 2
LPD5 43
41 42
44 LPD2
EC_PWR_ON# 33,34,41 Screw Hole
LPD7 43 44 LPD4
45 45 46 46 @DAN202U
47 48 LPD6
31,32 LPTSTB# 47 48
49 50 H10 H13 H5 H7 H1 H12 H6 H3 H2 H11
31,32 LPTAFD# 49 50
31,32 LPTERR# 51 51 52 52
31,32 LPTINIT# 53 53 54 54 LPTSLCT 31,32
31,32 LPTSLCTIN# 55 55 56 56 LPTPE 31,32
57 57 58 58 LPTBUSY 31,32
1
15,16 COMPS 59 59 60 60 LPTACK# 31,32
61 61 62 62
63 63 64 64 +5V_SW
65 66 L54 @FBM-L10-160808-301
11,16 DAC_RED 65 66
67 68 1 2 H9 H4 H8 H16 H15 H17 H14
3 67 68 DAC_VSYNC 11,16 3
11,16 DAC_GREEN 69 69 70 70 1 2 DAC_HSYNC 11,16
71 71 72 72 M_SEN# 16,30
73 74 L55 @FBM-L10-160808-301
11,16 DAC_BLUE 73 74 DDC_MD2
75 75 76 76 5VDDCCL 16
1
27 INTSPKOFF# 77 77 78 78 5VDDCDA 16
79 80 NPTH NPTH
27,33 LINE_OUT_PLUG 79 80 +5V_ALW
27,33 INTMICOFF# 81 81 82 82
83 84
LINEOUT_L 85
83 84
86
USB_OC#2 18 Fiducial Mark
27,33 LINEOUT_L 85 86 USB_OC#3 18
LINEOUT_R 87 88 FD4 FD6 FD5 FD2 FD3 FD1
27,33 LINEOUT_R 87 88
89 89 90 90 USB_PP2 18 1 1 1 1 1 1
26 DOCK_LIN_L 91 91 92 92 USB_PN2 18
93 94 FIDUCIAL MARK FIDUCIAL MARK FIDUCIAL MARK FIDUCIAL MARK FIDUCIAL MARK FIDUCIAL MARK
26 DOCK_LIN_R 93 94
95 96 CF17 CF18 CF19 CF20
95 96 USB_PP3 18
27 DOCK_MIC 97 97 98 98 USB_PN3 18 1 1 1 1
99 100 CONA#
99 100 CONA# 30
101
102
103
104
1 1 1 1 1 1
FIDUCIAL MARK FIDUCIAL MARK FIDUCIAL MARK FIDUCIAL MARK FIDUCIAL MARK FIDUCIAL MARK
@DOCKING 100
CF8 CF11 CF1 CF2 CF7 CF5
1 1 1 1 1 1
LINEOUT_L FIDUCIAL MARK FIDUCIAL MARK FIDUCIAL MARK FIDUCIAL MARK FIDUCIAL MARK FIDUCIAL MARK
LINEOUT_R
4
CF3 CF4 CF9 CF6 4
1
LPD[0..7] 1 1 1 1
31,32 LPD[0..7]
C23 C19
@100PF @100PF FIDUCIAL MARK FIDUCIAL MARK FIDUCIAL MARK FIDUCIAL MARK
2
Title
Compal Electronics, inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1012
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Custom 401200 1B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date: Friday, October 19, 2001 Sheet 36 of 45
A B C D E
A B C D E
Or use SI2305DS.
+3V_ALW Q57 +3VAUX
SI2301DS
D
3 1
1
C725
G
1
C741
2
1 1
1UF_0603
1UF_0603
2
2
JP31
TIP RING
29 EN_WOL#
KEY KEY
3 3 4 4
LAN RESERVED 5 5 6 6
7 7 8 8
9 9 10 10 LAN RESERVED
11 11 12 12
LED1_GRNN 13 14 LED2_YELN
25 LED1_GRNN 13 14 LED2_YELN 25
15 16 R477 2 1 0
15 16 W=30mils PCI_RST# 9,15,17,21,22,23,26,29,31
INT_PIRQD# 1 2 17 18
17,19,26 INT_PIRQD# 17 18 +5V_SW
+3V_SW 2 R483 1 W=40mils R481 0 19 19 20 20 1 2 INT_PIRQC#
PCI_REQ#4 R486 0 PCI_GNT#4 INT_PIRQC# 17,19
0_1206 17,19 PCI_REQ#4 21 21 22 22 PCI_GNT#4 17
1
1
31 32 C745 C752
PCI_AD31 31 32 MDM_PME#
17,22,23,26 PCI_AD31 33 33 34 34 MDM_PME# 30
PCI_AD29 35 36 LAN_PME# 100PF 1000PF
17,22,23,26 PCI_AD29 35 36 LAN_PME# 30
CLK_MINIPCI PCI_AD30
2
37 37 38 38 PCI_AD30 17,22,23,26
PCI_AD27 39 40
17,22,23,26 PCI_AD27 39 40
1
PCI_AD25 41 42 PCI_AD28
17,22,23,26 PCI_AD25 41 42 PCI_AD28 17,22,23,26
R484 PCI_AD22 1 2 43 44 PCI_AD26
2 IDSEL : AD22 PCI_C/BE#3 R494 100 45
43 44
46 PCI_AD24 PCI_AD26 17,22,23,26 2
17,22,23,26 PCI_C/BE#3 45 46 PCI_AD24 17,22,23,26
@10 PCI_AD23 47 48 1 2 PCI_AD18
17,22,23,26 PCI_AD23 47 48 IDSEL : AD18 +5V_SW
49 50 R471 100
PCI_AD21 49 50 PCI_AD22
12
1
PCI_C/BE#2 PCI_AD16
2
1
PCI_IRDY# 61 62 C730 C731 C727
17,19,22,23,26 PCI_IRDY#
63
61 62
64 PCI_FRAME#
+
63 64 PCI_FRAME# 17,19,22,23,26
PM_CLKRUN# 65 66 PCI_TRDY# 4.7UF_10V_0805 .1UF 1000PF
17,19,22,23,29,31 PM_CLKRUN# 65 66 PCI_TRDY# 17,19,22,23,26
PCI_SERR# PCI_STOP#
2
17,19,22,23 PCI_SERR# 67 67 68 68 PCI_STOP# 17,19,22,23,26
69 69 70 70
PCI_PERR# 71 72 PCI_DEVSEL#
17,19,22,23 PCI_PERR# 71 72 PCI_DEVSEL# 17,19,22,23,26
PCI_C/BE#1 73 74
17,22,23,26 PCI_C/BE#1 73 74
PCI_AD14 75 76 PCI_AD15
17,22,23,26 PCI_AD14 75 76 PCI_AD15 17,22,23,26
77 78 PCI_AD13
77 78 PCI_AD13 17,22,23,26 +3V_SW
PCI_AD12 79 80 PCI_AD11
17,22,23,26 PCI_AD12 79 80 PCI_AD11 17,22,23,26
PCI_AD10 81 82
17,22,23,26 PCI_AD10 81 82
83 84 PCI_AD9
83 84 PCI_AD9 17,22,23,26
PCI_AD8 85 86 PCI_C/BE#0
17,22,23,26 PCI_AD8 85 86 PCI_C/BE#0 17,22,23,26
PCI_AD7 87 88
17,22,23,26 PCI_AD7 87 88
1
89 90 PCI_AD6
89 90 PCI_AD6 17,22,23,26
1
PCI_AD5 91 92 PCI_AD4 C739 C743 C698 C699 C706
17,22,23,26 PCI_AD5
93
91 92
94 PCI_AD2
PCI_AD4 17,22,23,26 + +
93 94 PCI_AD2 17,22,23,26
PCI_AD3 95 96 PCI_AD0 4.7UF_10V_0805 .1UF .1UF 1000PF 4.7UF_10V_0805
17,22,23,26 PCI_AD3 W=30mils 95 96 PCI_AD0 17,22,23,26
2
+5V_SW 97 97 98 98
PCI_AD1 99 100
17,22,23,26 PCI_AD1 99 100
101 101 102 102
3 3
26 MD_SYNC 103 103 104 104
26 MD_SDATAI 105 105 106 106 MD_SDATAO 26
MD_BITCLK
26 MD_BITCLK 107 108 +3VAUX
107 108
109 109 110 110 MD_RST# 26
1
1
@10 117 118
117 118
1
119 120 C740 C729 C728
119 120 +
12
2
@15PF 127 128
127 128
2
Mini-PCI SLOT
4 4
Title
Compal Electronics, inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1012
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Custom 401200 1B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date: Friday, October 19, 2001 Sheet 37 of 45
A B C D E
A B C D E
1
6 3 R25 6 3
D S SYSON_ALW C376 C381 C384 D S +5VS_GATE C68 C70 C69
5 D G 4 1 2 +12V_ALW 5 D G 4
1 100K 1UF_0603 4.7UF_10V_0805 4.7UF_10V_0805 1UF_0603 4.7UF_10V_0805 4.7UF_10V_0805 1
1
1
SI4800
2
1
R14 C57 SI4800 R45
C36 470 .01UF_25V_0805 C71
4.7UF_10V_0805 4.7UF_10V_0805 470
2
2
1
D
2
2 SYSON#
12
1
D G D
SYSON# 2 S SYSON_ALW SUSP 2 Q13
SYSON_ALW
G Q34 Q9 G 2N7002
3
S 2N7002 2N7002 S
3
+3V_ALW TO +3V_SW Transfer +1.8V_ALW TO +1.8V_SW Transfer
+3V_ALW +3V_SW +1.8V_ALW +1.8V_SW
U5 U2
8 D S 1 8 D S 1
7 D S 2 7 D S 2
1
6 D S 3 6 D S 3
5 4 +5VS_GATE 1 R15 2 C40 C44 C45 5 4 +5VS_GATE C33 C15 C32
D G +12V_ALW D G
100K 1UF_0603 4.7UF_10V_0805 4.7UF_10V_0805 1UF_0603 4.7UF_10V_0805 4.7UF_10V_0805
1
1
SI4800
2
R265 C38 SI4800 R12
2 C37 470 .1UF_25V_0805 C26 2
4.7UF_10V_0805 4.7UF_10V_0805 470
2
2
12
12
1
D D D
SUSP 2 2 SUSP SUSP 2 Q5
Q7 G G Q6 G 2N7002
2N7002 S S 2N7002 S
3
3
+3V_ALW
+5V_ALW TO +5V_SW Transfer RTC Batt. Connector
1
+5V_ALW +5V_SW +RTCVCC BATT1 +RTC_BATT RTCVREF
U45 R402
8 1 2 1 W=30mils 100K
D S
1
7 D S 2
R514
6 D S 3 - +
1
2
5 D G 4
C708 C693 C701 RTCBATT SUSP 26
1
1UF_0603 4.7UF_10V_0805 4.7UF_10V_0805 D
1
2
29,32,39 EC_SUSP# 2
C694 G 2N7002
4.7UF_10V_0805 470 D32 1 2 RB751V 1 2 S
W=30mils W=30mils
2
3
3 D33 3
1
D RB751V
SUSP 2 Q55
G 2N7002
S
+3V_ALW
3
1
R398
100K
+12V_ALW TO +12V_SW Transfer
+12V_ALW +12V_ALW SYSON#
2
1
D
+3V_SW 2 Q44
29 SYSON
1
G 2N7002
R97 S
1
1
C150
3
100K R470
3
S
.1UF G
Q15 @10K
2
2
NDS352P
1
ACIN_SYS#
12
D
+12V_SW D
R98
1
2 Q51
18,29,40 ACIN
51K R92 G @2N7002
4
S 4
1
C144 100
2
3
1
Q19 D 4.7UF_25V_1206
12
EC_SUSP# 2 D Q14
2
G 2 SUSP
2N7002 S G
2N7002 Compal Electronics, inc.
3
S
Title
3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1012
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Custom 401200 1B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date: Friday, October 19, 2001 Sheet 38 of 45
A B C D E
A B C D E
1 1
B+
P6
+12VALWP
B+
3
PL1 B++ PR1 DAP202U
10 PD3 PC1
PC3 4.7UF_1206_25V
FBJ3216HS800 0.1UF_0805_25V VL
PC2
8
7
6
5
8
7
6
5
4.7UF_1210_25V
PC6 PQ3
1
D
D
D
D
D
D
D
D
PQ2 SI4800
0.1UF_0805_25V PC8 SI4800 PC5 PC4
1
PC7 4.7UF_1210_25V 0.1UF_0805_25V 4.7UF_1206_16V PC9
G
S
S
S
S
S
S
470PF_0805_100V PD4
4.7UF_1210_25V 25V PC10 EC11FS2
0.1UF_0805_25V PC11
1
2
3
4
1
2
3
4
22
21
0.1UF_0805_25V
2
2 25 4 2
PR2
VL
V+
PR3 BST3 12OUT
VDD 5 22_1206
27 18 PR4 4 2
DH3 BST5 PT1 10UH_SDT-1205P-100-120
PU1 DH5 16
0 26 17 B++ P7 P8
LX3 LX5 0
24 DL3 DL5 19 PQ4
P5 20 SI4800 1 3
PGND P9
CSH5 14
1 CSH3 CSL5 13
2
8
7
6
5
PC12 2 12
@1000PF CSL3 MAX1632 FB5
3 15
D
D
D
D
FB3 SEQ
8
7
6
5
PL2 10 9 PC13
SDT-1205P-100-120 PC107 SKIP# REF
23 6
D
D
D
D
SHDN# SYNC 22UF_1812_25V
11
G
47PF_0603 RST#
S
S
S
7 PR5
TIME/ON5 PQ5 0.015_2512
1
G
S
S
S
SI4800 1W
1
2
3
4
28
GND
PR7 RUN/ON3
PR6 PC108
1
2
3
4
29,32,38 EC_SUSP#
0.015_2512
1M 0 47PF_0603
8
+3VALWP PR139
PR8
10K
1
+ + PR140 PC109
3.65K_1%
PD5 100PF_0603
EC10QS04
3 3
2
PC15 PC17
+5VALWP
47UF_D_6.3V 47UF_D_6.3V PR141
1
10K_1%
PR126 PR142 PC18 PC19 PD6
2M PC110 PR143 + 47UF_D_6.3V + EC10QS04
1
2
5% UDZ5.6B VREF
0.1UF_0603_25V 10K_1%
0.47UF_0603_16V
PR127
100K
5%
VL
PR133 47K
4 4
Title
Compal Electronics, inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1012
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Custom 401200 1B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date: Saturday, October 20, 2001 Sheet 39 of 45
A B C D E
A B C D E
+3VALWP
1 1
PR11
100K PF1
5A PCN1
PR12 PR119
VMB 1 8
1K_1% 0_1206
29,41 LI/NIMH# 2
PR13 1K_1%
TS 3
+3VALWP 4
PR14 SLD
25.5K_1% SLC 5
3 3 6
7 9
1 1
PR15
BATT CONN.
VIN 2 2 1K
3 FBJ3216HS800
2
3 PC28 PC29
2 1000PF 0.01UF_0805_25V PC30 PC31 3
1000PF +5VALWP
DC JACK 0.01UF_0805_25V
2
2 2 PR18 2
200
PD9
@BAS40-04
29,30 EC_SMD_1
+5VALWP 3
2 PR21
PD10 200
@BAS40-04
29,30 EC_SMC_1
P1
8
10K PR33 LM393 @0 PR29
8
4
PC112 1% 2 NIMH/LI# 41
PR38 PC35 PC33 @1M
4
PR40 3
1
25V
PC113
0.22UF_0805_16V PR151
100K
4 4
Title
Compal Electronics, inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1012
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Custom 401200 1B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date: Saturday, October 20, 2001 Sheet 40 of 45
A B C D E
A B C D E
1
PC41 PC42 22UF_1812_25V
PR47
150K PC43
4.7UF_1210_25V 0.1UF_0805_25V PD14 PD29 4.7UF_1210_25V
40 PACIN EC31QS04
EC31QS04
PR152 4.7UF_1210_25V
2
VIN
B+
2
47K
PD27 PR50
PR49
1SS355
47K
4.7
1
OVP# 40
Modify by CT at 2/25
1
2
PQ13 3 PU5
2N7002 1 -INC2 +INC2 24
PR53 PR51 PR52
10K 0 @0
2 OUTC2 GND 23
PC44
2200PF
1
3 +INE2 CS 22
2 2
PQ14 PC46 4 21
100K 4700PF_0603_50V -INE2 VCC(o)
2 DTC115EK PR54
29 ACOFF PR55 PC45
PR56 27K_1% 0.1UF
5 FB2 OUT 20
100K 10K_1% 10K
PC48
3
6 VREF VH 19
TRICKLE
2200PF_0603_50V Add by CT at 29 FSTCHG
PR57 PC49
5/3
7 FB1 VCC 18
PR58 10K
PC47 PR59 0.1UF_0805_25V
0.1UF 24.9K_1%
8 -INE1 RT 17
2
68K
9 +INE1 -INE3 16
PD16 PD17
PR61 PR60 PR62 PR63 PC50 1SS355 1SS355
16.9K 1%
1
10 OUTC1 FB3 15
1.2K_0.5% PC51 PR64 10K 324K_1%
0.1UF_0805_25V
10K_1% 11 14 1500PF
OUTD CTL
1
1 2 PQ15
29 TRICKLE PQ16
2
3
3 12 -INC1 +INC1 13
PR65
CV:LI-ION 13.241V
2N7002 47K
2N7002 MB3878
NI-MH 16.202V
3 3
RB751V 150K_0.5%
2 1 PD19 CC: 0.265A NI-MH TRICKLE
VMB PR68
RLS4148
3 1
215K_0.5% CHGRTCP
PQ17
1
2
+5VALWP S-81235SG
CHGRTCP 2 1 3 1 100K
SHDN# 39 200_0805
1
PZD1
1
1
2
1
100K 2 LI/NIMH# 29,40 PC54 PZD2
PC55 1UF_0805_25V RLZ16B
2
10UF_1206_10V
2
1
100K
2
33,34,36 EC_PWR_ON# 1 2
PR72 PC53
3
22K 0.22UF_1206_25V
4 4
Title
Compal Electronics, inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1012
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Custom 401200 1B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date: Saturday, October 20, 2001 Sheet 41 of 45
A B C D E
A B C D E
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
B+
FBJ3216HS800
PC62 PC63 PC64 PC65 PC114 PC115
PC61 4.7UF_1210_25 V 0.1U_0603 1000PF_0 603
5
6
7
8
5
6
7
8
7 CPU_VID4
4.7UF_1210_25V 4.7UF_1210_25 V
P+ P- 43
7 CPU_VID3
PR79 +5VALWP 4 4
10
7 CPU_VID2
1 2 1.0UH
PQ20 PQ21
7 CPU_VID1
2
IR7811A IR7811A PL11
PR81 PD20
7 CPU_VID0 +VCC_H_COREP
1SS355
20 PL7
3
2
1
3
2
1
PU8 MAX1718 HK-RM136-20A0 R8 150UF_D_6.3V
VTTLX
1
21 D4 LX 27 2 1
PR87
22 28 1 2 PR85
D3 DH
1
2mR
23 26 2.2 PC69 PQ22 PQ23 PQ24 PR88 + +
D2 BST
5
6
7
8
5
6
7
8
5
6
7
8
PR154 0.1UF_0805 SI4404 SI4404 SI4404
24 16 1 2 PD28 @0
D1 DL VIN2 EC10QS 04
2.2
2
25 D0 V+ 1 4 4 4
+3V_SW +5VALWP
1
2 14 9 PC70 PC71 2
VGATE VCC PC72 150UF_D_6.3V
PR90 51K 2 1 3 4 0.1UF_0805 PR92 P+
10K PR91 TIME FB
1 2
2 13 PC103 P- 43
SDN/SKIP POS 100 0.1UF_0805
2
3
2
1
3
2
1
3
2
1
17,34 VGATE PU13
5
PC75 17 5 PC74 PC73 PR128 510
4.7UF_1206_16V VDD NEG 4.7UF_1206 @.01U/16V + 3 2 1
PC105 +5VALWP PC77 6 19 1 2 1
@0.1UF_0603 470PF_0 603 CC ZMODE PC76
- 4 2 1
20 18 1000PF_0 603 0 PR129
OVP SUS
1
1
PR130 1K_1%
PR134 PC78 PR93
2
11 REF S1 8 2 1
PD26 30K_1% 1U
RB751V PM_DPRSLPVR 7,17 1K PR131 1K_1% MAX4322
12 ILIM S0 7
PR94
2
2
29 VR_ON 1 2 15 GND TON 10
24.9K
1
2
2 NO3 COM 9
0 0 0 0 0.975 1.75
3 8 PR97
NO1 NO0 10K 0 0 0 1 0.950 1.70
4 INH ADDA 7 7,17 PM_SSMUXSEL
VIN3 PL8 B+ 0 0 1 0 0.925 1.65
1
3 3
5 GND ADDB 6
0 0 1 1 0.900 1.60
FBJ3216HS800 MAX4524
1
PQ25 0 1 0 0 0.875 1.55
2
PR99 +5VALWP PC79 PC80 PC81 2N390 4
0.1UF_0805 4.7U/25V 4.7U/25V 2 0 1 0 1 0.850 1.50
PR100 PR103 PR102 PR101
10 604K 16.2K 19.6K 61.9K 0 1 1 0 0.825 1.45
2
2
PC82 PC83
4.7UF_1206_16V 4.7UF_1206_16V 0 1 1 1 0.800 1.40
3
4 5 PR104
PU10 PD22 10K 1 0 0 0 0.775 1.35
15 14 1SS355 3 6 PL9 +VTTP
VCC VDD SDT-1205P-1 00-120 1 0 0 1 0.750 1.30
1
1
18 19 1.5VBST PC84 2 7
VIN3 SKIP BST PR138 0.1UF_0805 1 0 1 0 0.725 1.25
1
17 V+ DH 1 2 1 1 8
+ 1 0 1 1 0.700 1.20
10 20 1.5VLX 2.2 PD23 5,17 H_DPSLP#
5 VTT_P WRGD PGOOD LX 1 1 0 0 0.675 1.15
@EC10Q S04
3 13 1.5VDL PQ26
29 VTT_ON SHDN DL 1 1 0 1 0.650 1.10
SI4834
2
1.2VILIM 6 12
ILIM PGND PC85 MODE OFFSET RBOTTOM Vout(0A) ADDA ADDB 1 1 1 0 0.625 1.05
2 11 150U/6.3V DEEPER SLEEP 0mV X 0.850 X X
N/C N/C PR106 BATTEY SLEEP -56mV 16.2K 1.094 1 0 1 1 1 1 0.600 1.00
1 2 2.0VREF 7 9 3K/F PERFORMANCE SLEEP -51mV 19.6K 1.199 1 1
REF N/C BATTERY MODE -16mV 61.9K 1.134 0 0
4 PR107 16 5 PERFORMANCE MODE -1.8mV 604K 1.248 0 1 4
TON OUT
1
10K
PR108 8 4 1.25VFB
15K AGND FB
MAX1714A
PC89 PR109 +VTTP +VTTP
PC86 150PF_0 603PC90 12K/F
2
+5VALWP
VREF
4
5
6
1 1
2
+5VALWP PD24
D
D
S
ISS355 PR110
PR112 PQ27
G
D
D
PR111 PC91 2.2K 1 47K
105K_1% 0.1UF_0805_25V SI3443DV
1
2
3
2
1
PU11A 3
PC92
8
PQ28 JOPEN11
LM393 1000PF
3 2SC2411K 1 2
+ +VTTP +VTT
1
1
2 - PQ29 PD25 3MM
2SA1036K RB051L-40
JOPEN2
PC93 PR113
4
0.047UF 270K_1%
+VTTP 1 2 +VTT 80mil
2
2
3MM
PL10
JOPEN3
5UH_SPC1002 1 2
+VTTP +VTT
3MM
PR114
1
5.1K JOPEN12
+1.8VALWP +5VALWP 1 2 +5V_ALW
3MM
2 VREF + JOPEN4 2
PC94 1 2
+5VALWP +5V_ALW
150UF_D_6.3V
+12VALWP 3MM
PR115 JOPEN5
5
6
7
8
100K_1% 1 2
+3VALWP +3V_ALW
PU12A PQ30
D
D
D
D
8
LM358 3MM
SI4800
3 +
1 JOPEN6
G
S
S
S
2 - +VCC_H_COREP 1 2 +VCC_H_CORE
4
3
2
1
3MM
4
+1.5VALWP JOPEN8
+12VALWP 1 2 +12V_ALW
PR117 3K_1%
PR118 PC96 2MM
0.1UF_0805_25V +
15K_1% PC97 JOPEN9
47UF_D_6.3V 1 2
+1.5VALWP +1.5V_ALW
2MM
3 3
JOPEN10
+1.8VALWP 1 2 +1.8V_ALW
3MM
4 4
Title
Compal Electronics, inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-1012
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Custom 401200 1B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date: Saturday, October 20, 2001 Sheet 43 of 45
A B C D E
5 4 3 2 1
Power PIR
Item Fixed Issue Reason for change Page Modify item MB_Ver. Phase
D D
C C
B B
A A
Title
Compal Electronics, inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL SCHEMATIC, M/B LA-1012
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A 1B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE 401200
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date: Friday, October 19, 2001 Sheet 44 of 45
5 4 3 2 1
N32N101 LA-1012 Rev1.0 HISTORY LIST (PIR)
For C-Test 09/03/2001 Rev:1.0
Date Page Description Date Page Description
09/03 P26 Change SI9181( U12 & U59 ) from fixed to adjustable version.
Add 30Kohm resistor R592(R594) and 10Kohm resistor
R593(R595) to make output voltage at 4.8V.
P27 Add a 39Kohm serial resistor R596, change R94 value from
100Kohm to 470Kohm and add a 10uF/16V parallel with Q40.2
and GND to solve pop sound when Int-MIC mute.
P33 Change D48 from one DAN202U to two RB751Vs.
P7 Change R68 from 1Kohm_1% to 499ohm_1% and R65 from 2Kohm_1%
to 1Kohm_1% by Intel recommanded.
09/05 P26 Change C167, C299 value from .01uF to .1uF.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL SCHEMATIC, M/B LA-1012
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE 401200
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
Date: Friday, October 19, 2001 Sheet 45 of 45
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