This article has been accepted for publication in IEEE Journal of Emerging and Selected Topics in Power Electronics.
This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2023.3275230
IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS
Closed-Form Harmonic Compensation Using
Resonant Controllers Applied to Four-Leg VSI
Elı́as Oggier, Germán G. Oggier, Member, IEEE, Fernando Botterón, Guillermo O. Garcı́a, Senior Member, IEEE,
Abstract—Harmonic compensation employing resonant con-
trollers applied to voltage source inverters generally requires
complex techniques or a trial-and-error process to design the con-
troller parameters. This paper proposes a closed-form solution
for designing digital Proportional-Resonant controllers applied to
three-phase four-leg inverters. The proposal presents a sequential
procedure that uses closed-form expressions to establish the
harmonic frequencies at which resonant stages must be added to
comply with individual voltage harmonic distortion standards.
The method eliminates the need for a trial-and-error process
and ensures compliance with THD and individual harmonic
distortion limits. The frequencies that require compensation
and the gains of the resonant controllers are determined by
evaluating the difference that presents the output harmonic
impedance of the inverter concerning normalized three-phase
harmonic impedance limits defined in this work. Furthermore,
this paper adopts the harmonic distortion restrictions imposed by
the Standard IEC 61000-2-2, allowing the harmonic impedance
limits to be defined for the reference non-linear load indicated in
IEC 62040-3. Experimental results are presented to validate the
proposed design using a 5 kVA four-leg inverter, feeding balanced,
unbalanced, linear, and non-linear loads.
Index Terms—Inverters, DC-AC power converters, Digital con-
trol, Three-phase electric power, Three-phase four-wire converter.
I. I NTRODUCTION
The three-phase voltage source inverters (VSI) used in
stand-alone UPS and grid-forming applications feeding linear,
non-linear, three-phase, and single-phase loads require a neu-
tral wire to ensure the flow of zero-sequence currents. Usually,
a low-frequency delta-wye transformer between the inverter
and the load is used to provide the neutral connection, which
increases weight and cost. Other options consist of power
converters that allow a fourth wire connection, including the
Split-DC Link VSI [1] and the three-phase four-leg (TP4L)
VSI [2], [3], being this last topology, the most suitable for
four-wire applications [2], [4].
These applications require designing a controller for the
VSI, whose main objective is the output voltages to meet
power quality standards when different loads are supplied,
including single-phase and three-phase ones, linear and non-
linear. These loads can unbalance and distort the output
Manuscript received Month xx, 2xxx; revised Month xx, xxxx; accepted
Month x, xxxx. E. Oggier, G. G. Oggier and G. O. Garcı́a, are with
the Instituto de Investigaciones en Tecnologı́as Energéticas y Materiales
Avanzados (IITEMA) and with the Grupo de Electrónica Aplicada (GEA)-
CONICET, Facultad de Ingenierı́a, Universidad Nacional de Rı́o Cuarto, Rı́o
Cuarto, X5804BYA, Argentina (e-mail: eoggier@ing.unrc.edu.ar). F. Botterón
is with the Instituto de materiales de Misiones (IMAM) and with the Grupo
de Investigación y Desarrollo en Electrónica (GID-IE)-CONICET, Facultad
de Ingenierı́a, Universidad Nacional de Misiones, Oberá, 3304, Argentina (e-
mail:botteron@gmail.com).
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1
phase voltages when the output impedance is not adequately
synthesized.
The harmonic impedance gives the relationship between the
voltage distortion and the non-linear load current components
at each harmonic frequency [5]. Several control strategies
using linear controllers based on the internal model principle
(IMP) have been proposed to reduce it, mainly repetitive for
TP4L-VSI [6], [7] and proportional resonant (PR) [8], [9] for
single-phase [10]–[13], three-phase three-leg [14], [15], [16],
and TP4L-VSI [17]–[21]. These controllers present the ability
to track sinusoidal references and reject load disturbances,
even under parametric uncertainties of the output filter.
Repetitive controllers have a good regulation of the output
voltages, presenting a reduced THD when the inverter feeds
non-linear loads. This result is possible because the harmonic
impedance is reduced at the fundamental and all harmonic fre-
quencies. However, the high phase lag compromises transient
response and stability. In contrast, PR controllers allow tuning
their parameters individually, which results in a more flexible
design.
Different design methodologies of the resonant stages can
be found in [12]–[16], [22]–[24]. For example, a Generalized
Forced Oscillation Method (GFO) is presented in [22], using
tuning formulas to obtain a determined performance in both
current and voltage control loops. However, the method is
presented for a single resonant stage. In [13] multiple resonant
stages introduced in the voltage control loop are designed
using an optimization problem with a linear matrix inequality
(LMI), which requires computational packages to obtain the
solution.
On the other hand, the use of the linear quadratic regulator
(LQR) to design multiple resonant stages is proposed in [12]
for the voltage controller and in [14] is also used for a current
control loop. This technique requires a trial-and-error process
to meet the requirements. Other proposals consider the ex-
pected time evolution of the controlled inductor current in the
design process as [23], whereas [24] uses Naslin polynomials.
However, when multiple resonant stages are required, the
solving problem tends to be inconsistent.
In [15] the design of multiple resonant stages in the voltage
control loop is proposed using a method of selective pole
placement and cancellation for the PR controller. In addition,
reduced-order resonant controllers are proposed to minimize
the number of poles, using a feedforward loop to compen-
sate for differences caused by the approximation. On the
other hand, [16] proposes to use a PR controller tuned to
the fundamental frequency with complex coefficients in the
voltage loop, achieving a lower output impedance compared
 This article has been accepted for publication in IEEE Journal of Emerging and Selected Topics in Power Electronics. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2023.3275230

2 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS

to a conventional PR and a good transient response. In this DC-Link

work, a load current observer is used. sa s b sc sn
Some works reduce the harmonic impedance in several L r ia vAN ioa
va Four
frequencies, employing a large number of resonant stages in VDC
vb ib vBN iob Wire
the voltage control loop, tuned with high gains to achieve
phase voltages with low THD [11], [13], [17]–[21]. However, vc ic vCN ioc Load
the only objective to obtain a reduced THD may cause the vn
sa sb sc sn 3×C ion
following critical consequences: excessive resonant stages with Ln rn i
higher computational overhead; unnecessary phase margin n N
reduction, compromising the system stability; and the non- ia ib ic vAN vBN vCN
compliance of the individual harmonic distortion limits im- fs
ADC
posed by power quality Standards.
s a s b s c sn
In [25] the harmonic impedance limits are established for abc abc
αβ0 αβ0
single-phase inverters, which allow the necessary resonant iα iβ i0 vα vβ v0
u e i*α e
stages to be determined to comply with the voltage harmonic e-Tds α P iα PR vα v*α
distortion limits imposed by power quality standards. -Tds uβ eiβ i*β e
e P PR vβ v*β
This article presents a closed-form method to design res- u0 e i*0 e
e-Tds P i0 PR v0 v*0
onant voltage controllers. By assessing the difference that 3D-SVM Inner current loop Outer voltage loop
presents the inverter output impedance concerning normalized Fig. 1. Scheme of the four-leg inverter with LC filter and control strategy.
three-phase harmonic impedance limits, the proposal deter-
mines the precise harmonic frequencies at which resonant ioa rs iob rs ioc rs
stages must be added and calculate their gains to meet in- Cc R1 Cc R1 Cc R1
dividual harmonic distortion limits. As a result, lower compu- van vbn vcn
tational overhead and a higher stability margin than previous
proposals are achieved. The limits are established for three- Fig. 2. Reference non-linear (RNL) load configuration.
phase four-leg inverters to meet the restrictions imposed by
Standard IEC 61000-2-2 [26] for balanced and unbalanced TABLE I
non-linear loads. The proposed closed-form solution allows PARAMETERS OF THE REFERENCE NON - LINEAR LOAD
evaluating all the parameters following a sequential procedure
Symbol Parameter Value
to meet the specifications of harmonic impedance limits and Cc Non-linear load capacitor 2300 µF
phase margin, which avoids a trial-and-error process. rs Non-linear load series resistor 1.16 Ω
Experimental results obtained with a 5 kVA prototype are R1 Non-linear load resistor 65.2 Ω
presented and analyzed, verifying the practical viability of the
theory proposed.
The paper is organized as follows. In Section II the three- procedure proposed in [25] for single-phase inverters to
phase harmonic impedance limits are established. Section III establish the harmonic impedance limits is completed for
presents the discrete-time model of the inverter. The control three-phase four-wire inverters.
design methodology is proposed in Section IV and applied in The three-phase harmonic impedance is defined in the αβ0
Section V to design the controllers of a TP4L-VSI. Section reference frame as the ratio between the voltage distortion
VI presents the experimental results. Finally, conclusions are and the non-linear load current at each harmonic frequency
drawn in Section VII. [5], according to,

II. I NVERTER OUTPUT IMPEDANCE REQUIREMENTS
Fig. 1 shows the TP4L-VSI and the multi-loop control strat-
egy analyzed in this work, represented in the αβ0 reference
frame, using proportional (P) and PR controllers in the inner
and outer loop, respectively. The outer loop allows tracking the
voltage reference, vy∗ , creating the inductor current reference
i∗y for the inner loop. The latter improves the relative stability
and generates the components of the 3D-SVM, uy , where
y = α, β, 0.
This section establishes the three-phase harmonic
impedance limits to meet the phase voltage distortion
imposed by the power quality standards when the inverter
feeds balanced and unbalanced non-linear loads. In addition,
these limits represent the references to tune the voltage
loop controllers in the following sections. In this paper the
|Vh,lim |pu
|Zhy,lim |pu = , (1)
|ioy,h |pu
where y is the axis where the harmonic impedance is evalu-
ated, h is the order of the harmonic, |Vh,lim | is the individual
voltage harmonic limit, and |ioy,h | is the h−component of the
current consumed by a non-linear load. |Vh,lim |pu and |ioy,h |pu
are normalized concerning the rated peak phase voltage (V̂o )
and the output peak current Iˆo , respectively.
In this paper, the Vh,lim values are established by the
Standard IEC 61000-2-2, according to the steady-state non-
linear load test defined by the Standard IEC 62040-3 for stand-
alone applications. This test consists of feeding the three-phase
four-wire reference non-linear (RNL) load shown in Fig. 2,
defined by Annex E of this Standard, whose parameters are
detailed in Table I.

© 2023 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information.
Authorized licensed use limited to: University of Arkansas. Downloaded on May 11,2023 at 22:08:18 UTC from IEEE Xplore. Restrictions apply.
 This article has been accepted for publication in IEEE Journal of Emerging and Selected Topics in Power Electronics. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2023.3275230

OGGIER et al.: CLOSED-FORM HARMONIC COMPENSATION IN FOUR-LEG VSI 3

0.7

Amplitude (pu)
0.6 jio, j
0.5
0.4
jio- j
0.3 jio0 j
0.2
0.1
0
3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37
Harmonic order (h)
(a)
(a) 0.7

Amplitude (pu)
0.6 jio, j
0.5
0.4
jio- j
0.3 jio0 j
0.2
0.1
0
3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37
Harmonic order (h)
(b)

(b) Fig. 4. Harmonic content of the current consumed by the RNL load: (a)
unbalanced condition (C1), and (b) maximum values of all the conditions
listed in Table II.

TABLE III
R ESULTING HARMONIC IMPEDANCE FOR BOTH BALANCED AND
UNBALANCED RNL LOAD , EXPRESSED IN P. U .

Harmonic order α axis β axis 0 axis

(c) h=3 0.10990 0.12695 0.07321
h=5 0.12155 0.12153 0.36479
Fig. 3. Current consumed by the balanced RNL load: (a) abc reference frame,
h=7 0.17833 0.17837 0.53508
(b) αβ0 reference frame, and (c) harmonic content.
h=9 0.22971 0.26525 0.15341
h=11 1.20479 1.20207 3.62658
h=13 0.43526 0.43552 1.30756
TABLE II h=15 0.07931 0.09157 0.05290
U NBALANCED N ON - LINEAR LOAD CONDITIONS h=17 1.00047 0.99391 2.98009
h=19 0.93086 0.93257 2.80891
Phase C1 C2 C3 C4 C5 C6 h=21 0.10409 0.12025 0.06934
a No load Loaded Loaded No load No load Loaded h=23 0.69849 0.69647 2.08786
b Loaded No load Loaded No load Loaded No load h=25 3.05425 3.02097 9.06202
c Loaded Loaded No load Loaded No load No load h=27 0.25720 0.29748 0.17079
h=29 0.40103 0.40055 1.20145
h=31 0.63198 0.62849 1.88525
h=33 1.30663 1.51595 0.86113
On the other hand, |Ioy,h | has to be obtained as the h=35 0.62658 0.62558 1.88313
h=37 0.57275 0.57172 1.71493
current drained by the RNL load, which takes into account h=39 0.71533 0.82600 0.48327
the apparent power capacity of the inverter, feeding by an h=41 1.59161 1.58414 4.81471
ideal three-phase voltage source. Fig. 3 (a) and (b) show the
resulting load currents in the abc and αβ0 reference frame,
respectively, using Clarke transform invariant in amplitude, III. D ISCRETE - TIME MODELING OF THE INVERTER
and Fig. 3 (c) shows its harmonic content. It can be observed
This section presents the discrete-time model of the TP4L-
that the load currents of α and β axes do not have the third
VSI shown in Fig. 1, considering the delay introduced by the
harmonic multiples, which are only present on 0 axis.
digital implementation.
Since the inverter must comply with the voltage distortion Let us consider fs >> f1 , where fs and f1 represent
limits, even when supplying unbalanced non-linear loads, the the sampling and fundamental frequency, and the loads as
resulting harmonic content for different unbalanced conditions disturbance. The average inverter state-space model can be
is also determined. These conditions are listed on Table II. obtained in the continuous-time domain, as shown in (2) [27],
Fig. 4 (a) shows the harmonic content of the load currents [28], being the inductor currents, iy , and phase voltages, vy ,
for the condition C1; compared to a balanced non-linear load, state variables, and uy the control inputs, where uα , uβ , and
ioα and io0 contain all the odd components, while ioβ does u0 form the reference vector of the three-dimensional space
not include the multiples of the third harmonic. The third vector modulation (3D-SVM).
component of io0 is also higher for the balanced condition.
After evaluating each condition indicated before, the max- ẋy (t) = Ay xy (t) + By uy (t) + Dioy (t) (2)
imum current values for each condition are shown in Fig. 4
(b). Finally, the three-phase harmonic impedance limits in the where y = α, β, 0,
αβ0 reference frame are obtained by evaluating (1) using the
1
   
maximum current values. Table III lists the results expressed 1
 0 0
Aα =Aβ = 1 Cr , A0 = C
in per-unit system, independent of the inverter parameters, and r+3rn ,
  
1
valid for balanced and unbalanced non-linear loads. − − − −
L L L+3Ln L+3Ln

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 This article has been accepted for publication in IEEE Journal of Emerging and Selected Topics in Power Electronics. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2023.3275230

4 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS

 
0 1
" # " #
0  
v
ioy
−
Bα=Bβ = VDC , B0= VDC  , D= C , xy= y , Fy Cv vy
0 iy
L L + 3Ln eiy uy _ φy
iy* +- KPiy Hy  -1
Z I3x3 Ci iy
By considering the load current ioy(t) = 0 and applying iy Gy
Plant
the Laplace transform to (2), the transfer functions that relate
Uy (s) to the state variables can be obtained for each axis as Fig. 5. Block diagram of the inner control loop.
follows:
Rh,y(z)
   
−1 P (s) V (s)/Uy (s)
Py (s)=(zI2×2 −Ay ) By= vy = y . (3) Evy(z) R1,y(z) Iy*(z)
Piy (s) Iy (s)/Uy (s)
The implementation of the digital controllers introduces a
KPvy
transport delay into the system defined as Td . Both iy and vy , Fig. 6. Block diagram of the PR controller.
are sampled in half of the switching period to avoid sampling
during the commutations, resulting: Td = T /2 [29].
impedance, allowing voltage references to be tracked and
To obtain the discrete-time state-space model of the inverter,
reject balanced and unbalanced load disturbances. On the other
(2) is solved in a sampling period, resulting [30],
hand, the voltage resonant stages at the harmonic frequencies
are tuned to meet the three-phase harmonic impedance limits
xy(k+1) = Φy xy(k) +Γ1y uy(k−1) +Γ2y uy(k) +Γ3y ioy(k) (4) obtained in section II.
where
A. Design of the inner current control loop
Φy=eAy T , Γ1y=Ay −1 eAy Td − I By ,
 
The open-loop transfer functions of the current control with
h i
Γ2y=Ay −1 eAy (T −Td ) − I By , Γ3y=Ay −1 eAy T − I D.
  the P controller result,

Expression (4) depends on both the current duty cycle, GiyP,OL (z) = [Iy (z)/Eiy (z)]P = KP iy Piy (z) (7)
uy(k) , and the duty cycle of the previous period, uy(k−1) .
The KP iy gain values for each axis are designed to meet a
Therefore, uy(k−1) is defined as a new state variable, uDy(k) ,
required phase margin PMP . To do this, from the frequency
that models the transport delay [29], [30]. The discrete-time
response of Piy (z) indicated in (6), the frequency value ωP
state-space model for each axis results,
for which the phase reaches the value of φP = −180◦ + PMP
( is obtained. From (7), and replacing z by ejωP T , the following
φy(k+1) = Gy φy(k) + Hy uy(k) + Fy ioy(k) can be obtained.
(5)
vy(k) = Cv φy(k) , iy(k) = Ci φy(k) ,
GiyP,OL (ejωP T ) = KP iy Piy (ejωP T ) (8)
where
  Therefore, the proportional gain that satisfies the imposed
      vy
Φy Γ1y Γ Γ phase margin condition results,
Gy= , Hy= 2y , Fy= 3y , φy= iy ,
01×2 0 1 0
uDy
    KP iy = 1/|Piy (ejωP T | (9)
Cv = 1 0 0 , Ci = 0 1 0 .
Then, with ioy(k) = 0 and applying the z-transform to (5), B. Design of the outer voltage control loop
the transfer functions that relate Uy (z) to the state variables Fig. 5 shows the block diagram of the plant with the
can be obtained for each axis by, inner loop previously designed. By solving this block diagram
with ioy = 0, and i∗y = 0, the model to design the outer
Pvy (z)
  
Vy (z)/Uy (z)
 loop controller (Gvy (z)) and the output impedance (Zoiy (z)),
−1
Py (z)=(zI3×3 −Gy ) Hy= Piy (z) = Iy (z)/Uy (z) . (6) respectively, can be obtained as (10) and (11), respectively.
PDy (z) UDy (z)/Uy (z)
Gvy (z)=Vy (z)/Iy∗ (z)=Cv zI3×3 −(Gy −Hy KP iy Ci) −1 Hy


IV. C ONTROLLER D ESIGN

(10)
This section presents the controllers design procedure for Zoiy (z)=Vy (z)/Ioy (z)=−Cv zI3×3 −(Gy −Hy KP iy Ci)−1 Fy
each axis and inner and outer loops. The proportional (P) (11)
controllers are designed to provide stability. In addition, the The block diagram of the PR controller for each axis is
resonant stages in the outer loop are incorporated to reduce shown in Fig. 6.
the output impedance at specific frequencies without compro- The resonant controller transfer function is shown in (12),
mising the stability achieved with the P controllers. where the first-order hold method is used for discretization
Voltage resonant controllers tuned at the fundamental fre- since it allows a high correlation with the continuous-time
quency on each axis are designed to reduce the output frequency response [31].

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 This article has been accepted for publication in IEEE Journal of Emerging and Selected Topics in Power Electronics. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2023.3275230

OGGIER et al.: CLOSED-FORM HARMONIC COMPENSATION IN FOUR-LEG VSI 5

Ioy(z)

cos (θh,y ) s − ωh sin (θh,y )
 Zoiy(z)
Rh,y (z) = KRh,y FOH (12) Vy*(z) Evy(z) PRvy(z) Iy*(z) Vy(z)
s2 + 2ωc s + ωh 2 _ Gvy(z)

where KRh,y is the gain, ωh = 2πhf1 rad/s is the resonant

frequency, h is the harmonic order, θh,y is the controller phase Fig. 7. Block diagram of the outer control loop.
at ωh , and ωc is the cut-off frequency of the resonant controller
which allows the digital implementation [9], [32].
The normalized inverter output impedance at each harmonic
1) Design of the proportional controllers: The Kpvy gains
frequency can be obtained from the following expression,
are designed following the same procedure described in sec-
tion IV-A, applied to the outer-loop transfer function with P

Iˆo
controller given by, Zov1y ejhω1 T = Zov1y ejhω1 T


pu
(21)
V̂o

MvyP,OL (z) = [Vy (z)/Evy (z)]P = KP vy Gvy (z).
2) Design of the fundamental frequency resonant con-
trollers: The PR controller with a resonant stage tuned at
ω1 = 2πf1 , P R1vy (z), and the resulting transfer functions
for the open and closed-loop system, are indicated in (14),
(15) and (16), respectively.
P R1,y (z) = Iy∗ (z)/Evy (z) = KP vy + R1,y (z)
M1vy,OL (z) = Vy (z)/Evy (z) = P R1,y (z)Gvy (z)
Vy (z) M1vy,OL (z)
M1vy (z) = ∗ = .
Vy (z) 1 + M1vy,OL (z)
The phase of the resonant controller θ1y designs according
to (17), to compensate the phase lag of the pre-compensated
outer loop with the P controller (18) at the ω1 frequency.
(13) where, h = (2p + 1); p = 0, 1, 2, . . . ; and z = ejhω1 T .
The output impedance values obtained from (21) are com-
pared with the three-phase harmonic impedance limits estab-
lished in Section II to identify the harmonic frequencies for
which resonant stages must be incorporated.
The next step consists of designing the phase contribution
and the gain for each resonant stage. The phase θh,y for each
R stage can be evaluated as
(14)
(15)
θh,y = −̸ M1vy ejωh T .


(22)
(16)
To determine the resonant gains, the block diagram shown
in Fig. 7 is solved for Vy∗ (z) = 0, obtaining the following
output impedance transfer function considering the resonant
stages at harmonic frequencies,

θ1y = −̸ MvyP ejω1 T ,

(17) Vy (z) Zoiy (z)
Zovh,y (z)= = Gvy (z). (23)
  Ioy (z) 1+KP vy +R1,y (z)+Rh,y (z)
Vy (z) KP vy Gvy (z)
MvyP (z) = = . (18) ′
∗
Vy (z) P 1 + KP vy Gvy (z) Finally, replacing Rh,y (z) by KRh,y Rh,y (z), according to
(29), the gain expression can be obtained for each resonant
A high value of KR1,y decreases the tracking error and the stage as follows
response time. However, an increase in this gain reduces the
phase margin of the open-loop transfer function [8].
Zoiy(z)−|Zhy|lim
 
Being ωa the gain crossover frequency of MvyP,OL (z), 1
KRh,y= −KP vy −R1,y(z)−1 ′
for which the phase margin PMP is evaluated, the following |Zhy|limGvy(z) Rh,y (z)
z=ejωhT
design criterion can be established for the phase lag introduced (24)
by the PR controller at ω = ωa , where |Zhy,lim | represents the harmonic impedance limit for
the harmonic order h, indicated in Table III, which is evaluated
P R1,y (ejωa T )

̸
max
= φmax ≤ 0.05PMP . (19) according to the following expression.
The experimental results presented later will confirm that V̂o
this design criterion is adequate to establish the maximum |Zhy,lim | = |Zhy,lim |pu . (25)
phase lag that can be admitted. Finally, the expression that Iˆo
allows evaluating the gain KR1,y to satisfy (19) is presented Fig. 8 shows a flowchart that summarizes the proposed
in the Appendix. controller design process. It can be seen that no iterations - or
3) Design of resonant stages at the harmonics frequencies: a trial-and-error process - are required, resulting in a closed-
Fig. 7 shows the simplified block diagram of the outer loop. form controller design.
By setting Vy∗ (z) = 0, the output impedance transfer function
with the resonant stage at the fundamental frequency can be
obtained as follows V. A PPLICATION OF THE PROPOSED DESIGN TO A
EXPERIMENTAL PROTOTYPE
 
Vy (z) Zoiy This Section applies the proposed control design to a 5-kVA
Zov1y (z)= = . (20) TP4L-VSI, whose parameters are given in Table IV.
Ioy (z) P R1v 1+(KP vy +R1,y (z))Gvy (z)

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6 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS

Inner loop - KPiy
Outer loop - R1(z) Outer loop - KPvy
Stablish the desired Phase margin (PMP) for the inner loop.
Find the frequency ωP at which the phase of the open loop
frequency response given in (7), reaches φP = -180°+PMP.
Calculate the KPiy gain using (9).

Stablish the desired PMP for the outer loop.

Find the frequency ωP for which the phase of MvyP,OL(z),
Calculate the Kreaches
given in (13), Piy gain using (9).
φP = -180°+PMP.
PMP=60°
Calculate the KPvy gain using (9).

Calculate the phase contribution θ1y using (17).

Fig. 9. Design of the inner loop with P controller.
Determine the maximum allowed phase margin reduction
introduced by the R1(z) using (19).
Calculate the KR1,y,max gain that satisfies (19) using (32).

Obtain the output impedance by (20).

From (20), obtain the output impedance at each harmonic
frequency, and normalize them using (21).
Outer loop - Rh(z)

Compare the results of (21) with the harmonic impedance

PMP=60° PMP=60°
limits listed in Table II to identify the frequencies at which PM=57° PM=57°
resonant stages must be incorporated.
Calculate the phase contribution θhy with (22).
(a) (b)
Obtain the output impedance with the incorporated Fig. 10. Design of the outer loop with P and PR controller at fundamental
Resonant stages using (20). frequency: (a) α and β axes, and (b) 0 axis.

Calculate the KRh,y gains using (24).

Fig. 8. Flowchart of the controller design process. not vary with the load condition at the cross-over frequency,
maintaining the desired phase margin.
TABLE IV
I NVERTER PARAMETERS
B. Design of the outer-loop PR controllers
Symbol Parameter Value
S Rated power 5 kVA Next, the design of the outer voltage control loop of each
VDC DC-Link voltage 600 V axis is presented, following the procedure indicated in the
Vo Rated RMS output phase voltage 220 V subsection IV-B.
V̂o Rated peak output phase voltage 311 V 1) Design of the proportional controller: Similar to the
Iˆo Rated peak output phase current 10.7 A inner-loop, the KP vy gains are designed to get, a 60◦ phase
f1 Fundamental frequency 50 Hz
L, Ln Output filter inductance 600 µH margin in MvyP,OL(z) on each axis (given in (13)), resulting
r, rn inductors resistence 0.2 Ω in the values indicated in Table V. The resulting frequency
C Output capacitors 48 µF responses of (13) are shown in Fig. 4, verifying the desired
fs Switching frequency 20 kHz phase margins.
T Switching and Sampling period 50 µs
2) Design of the resonant controller at the fundamental
Rd Rated resistive load 29 Ω
frequency: The phase angle of the resonant controllers of the
outer loop, θ1y , are calculated by (17), resulting in the values
given in Table V.
A. Design of the inner-loop proportional controllers
The KR1,y values are designed according to (32) for an
To achieve a good compromise between relative stability allowed phase lag introduced by the PR controller of 5%.
and transient response, the present paper adopts the criterion Fig. 10 shows the resulting frequency response of (15) with
that the desired phase margin PMP of the open-loop transfer the KR1,y gains indicated in Table V. The obtained phase
function given by (7) results in 60◦ . Following the design margins correspond to a decrease of 5% allowed concerning
procedure described in subsection IV-A, the gain values in- those achieved with the P controller, satisfying the condition
dicated in Table V are obtained. Fig. 9 shows the resultant (19).
frequency response of (7), where the desired phase margins of 3) Design of the resonant controller at the harmonic fre-
60◦ are obtained. In addition, the frequency responses when quencies: Fig. 11 compares the harmonic impedance limits
the inverter feeds the rated load (Rd ) are plotted in blue color. (see Table III) with the harmonic output impedance in per-
It can be observed that the phase response practically does unit system obtained by (21).

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 This article has been accepted for publication in IEEE Journal of Emerging and Selected Topics in Power Electronics. This is the author's version which has not been fully edited and
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OGGIER et al.: CLOSED-FORM HARMONIC COMPENSATION IN FOUR-LEG VSI 7

(a) (b) (c)

Fig. 11. Comparison between harmonic impedance limits (black bars) and output impedance (gray bars): (a) α axis, (c) β axis, and (c) 0 axis, highlighting
the harmonics required to be compensated.

PM=55.7°
101 102 103 104
Frequency (Hz)
Fig. 13. Resulting frequency response of Mv0,OL (z).
Fig. 12. Resulting output impedance: (a) α and β axes, and (b) 0 axis.

TABLE V
It can be concluded that the output impedance in the α and PARAMETERS OF THE INNER AND OUTER - LOOP CONTROLLERS
β axes complies with the harmonic impedance limits, avoiding y KP i KP v KR1 KR3 KR15 KR21 θ1 θ3 θ15 θ21
having to introduce additional resonant stages. In contrast, it α 0.00839 0.3830 170 - - - 1.8◦ - - -
requires three resonant controllers on the 0 axis, to reduce the β 0.00839 0.3830 170 - - - 1.8◦ - - -
0 0.04223 0.3196 114 1.2 3.6 2.7 2.5◦ 9◦ 41◦ 60◦
output impedance at the 3f1 , 15f1 , and 21f1 frequencies.
The θhv values of these new resonant stages are obtained
by (17), resulting in the phase values indicated in Table V.
The minimum gain values can be obtained from (24), with
h = 3, 15, 21, resulting in the values indicated in Table V. Current sensors LEM LA-55P

By adding these new resonant stages, the transfer function Voltage transducers LEM LV-25P
DSC TI-TMS F28335

of the PR controller, open-loop system and output impedance

for the 0 axis result in (26), (27), and (28), respectively.
Power analyzer

Load Command
P Rv0 (z) = KP v0 +R1,0 (z)+R3,0 (z)+R15,0 (z)+R21,0 (z) (26)
Mv0,OL (z) = V0 (z)/Ev0 (z) = P R0 (z)Gv0 (z) (27)
V0 (z) Zoi0 (z)
ZoT,0 (z) = = . (28)
Io0 (z) 1 + P R0 (z)Gv0 (z)
Output LC filter Loads Gate Drivers
Fig. 12 shows the frequency responses of the resulting
output impedance before and after including the compensation. Fig. 14. Experimental setup of the 3P4L-VSI prototype.
In the α and β axes, the impedance was compensated only at
f1 . In contrast, the output impedance of the 0 axis is reduced in
3f1 (150 Hz), 15f1 (750 Hz), and 21f1 (1050 Hz). The output IEC 62040-3. The control strategy is implemented using a
impedance evaluated in these frequencies by (21) results in: Texas Instruments TMS320F28335 digital signal controller
0.0648 p.u., 0.046 p.u., and 0.065 p.u., respectively, being all (DSC). The inverter was implemented using IGBT modules
of them lower than the limits given in Table III. The open-loop FF50R12RT4 from Infineon.
frequency response of (27) is shown in Fig. 13, with a stable
phase margin equals to 55.7◦ . A. Model validation through the frequency response
This section validates the models of the system expressed
VI. R ESULTS with the set of equations indicated in (6). This evaluation
This section presents experimental results using a TP4L-VSI compares the model’s frequency response with the one ob-
prototype shown in Fig. 14, with parameters indicated in Table tained using the experimental prototype. A small-amplitude
IV, following the test procedures indicated in the Standard sinusoidal signal was added to the uα and u0 components

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8 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS

950
950 Hz
Hz
550
550 Hz
Hz
Phase voltages (V)

450
450 Hz
Hz
Phase voltages (V)

650
650 Hz
Hz Frequency (Hz)
(a)

00 0.05
0.10
0.05
0.10 0.15
0.15 0.20
0.20
Time (sec.)
Time (sec.)
Fig. 15. abc reference-frame phase voltages under small-signal perturbations
of the 3D-SVM reference vector components: uα perturbation (top), and u0
perturbation (bottom). Frequency (Hz)
(b)
Fig. 16. Experimental validation of the discrete-time model and comparison
of the 3D-SVM reference vector (see Fig. 1), to perturb the with the continuous time model. (a) α and β axis, and (b) 0 axis.
system. Fig. 15 shows the waveforms of the output voltages in
the αβ0 reference-frame corresponding to the indicated axes vvan
an vvbn
bn v
vcn
cn
for two different frequencies, processed through Matlab to
obtain their representation in the αβ0 reference frame, and
then get the magnitude and phase at each frequency for all
axes. The results in Fig. 16 indicate the frequency response of
the continuous-time model given in (3) (blue dashed line),
the discrete-time model (solid line), and the one obtained
experimentally (red marks). A good correlation can be ob- 80% iioa
oa
80%
served between the experimental frequency responses and the
discrete-time model, in which the phase delay introduced by
the discretization is observed. This result differs from the
phase response obtained with the continuous-time model as 20%
20% 100%
100% 20%
20%
expected. (a)
IEC
IEC 62040-3
62040-3 overvoltage
overvoltage transient
transient limit
limit
B. Linear load results
Fig. 17 (a) shows the step linear load test, which consists
Load
Load decrease
decrease
of 80% of load step variations (between 20% and 100%) of
the rated one, achieving a fast voltage recovery with slight Load
Load increase
increase
variations. Fig. 17 (b) shows the RMS voltage deviation of
each phase. The deviation complies with the most stringent
limits indicated in the Standard IEC 62040-3. IEC
IEC 62040-3
62040-3 undervoltage
undervoltage transient
transient limit
limit
Fig. 18 shows the unbalanced linear load test. First, the
inverter operates at no-load. Then, the rated resistive load
is connected at two inverter phases. As a result, the phase (b)
voltages recover quickly from the transient, with an unbalance Fig. 17. 80% of linear load step test (20%, 100% and 20% of rated load),
and (b) RMS phase voltage variation.
factor (UF) in steady-state equal to 0.11%, lower than the limit
of 2% imposed by the Standard IEC 61000-2-2. In addition, it
can be observed that no oscillations are present in the transient
IEC 61000-2, when the inverter feeds the RNL load shown
response, which denotes the high phase margin achieved in the
in Fig. 2, whose parameters are detailed in Table I. Fig. 19
design process.
shows the result for balanced load, while Fig. 20 shows the
result for the unbalanced load, with two phases without load
C. Non-Linear load results (condition C4 of Table II) . It can be observed the compliment
Fig. 19 shows the steady-state non-linear load test, and the of all the individual harmonic distortion limits. On the other
FFT of the phase voltages along with the limits imposed by hand, the THD and UF comply with the limits indicated by

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OGGIER et al.: CLOSED-FORM HARMONIC COMPENSATION IN FOUR-LEG VSI 9

van vbn vcn

van vbn vcn

ion
No Load Loaded No Load

ioc

Fig. 18. Unbalanced linear load test (a)

.

van vbn vcn

(b)
Fig. 20. Steady-state unbalanced non-linear load test, with phases a and b
Loaded Loaded Loaded without load: (a) Phase voltages and output current io c, and (b) FFT of phase
voltages.

ioc TABLE VII

C OMPARISON OF THE PROPOSAL WITH REFERENCES BASED ON VOLTAGE
PR CONTROLLERS IN FOUR - LEG VSI
(a)
Total of THD Minimum UF UF Computa- Meet
Ref. voltage non-linear phase linear non-linear tional IEC
R-stages load margin load load cost 61000-2-2
[17] 21 3% - 0.3% 0.4% High -
[20] 12 2.61% - 0.46% 0.85% Medium -
[19] 12 4.82 % 31.5◦ - - Medium -
[18] 24 1.9% - - - High -
[21] 12 2.4% - - - Medium -
Proposal 6 ◦
4.1 to 4.8% 55.7 0.11% 1.6% Low Yes

(b)
Fig. 19. Steady-state balanced non-linear load test: (a) Phase voltages and
output current io c, and (b) FFT of phase voltages.
TABLE VI
THD AND UF VALUES FOR THE STEADY- STATE NON - LINEAR LOAD TESTS
%THD (LIM=8%)
Condition
van vbn vcn
Balanced (Fig. 20 (a)) 4.8% 4.8% 4.8%
Unbalanced C4 (Fig. 20 (c)) 1.2% 1.07% 4.1%
the standards IEC 62040-3 and IEC 61000-2-2, respectively,
as shown in Table VI.
Table VII compares the number of resonant stages used in
the outer voltage loop, the THD, the system phase margin, and
the UF obtained with the design proposed in this paper and
different design methodologies presented in the literature. It
can be observed that a very low THD is achieved in [18] and
[17]. Nevertheless, many resonant stages are used, increasing
the computational costs. Furthermore, this paper obtains a
phase margin higher than the one given in [19].
Fig. 21 shows the result adopting the voltage harmonic
compensation used in [19], [20], and [21], where resonant
stages are incorporated in 3f1 , 5f1 , and 7f1 frequencies,
obtaining a THD of 1.53%. However, the phase margins are
reduced to 40.7◦ for the α and β axis and 36.1◦ for the 0
axis. From this result, it can be seen that the 15th and 21st
individual harmonic distortion limits imposed by Standard IEC
61000-2-2 have not complied.
% UF
(LIM 2%) From this comparison it can be concluded that the proposed
0.05 % method allows the use of fewer resonant stages than mentioned
1.60 % in previous studies to meet the individual harmonic limits,
THD, and UF, without compromising the system stability, and
designing the controllers in a closed and sequential procedure.
VII. C ONCLUSION
A closed-form solution to design the voltage resonant con-
trollers of a three-phase four-leg inverter was proposed in this
work. The controllers were designed based on the discrete-
time inverter model in the αβ0 reference frame, considering
the phase delay introduced by the digital implementation.
The three-phase harmonic impedance limits were defined
for designing the outer voltage loop resonant controllers at
harmonic frequencies. This proposal makes identification of
the frequencies at which the output impedance of the inverter
must be reduced to comply with the individual harmonic limits

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10
van vbn vcn
Loaded Loaded Loaded
ioa
(a)
Amplitude (%)
x x
Harmonics order
(b)
Fig. 21. Steady-state balanced non-linear load test adopting the voltage
harmonic compensation used in [19], [20], and [21]: (a) Phase voltages and
output current ioa , and (b) FFT of phase voltages.
imposed by a determinate Standard for non-linear loads. In
this paper, the IEC 61000-2-2 was adopted to establish these
limits. This proposal facilitates the design of the controllers for
voltage harmonic compensation, allowing a minimum number
of resonant controllers, minimizing the phase lag, maximizing
the stability margins, and ensuring the compliment of the THD
and individual harmonic limits requirements.
The established three-phase harmonic impedance limits are
independent of the LC filter parameters. In addition, they are
expressed in the per-unit system, allowing the use in the design
of the voltage control of any three-phase four-leg inverter.
The results showed that the proposed methodology allows
complying with the harmonic distortion of the output voltages
according to the limits imposed by standards, even under
unbalanced conditions, using fewer resonant stages compared
to previous proposals.
A PPENDIX
The expression that relates φmax with the maximum gain
KR1,y that meets the condition (19) is deduced below. The
transfer function of the resonant controller can be written as,
′ vol. 18, no. 3, pp. 814–822, 2003.
R1,y (z) = KR1,y Rh,y (z) = KR1,y (N (z)/D(z)),
′ D. Abbott and S. F. Al-Sarawi, “Comparative Study of Discrete PI and
where R1y (z) represents the resonant controller expressed in
(12) with unity gain.
Replacing the variable z by ejωa T in (29), being ωa the
gain crossover frequency, yields
D(ejωa T )KP vy + N (ejωa T )KR1,y
P R1,y (ejωa T ) = . (30)
D(ejωa T )
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IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS
The terms N (ejωa T ) and D(ejωa T ) can be expressed as sum
of a real part (Re) and an imaginary part (Im), from which the
phase of (P R1y (ejωa T )) can be expressed as,

 φ = ̸ P R1,y (ejωa T)  
KP vy Im{D}+KR1,y Im{N} Im{D}
= tan−1 −tan−1 .
KP vy Re{D}+KR1,y Re{N} Re{D}
(31)
Replacing the value of φ by φmax in (31), the maximum
gain value KR1,y that satisfies the condition (19) results in,
Im{D} − QRe{D} KP vy
KR1,y,max ≤ , (32)
QRe{N } − Im{N }
where,
Q = tan φmax + tan−1 (Im{D}/Re{D}) .


ACKNOWLEDGEMENT
This research was supported by the Secretarı́a de Ciencia
y Técnica de la Universidad Nacional de Rı́o Cuarto (SeCyT,
UNRC), FONCyT (Agencia Nacional de Promoción Cientı́fica
y Tecnológica) and the Red MEIHAPER- CYTED.
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