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Marks 3
Marks 3
Sr. No Experiments
1 Introduction to Xilinx EDA software and to implement basic logic gates
Design and Implementation of 1-Bit,2-Bit,4-Bit and 8-Bit comparator in Xilinx by using
2
Verilog HDL
3 Design and Implementation of Half Adder, full adder and 4 bit Adder using Verilog
Design and Implementation of Half Subtractor ,Full Subtractor and 4 Bit Subtractor using
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Verilog
Design 8:3 Bit Encoder and 3:8 Bit decoder by using behavior modeling and data flow
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modeling techniques
Design 4:1 and 8:1 Multiplexer and 1:4 and 8:1 Demultiplexer in Verilog HDL and verify
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the code by Test bench
Design S-R flip-flop J-k Flip-flop T Flip-flop and D flip-flop using behavior modeling
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HDL
8 Design and Implementation of shift register; and its four types; SISO and SIPO,
9 Design and Implementation of shift register; and its four types; PISO and PIPO
Design and Implementation of Up counter, down counter and up/down counter by using
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HDL Verilog and its verification through test bench
11 Design and Implementation of Universal Shift register and bidirectional shift register
Design and Implementation of Moore& Mealy finite state machine using Verilog code
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and verify its test bench
13 Implementation of pulse 10 MHz PWM signal using Verilog and verify it on FPGA kit