Chapter 3 Final

Prepared By: Prof. C. S.
Mogare
Lecturer
MET BKC IOT Polytechnic, Nashik
9595159287
Prepared By: Prof. C. S. Mogare (9595159287)
Combinational Circuits:
 Its out put is depends on present input.
 Examples: Half adder, Full adder, Half Subtractor, Full Subtractor,
MUX, DEMUX.
Sequential Circuits:
 Its out put is depends on present inputs and past outputs.
 To store previous output memory element is required.
 Examples: All flip flops, registers, counters.
Comparison :
Combinational circuits Sequential circuits
• Its out put is depends on present input. • Its out put is depends on present inputs
as well as past outputs.
• Memory not required • Required memory unit.
• It is Faster. • It is Slower.
• These are easy to design. • These are difficult to design.

• Examples of combinational circuits are a
half adder, full adder, magnitude • Examples of sequential circuits are flip-
comparator, multiplexer, demultiplexer, flop, register, counter, clocks, etc.
etc.

One bit Memory Cell:

 NAND gates 1 & 2 are basically acting as inverter.
 Assume that output of gate 1 i.e. Q=1. Hence B2=1.
 As B2=1, output of gate 2 i.e. Q=0. This makes B1=0.
 Hence Q continues to be equal to 1.
 Similarly we can demonstrate that if we start with Q=0 then we
end up obtaining Q=0 & Q=1
 Output of circuit is always complementary i.e. If Q=0 then Q=1.

SR Latch:
 CASE I : S=0, R=0  CASE II : S=0, R=1  CASE III : S=1, R=0  CASE IV : S=1, R=1
Q= S+Q & Q= R+Q  As R=1 o/p of gate  As S=1 o/p of gate  If S=R=1 then one
 Insert S=R=0 1 i.e. Q=0. 2 i.e. Q=0. i/p of NOR gate 1& 2
 Q= 0+Q & Q= 0+Q  Hence both i/p of  Hence both i/p of is logic 1. So o/p of
gate 2 are 0 gate 1 are 0 both these gates will
 Q=0.Q & Q= 0.Q try to become 0.
therefore Q=1. therefore Q=1.
 Q=1.Q & Q= 1.Q  This case is avoided.
 Q= 0 & Q= 1  Q= 1 & Q= 0
 Q= Q & Q= Q
*Truth Table:
 A latch is basically an unclocked flip flop. INPUTS OUTPUTS States
and
Qn+1 Qn+1
*Circuit: *Symbol: S R (Present (Next Conditio
ns
State) State)
No
0 0 Qn Qn
1 Change
Reset
0 1 0 1
state
Set
1 0 1 0
state
2 1 1 1 1
Race
Avoid
Triggering of Flip flop:

 Providing clock signal to flip flop is called triggering.
 Flip flop perform its all operations as per particular clock signal.
 Four way of applying clock signal decides four triggering method.
1. Positive Level Triggering: Flip flop work at positive level of clock
2. Negative Level Triggering: Flip flop work at negative level of clock
3. Positive Edge Triggering: Flip flop work at positive Edge of clock
4. Negative Edge Triggering : Flip flop work at negative Edge of clock
CLK = 1 CLK = 0 CLK =

CLK =
Prepared By:Prof. C. S. Mogare (9595159287)
SR Flip flop JK Flip flop

INPUT OUTPUT INPUT OUTPUT
Qn+1 Qn+1 States Qn+1 Qn+1 States

S R (Present (Next J K (Present (Next
State) State) State) State)
0 0 Qn Qn No Change
Truth 0 0 Qn Qn No Change
0 1 0 1 Reset state 0 1 0 1 Reset state
1 0 1 0 Set state
Table 1 0 1 0 Set state
1 1 1 1 Race Avoid of 1 1 Qn Qn Toggle
Flip
INPUT OUTPUT
INPUT OUTPUT flops Qn+1 Qn+1 States
States T (Present (Next
Qn+1 Qn+1
State) State)
D (Present (Next
State) State)
0 Qn Qn No Change
0 0 1 Reset state
1 Qn Qn Toggle
1 1 0 Set state
T Flip flop
D Flip flop Prepared By: Prof. C. S. Mogare (9595159287)
SR Flip flop JK Flip flop
Ckt.
Dia.
of
Flip
flops
T Flip flop
D Flip flop Prepared By: Prof. C. S. Mogare (9595159287)
Working of positive Level triggered SR Flip flop:

 This Flip flop works with positive level of clock.
 If S = R = 0 then output of NAND gates 3 and 4 are forced to become 1.Hence R' and S' both will be
equal to 1. Since S' and R' are the input of the basic S-R latch using NAND gates, there will be no change
in the state of outputs.
 Since S = 0, output of NAND-3 i.e. R' = 1 and E = 1 the output of NAND-4 i.e. S' = 0. Hence Qn+1 = 0 and
Qn+1 bar = 1. This is reset condition.
 Output of NAND-3 i.e. R' = 0 and output of NAND-4 i.e. S' = 1.Hence output of S-R NAND latch is Qn+1 = 1
and Qn+1 bar = 0. This is the reset condition.
 As S = 1, R = 1 and E = 1, the output of NAND gates 3 and 4 both are 0 i.e. S' = R' = 0. Hence
the Race condition will occur in the basic NAND latch.
*Circuit: *Symbol: *Truth Table:
CLK
Positive Level triggered SR Flip flop :

*Circuit: *Truth Table:
INPUTS OUTPUTS
Qn+1 States
Qn+1
Clk S R (Present
(Next State)
State)
No
0 ✖✖ Qn Qn Change
No
✖✖ Qn Qn Change
No
✖✖ Qn Qn Change
No
1 0 0 Qn Qn Change
*Symbol: Reset
1 0 1 0 1 state
1 1 0 1 0 Set state
CLK = 1 CLK
Race
1 1 1 1 1 Avoid
Negative Level triggered SR Flip flop :

INPUTS OUTPUTS
Qn+1 States
Qn+1
Clk S R (Present
(Next State)
State)
No
No
✖✖ Qn Qn Change
No
✖✖ Qn Qn Change
No
0 0 0 Qn Qn Change
*Symbol: Reset
0 0 1 0 1 state
0 1 0 1 0 Set state
CLK = 0 CLK Race

0 1 1 1 1 Avoid

Positive Edge triggered SR Flip flop :

INPUTS OUTPUTS
Qn+1 States
Qn+1
Clk S R (Present
(Next State)
State)
No
No
No
✖✖ Qn Qn Change
No
0 0 Qn Qn Change
*Symbol: Reset
0 1 0 1 state
1 0 1 0 Set state
CLK = CLK Race
1 1 1 1 Avoid

Negative Edge triggered SR Flip flop :

INPUTS OUTPUTS
Qn+1 States
Qn+1
Clk S R (Present
(Next State)
State)
No
No
No
✖✖ Qn Qn Change
No
0 0 Qn Qn Change
*Symbol: Reset
0 1 0 1 state
1 0 1 0 Set state
CLK = CLK Race
1 1 1 1 Avoid

Positive Level triggered D Flip flop:

INPUTS OUTPUTS
Qn+1 Qn+1 States

Clk D (Present (Next
State) State)
0 ✖ Qn Qn No Change
✖ Qn Qn No Change
✖ Qn Qn No Change
1 0 0 1 Reset state
*Symbol:
1 1 1 0 Set state
CLK = 1

Negative Level triggered D Flip flop :

INPUTS OUTPUTS
Qn+1 States
Qn+1
Clk D (Present
(Next State)
State)
No
1 ✖ Qn Qn Change
No
✖ Qn Qn Change
No
✖ Qn Qn Change
Reset
0 0 0 1 state
*Symbol:
0 1 1 0 Set state
CLK = 0

Positive Edge triggered D Flip flop :

INPUTS OUTPUTS
Qn+1 States
Qn+1
Clk D (Present
(Next State)
State)
No
1 ✖ Qn Qn Change
No
0 ✖ Qn Qn Change
No
✖ Qn Qn Change
Reset
0 0 1 state
*Symbol:
1 1 0 Set state
CLK =

Negative Edge triggered D Flip flop :

INPUTS OUTPUTS
Qn+1 States
Qn+1
Clk D (Present
(Next State)
State)
No
1 ✖ Qn Qn Change
No
0 ✖ Qn Qn Change
No
✖ Qn Qn Change
Reset
0 0 1 state
*Symbol:
1 1 0 Set state
CLK =

Positive Level triggered JK Flip flop :

INPUTS OUTPUTS
Qn+1 States
Qn+1
Clk J K (Present
(Next State)
State)
No
No
✖✖ Qn Qn Change
No
✖✖ Qn Qn Change
No
1 0 0 Qn Qn Change
*Symbol: Reset
1 0 1 0 1 state
1 1 0 1 0 Set state
CLK = 1 CLK
1 1 1 Qn Qn Toggle

Negative Level triggered JK Flip flop :

INPUTS OUTPUTS
Qn+1 States
Qn+1
Clk J K (Present
(Next State)
State)
No
No
✖✖ Qn Qn Change
No
✖✖ Qn Qn Change
No
0 0 0 Qn Qn Change
*Symbol: Reset
0 0 1 0 1 state
0 1 0 1 0 Set state
CLK = 0 CLK
0 1 1 Qn Qn Toggle

Positive Edge triggered JK Flip flop :

INPUTS OUTPUTS
Qn+1 States
Qn+1
Clk J K (Present
(Next State)
State)
No
No
No
✖✖ Qn Qn Change
No
0 0 Qn Qn Change
*Symbol: Reset
0 1 0 1 state
1 0 1 0 Set state
CLK = CLK
1 1 Qn Qn Toggle

Negative Edge triggered JK Flip flop :

INPUTS OUTPUTS
Qn+1 States
Qn+1
Clk J K (Present
(Next State)
State)
No
No
No
✖✖ Qn Qn Change
No
0 0 Qn Qn Change
*Symbol: Reset
0 1 0 1 state
1 0 1 0 Set state
CLK = CLK
CLK
1 1 Qn Qn Toggle

Positive Level triggered T Flip flop:

INPUTS OUTPUTS
Qn+1 Qn+1 States

T Clk T (Present (Next
State) State)
No
0 ✖ Qn Qn Change
No
✖ Qn Qn Change
No
✖ Qn Qn Change
No
1 0 Qn Qn Change
*Symbol: 1 1 Qn Qn Toggle
Negative Level triggered T Flip flop:

INPUTS OUTPUTS
Qn+1 Qn+1 States

State) State)
No
1 ✖ Qn Qn Change
No
✖ Qn Qn Change
No
✖ Qn Qn Change
No
0 0 Qn Qn Change
*Symbol: 0 1 Qn Qn Toggle
Positive Edge triggered T Flip flop:

INPUTS OUTPUTS
Qn+1 Qn+1 States

State) State)
No
0 ✖ Qn Qn Change
No
1 ✖ Qn Qn Change
No
✖ Qn Qn Change
No
0 Qn Qn Change
*Symbol: 1 Qn Qn Toggle
Negative Edge triggered T Flip flop:

INPUTS OUTPUTS
Qn+1 Qn+1 States

State) State)
No
0 ✖ Qn Qn Change
No
1 ✖ Qn Qn Change
No
✖ Qn Qn Change
No
0 Qn Qn Change
*Symbol: 1 Qn Qn Toggle
Positive Level triggered Master Slave JK Flip flop :

INPUTS OUTPUTS
Qn+1 States
Qn+1
Clk J K (Present
(Next State)
State)
No
No
✖✖ Qn Qn Change
No
✖✖ Qn Qn Change
No
1 0 0 Qn Qn Change
*Symbol: Reset
1 0 1 0 1 state
1 1 0 1 0 Set state
CLK = 1 CLK
1 1 1 Qn Qn Toggle

Clock Possibilities in States & Output which

All Flip flops : we observe in Flip flops :
OUTPUTS
Qn+1 States
Qn+1
(Present
(Next State)
State)
No
Qn Qn Change
Reset
0 1 state
Set
1 0 state
Race
1 1 Avoid
Qn Qn Toggle

Preset & Clear inputs in Flip flop:

*Symbol:
 Asynchronous inputs on a flip-flop have control over the outputs (Q and not-Q)
regardless of clock input status.
 These inputs are called the preset (PRE) and clear (CLR).
 The preset input drives the flip-flop to a set state while the clear input drives it to
a reset state.
 Asynchronous inputs, just like synchronous inputs, can be engineered to be
active-high or active-low. If they’re active-low, there will be an inverting bubble
at that input lead on the block symbol, just like the negative edge-trigger clock
inputs.
Positive Edge triggered D Flip flop with PRE & CLR :

 Here, Asynchronous inputs are *Truth Table:
active-low, there will be an INPUTS OUTPUTS
inverting bubble at that input Qn+1 States
Qn+1
lead on the block symbol. CLR PRE Clk D (Present
(Next State)
State)
 The preset = 0 drives the flip-
No
flop to a set state while the 1 1 1 ✖ Qn Qn Change
clear = 0 drives it to a reset
No
state. 1 1 0 ✖ Qn Qn Change
 PRE=CLR= 1 Flip flop work No
Normally. 1 1 ✖ Qn Qn Change
Reset
*Symbol: 1 1 0 0 1 state
1 1 1 1 0 Set state
Reset
0 1 ✖ ✖ 0 1 state
CLK = ✖ ✖
1 0 1 0 Set state

Race Around condition in JK flip flop:

 As you can see, when J, K and Clock are equal to 1, toggling takes place, i.e. The
next state will be equal to the complement of the present state.
 In level triggered JK flip flop whenever Clock is enabled and J=K=1 there are
consecutive toggling. This condition is called as Race around condition.
 How to avoid toggling:
1. Use of edge-triggered flip-flop
2. Use of master-slave JK flip-flop
3. Increasing the delay of flip-flop

Assignment:
Draw Symbol, Circuit Dia., applications & Truth table of this flip flop
1.
i)SR ii)JK iii) D iv) T .
Q.3 c) Draw waves for positive and negative edge triggering with proper labeling. W-18
2.
Identify two situations where these triggering can be used?
3. Q.4 c) Compare 1. combinational and sequential circuits 2. D FF and T FF. W-19
Q.4 d) Describe race-around condition in JK flip flop and suggest ways to
4. S-19
overcome it.
Q.5 b) Describe the principle of working of JK FF and draw its circuit diagram and
5.
truth table.
Q.3 c) For the given circuit, identify the W-19
inputs and outputs. Name the circuit
6.
and draw its truth table.
7. How to covert flip flop SR in to D & JK in to T.

8. Explain S-R flip flop using NOR gate. Write truth table.
Draw output waveform at point A S-22
9. and at point B for the circuit shown
in given Figure
Thank You

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Prepared By: Prof. C. S.

• Memory not required • Required memory unit.

• These are easy to design. • These are difficult to design.

Prepared By: Prof. C. S. Mogare (9595159287)

One bit Memory Cell:

Prepared By: Prof. C. S. Mogare (9595159287)

Triggering of Flip flop:

CLK = 1 CLK = 0 CLK =

SR Flip flop JK Flip flop

Qn+1 Qn+1 States Qn+1 Qn+1 States

0 1 0 1 Reset state 0 1 0 1 Reset state

1 1 1 1 Race Avoid of 1 1 Qn Qn Toggle

SR Flip flop JK Flip flop

Working of positive Level triggered SR Flip flop:

Positive Level triggered SR Flip flop :

Negative Level triggered SR Flip flop :

CLK = 0 CLK Race

Prepared By: Prof. C. S. Mogare (9595159287)

Positive Edge triggered SR Flip flop :

Prepared By: Prof. C. S. Mogare (9595159287)

Negative Edge triggered SR Flip flop :

Prepared By: Prof. C. S. Mogare (9595159287)

Positive Level triggered D Flip flop:

Qn+1 Qn+1 States

Prepared By: Prof. C. S. Mogare (9595159287)

Negative Level triggered D Flip flop :

Prepared By: Prof. C. S. Mogare (9595159287)

Positive Edge triggered D Flip flop :

Prepared By: Prof. C. S. Mogare (9595159287)

Negative Edge triggered D Flip flop :

Prepared By: Prof. C. S. Mogare (9595159287)

Positive Level triggered JK Flip flop :

Prepared By: Prof. C. S. Mogare (9595159287)

Negative Level triggered JK Flip flop :

Prepared By: Prof. C. S. Mogare (9595159287)

Positive Edge triggered JK Flip flop :

Prepared By: Prof. C. S. Mogare (9595159287)

Negative Edge triggered JK Flip flop :

Prepared By: Prof. C. S. Mogare (9595159287)

Positive Level triggered T Flip flop:

Qn+1 Qn+1 States

Negative Level triggered T Flip flop:

Qn+1 Qn+1 States

Positive Edge triggered T Flip flop:

Qn+1 Qn+1 States

Negative Edge triggered T Flip flop:

Qn+1 Qn+1 States

Positive Level triggered Master Slave JK Flip flop :

Prepared By: Prof. C. S. Mogare (9595159287)

Clock Possibilities in States & Output which

Prepared By: Prof. C. S. Mogare (9595159287)

Preset & Clear inputs in Flip flop:

Positive Edge triggered D Flip flop with PRE & CLR :

Prepared By: Prof. C. S. Mogare (9595159287)

Race Around condition in JK flip flop:

Prepared By: Prof. C. S. Mogare (9595159287)

7. How to covert flip flop SR in to D & JK in to T.

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