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Chapter 02 Programmable Logic Device
Chapter 02 Programmable Logic Device
• F = A’B + AB’ + AB
• Product of Sums (POS)
• To get the desired canonical POS expression we will multiply the maxterms
(sum terms) for which the output is 0.
• F = (A+B) . (A’+B’)
Simple Programmable Logic Device (SPLD)
• Programmable Array Logic (PAL)
• Generic Array Logic (GAL)
• The structure of PAL and GAL is composed of the programmable AND
followed by the programmable OR gate.
• PAL, GAL can be used to configure the Sum of Product logic circuit.
Input lines
Input buffer
A B A B A A B B
A B A B A
Fix connection
B
Product
2
X 2 X=AB+AB+AB
X=AB+AB+AB term
lines
2
GAL:
reprogrammable
OR Output
logic O3
GATE
In-1 OR Output
In logic Om
GATE
Macrocell
Tristate control
From Output/input
and gate
array
Programmable fuse
Complex Programmable Logic Device (CPLD)
• CPLD is consist of SPLDs
IO IO
block block
IO IO
block block
IO IO
block block
IO IO IO IO
block block block block
FPGA
CLB
CLB CLB
Logic module Logic module
Global column
Global row
interconnect
interconnect
Logic Module – Lookup table (LUT)
A2 A1 A0 A2 A1 A0 A2 A1 A0 A2 A1 A0 A2 A1 A0