Q(1) Choose the correct answer from multiple choices : [10 Marks]

1. What are the limitations of memory system performance?

A. Instruction execution and scheduling
B. Latency and bandwidth
C. Parallelism and throughput
D. Data dependency and resource dependency
2. What is the physical organization of parallel platforms?
A. Communication model and routing mechanisms
B. Implicit parallelism and trends in microprocessor architectures
C. Processor, memory system, and datapath
D. Mapping techniques and case studies
3. What are the communication costs in parallel machines?
A. Physical organization of parallel platforms
В. Messaging cost models and routing mechanisms
C. Limitations of memory system performance
D. Dichotomy of parallel computing platforms
4. What are the different types of processors?
A. Pipelining and superscalar execution
B. Very Long Instruction Word (VLIW) processors
C. Microprocessor, microcontroller, embedded processor, digital signal processor
D. Single-core, dual-core, Quad-core, Hexa core, Octa-core, and Deca core processor
5. What is the purpose of parallelism in different applications?
A. Utilize high aggregate throughput, network bandwidth, and processing/memory system
performance
B. Achieve high parallelism using multiple pipelines
C. Improve memory system performance using caches
D. Address performance bottlenecks in processor, memory system, and datapath
6. What is the concept of pipelining in processors?
A. Using multiple pipelines to alleviate bottlenecks
B. Overlapping stages of instruction execution to achieve performance
C. Executing multiple instructions in the same cycle,
D. Scheduling instructions based on data dependencies and resource dependencies
7. What are the limitations of pipelining?
A. In-order issue and dynamic issue
B. Conditional jumps and misbehavior penalties
C. Resource dependency and scheduling constraints
D. True data dependency and branch dependency
8. What is the purpose of superscalar execution?
A. Identify and bundle together instructions for concurrent execution
B. Improve memory system performance using caches
C. Execute multiple instructions concurrently based on scheduling factors
D. Issue instructions in the order they are encountered
9. What is the advantage of VLIW processors?
A. Reduce hardware cost and complexity of the scheduler
B. Utilize compile-time analysis to extract parallelism
C. Improve memory system performance using caches
D. Execute instructions out of order for better performance
10. The core application of uses with Embedded systems in parallel computing?
A. Cryptography
B. Commercial Applications
C. Distributed control algorithms
D. Search applications
11. When clock rates of high-end processors are increased by approximately 40% per year over the past
decade. DRAM access times have only improved at the rate of approximately 10% per year over
this interval. Coupled with increases in instructions executed per clock cycle.
(a) Computational Argument
(b) Data Communication Argument
(c) Disk Space Argument
12. One of these applications forms a major problem requiring the use of supercomputing in the parallel
domain.
(a) Structural Mechanics.
(b)Computational Biology.
(c) Commercial Applications
13. With a high level of abstraction. it can be executed an instruction while the next one is being decoded
and the next one is being fetched.
(a)Pipeline
(b)Channel
(c) Conduit
14. ________ resembles the study of designing algorithms such that the time complexity is minimum. Thus
the speed-up factor is taken into consideration.
(a) Parallel computing
(b) Parallel computer
(c) Pipelining
15. Instructions that can be executed concurrently arc packed into groups and parcelled off to the
processor as a single tong instruction word to be executed on multiple functional units at the
same time.
(a) Uniprocessor
(b) VLIW processor
(c) Core processor
16. It is a unit considered a measure of computer performance, and it can compute peak processor rating,
so it is useful in fields of scientific computations.
(a) KPIs
(b) GHz.
(c) FLOPS
17. is the rate at which data can be pumped to the processor by the memory system.
(a) Bandwidth
(b) Latency
(c) Dormancy
18. An architecture referred to as a single instruction swam. a single control unit dispatches instructions to
multiple processing units. The instruction is executed synchronously by all processing units.
(a) SIMD
(b) MIMD
(c) MISD
19. the communication model in which networks communicate point-to-point communication links among
processing nodes is referred to as
(a) Dynamic network
(b) Static network
(c) Immobile network
20. Processor operating at I GHz (I ns clock) connected to a DRAM with a latency of 100 ns. Also, it has two
multiply-add units and can execute eight instructions in each cycle of 1 ns: as well as and has a
cache of size 32 KB. which takes approximately 4 us with a latency of one cycle. It is used to
compute the multiply two matrices A and 13 of dimensions 16 n 16. The peak computation rate
of that processor is
(a) 3 FLOPS
(b) 4 FLOPS
(c) 5 FLOPS
Q(2) Identify the correct statements from the wrong statements as follows: [10 Marks]
1. In the PRAM model, all processors operate asynchronously under a single clock. (F)

2. In parallel computation, the code fragment provided sums rows of the matrix into a vector
column_sum. (T)

3. In multiplying a matrix with a vector, computing each element of the result as a dot product of
a row of the matrix with the vector is more efficient than multiplying column-by-column. (F)

4. Exploiting spatial and temporal locality in applications has no impact on memory latency or
effective memory bandwidth. (F)

5. The ratio of operations to memory access is not a good indicator of anticipated tolerance to
memory bandwidth. (F)

6. Organizing computation appropriately does not affect spatial and temporal locality. (F)

7. Dynamic interconnection networks are also known as direct networks. (F)

8. In current parallel computers, the per-hop time t ₕ is greater than t ʷ. (F)

9. For most parallel algorithms, the per-hop time t ₕ is less than t ʷ *m, even for small values of
m. The total communication cost for a message in a parallel machine is directly proportional to
the number of communication links. (T)

10. In dynamic interconnection networks, switches, and communication links are not used. (F)

11. If the time taken by a processor to access any memory word in the system is identical. the
platform is classified as (UMA). (T)

12. The time is taken to put a memory request and returns a block of data of size P containing the
requested word is referred to as the latency of the memory (T)

13. A parallel Computer is a collection of processors. typically, of the same type. interconnected
in a certain fashion to allow the coordination of their activities and the exchange of data. (T)

14. In the aggressive model instructions can be issued only in the order in which they are
encountered. (F)

15. VLIW processors rely on compile-time analysis to identify and bundle together instructions
that can be executed concurrently (T).
 16. In distributed address space platform is ensuring that concurrent operations on multiple
copies of the same memory have well-defined semantics (T).

17. Buses are responsible for transferring data to and from the computer's internal hardware
such as memory. processor. and input and output devices (T).

18. Memory bandwidth can be improved by increasing the size of memory blocks (T)

19. Interactions of processing nodes in the network are accomplished using messages

non-synchronically among the process. during message passing in the network model (F).

20. The memory computer is historically used for architectures in which the memory is physically
shared among various processors. (T)

Q (3) Match the following with their utilization of parallel platforms: (5 Marks]
Application Utilization
1. Automobile processors A. Embedded systems
2. Mail servers B. Large scale servers
3. Network intrusion detection C. Optimizing business and marketing decisions
4. Overlay networks D. Structured peer-to-peer networks
5. Data mining and analysis E. Computer Systems
1. Automobile processors __ A. Embedded systems
2. Mail servers __ B. Large scale servers
3. Network intrusion detection __ E. Computer Systems
4. Overlay networks __ D. Structured peer-to-peer networks
5. Data mining and analysis __ C. Optimizing business and marketing decisions