Lecture 01 ES 221 V2

University of Dar es Salaam
ES 221: Digital electronics II
6 May 2021 1
Outline
1. Introduction
1.1 Basic digital electronics circuit
1.2 Digital data notation
1.3 The structure of sequential circuits
1.4 Finite state machines
6 May 2021 2
1.1.1 Logic Signals
• Variables in a Boolean expression take

 either logic 1
 or logic 0 states
• These states in electronics circuits are represented by two distinct voltage
levels as switching signals–
 HIGH voltage or
 LOW voltage
• How LOW and how HIGH in voltage magnitudes depends on the technology
in use.
6 May 2021 3
1.1.1 Logic Signals
Positive and Negative Logic

Relating Logic 0 and Logic 1 to voltage levels:
For Positive Logic For Negative Logic
Logic 0 is for LOW voltage, Logic 1 is for LOW voltage
e.g. logic 0→0V e.g: logic 1 → 0V,
Logic 1 is for HIGH voltage,
e.g. logic 1 → 5V Logic 0 is for HIGH voltage
e.g: logic 0 → 5V,
6 May 2021 4
1.1.1 Logic Signals Different technologies are used in deriving a circuit to
implement the gate truth table
Logic gates are electronic circuits having
Different technologies have different voltage levels:
 input terminals where input variables, say, A, B,
C,… are applied and Common Technologies with ideal logic voltage levels are:
 output terminals where the function of input Transistor Transistor Logic (TTL): 0V→ logic LOW
variables comes out, e.g. Q(A,B,C,…) 5V → logic HIGH.
Complementary Metal Oxide Semiconductor (CMOS)

Both input and output terminals will be at either technology: 0V → logic LOW
LOW or HIGH voltage levels any voltage above 3.5V → logic HIGH
Emitter Coupled Logic (ECL) technology:

0V → logic HIGH –5.2V → logic LOW
6 May 2021 5
1.1.1 Logic Signals
The actual waveform of Q(A,B,C,…) differ from an ideal one due to the finite response time
of circuit components.
 Delay Time:
Normally the output waveform will be delayed by time Td: Td = (td(LH) + td(HL))/2
t
td(LH) td(HL)
6 May 2021 6
1.1.1 Logic Signals
Slew Rate
The rise and fall of
the logic levels
(voltage) take time:
tr = rise time,
tf = fall time,
Transition times are due to capacitive and inductive effects

of components.
It is important the period of the input signal to be low
enough to allow rise and fall time of the circuit
6 May 2021 7
1.1.2 Signal Level Limits
A logic high or low signal

is interpreted correctly
if it falls within the
acceptable magnitude
ranges.
i.e. ≥ VOHmin, ≤ VOLmax ,
≥ VIHmin, ≤ VILmax
The voltage ranges between the limiting voltage values are

not allowed.
6 May 2021 8
• Current Limits
The forbidden region is a measure of  Each component has a limited capacity of sourcing or sinking
discrimination between noisy signals. current
 Sinking current
 LOW level input current, IIL
 LOW level output current IOL
Noise margins:
NMH =VOHmin -VIHmin,

NML =VILmax- VOLmax
The values of the limits vary with

technologies and the power supply
magnitude used
6 May 2021 9
Sourcing Current
HIGH level input current, IIH Fan Out
HIGH level output current, IOH The number of components that can be driven by a gate
without exceeding the current and voltage limits
Example:
From Sinking Current circuit:
The maximum number of gates connected
N=16/1.6=10
From Sourcing Current circuit:
The maximum number of gates connected,
N=400µA/40µA=10
Fan out=10
6 May 2021 10
1.1.3 Logic Families/Technologies Diode Resistor Logic Technology
With two inputs A, B and one output Q
What is inside the gates? The truth table holds:
These are electronic circuits of different

technologies with different characteristics:
They have different:

Power supply values
Speed
Power consumption
Driving power-fan in and fan out
Integration level
What is the Boolean expression for the circuit?
6 May 2021 11
Resistor Transistor Logic technology
Transistor as a Switch
Consider Analogue operation
Characteristics:
Input: Vcc=IBR1+VBE
Output: Vcc=ICRL+VCE IC
Transfer: IC=hFE. IB
Signals: Vi= Vbe, Vo= Vce
Regions:
Active, Cut-off, Saturation.
Pmax< (IC)(VCE)
VCE
6 May 2021 12
Resistor Transistor Logic (RTL) technology

Characteristics of RTL technologies:
The first logic gates circuits(1962)used transistor circuit
Typical ratings:
amplifier as a switch.
Regions of operation:  Power supply =+3.6V,
saturation
cut-off region  Fan-out =5,
 Power dissipation, Pd (average)
Forbidden region: =(VCC(ICCH + ICCL))/2
Active Region =16 mW,
Power rating , P= ICVCE is exceeded
Propagation delay time, tp
=(tpHL + tpLH)/2
Since it was using resistors and transistors only it was =12 nsec.
called RTL technology.
6 May 2021 13
NMH =VOH -VIH, NML =VIL- VOL
VOH =1.2V, VOL= 0.2V,

VIH = 0.8V VIL = 0.7V
NMH/NML = 0.4/0.5V, Logic swing = 1.0V
Advantages :
Simple, Low power dissipation
Disadvantages:
Small logic swing, Small noise margin
6 May 2021 14
Diode Transistor Logic (DTL) technology
Diodes are added to isolate and control current flow

between two cascaded gates.
When transistor is cut-off

Voltage VQ=VCC=4V
Input voltages at A and B
equal to zero,
VD4(on) =0.7V,
Hence x <VBE(on)
When transistor is saturated VQ=VSAT=0.1V.

Input voltages VIH, at A and B
VIH>VBE(sat)+2VD(on), VBE(sat)=0.8V
6 May 2021 15
Diode Transistor Logic (DTL) technology
 DTL, as a driver, behaves as a current sink of current

from the diodes when it is LOW .
 When HIGH no current is sourced from the DTL driver

due to reverse biased diodes, giving high fan-out, as an
advantage.
C.F.: RTL behaves as a current source for the
load minimizing the fan out.
Disadvantage of DTL:
Higher propagation delay time,
Need more silicon material for integration.
6 May 2021 16
Transistor Transistor Logic (TTL) technology

Characteristics:
An improvement of DTL where diodes are Power supply = 5.0V,
implemented by transistors. Commonest Power dissipation 10mW
technology. Propagation delay time 10nsec
Fan out = 10
The surface area of integration is reduced, VOH/VOL=3.5/0.2V, VIH/VIL = 1.5/0.5V

Use of transistors improve fan out and fan- NMH/NML = 2/ 0.3V, Logic swing = 3.3V
in.
6 May 2021 17
Transistor Transistor Logic (TTL) technology √Reduction of Power Dissipation
This is achieved by designing transistor circuits with
New TTL Circuits
Schottky diodes to produce Schottky transistors. These
are TTL series 54/74S.
Designers wanted high speed and low power at the
same time I.e. the speed power product. A new TTL
technology was developed. In addition to Schottky designs the resistances were
increased to reduce power consumption.
Increasing Speed
To reduce propagation delay time the transistors Series 54/74LS represent Low power Schottky
usually driven to saturation are biased so that they components.
do not go deep to saturation. This reduces the
charging and discharging time of the transistor’s
parasitic capacitance.
6 May 2021 18
Comparison of some standard Schottky circuits.
To meet different requirements a combination of TTL

technology is employed. Different series are obtained.
Examples of TTL families:

74AS-Advanced Schottky TTL: double the speed of 74S
series.
74ALS- Advanced Low-Power Schottky: offers lower

power and higher speed than 74LS series.
74F-Fast TTL - good power-speed product. Most

popularly used in communication.
6 May 2021 19
Transistor Transistor Logic (TTL) technology Some Advanced Schottky gates
Note the improvement of power – speed product
Advanced Schottky Transistors
High integration suffers from high power dissipation

Fast communication call for fast components.
The standard Schottky circuits are not adequate.

With limitation, Advanced Schottky transistors are in
use
6 May 2021 20
TRISTATE
Some TTLs are designed to have a control input so

that it can be enabled or disabled to receive data.
6 May 2021 21
Open Collector Circuits

Open collector components should use pull-down resistors
Rpd or pull-up resistors Rup that limit the maximum source or
sink currents from or to the gate.
To boost fan-out one can select the appropriate load resistance

RL to be connected to the Output transistor.
If large current is required then RL can be made small.
6 May 2021 22
Emitter Coupled Logic
 DTL and TTL technologies operate at cut-off and

saturation regions.
 The saturation region contributes a great deal in

delay time.
The current switches between Q1’s collector
 Before the advent of Schottky diodes an obvious and Q2’s collector as Vin switches between logic
solution to the delay time problem was to design levels
switching voltage levels to fall within the active
region.
 This was achieved using a differential (long tail pair)

amplifier.
1.1 Basic digital electronics circuit If any input in the ECL gate is high, the
corresponding transistor is turned on and Q5
is turned off.
6 May 2021 24
Characteristics for 10K series ECL Characteristics for 100K series ECL
Propagation delay time = 2nsec. Shorter propagation time =0.75 nsec.
Fan out = 10 Shorter transition time (rise and fall time)=0.7 nsec
Power dissipation = 24mW Higher power consumption = 40mW per gate
Power supply = -5.2V Good fan out of 20 to 30.
Logic swing = 0.8V ECL maintain constancy in power usage with varying
frequency
NMH/NML = 0.3V/ 0.3V,
VOH/VOL=-0.9/-1.7V,
VIH/VIL = -1.2/-1.4V
6 May 2021 25
1.1 Basic digital electronics circuit CMOS Logic Levels
Metal Oxide Technology Logic levels for CMOS depend on supply voltage VDD
Based on old transistor technology –MOSFET VDD of many CMOS components can vary from 3.5V-15V
Currently use complementary MOS transistors With typical VDD=5 the voltage ranges shown apply
(CMOS)
Older technology than bipolar technology failed to

flourish due to fabrication problems
Liked by designers due to low power dissipation and

higher level of integration.
Commonly used in LSI and VLSI
6 May 2021 26
MOS Transistors
Transistors operate as voltage driven switches (cf

bipolar transistor switches)
The gate current is zero but presence of a voltage at

the gate produces a field effect, hence MOSFET Q1 acts as the load resistor
Two complimenting transistors are normally used Q2 as the active device
-p-channel and The load resistor MOS has its gate connected to
VDD, thus maintaining it always in the
n-channel conduction state.
6 May 2021 27
Characteristics for CMOS
The fan-out of CMOS devices is usually greater than 50
The propagation delay times for CMOS are 60 nsec for

VDD = 5 V, and 25 nsec for VDD = 10 V.
Figure : Dynamic Power Dissipation of a Typical CMOS

Logic Gate.
6 May 2021 28
The basic building blocks for digital circuits are the gates – AND, NAND, OR, NOR, EXOR, and NOT
A B A B C
C
0 0 0 A 0 0 1
A
C 1 0 & C 0 1 1
& 0 B
B 1 0 1
1 0 0
1 1 1 1 1 0
The symbol and truth table of an AND gate The symbol and truth table of an NAND gate
6 May 2021 29
1.1 Basic digital electronics circuit…
A B C
A B C
A 0 0 1
A 0 0 0 >= 1 C 0 1 0
>= 1 C 0 1 1 B
B 1 0 0
1 0 1
1 1 0
1 1 1
The symbol and truth table of an OR gate The symbol and truth table of an NOR gate
6 May 2021 30
1.1 Basic digital electronics circuit…
A B C A C
A 0 0 0
C C 0 1
=1 0 1 1 A 1
B
1 0 1 1 0
1 1 0
The symbol and truth table of an EXOR gate The symbol and truth table of an NOT gate
6 May 2021 31
1.2 Digital data notation
All digital information is represented in sequences of 1's and 0's, the two binary digits or bits.
Octal (3 bit values), decimal (4 bit values) and hexadecimal (4 bit values) are obtained from bits.
For standardization, the byte (8 bits) is used for binary data, the ASCII code (7 bits) is used for text.
Data is mostly stored as series of 8 0's and 1's (bytes) in consecutive storage locations or memory.
6 May 2021 32
1.3 The structure of a sequential circuit
There are three types of sequential circuits, or Finite State Machines.
Moore Sequential Circuits Mealy Sequential Circuits
In which the present outputs are a function of only the previous inputs.
In which the present outputs are a function of both the present
and previous inputs.
INPUT BISTABLE OUTPUT
COMBINAT. MEMORY COMBINAT.
CIRCUIT DEVICE CIRCUIT INPUT BISTABLE OUTPUT
CIRCUIT DEVICE CIRCUIT
Fig. A more type sequential circuit
Mixed Type Circuits Fig. A mealy type sequential circuit

Which have both Moore type and Mealy type outputs
INPUT BISTABLE OUTPUT

CIRCUIT DEVICE CIRCUIT
Fig. A mixed type sequential circuit

6 May 2021 33
1.3 The structure of a sequential circuit
Choosing between Moore and Mealy machine

The answer to each of these questions determines the
It actually comes down to the task at hand when type of machine that would work best.
choosing between Mealy and Moore machines.
There are few questions to ask when choosing

between either of the two:
 Does one want to have a synchronous or

asynchronous machine?
 Is speed paramount?
 Are both the inputs and present state readily

available?
6 May 2021 34
1.4 Finite state machine
Sequential circuit can also be represented in terms of Finite State Machine (FSM)
The asynchronous FSM which has the following features:
 A set of 𝑁 external inputs
 A set of 𝑀 external outputs
 A set of 𝐾 feedback lines
 A DELAY element (e.g a wire or a designed artificial delay)
 A combination circuit [CC]

Fig. Finite state machine representation
Of an asynchronous sequential circuit
6 May 2021 35
1.4 Finite state machine…
The synchronous FSM which has the following features:
 A set of 𝑁 external inputs
 A set of 𝑀 external outputs
 A state (storage) register MEM with 𝐾 inputs

representing the present and previous state of FSM, respectively.
 A combinational circuit [CC]
 A control clock signal CK

Fig. Finite state machine representation
of a synchronous sequential circuit.
6 May 2021 36
1.4 Finite state machine…
In synchronous sequential circuits, the changes in the inputs and the outputs occur in synchronization with
the clock, whereas in asynchronous sequential circuit the changes only depends on primary inputs 𝑁.
The examples of FSM given above, represents the non-autonomous FSM
An autonomous FSM employ clock as the only input A counter is an example of autonomous FSM
A register is an example of non-autonomous FSM
Figure. Shift register
6 May 2021
Figure. Seven segment counter circuit 37
Thank you
6 May 2021 38

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University of Dar es Salaam

ES 221: Digital electronics II

1.1 Basic digital electronics circuit

1.2 Digital data notation

1.3 The structure of sequential circuits

1.4 Finite state machines

• Variables in a Boolean expression take

Positive and Negative Logic

Complementary Metal Oxide Semiconductor (CMOS)

Emitter Coupled Logic (ECL) technology:

Transition times are due to capacitive and inductive effects

1.1.2 Signal Level Limits

A logic high or low signal

The voltage ranges between the limiting voltage values are

NMH =VOHmin -VIHmin,

The values of the limits vary with

These are electronic circuits of different

They have different:

What is the Boolean expression for the circuit?

Resistor Transistor Logic technology

Resistor Transistor Logic (RTL) technology

NMH =VOH -VIH, NML =VIL- VOL

VOH =1.2V, VOL= 0.2V,

NMH/NML = 0.4/0.5V, Logic swing = 1.0V

Diodes are added to isolate and control current flow

When transistor is cut-off

When transistor is saturated VQ=VSAT=0.1V.

 DTL, as a driver, behaves as a current sink of current

 When HIGH no current is sourced from the DTL driver

Transistor Transistor Logic (TTL) technology

The surface area of integration is reduced, VOH/VOL=3.5/0.2V, VIH/VIL = 1.5/0.5V

To meet different requirements a combination of TTL

Examples of TTL families:

74ALS- Advanced Low-Power Schottky: offers lower

74F-Fast TTL - good power-speed product. Most

Advanced Schottky Transistors

High integration suffers from high power dissipation

The standard Schottky circuits are not adequate.

Some TTLs are designed to have a control input so

Open Collector Circuits

To boost fan-out one can select the appropriate load resistance

If large current is required then RL can be made small.

Emitter Coupled Logic

 DTL and TTL technologies operate at cut-off and

 The saturation region contributes a great deal in

 This was achieved using a differential (long tail pair)

Older technology than bipolar technology failed to

Liked by designers due to low power dissipation and

Commonly used in LSI and VLSI

Transistors operate as voltage driven switches (cf

The gate current is zero but presence of a voltage at

Two complimenting transistors are normally used Q2 as the active device

The fan-out of CMOS devices is usually greater than 50

The propagation delay times for CMOS are 60 nsec for

Figure : Dynamic Power Dissipation of a Typical CMOS

Fig. A more type sequential circuit

Mixed Type Circuits Fig. A mealy type sequential circuit

INPUT BISTABLE OUTPUT

Fig. A mixed type sequential circuit

Choosing between Moore and Mealy machine

There are few questions to ask when choosing

 Does one want to have a synchronous or

 Are both the inputs and present state readily