LECTURE 1: SAP 1 ARCHITECTURE
BRIEF INTROCUTION OF SAPs
• SAP stands for Simple-As-Possible.
• SAP computers (SAP-1, SAP-2, SAP-3) were first
introduced by Albert Paul Malvino in his book
“Digital Computer Electronics”.
• SAPs have a very simplified computer
architecture.
• The main reason behind introducing these
computers is that, SAPs help us understand the
crucial ideas behind computer operation
without burying us with unnecessary details.
• SAP-1
➢ The first evolution of SAPs.
➢ Contains the basic necessities for a functional
microprocessor.
➢ Its primary purpose is to develop a basic
understanding of how a microprocessor works,
interacts with memory and other parts of the
system like input and output.
➢ The instruction set is very limited and is simple
1. ARCHITECTURE
• All register outputs to the 8-bit bus are three-
state; this allows orderly transfer of data.
• All other register outputs are two-state; these
outputs continuously drive the blocks they are
connected to.
• Main Clock Signal
➢ Clock signal should be generated using 555
timer IC.
➢ Main clock signal driving the computer should
have tow modes of operation:
i. Auto.
ii. Manual. In manual mode, pressing a
switch/ push button will advance each
clock cycle.
• 8-bit Bus
➢ Basically 8 wires/lines used for data transfer
between modules.
➢ Rules:
i. At a single time, instance only one module
will send data to the bus, and only one
module will receive that data.
ii. Two modules can never send data to the
bus at the same time (bus contention).
iii. When module is sending data to the bus, all
other modules outputs must be
disconnected (or use tri-state buffers).
Description of Submodules or Blocks
1. Program Counter (PC).
- Basically a 4-bit counter, counts from 0000
up to 1111.
- Its job is to store and send out memory
address of the next instruction to be
fetched.
- It will increment its value after each
instruction cycle (completion of an
instruction).
- Sometimes called a pointer, since it points
to an address in memory where
something important is being stored.
- Control bits:
1
 i.Counter Enable (CE). Increments the
program counter on the next clock-
cycle.
ii. Counter Out (CO). Puts the current
program counter value on the bus.
Output is disconnected when CO is
low.
2. Memory Address Register (MAR).
- A 4-bit register.
- It stores the memory address of Ram from
which data will be fetched.
- This 4-bit address is obtained via the bus
from the Program Counter and then
stored.
- This stored address is sent to the RAM
where data r instructions are read from.
- Control bits:
i. Memory Address In (MI). Stores the
current values of the bus into the
Memory Address register (MAR).
3. Input Unit.
- Used when computer is needed to be
programmed by wiring data into the RAM
(PROG state).
- All switches of input unit:
i. Data Switch. 8 switches (D7-D0) for
writing 8-bit data to RAM.
ii. ADRS Switch. 4 switches (A3-A0) for
accessing a particular address of RAM
for writing.
iii. R/W Switch. For switching between
read and write mode.
4. RUN/PROG Selector Switch (under Address
Selector).
- There are two states to our computer:
i. RUN state. When a program is in
execution on the computer.
ii. PROG state. Before running the
computer, it needs to be programmed
by writing data into the RAM. This is
PROG state.
- Based on RUN/PROG state, a 4-bit address
will be selected from either MAR or Input
Unit using Address Selector.
- If in RUN state, MAR will be selected.
- If inn PROG state, Input Unit will be
selected.
5. Random Access Memory (RAM)
- RAM size should be 16x8 bit (16 memory
locations each storing 8 bits of data).
- The RAM will be programmed by means of
the address switches and data switches of
input unit.
- During a computer run, the RAM will
receive its 4-bit address from the MAR.
- Control bits:
i. RAM Out (RO). Put the currently
selected RAM byte onto bus. Output is
disconnected when Ro is low.
- Using Input Unit to Write in RAM. Usually,
Input Unit in SAP-1 is built using keypad
and address switch registers to write
program into the RAM.
6. Accumulator (A).
- A buffer register that stores intermediate
answers during a computer run.
- Should be of 8-bit size.
- Has two outputs.
- The two-state output will be used to store
8-bit data as input to ALU input.
- The three-state goes to the 8-bit bus.
- Accumulator should have the ability to
output intermediate results after each ALU
operation.
- Control bits:
2
 i.
Accumulator In (AI). Stores the current
values of the bus into Accumulator.
ii. Accumulator Out (AO). Accumulator
sends its stored content to the bus.
7. B Register.
10. Instruction Register.
- Another buffer register used to store 8-bit
data as input to ALU input.
- The two-state output of the B register
drives the ALU, supplying the number to
be added or subtracted from the
contents of the accumulator.
- Control bits:
i. B Register In (BI). Stores the current
values of the bus into B register.
8. Arithmetic and Logic Unit (ALU).
- ALU should be capable of 8-bit binary
addition and subtraction.
11. Controller-Sequencer.
- Control bits:
i. Addition/ Subtraction Select (SU).
When SU=0, addition operation.
When SU=1, subtraction operation.
ii. ALU Out (AO). Puts the ALU output onto
the bus. Output of ALU should be
disconnected when RO is low.
9. Output Unit (Register).
- Basically an 8-bit register.
- The purpose of output register is store result
to display when requested.
- When output unit needs to display result, it
receives the data from Accumulator via
bus.
- Often called an output port because
processed data can leave the computer
through the register.
- Can be connected to any modules (i.e.,
LED) for showing the output.
- Control bits:
i. Output Register In (OI). Stores the
current values of the bus into Output
Register.
- Stores the 8-bit instruction received from
the RAM.
- Then this 8-bit data is split into two nibbles.
- The upper nibble is a two-state output
goes into the controller-sequencer.
- The lower nibble is a three-state output
sent to the bus.
- Control bits:
i. Instruction Register In (II). Writes the
current values of the bus into the
instruction register.
ii. Instruction Register Out (IO). Sends the
stored data (only lower nibble) onto
the bus.
- It generates necessary control signals for
each block so that actions occur in a
desired sequence.
- 12 control bits come out of the controller-
sequencer block. The 12 wires carrying the
control word are called the control bus.
- These control bits determine how all other
blocks will react to the next positive CLK
edge.
3
 - Controller-sequencer also generates a HLT accumulator contents”; the sum replaces
(halt) signal, which can halt the process of the original contents of the accumulator.
computer by stopping the main clock. 3. SUB.
• The SAP-1 control unit consists of the program - Instruction: Subtract
counter, the instruction registers, and the - Mnemonic: SUB
controller-sequencer that produces the control - Opcode: 0010
word, the clear signals, and the clock signals. - Function: Subtracts value stored in a
The SAP-1 ALU consists of an accumulator, an particular Ram address from the value in
adder-subtracter, and a B Register. The SAP-1 the accumulator. RAM address is given by
memory has the MAR and a 16x8 RAM. The I/O address field of instruction.
unit includes the input programming switches, Example: SUB BH
the output port, and the binary display. In Binary: 0010 1011
- SUB 9H, for example, means “subtract the
2. SPECIFICATION OF INSTRUCTION SET contents of memory location BH from the
• An instruction in the SAP-1 architecture consists contents of the accumulator”; the
of 1 byte (8 bit). difference out of the adder-subtracter
• The upper nibble of this byte (bits 7-4) is called (ALU) then replaces the original contents
“opcode” and it defines the instruction. of the accumulator.
• The lower nibble (bits 3-0) can be used to pass 4. OUT.
parameters to the instruction (for example a - Instruction: Output
RAM Address). - Mnemonic: OUT
• Some instructions use lower nibble, they are - Opcode: 0011
called memory reference instruction. - Function: Load data from the
• But some other instructions don’t use lower accumulator and send that to the output
nibble. register.
• Executing 5 instructions: LDA, ADD, SUB, OUT, Example: OUT
HLT. In Binary: 0011
1. LDA. - OUT is complete by itself; that is, you do
- Instruction: Load Accumulator not have to include an address when
- Mnemonic: LDA using OUT because the instruction does
- Opcode: 0000 not involve data in the memory.
- Function: Loads the value in a particular 5. HLT.
RAM address which is specified by the - Instruction: Halt
address field of the instruction, then stores - Mnemonic: HLT
it in accumulator. - Opcode: 1111
Example: LDA 9H - Function: Halts the process of computer
In Binary: 0000 1001 by stopping the main clock.
- LDA 9H, for example, means “load the Example: HLT
accumulator with the contents of memory In Binary: 1111
location 9H”. - HLT is complete by itself; you do not have
2. ADD. to include a RAM word when using HLT
- Instruction: Add because this instruction does not involve
- Mnemonic: ADD the memory.
- Opcode: 0001 • Instruction Cycle
- Function: Adds the value stored in a ➢ The time required to execute one single
particular RAM address to the value in the instruction is called instruction cycle.
accumulator. RAM address is given by ➢ Each instruction consists of several smaller
address field of instruction. instructions called microinstruction.
Example: ADD 8H ➢ For SAP-1, length of an instruction cycle is 6-
In Binary: 0001 1000 time states (T states).
- ADD 8H, for example, means “add the ➢ T state is the time required to complete one
contents of memory location 8H to the microinstruction.

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➢ Instruction cycle can be further divided into T5 RO BI
two parts: T6 EO AI
i. Fetch Cycle (First 3 states: T1, T2, T3) o During the T4 state, the instruction field goes
o Fetch cycle (T1, T2, T3) is responsible for to the controller-sequencer and the
fetching the instruction from memory. address field to the MAR. during this state IO
o Fetch cycle is exactly same for all and MI are active.
instructions. o Control bits RO and BI are active during the
o So, microinstructions during T1-T3 states will T5 state. Allowing the addressed Ram word
be always same for SAP-1 for any to set up the B register. As usual, loading
instruction. takes place midway through the state
Activated Control when the positive clock edge hits the CLK
T State Name
Bits input of the B register.
T1 Address State CO MI o During the T6 state EO and AI are active;
T2 Increment State CE therefore, the adder-subtracter sets up the
T3 Memory State RO II accumulator. Halfway through this state,
o The T1 state is called the address state the positive clock edge loads input of the B
because the address in the program register.
counter (PC) is transferred to the memory o Execution Cycle for SUB:
address register (MAR) during this state. Activated Control
o T2 state is called the increment state T State
Bits
because the program counter is T4 IO MI
incremented. T5 RO BI
o The T3 state is called the memory state T6 EO AI SU
because the addressed Ram instruction is o During the T4 state, the instruction field goes
transferred from the memory to the to the controller-sequencer, where it is
instruction register. decoded; the address field is loaded into
ii. Execution Cycle (Last 3 states: T4, T5, T6) the MAR.
o During the execution cycle (T4, T5, T6) o During the T5 state, AI and Ro go low. This
fetched instruction gets executed. means that the addressed data word in the
o Microinstructions during these three states Ram will be loaded into the accumulator
can vary depending upon the instruction. on the next positive clock edge.
o Execution Cycle for LDA: o During the T6 state, a high SU is sent to the
Activated Control adder-subtracter.
T State
Bits o Execution Cycle for SUB:
T4 IO MI Activated Control
T State
T5 AI RO Bits
T6 No Operation T4 AO OI
o During the T4 state, the instruction field goes T5 No Operation
to the controller-sequencer, where it is T6 No Operation
decoded; the address field is loaded into o Since AO and Oi are active, the next
the MAR. positive clock edge loads the accumulator
o During the T5 state, AI and Ro go low. This contents into the output register during the
means that the addressed data word in the T4 state.
Ram will be loaded into the accumulator o The T5 and T6 states are nops.
on the next positive clock edge. o Execution Cycle for HLT:
o T6 is a no-operation (Nop). During this third o HLT does not require any execution cycle
execution state, all registers are inactive. because no registers are involved in
This means that the controller-sequencer is execution of halt instruction.
sending out a word whose bits are all o Controller-sequencer simply activates the
inactive. HLT bit, which stops the main clock.
o Execution Cycle for ADD:
Activated Control
T State
Bits
T4 IO MI
5
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