AKSHAY.

R
Mobile: + 91 8618759024
E-mail: akshayrkarathnar@gmail.com

OBJECTIVE
To work in a challenging environment demanding all my skills and efforts to explore and
adapt myself in different fields and realize my potential where I get the opportunity for
continuous learning.

PROFESSIONAL SUMMARY:
 Have 1.2 years of experience in Design for Test (DFT) & its related fields of VLSI.
 Knowledge in Scan-Insertion and Scan architecture development.
 Experienced in Scan Insertion and ATPG Generation.
 Have Knowledge of JTAG, MBIST and Diagnosis.
 Hands on tools like Design Compiler, Test Kompress, VCS Simulator, Xilinx ISE
14.7 and Aldec Riviera Pro 2.0.
 Have knowledge of scripting like TCL, Python and shell commands.
 Knowledge in Digital and Verilog programming.

JOB SUMMARY:
 At present doing as DFT Engineer in L & T Technology Services Ltd., Mysore in
India.

PROFESSIONAL EXPERIENCE in DFT:

Project_4: (Inserting , Generating Patterns and Reporting )

 Handling Complete Scan Insertion activities.

 Generated ATPG patterns and validated them in simulation.
 Worked on ATPG Test Coverage improvement.
 Worked on Scan tracing issues during ATPG generation.
 Debugging clock violations C1C3.
 Reporting the Fault Universe reports like Test Coverage and Fault Coverage and
ATPG Effectiveness.

Project_3: (Configuring Scan and Test Logic and Reporting Clocking Violations)

 Handling Complete Scan Insertion activities.

 Identifying clock violations and fixing it.
 Generated ATPG SAF patterns and validated them in simulation.
 Worked on ATPG Test Coverage improvement.
 Worked on Scan tracing issues during ATPG generation.
 Project_2: (Understanding ATPG Messaging and reporting Test coverage)

 Got familiar with all do files and scripts used in Scan, ATPG and simulation.
 Handling Complete Scan Insertion activities.
 Analyzing ATPG Messaging,
 Worked on ATPG Test Coverage improvement.
 Worked on Scan tracing issues during ATPG generation.
 Determining the causes of Undetected Faults.
 DRC Reports /Messages
 Getting quick Estimation of Test coverage.

Prject_1: (Troubleshooting Low Test Coverage)

 Implemented Scan insertion for the design and resolved scan DRC check violations.
 Identify Blocks of Low coverage and untestable fault classifications.
 Performed test point insertion as part of scan DRC checks failure fixes.
 Created Compressed and uncompressed test patterns for the given design bundle and
resolved test setup issues and ATPG scan tracing issues as part of ATPG DRC check
failures.
 Determine the cause of ATPG AU faults.

SUMMARY OF EDUCATIONAL QUALIFICATIONS:-

 B.Tech. (2015-2019) in E.C.E. from GM Institute of Technology with 68.7%.

 Pre University (2012-2014) in MKET Independent PU Science college with 71.0%.
 Secondary Board (C.B.S.E) (2012) from MKET LK English Medium (CBSE )High
School with 70.5%.

Akshay R