Executive Summary:

This report discusses the techniques for achieving low power consumption in VLSI (Very
Large-Scale Integration) circuits. The demand for low power consumption in VLSI circuits
has increased due to the emergence of portable electronic devices. This report analyzes
various low-power techniques, such as clock gating, power gating, voltage scaling, and
leakage reduction, and their effectiveness in reducing power consumption.

Introduction:

VLSI circuits have become an integral part of modern electronic devices. The integration of a
large number of transistors on a single chip has led to an increase in power consumption. The
demand for portable electronic devices with a longer battery life has increased the need for
low-power VLSI circuits. In this report, we discuss various techniques for achieving low
power consumption in VLSI circuits.

Low Power Techniques:

1. Clock Gating: Clock gating is a technique that reduces power consumption by

disabling the clock signal to the unused circuit blocks. By doing so, the power
consumption of the unused circuit blocks is reduced to zero. This technique is
effective in reducing power consumption in circuits that have a high proportion of
unused circuit blocks.
2. Power Gating: Power gating is a technique that reduces power consumption by
shutting off the power supply to unused circuit blocks. Power gating is effective in
reducing power consumption in circuits that have a low switching activity. The power
gating technique has two types, namely, retention and non-retention power gating.
The retention power gating technique stores the state of the circuit before shutting
down the power, while the non-retention power gating technique does not store the
state of the circuit.
3. Voltage Scaling: Voltage scaling is a technique that reduces power consumption by
reducing the operating voltage of the circuit. By doing so, the power consumption of
the circuit is reduced since the power consumption of a circuit is proportional to the
square of the voltage. However, voltage scaling has a tradeoff between power
consumption and performance since reducing the operating voltage of the circuit
reduces the performance of the circuit.
4. Leakage Reduction: Leakage current is a current that flows through a transistor when
it is in the off state. Leakage current is a significant contributor to power consumption
in VLSI circuits. Leakage reduction techniques reduce the leakage current by
reducing the threshold voltage of the transistor and reducing the sub-threshold
leakage.

Conclusion:

The demand for low-power VLSI circuits has increased due to the emergence of portable
electronic devices. This report discussed various low-power techniques such as clock gating,
power gating, voltage scaling, and leakage reduction. The effectiveness of these techniques
depends on the design of the circuit, the application, and the required performance. These
techniques can be combined to achieve low power consumption in VLSI circuits while
maintaining the required performance. The selection of the low-power technique depends on
the specific requirements of the application.