Timing analysis (STA) STA Advantages and Disadvantages: Clock uncertainty:
Advantages: Clock uncertainty is the variation in the arrival time of the clock signal
Static timing analysis (STA) is a method of validating the timing  Much faster than timing-driven, gate-level simulation
performance of a design by checking all possible paths for timing violations.  Exhaustive timing coverage
STA breaks a design down into timing paths, calculates the signal propagation
 Does not require input vectors
delay along each path, and checks for violations of timing constraints inside
 More efficient than DTA in memory and CPU resources
the design and at the input/output interface.
 Capacity for millions of gates
Dynamic Timing Analysis (DTA): The process of verifying the timing Limitations:
performance of integrated circuits by simulating their behavior over time with  Works best with synchronous (not asynchronous) logic
specific input vectors. This method captures the actual dynamic interactions  Complex to learn
within the circuit, offering insights into how the circuit performs under  Must define timing requirements / exceptions
realistic operating conditions. Here's a detailed overview of DTA in the  Difficulty in handling:
context of VLSI:
 Multiple clocks
 false paths
 Multicycle paths
-----------------------------------------------------------------------------------------------
what is setup and hold time?
Setup and hold time are the minimum and maximum durations that a
data signal must be stable before and after the clock edge, respectively.
Set up time : The time required for the input signal to be stable before the
clock edge signal is called set up time.
If the data isn't stable/isn't captured at the expected clock edge then the
data will be captured at next clock edge.
Hold time : The time required for the input signal to be stable after the clock
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
edge signal is called hold time.
How does STA work? If the data isn't stable then the data might interpreted as 0 instead 1.
When performing timing analysis, STA first breaks down the design into
----------------------------------------------------------------------------------------------
timing paths. Each timing path consists of the following elements:
How to fix setup violations?
 Start point. The start of a timing path where data is launched by a
 Upsize the cell
clock edge or where the data must be available at a specific time. Every
 Swap the cells from HVT to LVT
start point must be either an input port or a register clock pin.
 Add buffer if net delay dominates the buffer delay
 Combinational logic network. Elements that have no memory or
internal state. Combinational logic can contain AND, OR, XOR, and  Pushing the Capture path
inverter elements, but cannot contain flip-flops, latches, registers, or  Pulling the launch path.
RAM.  Increasing the metal width
 Endpoint. The end of a timing path where data is captured by a clock  Route with highest metal layer
edge or where the data must be available at a specific time. Every How to fix setup violations?
endpoint must be either a register data input pin or an output port.  Down size the cell
 Swap the cells from LVT to HVT
Types of exceptions:  Add buffer at D-pin of the flip flop

False path: A path that is never sensitized due to the logic  Pushing the launch path
configuration, expected data sequence, or operating mode.  Pull the capture path.
 Multicycle path. A path designed to take more than one clock cycle  Detour the net
from launch to capture.  Route with lower metal layer.
 Minimum or maximum delay path. A path that must meet a delay
-------------------------------------------------------------------------------------------------------- parts of the chip at different times. This can lead to timing discrepancies and
constraint that you explicitly specify as a time value. What is threshold voltage: The minimum voltage required to ON the
-----------------------------------------------------------------------------------------------
transistor is called Threshold voltage. It is observed as positive value for
DTA Advantages and Disadvantages:
NMOS transistor and negative value for PMOS transistor.
Advantages: HVT : high Vtg threshold. Can be used in the path where timing is not critical.
 Can be very accurate (spice-level) So, by using HVT cells we can save power. It is more delay and less leakage
 Simulator calculates the logic value and delays power.
Disadvantages: LVT: Low Vtg threshold. One should use these cells in timing critical paths.
 Vector creation takes too long, slow These cells are fast but , consumes more power due to its leakage. So, use only
when timing is critical.
 Incomplete timing coverage
SVT: Standard Vtg threshold. The range b/w HVT and LVT. Medium delay
 Analysis quality depends on stimulus vectors
and medium power requirement. So, if timing is not met by small margin with
 Requires more memory and CPU resources over STA HVT, you should try with SVT. And at last LVT.
at different points in the clock tree due to process, voltage, temperature, noise,
and other effects. In physical design uncertainty will be used to model several
factors like jitter, skew and Latency.
Skew: The Difference between arrival times of the clock at different devices is
called cloch skew
Skew is the variation in signal arrival times among different paths
within a chip. It represents the difference in propagation delay by signals
taking distinct routes from a common starting point to their respective
destinations
Positive Skew: This occurs when signals arrive later at downstream
components compared to upstream components. It can lead to setup time
violations.
Negative Skew: This occurs when signals arrive earlier at downstream
components compared to upstream components. It can lead to hold time
violations.
Local skew: is the difference in the arrival of clock signal at the clock pin of
related flops.
Global skew :is the difference in the arrival of clock signal at the clock pin of
non-related flops.
Useful skew: If clock is skewed intentionally to resolve violations, it is called
useful skew. For example, there is setup violation in the design, then we add
some skew along the clock path in order to eliminate the setup violation.
-----------------------------------------------------------------------------------------------
Clock jitter: is the Frequency variation in the clock source, and the
Difference between the actual clock period and ideal clock period.
Power supply noise and variations in the temperature are the main sources of
jitter
-----------------------------------------------------------------------------------------------
Clock Latency: (clock insertion delay) is defined as the amount of time
taken by the clock signal in traveling from its source to the sinks.
Source latency of clock (Source insertion delay): Source latency is defined
as the time taken by the clock signal in traversing from clock source to the
clock definition point. It is also known as source insertion delay. It can be used
to model off-chip clock latency when clock source is not part of the chip
itself.
Network latency of clock (Network insertion delay): Network latency is
defined as the time taken by the clock signal in traversing from clock
definition point to the sinks of the clock. Thus, each sink of the clock has a
different network latency.
-----------------------------------------------------------------------------------------------------------------
Clock Skew: Clock skew occurs when the clock signal arrives at different
impact the overall performance.
Signal Integrity: Issues such as reflections, crosstalk, and noise can
degrade the quality of signals, leading to data corruption or timing violations.
-----------------------------------------------------------------------------------------------
Slack: It is difference between the desired arrival times and the actual arrival
time for a signal.
Positive Slack indicates that the design is meeting the timing and still it can be
improved.
Zero slack means that the design is critically working at the desired frequency.
Negative slack means , design has not achieved the specified timings at the
specified frequency. Slack has to be positive always and negative slack
indicates a violation in timing.
 List of input files
Gate level netlist, SDC (Synopsys Design Constraint), .lib file (Library Timing
File), .lef file (Library Exchange Format), .tf (Technology file) TLU+ file, Scan
def file. MMMC (Multi-Mode Multi Corner), UPF file (Power Intent File) and
don’t touch and don’t use.
------------------------------------------------------------------------------------------------
Technology file:
Tech file is an important type of input file for semiconductor industries. If you
want to create a design, we must have it ready in your hand otherwise we can’t
design anything. Many companies start preparing their own tech file based on
design rule run sets provided by foundry.
This file contains
 It contains Contain the number of metal layers and vias and their name and
conventions.
 Design rules for metal layers like the width of metal layer and spacing
between two metal layers.
 Metal layers resistance and capacitance as well as routing grid.
 Unit, precision, color, and pattern of metal layer and via.
 Maximum current density is also present in the tech file.
 It contains nwell,pwell, metal pitch
 Contains ERC rules, Extraction rules, LVS rules.
 Physical and electrical characteristics of each layer and via.
-----------------------------------------------------------------------------------
UPF file (Power Intent File)
UPF is stands for "Unified Power Format". This file is mainly associated with
low-power (Multi-power domains) designs and important for optimizing
power consumption in modern electronic devices. This file describes the power
intent or power management specifications for low-power designs. This UPF
file was implemented using CL Programming.
UPF generally contains:
 Details of various power domains in the design like name, scope,
supply ports and nets, power switches.
 Power state tables- these define the states of various power domain
states like ON/OFF for every domain.
 Level shifter, isolation, retention cell types, scope.
Isolation cells:
Isolations cells always used between two domains active mode domains and
shut down mode domain.
Consider there are two power domains one D1 is in shutdown mode and D2 is
in active mode, if data is passed through D1 to D2 this will not a valid data
received at D2. To prevent this condition, we insert an isolation cell b/w these
two power domains to clamp a known value at the D2 otherwise it will give
unknown value.
Level shifter:
The chip may be divided into multiple voltage domains, where each domain is
optimized for the needs of certain circuits.
Retention Registers:
To reduce power consumption when the devices are not in use, the power
domain is switched off for those devices. When the design blocks are in
switched off or sleep mode, data in all flip-flops contained within a block will
be lost. If the designer desires to retain this state, then retention registers are
used. Retention register requires D flip-flop and latch and required always-on
supply to retain the data. Using the retention register area required more as
compared to normal flop because here we are using flip-flop with always-on
supply. So, the area required more when we are using retention registers.
Gate level netlist:
This is the synthesized netlist. It performs synthesis on RTL code with
the standard cell libraries and constraints and converts the RTL code
into the gate-level netlist based on available standard cells.
This file contains
 It contains the logical connectivity of all the cells.
 It can also be a collection of resistors, capacitors or transistors.
-----------------------------------------------------------------------------------------------
Timing library (.lib)
Timing library (.lib) It can be readable through human because of it is
implemented in ASCII format. These timing libraries generated by the library
vendors or foundries.
A timing library will have information of standard cells like timing, area and
power. Timing can be implemented by using timing models under different
operating conditions (PVT).
Timing libraries will have 3 parts:
Header
 It contains some information which is common for all the standard cells.
 The information is like library name, units, operating conditions and date
Cell definition
 Cell definition section contains cell information like cell name, cell area,
leakage power, rail connection for both VDD and VSS.
 This section includes pin definition also. Pin definition contains information
like pin direction (input, output or in/out), signal level, pin capacitance, rise
capacitance, fall capacitance.
 If the pin is output pin, then function of the cell (logic of cell).
 State tables are available for every sequential element.
LUT (Look-up table)
 LUT means look-up table. It can be find just below of header section.
 It's the prototype of delay, hold, recovery and removal and power.
 Look-up table values are subjected to change inside pin definitions.
----------------------------------------------------------------------------------------------
Library Exchange Format (LEF)
LEF stands for Library Exchange Format. It is also termed as physical
library, because this file contains physical abstract information of Layers and
standard cells / macros. It is implemented in ASCII format, so it can be
readable by human. These physical libraries generated by the library vendors
or foundries.
Physical libraries are two types:
 Technology LEF
 Standard cell/macro LEF
Technology LEF
Technology LEF will have information of library version, units,
manufacturing grid and layers information.
Library version: This field show the library version.
Unit definition: This field contains information ofunits likedatabase, time,
capacitance and resistance information. Values specified in the file will be
multiplied with units.
Manufacturing grid: The minimum metal length that can be manufacturedis
called manufacturing grid.
Site: Site is the minimum standard cell area that can be manufacturable.
Layer information: This field contains information like Layer name, Type,
Direction, Pitch, Width, Area, Spacing and thickness, etc.,
Standard cell/macro LEF: This LEF contains abstract view of each and every
standard cell. The cell LEF contains basic information like Cell name, Class,
Origin, Size, Symmetry, Pin information (pin name, direction, shape, etc...)
Design Exchange Format (DEF)
DEF stands for Design Exchange Format. DEF file is a standardized
data file that represents the physical layout of design. This file is given as an
input to the EDA tool. We can generate this file at every stage of design flow.
To send placement information from one stage to another stage. By using this
file, we can load the design from one EDA tool to another EDA tool (like from
cadence Innovus tool to synopsis ICC tool or vice-versa).
Contents of a DEF file
A DEF file contains detailed information about the physical placement
and connectivity of all components, metal layers and other structures in the
design.lt serves as a detailed representation of design.
Die Area • Tracks • Components (macros) • I/O Pins • Nets • Blockages
• Halo • Scan Chain • Vias • Slots • Fills • Region • Row • Metal layers.
Scan Chain: Scan chains are the elements in scan-based designs that are used
to shift-in and shift-out test data. A scan chain is formed by a number of flops
connected back-to-back in a chain with the output of one flop connected to
another.
Halo: Halo is special hard blockage around the macro which blocks the
placement of std. cells near the macro.
----------------------------------------------------------------------------------------------
Multi-Mode Multi Corner
MMMC means Multi Mode Multi corner. This file is used to analyze
the design in different Modes and corners Because the chip after manufacture
have to work properly for different temperatures, voltage, and while
manufacturing there might be some process variations which leads to variation
in delays. This MMMC file usually develop using TCL script to execute all the
commands into the tool.
The above variations we represent as PVT (Process, Voltage and
Temperature). As I said these PVTs impact the delay of the design which
leads to not meet the timing constraints. So, to create analysis view (MMMC
we can say) .
we need some files they are:
Timing Libraries (.libs)
Timing constraints (.sdc)
What is Corner?: A corner is set of parameters which describes the process,
supply voltage and temperature for the standard cells for the specific
technology node. This information can be carried by the timing libraries.
What is Mode? :The design will have multiple modes like Functional mode,
test mode, etc. Each mode will have separate SDC files (Timing Constraints)
like func_mode.sdc (functional mode), scan_mode.sdc (scan mode).
So, in MMMC by using those files multiple modes and corners have to create.
Different set of libraries are available for each technology nodes which are ss
(Slow-Slow), ff (Fast-Fast) and Typical.
Slow-Slow will have worst delays (Max delays). Both PMOS and NMOS
works slow.
Fast-Fast will have best delays (Min delays). Both PMOS and NMOS works
fast.
Typical will have moderate delays. Both PMOS and NMOS works normally.
-----------------------------------------------------------------------------------------------
TLU+ file is the right location to have a look on net delay details. which
contains only the complete details of net delay in the forms of combined
Resistance and Capacitance. Table Look Up is an expansion for this file and
these files are with the extraction of “.tluplus”.
SDC(for Synopsys Design Constraints)
SDC stands for Synopsys Design Constraints. It was developed by
Synopsys Company.
It is an open-source file with ".sdc" as an extension.
SDC commands are developed based on TCL (Tool Command Language)
which is supported by almost all EDA tools. By using SDC, timing, area and
power constraints are provides to the tools like synthesis, PnR and STA
It contains design timing information like clock definitions, generated
clocks, virtual clocks, clock transitions, input port delays, output port delays,
wireload model, timing exceptions and DRVs, etc...
Timing constraints:
create_clock create_generated_clock  set_clock_groups
set_clock_latency  set_clock_transition set_clock_uncertainty
Area and power constraints:
set_max_area ■ create_voltage_area ■ set_level_shifter_threshold
■ set_max_dynamic_power ■ set_level_shifter_strategy.
Design rule constraints:
■ set_max_capacitance ■ set_min_capacitance ■ set_max_transition
■ set_max_fanout
Interface constraints:
■ set_drive ■ set_driving_cell ■set_input_transition ■ set_load
■ set_fanout_load ■set_port_fanout_number
Timing exceptions:
■ set_false_path ■ set_multi_cycle_path ■ set_disable_timing
■ set_max_delay*
-------------------------------------------------------------------------------------------
Standard Parasitic Exchange Format (SPEF)
SPEF stands for "Standard Parasitic Exchange Format”. It is commonly
used file format to represent the parasitic information of a design. Parasitics
means the unwanted resistance, capacitance and inductance are formed in the
design interconnects (wires and vias).
The SPEF file provides accurate and detailed information about the
parasitics and their impact in the design in an ASCII format (human readable).
The SPEF file supports specifications of all the cases like best, worst and
typical.
Content in SPEF file:
Header section  Name mapping  Port section  Parasitic information
Header section: In the Header section, here, some basic information about the
file available which includes design name, date of creation, vendor name, units
of RLC etc.,
Name mapping: After the header section with the keyword " "NAME_MAP.
During this section all the nets and instances names are mapped to indices (a
unique integer value for each net) preceded by asterisk (*).This mapping done
mainly to reduce the complexity and size of the file.
Port section: This section starts after the Name mapping section with the
keyword ""PORTS". Here, mapped indices are defining their port directions
i.e., I (input), O (output), B (Bidirectional).
-----------------------------------------------------------------------------------------------
ECO Engineering change order:
After post route stage, the routed netlist is send to all sign off stages. At
sign off stage if they found any timing , IR , lec and DRC’s related issues, then
sign off people wrote some ECO’s ( engineering change order) to solve those
issues and send back to the PD people.
What is crosstalk?
It is the crossing of signal from one side to other or mixing due to
which distorted signal or completely other signal would be received.
It can occur due to capacitive, inductive, or resistive effects. Crosstalk can
cause signal distortion, delay, or switching errors, especially in high-speed or
low-voltage circuits.
The reasons for crosstalk are:
• High Routing density and large number of standard cells.
• Increase in number of metal layer resulting in increase in lateral capacitance.
• Lower supply voltage leading to lesser noise margin.
How to fix crosstalk?
Increasing the twisting frequency of the wires can reduce the crosstalk
influence in unshielded cable pairs. It prevents interference crossover between
twisted cable pairs. To reduce crosstalk in data communications, shielded pairs
of twisted cables are more effective than unshielded twisted pairs.
---------------------------------------------------------------------------------------------
What is Congestion?
If the number of required routing resources are more than the number
of available routing tracks, then the area becomes congested. High congestion
causes detours and leads to worse results. Congestion makes the design non-
routable that means routing will not be converged if there are congestion in the
design.
Types of Congestion
 placement congestion  Routing congestion.
Reasons for Congestion
o Bad Floorplan.
o High standard cell density in particular area.
o High pin density in particular area.
o Missing/Small Halos near macro cell.
o Huge number of cells sitting near the macro cell.
Fixes for Congestion
o Use blockages in the design, partial blockages help more in
optimized way.
o Cell padding
o Module padding
o Decomposition of large cells into small cells (Pin distribution
happens).
--------------------------------------------------------------------------------------------
Standard cell: is a cell with a pre-determined functionality. Its height is a
multiple of a library-specific fixed dimension. In the standard-cell
methodology, the logic design is implemented with standard cells that are
arranged in rows.
Macro cell is a cell without pre-defined dimensions. This term may also
refer to a large physical layout, possibly containing millions of transistors, e.g.,
an SRAM or CPU core, and possibly having discrete dimensions, that can be
incorporated into the IC physical design.
Soft macros are synthesizable register transfer level (RTL) design forms, have
more flexibility, and can be configured compared to hard complex macros.
Using Soft macros in the design is a risk factor because of its being
unpredictable behavior in timing, performance and power. Often However,
soft macros can provide better IP protection as the RTL source code is more
portable
Hard macros are targeted Integrated Circuits (IC) manufacturing technology.
One can only access pins of hard macros and cannot manipulate the RTL of
this hard macro. Hard macros are block- level designs optimized for power,
area, or timing.
Clock: the clock is periodic synchronization signal used as a time
reference for data transfers in synchronous digital systems
Asynchronous Clocks: In multiple clock domains, if these clocks do not have
a common base period, then they are called as asynchronous clocks. Clocks
generated from two different crystals, PLLs are asynchronous clocks. Different
clocks having different frequencies generated from single crystal or PLL are
not asynchronous clocks but they are synchronous clocks.
Gated clocks: Clock signals that are passed through some gate other than
buffer and inverters are called gated clocks. These clock signals will be under
the control of gated logic.
Generated clocks: Generated clocks are the clocks that are generated from
other clocks by a circuit within the design such as divider/multiplier circuit.
Virtual clock: is the clock which is logically not connected to any port of the
design and physically doesn’t exist. A virtual clock is used when a block does
not contain a port for the clock that an I/O signal is coming from or going to.
Virtual clocks are used during optimization; they do not really exist in the
circuit.
-----------------------------------------------------------------------------------------------
Timing Paths
Timing path: is defined as the path between start point and end point.
Start Point: All input ports or clock pins of a sequential element are
considered as valid start point.
End Point: All output port or D pin of sequential element is considered as End
point.
Different Timing Paths:
Input to Output: It starts at input port and ends at output port. This is pure
combinational path. we can hardly find this in a synchronous design.
Input to Register: Semi synchronous; Register is controlled by the clock.
Input data can come at any time.
Register to Register: Purely sequential; both starting and ending flops are
controlled by the clock.
Register to Output: Data can come at any point of time.
Data path: The path where in data traverses is known as data path. Data path
is a pure combinational path. It can have any basic combinational gates or
group of gates.
Launch path: It refers to the path traversed by clock signal from clock source
to the start point.
Launch path is part of clock path. Launch path is launch clock path
which is responsible for launching the data at launch flip flop. Launch path and
data path together constitute arrival time of data at the input of capture register.
Capture path: It refers to the path traversed by clock signal from clock source
to the endpoint.
Capture path is part of clock path. And capture clock path which is
responsible for capturing the data at capture flip flop. Capture clock period and
its path delay together constitute required time of data at the input of capture
register.
Multi-Cycle Path: A multi-cycle path is a path that is allowed multiple clock
cycles for propagation. Again, it is a path that starts at a timing start points and
ends at timing ends point. However, for a multi-cycle path, the normal
constraint on this path is overridden to allow for the propagation to take
multiple clocks.
The critical path: is the longest path through a circuit from the input to the
output, where the delay is maximum. This path determines the maximum
speed at which the circuit can operate, as the circuit's clock period must be
long enough to allow signals to propagate through this path.
 Synthesis PNR FLOW Placement
Synthesis: is the process of converting RTL (Register Transfer Level) code PNR (Place and Route) flow is part of flow which starts after synthesis. It is Placement: is the process of placing of all standard cells that are present in
netlist by the tool into the core area. Tool also optimizes the design while
(i.e.., Verilog format) to optimized Gate level netlist to the targeted technology termed as backend process in ASIC flow. During PnR flow, actual layout of
by meeting area, timing and power constraints. placing. During placement trail routing also can be done by the tool.
design can be implemented by using EDA tools like cadence - innovus,
Synopsys - ICC2 (These two are most famous for PnR). PnR Flow goal is to
Placement different techniques:
Types of synthesis  Timing driven placement: Placement happens with timing as a priority
Logic synthesis  Physical aware synthesis implement a layout of design for targeted technology without any timing and
 Congestion driven placement: Placement happens with routing as a priority
Logic Synthesis: The below flow chart shows the cadence logic synthesis DRC (Design Rule Check) errors after routing stage. If in case any violations  Power driven placement : Placement happens with power as a priority
flow to convert RTL code to netlist (almost all tools follow the same flow with are there after routing, we go for signoff stage. In this signoff stage, all -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

minimal changes) remaining violations (like timing, DRC, LVS, EM and IR) can be fixed. Goals of placement
Now a days most of the companies are moving to Fusion Compiler Flow Chart: ■ Timing, area and power optimization ■ No timing DRV'S
(Synosys) instead of Design Compiler. The main advantage of this tool is we Importing input files Sanity checksFloorplanPre-placement ■ Minimize congestion and congestion hotspots
can do both synthesis and PnR in the same tool. In other words, it is a PlacementCTS (Clock Tree Synthesis)Routingpost-RouteSignoff ■ Minimum cell density, pin density
combination of both Design Compiler & ICC2. GDSII File
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Inputs of placement
---------------------------------------------------------------------------------------------------------------------------------------------- ■ Netlist ■ Physical libraries (.lef) ■ Floorplan DEF file
Floorplan
Logic synthesis flow Floorplan is simply the planning of where things will be placed in an
■ MMMC (Multi Mode Multi Corner)
Importing Input files (RTL code and .lib files) ElaborateRead SDC file Timing libraries (lib) RC corners  SDC file
orderly manner. In simple words its similar to house construction, when you
Sanity checks (check_design, check_timing)Generic mapping ■ UPF file (if the design has multiple voltage domains).
are planning to construct a house first we need a plan right! similarly In PD -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Technology mappingOptimizationDFT (Design for Testability) also we need floorplan. During placement mainly 3 steps can be done:
implementation (Done by DFT team)Incremental optimization Generating Floorplan is the major stage in the PnR flow. It will decide how good Global placement :During global placement, tool places all the standard cells
outputs (Netlist, SDC, Scan DEF, Required reports). your design. A good floorplan gives better PPA (Power, Performance and into the core area. In this step, tool will not follow any DRCS (like standard
Inputs of logic synthesis: Area). cells overlapping, miss alignment to the std cell rows) and creates more density
• RTL code • Timing libraries(lib files) • SDC (synopsis design constraints) Floorplanning is the process of creating core area, specifying core to areas. Trail routing also can be done by the tool after one global
I/O boundary spacing, standard cell rows, placing I/O pins, placing macros placement iteration.
Elaborate: Elaboration is the process that occurs between parsing and using macro guidelines and adding placement blockages and halo. So, during
simulation. It binds modules to module instances, builds the model hierarchy, Legalization: During legalization tool tries to spread the standard cells. If the
this stage above things have to do to avail better area to place standard cells in
computes parameter values, resolves hierarchical names, establishes net cell density is more in a particular area in order to get rid of power issues, tool
the core area, to avoid congestion and to avoid IR drop.
connectivity, and prepares all of this for simulation. ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- will distribute the cells. In this step the tool exactly aligns all the overlapped
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Types of designs standard cells into standard cell rows by following DRC rules and it makes
Read SDC: Read SDC is a command used to read all the contents of SDC  Core limited design  Pad limited design sure that there are no standard cells placed out of the core area.
file. SDC means Synopsis Design Constraints. It contains design timing Core limited design: The size of the die is restricted by the core's area. High Fanout Net Synthesis: Some of the nets will have very high number of
information, wire load models and DRV'S. These constraints are like timing Possible lower number of IO pads. fanouts like Reset, Scan Enable etc... But, there is a restriction for maximum
guidelines for the design, tool always follows these constraints. Pad limited design: The size of the die is restricted by the Pad area. Core area fanout in timing constrains. The tool optimizes these nets by picking the right
Sanity checks: Before the mapping stage, we must perform sanity checks is dominated by the Pad area. drivers or adding buffers to drive the load, adding repeaters to reduce on delay
on RTL code and SDC file to check the quality of input files. Importing input files and signal integrity, and balancing the net's capacitance and resistance to
The various sanity checks are strengthen the signal integrity.
• Netlist (.v) • Physical libraries (.lef) - Tech LEF & Standard cell LEF ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
check_design_netlistempty modulesunloaded parts combinational Checks before placement check
• MMMC Timing libraries (.lib) RC Coefficient files SDC
loopsUnconstrained endpointsMissing Input/output delays for the ports.
• UPF (Unified Power Format) - (Optional) • Floorplan DEF (Optional). ■ Netlist should be clean. ■ Floorplan DEF should be good
Generic mapping: ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
■ Proper Pin placement ■ Macros and pre-placed cells should be in fix.
During generic mapping, tool converts RTL code to the symbolic gate Floorplan control parameters
level representation. Tool maps the cells to the generic library. It is Core area: Core area is part of the Die (Full chip) where all type of cells (like ■ Power routes should be free of DRCS
independent of technology. standard cells, macros, blockages, physical only cells) can be placed. All types ■ Check for don't use, don't touch cells and routes should be applied properly.
of cells must be place only inside the core area. After Placement check
Optimization core size=(Standard cell area + Macro area + Blockage’s area)/(Standard cell ■ timing (drv’s , setup and hold) ■ congestion Report ■ core area utilization
During optimization, tool optimizes the design to meet all design utilization)
■ cell Plcement in a legalized manner or not.
constraints (area, timing and power). Some of optimization techniques are Aspect Ratio: Aspect ratio is the difference between the height of the core and ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

changing VT of cells, changing drive strength of cells, logic restructuring, width of the core.
adding repeaters, cloning and buffering.
Macro Guidelines
Aspect ratio=(Height of the core area)/(width of the core area). ■ Macros should be place at periphery of the core boundary.
DFT (Design For Testability) implementation: Die area: Die is the combination of core area and I/O pad area.
■ Macro pins should be face towards the center of the core area.
 DFT is one of the most important process in the SOC design cycle, ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
which helps us in detecting manufacturing defects in the designs. Types of floorplans ■ Macros should not place at middle of the core area.
 DFT engineer works on inserting extra hardware blocks as part of the Abutted floorplan type: For this technique, no spacing can be maintained ■ If it places middle of the core it will routing paths.
design itself, for increasing the testability of chips. between the elements in the floorplan
■ Avoid notches in the core area. ■ Avoid criss-cross.
 Testing is required to guarantee fault-free chips. Non-Abutted floorplan type: For this technique, some spacing can be
■ Place talking Marcos near to each other.
 DFT team will insert scan chains to the design.Scan chains are nothing maintained among the elements in the floorplan.
but adding extra input and enable pin to the flops, these are used to Mixed floorplan type: For this technique, name of type itself explaining that ■ Maintain proper halo around the macros.
check whether the flop is working or not by giving test inputs during combination of both Abutted and Non-Abutted type floorplan techniques.
testing. There will be some spacing for few elements and no spacing for few elements.
 CTS (Clock Tree Synthesis) Routing Power Planning
CTS (Clock Tree Synthesis) is the process of connecting the clock from clock Routing is the process of creating physical connections between or among the while technology got advanced (lower technology nodes), the power
port to the clock pin of sequential cells in the design by maintaining minimum signal pins by following DRC rules and also after routing timing (setup and started dominating the area and performance. Because nowadays all devices
insertion delay and balancing the skew between the cells using clock inverters hold) have to meet. are becoming portable, movable, and powering those devices using batteries,
and clock buffers. so small capacity batteries should last for more time while used. The best
Types of routing
example of portable devices is TWS earbuds, smart watches, fitness bands,
Types of clock tree structures ■ Pre-routing:also known as power routing which comes under power
etc...
Different structures are available to build clock tree to maintain planning
The main agenda of the power plan is to create a proper way to send
minimum insertion delay and balance the skew. ■ Clock routing: it can be done while building clock tree in CTS stage
the power from outside of the world to the standard cells and macros through
■ H-Tree structure ■ X-Tree structure ■ Geometric Matching Algorithm ■ Signal routing: it is the stage after CTS.
the power routes.
(GMA) ■ Pi Tree structure • Fish bone. Goals of routing
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ Power distribution shown in below flow:
■ Minimize the total interconnect or wire length and vias. Power pads are placed along with IO pads in the pads section of the full chip.
CTS Inputs: ■ Complete the routing within the area of the design. ■ No DRC violations.
■ Placement DB ■ Netlist after placement ■ LEF and Tech LEF files These pads pass the power from outside of the chip to the power rings. So,
■ Meeting the timing and No LVS (Layout Vs Schematic) errors. power pads act as a bridge to pass the power from the outside to the chip.
■ Placement DEF file ■ MMMC file . ■ LIB files ■ Tech files
■ SDC • UPF file ■ CTS spec file. Inputs of routing: Trunks: are the nets that connect the power pads and the core rings.
CTS outputs ■ Netlist and CTS DEF ■ Timing libraries and Physical libraries Core rings: A set of rings creates around the core (Exactly in the area of the
■ Netlist after CTS ■ CTS DEF Timing reports (setup and hold) ■ Tech LEF■ CapTables or QRC tech file. ■SDC. core to IO boundary). These rings get power from the pads and supplies to the
power stripes.
■ Skew and Latency reports Outputs of routing:
■ Routing DEF file with no opens & shorts ■ Timing & Congestion report Stripes: Power stripes are flies over the core area. The power stripes on both
Check before CTS: ends connect to the core rings. Power stripes are always created in the top
■ SPEF ■ SDC.
■ Placement – Completed ■ Power ground nets - Pre Routed metal layer. And these stripes supply power from the core rings to the power
■ Estimated Congestion – acceptable ■ Estimated Timing Routing Flow: rails (Sroutes).
■ Estimated Max Tran/Cap - No violations • High Fanout Nets Power rails (Sroutes): Power rails are connected to the power stripes using
■ Logical/physical library should have special clock cells (clkBuf or cikinv). Global routing :
Checks after CTS During the global routing tool removes all existing routing and do trail power vias. These rails are created at Metal layer I and vias are dropped from
routing again without following any DRCS. the top metal layer to the bottom layer. The power pins of standard cells are
■ Insertion delay (Target have to meet) ■ Skew (Target have to meet)
■ Routing congestion ■ Placement legality ■ Signal integrity and crosstalk In this stage, tool divides entire core area into global cells (gcells) and directly connected to the power rails which are present in layer I because the
■ Clock duty cycle ■ Clock tree power consumption tries to find the shortest path from pin to pin as per the logical connectivity to power pins of the standard cells are available in metal layer.
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

route using the gcells. While doing global routing tool tries to avoid routing
CTS Goals: Inputs of Power plan
over the routing blockages, and never touches the pre-routes (power
■ Minimum Skew ■ Minimum Insertion delay ■ Netlist ■ Timing libraries ■ Physical& technology libraries
planning) and CTS nets.
■ Complete the clock tree with no DRV (Tran, cap and fanout) violations. ■ RC coefficient ■ SDC ■ UPF (Unified Power Format) or CPF (Common
■ No timing violations (Setup and Hold). Track assignment: Power Format) - (if the design have multiple voltage domains)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
During this stage, tool replaces the global routes with actual metals, Outputs of power plan
Steps in CTS: and those actual metals have to follow DRC rules. Then now those actual ■ Floorplan DEF with Power Distribution Network (PDN).
metals will get real DRC violations, signal integrity (SI) and timing violations. ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Clustering: During clustering, tool will build only a DRV-aware clock tree Those violations are fixed in the succeeding stages. Static power dissipation: When the circuit is not switching, means no change
and will not balance the clocks. AT the start of this step, tool will print the in input and the clock is also not applying to the circuit, under the presence of
maximum driver distance and the unit delay for the clock buffer/inverter from Detailed routing: a power supply. During this period, some power consumption happens by the
a user- provided list or from the library. This is the final stage of routing of the design and this can be done after circuit. This is known as static power dissipation.
Balancing: during this step, tool will balance the design per the skew group CTS stage. During this stage, tool takes care of routing and completes the ■ Reverse bias pn junction
constraint. Look for the pattern balancing in the log file. This pattern will routing without leaving DRC violations and also improves the signal integrity ■ Gate tunneling
repeat multiple times in the log file. (SI). While doing detail routing, tool divides entire block into multiple switch Dynamic power dissipation: When the circuit is switching from logic 0 to 1
Routing of clock tree: During this step, tool will route all the clock tree nets boxes or Sboxes. Each switch box will carry multiple gcells. The switch boxes or logic 1 to 0, it consumes power to charge and discharge the load capacitors
using a Nanoroute engine. boundaries are align to the gcells. in the circuit.
Post conditioning: This step is run to clean up any minor degradation after the Search and Repair: Dynamic power dissipation happens for two reasons. They are:
clock routing. This stage is the part of the detailed routing, but search and repair starts ■ Switching power: When the circuit is switching from logic 0 to logic 1 then
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

CTS Exceptions after first iteration of detailed routing. During this stage, all shorts and spacing power gets drawn from VDD which goes through the PMOS and charges the
■ Stop pin ■ Nonstop pin ■ Float pin ■ Exclude pin violations are identified and resolved by the tool. load capacitor along with other parasitic capacitors. Switching power depends
Stop pin also called as Leaf pin or sink pin. Stop pins are the indication to the on how often the load capacitor is getting charged and discharged.
Post routing: Short circuit power: is a disastrous condition in CMOS circuits, because
tool to stop building clock tree at that pin i.e. end point of the clock tree.
■ Signal Integrity (SI) Optimization by NDRs and Shielding for the sensitive when the input of the CMOS circuit is switching (transition) from logic 0 to
Float pin also called as macro modeling. Suppose, if there is some insertion
nets. logic 1 or vise-versa, during this transition some period of time both PMOS
delay inside of the sequential element which have to consider and balance
■ Types of Shielding for sensitive nets and NMOS transistors gets turned ON at the same time. Due to this a direct
accordingly while building the clock tree.
Same layer shielding path (low impedance path) can be formed from VDD to GND. Short circuit
Exclude pins: are isolates the pins from clock tree even clock is going to that
Adjacent layer/ Coaxial shielding. power is directly proportional to the transition times. Hence, if the transition
particular pin. Isolates means timing, balancing and optimization are not
consider for the clock tree calculations. time is more than short circuit power also more and vise-versa. Following
diagram gives you a basic idea of short circuit power.