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 Published by IOP Publishing for Sissa Medialab
Received: November 3, 2023
Revised: January 19, 2024
Accepted: February 29, 2024
Published: April 24, 2024

Topical Workshop on Electronics for Particle Physics

Geremeas, Sardinia, Italy
1–6 October 2023

2024 JINST 19 C04053

Design and measurements of SMAUG1, a prototype ASIC
for voltage measurement using noise distribution

Grzegorz Węgrzyn ∗ and Robert Szczygieł

Departament of Electronics and Metrology, AGH University of Kraków,
al. Adama Mickiewicza 30, Kraków, Poland

E-mail: wegrzyn@agh.edu.pl

Abstract: We present the implementation of the indirect voltage measurement using a noise distribution
algorithm [1] in the prototype application-specific integrated circuit (ASIC) SMAUG_ND_1 designed
in CMOS 28 nm technology. The chip implements the matrix of 7×7 pixels with the size of 68×68 μm.
Each pixel contains eight independent comparators implementing the described algorithm and optional
correlated-double-sampling method. The paper describes the ASIC architecture and briefly presents
preliminary test results and encountered problems.

Keywords: Analogue electronic circuits; Analysis and statistical methods; VLSI circuits

∗ Corresponding author.

© 2024 The Author(s). Published by IOP Publishing Ltd on behalf of

Sissa Medialab. Original content from this work may be used under the
terms of the Creative Commons Attribution 4.0 licence. Any further distribution of this https://doi.org/10.1088/1748-0221/19/04/C04053
work must maintain attribution to the author(s) and the title of the work, journal citation
and DOI.
Contents
1 Algorithm description 1

2 Design requirements 2

3 ASIC design 3

4 Preliminary tests 4

5 Summary 6

2024 JINST 19 C04053

1 Algorithm description

The primary motivation of the presented work is to test the physical implementation of the indirect
voltage measurement algorithm using the noise distribution [1]. The algorithm aims to increase the
accuracy of the photon/particle energy measurements in solid-state detector systems. The described
algorithm can be divided into two parts: measurement, during which the system collects data about
noise superimposed with measured signal, and signal processing stage when the processor fits the
distribution curve to the collected data. Based on the simulation results, the algorithm may be better
than the traditional approach using analog filters and discriminators.
During the measurements, the system utilizes a set of comparators in which comparison levels
are distributed close to each other and close to the expected value of the measured signal (what is
introducing the need of a priori information about expected signal amplitude or need of dynamic
range adjustments what is out of the scope in the first implementation). The architecture is similar to
the regular analog-to-digital converters. The main difference is how the data are collected, stored, and
processed. Instead of triggering the converter with a clock signal, the converter works in a free-running
mode (asynchronous). During this operation, noise superimposed with the measured signal starts to
toggle the comparators (more often if a threshold level is closer to the pulse amplitude, see figure 1).
After some time of counting how many times a specific comparator was toggled, we get the histogram
stored in counters, and data can be sent to the following algorithm stage.

Figure 1. The number of noise-induced comparator switchings creates a Gaussian curve.

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 The second stage, data processing, is to fit the appropriate distribution curve (in our case, a
Gaussian) to the collected histogram data. The fitting accuracy depends on parameters like system
noise, spacing between adjacent threshold levels, signal position (how close to the nearest comparator
it is), measurement time, used fitting algorithm, and uncertainties caused by the manufacturing
process mismatches.
In this and original ([1]) publications, the algorithm was described in terms of single photon
counting imaging systems, but it can be suitable for any other application with voltage measurement.

2 Design requirements

2024 JINST 19 C04053

The first component in the signal processing chain, which is essential from the implemented algorithm
point of view, is the charge-sensitive amplifier (CSA), which is responsible for integrating and
amplifying the charge collected from the detector. It should be able to provide an output signal as
a step response for the input stimulation (CSA working in “charge mode” or “integrating mode” [2]).
The amplitude of the step response is more straightforward to reconstruct than any other, as only the
noise superimposed with the signal will contribute to the noise distribution curve [3]. As the algorithm
accuracy strongly depends on the measurement time, we target the measurement time within the 100 ns
to 100 μs range and improve the initial SNR by the factor 20 for a 10 μs measurement. To achieve this,
the error introduced by discharging CSA feedback capacitance should be negligible, and the voltage
drop should be below 0.5% for the maximum measurement time. This working mode introduced another
requirement: implementing the CSA discharge system to prevent amplifier saturation after several input
stimulations. Pixel size and power consumption should be comparable to other modern Xray imaging
pixelated sensor systems (i.e., [4, 5]) and not exceed 75×75μm and 100 μW/pixel, respectively.
Another critical element is a discriminator and its parameters: speed, hysteresis, and offset. The
high speed will help collect necessary statistics faster, resulting in a shortened measurement time
(long measurement time is the main inconvenience of the proposed algorithm). The discriminator
should provide no less than 100 counts in 1 μs long measurement, with an input overdrive of 2–3 mV
(CSA output noise sigma). Hysteresis should be negligible compared to achieved CSA output
noise; otherwise, switching the comparator with a small overdrive, i.e., the noise signal, will be
impossible. Another aspect is the implementation of trimming circuits to cancel comparators’ offsets
and compensate for differences in speed within the pixel (any mismatches will cause inaccuracy in
curve fitting). The number of comparators within the channel should be greater than or equal to the
number of unknowns in the assumed noise distribution curve formula. The Gaussian curve assumption
will require at least three comparators in each channel (there are three unknown parameters: mean,
sigma, and scale, which can be seen in eq. (2.1)).
− ( 𝑥−𝜇) 2
𝑓 𝜎, 𝜇 (𝑥) = 𝑁𝑒 2𝜎 2 . (2.1)

A higher number of comparators can improve the final resolution; however, the analysis presented
in [1] shows that it is valid for up to 6 comparators, and its higher number will not significantly
improve algorithm performance. Moreover, more comparators would require more careful calibration
procedures. Finally, appropriate memory should be implemented to avoid an overflow during longer
measurements. Assuming the count rate (with low overdrive) at the level of 100 MHz and maximum
measurement time of 100 μs, counters should be able to store more than 10,000 counts.

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 The last point concerns the threshold levels that should be set carefully with high precision since
we will try to differentiate signals with differences in amplitude smaller than noise power. Because
of that, all DACs responsible for setting the threshold should provide good linearity or at least be
perfectly mapped for further compensation.

3 ASIC design

To fulfill algorithm requirements, a prototype ASIC called SMAUG_ND_1 (Sigal MeAsurement

UsinG Noise Distribution) has been designed using CMOS 28 nm technology and produced using
mini@sic service provided by EUROPRACTICE. The technology has been chosen for its high speed,

2024 JINST 19 C04053

important for discriminator design, and cost efficiency for small designs (ASIC occupies 1 mm2
area) using the mentioned service. The main part of the designed ASIC is a matrix of 7×7 pixels,
where each pixel is a 68×68 μm square (post-shrink). An SPI interface provides communication
with the ASIC and the matrix and is used for reading measurement data and writing configuration
(figure 2). As it is a prototype design, we did not foresee the possibility of a real detector connection.
Instead, we implement a calibration circuit (series capacitance to inject charge to the channel) with
series capacitance (MOM type) of 15.3 fF. Such small capacitance allows us to inject input charges
with very fine step (Δ1 mV ≈ Δ0.0153 fC).
The signal processing chain within each pixel is simple and contains only a charge-sensitive
preamplifier (CSA) and eight comparators (figure 4). There are also additional supporting blocks
such as analog multiplexer (AMUX) and trimming DACs. The power consumption of the analog
part of the pixel is about 80 μA, and the power supply voltage is 0.9 V.
Since we did not foresee any detector connected to the chip, requirements for the first stage were
relaxed. The input stage has been designed in a folded cascode architecture with a thick-oxide PMOS
input transistor (figure 5). A thick oxide input transistor was used to minimize the gate leakage current
that might charge the feedback capacitance during the measurement procedure. The dimensions of
the input transistor are 12 μm/300 nm while the bias current is only 11 μA. The CSA can work in
the integration mode as well as in transimpedance mode. A single NMOS transistor in the feedback
works as a resistor; its gate voltage is common to the entire matrix and can be applied externally.
During measurement time, the transistor is turned off, and after measurement, the transistor is used
to discharge the input stage. With the 5.5 fF feedback capacitor, CSA achieves a gain at the level of
150 mV
fC . The simulated noise RMS of 2.5 mV makes a requirement for the threshold DAC step.
Each pixel contains eight comparators divided into two sections. Each section has a separate
coarse threshold tuning circuit. This approach enables two different usage scenarios: the first one,
when both sections are used to measure the signal amplitude increasing the dynamic range [1] or the
second one, to form a correlated double sampling circuit [6, 7] where one section constantly monitors
the base level and the second one measures the signal amplitude. Each comparator also contains
two 5-bit trimming DACs: one for the threshold fine-tuning to cancel offset mismatches (figure 6)
and the second to control comparator current to cancel speed mismatches (current trimming in range
+/-20%). Comparator design uses a differential pair with a diode load to minimize sensitivity to
PVT variations. Each comparator’s threshold level is also buffered separately to minimize the risk
of kick-back noise propagation to neighborhoods. The CSA and the comparator are DC coupled
since we would like to work with slow signals (step response of the CSA) and monitor the CSA DC
level. The single comparator consumes ≈ 10 μW of static power.

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 2024 JINST 19 C04053
Figure 2. ASIC block diagram. Figure 3. ASIC in JLCC44 package photo.

Figure 4. Schematic of single channel. Figure 5. Schematic of charge-sensitive

amplifier.

The pixel digital part comprises eight 16-bit ripple counters (one-to-one with comparators) and
configuration registers. Counters can be configured as a shift register for reading/writing data and
write configuration by latching the actual counter (shift register) value. All digital circuits (in-pixel
and at the chip level) were generated using synthesis and place-and-route tools.
Most bias currents and potentials can be regulated using global coarse-tuning circuits or local
fine-tuning DACs. Global tuning is done by external resistors connected to ASIC pads (figure 2).
The power grid is separated for each functional block: CSA, biases, comparators, digital part,
calibration circuit, etc.

4 Preliminary tests

A preliminary test has been performed on a test setup comprising three PCBs: ASIC carrier, power,
and FPGA boards. The carrier board contains 7-bit digital resistors to set and trim bias currents and
voltages like thresholds for two sections and gate potential for the transistor in CSA feedback. It also
contains a socket for the ASIC. For better flexibility, the ASICs were encapsulated into the JLCC44
package (figure 3). There are also two types of power boards: one with LDOs and one with DC-DC
converters. Both provide voltage regulation from 0.6 V and output voltage and current monitoring.
They can be powered by a battery or a power supply unit. The central processing unit is the FPGA

–4–
board PYNQ-Z2, which handles communication with the ASIC, global biases, and the power board,
as well as the logic for processing data and fitting the distribution curve.
The first step of ASIC testing was to characterize the analog buffer used in the analog multiplexer
that will be used for further trimming DACs characterization. Measurements show that the buffer
has a strongly limited dynamic range compared to simulations (300 mV and 840 mV, respectively).
Because of that, the characterization of trimming DACs with a wide range is only partially possible.
Figure 6 shows the measurement of the fine-tuning threshold DACs for all comparators within one
channel. The achieved DAC step is about 0.5 mV, much less than the simulated noise RMS: 2.5 mV
(as required by the implemented algorithm). After tuning slightly the biases, the DC level of the
CSA output could be moved to the linear region of the analog multiplexer, which allowed us to

2024 JINST 19 C04053

make the following measurements.
Noise RMS extracted from a noise occupancy scan (figure 7) varies between channels and is
within the 1.7 to 2.5 mV range.

Threshold fine DAC CSA baseline

Comparator 0, LSB: 0.742 mV 17500
440 Comparator 1, LSB: 0.727 mV
Comparator 2, LSB: 0.758 mV
Comparator 3, LSB: 0.694 mV 15000
Comparator 4, LSB: 0.756 mV
Comparator 5, LSB: 0.739 mV 12500
Voltage [mV]

430 Comparator 6, LSB: 0.804 mV

Comparator 7, LSB: 0.732 mV
10000
Counts

420 7500
5000
410 2500
0
0 5 10 15 20 25 30 0 5 10 15 20
DAC code Offset [mV]

Figure 6. Treshold fine-tuning DACs characteristics Figure 7. Noise occupancy scan, extracted noise
within a single channel. RMS = 2.2 mV.

Figure 8 shows the channel gain extracted from threshold scan analysis, performed for three
different input charges, 1.0, 0.75, and 0.52 fC. Measured and calculated gain of approximately
165 mV mV
fC fits the simulated value (150 fC ).

Channel gain Threshold scan

480 104
Signal amplitude [mV]

460 103
Counts

440 102

420 101

400 100
0.5 0.6 0.7 0.8 0.9 1.0 300 350 400 450 500
Input charge [fC] Threshold level [mV]

Figure 8. Extracted channel gain is ≈ 165 mV

fC . Figure 9. Threshold scan results. Two spikes stem
from the CSA baseline and the signal peak.

–5–
 Figure 9 presents exemplary threshold scan results for a single comparator in one of the pixels.
Each point of the plot corresponds to a value counted by the corresponding counter for a single test
pulse. The points on the left side of the plot show the value of ‘1’ — this is justified as for low
threshold values comparator’s output is always high. The first peak (left) is generated for the thresholds
close to the CSA output DC level. The second (right) comes from the top of the test pulse. The mean
of the Gaussian curve fitted to this peak equals the pulse amplitude. For the thresholds above the
second peak, we expect zero counts — not visible on the plot with the log scale.
This test demonstrated the correct operation of the CSA, comparator, and counter suitable for
the presented measurement method.

2024 JINST 19 C04053

5 Summary

The prototype ASIC SMAUG_ND_1 implementing indirect voltage measurement using a noise
distribution algorithm has been designed and produced. During preliminary measurements, we
encountered problems with the analog buffer used for trimming DAC characterization. Performed
analysis shows good compatibility of extracted parameters like gain, noise power, etc., with simulations.
The CSA, comparator, and counter in the pixels operate correctly. The main measurement tests
of the described algorithm are ongoing.

Acknowledgments

The work was supported by the Polish Ministry of Science and Education (contract no. 0138/DIA/2020)

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