UVM AXI VIP User Guide

Author Mikko
Kemppinen
Owner Mikko
Kemppinen
Organization SoC
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0.1 Draft 01-03-2016 Mikko Kemppinen Mikko Kemppinen Doc created

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Contents
1 Introduction........................................................................................................................................
2 Features.............................................................................................................................................
2.1 Implemented features for AXI master.............................................................................................4
2.2 Implemented features for AXI slave................................................................................................4
2.2 Future development ideas...............................................................................................................5
3 Structure.............................................................................................................................................
4 Configuration......................................................................................................................................
5 Example testbench.............................................................................................................................
5.1 How to run example test bench......................................................................................................9
6 Links to code and bug reporting.........................................................................................................
6.1 ICManage repository.......................................................................................................................9
6.1.1 Admin list......................................................................................................................................9
6.2 JIRA.................................................................................................................................................9
8 References.......................................................................................................................................

1 Introduction
AXI_MASTER_AGENT provides VIP for doing AXI master accesses in UVM environment. It also
provides UVM RAL adapter and example environment to do register accesses through RAL
(Register Abstraction Layer). RAL is part of UVM and enables register accesses based on register
names instead of addresses. UVM includes register access functions and sequences for register
testing. AXI4 agent also includes AXI4 SLAVE agent which is implements slave functionality.
Example environment also provides convenience functions to do RAL register and register field
accesses using register/field names without defining register model hierarchy.
FISU agent guideline [2] is used as reference when creating the VIP.

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2 Features
AXI VIP is designed to be used with both VCS and Questa simulators and is compatible with UVM
versions 1.1d and 2.0.
2.1 Implemented features for AXI master

• Master mode
• Single read and write functions one at a time (no simultaneous or overlapping transactions)
• Always uses zero-ID
• 2 timing modes o Default: interface timings, order of address/data cycles and delay of
bready/rready responses randomized
o Fast_mode: Interface timing fixed, address and data cycle started
simultaneously with no delay. Immediate bready and rready responses
• RAL integration in example environment
• reg_read, field_read, reg_write and field_write functions for RAL accesses
• Write and read sequences to do accesses outside RAL
• Write strobe support with and without RAL
• Configurable data and address widths o Supports also data widths outside AXI-lite scope
(32, 64).
o Data widths supported: 8, 16, 32, 64, 128, 256, 512, 1024.
• Unaligned transfers
• Transaction and channel level timeout checking
• Transaction latency printed to log and passed to analysis port.
• Features outside of AXI-lite scope o Support for different transaction sizes (AWSIZE and
ARSIZE) o Incr Burst support

• Supports Synopsys VCS and Mentor Graphics Questa. • Very simple sanity test suite
2.2 Implemented features for AXI slave
•
•

- Single accessit
- Incrementing burst tyyppi

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 - Randomoitu vastauksen viive
- Error response generointi
- Dynaaminen slave muisti-toiminto (assosiatiivinen array)
o Backdoor access write() ja read() funktioilla
- Write strobe tuki
- Timeout, jos masterilta ei vastausta
- VCS ja Questa tuki
- Featuret joille ei tarvetta juuri nyt:
o Muut burst tyypit
o multiple pending transactions
o multiple ID:s
o Locked transfers
o Protected transfers

2.2 Future development ideas

• Fixed and wrap burst type support

• Functional coverage
• Out-of-order responses

3 Structure
<Insert example TB figure here>

4 Configuration
Maximum AXI data and address bus widths are configured through system verilog defines
AXI_MAX_AW and AXI_MAX_DW in axi_defines.svh.
VIP configuration object is passed to agent through UVM config database. Configuration object has
configuration variables described in Table 1. (Both master and slave object variables are presented
in the table, which explicitly defines if the variable is master or slave only.)

Table 1: Configuration object variables

Variable Explanation
data_width VIP instance data bus width. Default value is
AXI_LITE_MAX_DW.
Has_driver (bit) 1 – Driver instantiated (Default value)
0 – Passive mode, no driver
has_monitor (bit) 1 – Monitor instantiated (Default value)

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 0 – No monitor
num_timeout_cycles (int) Number of clock cycles to wait for channel handshake
responses before giving timeout. Num_timeout_cycles*2 is used
as timeout value in transaction-level checks. Default is 300.
Bresp_error (bit) 1 – uvm_error if bresp is not 2’b00 (Default value)
0 – uvm_warning if bresp is not 2’b00
rresp_error (bit) 1 – uvm_error if bresp is not 2’b00 (Default value)
0 – uvm_warning if bresp is not 2’b00
log_verbosity (string) Verbosity of bus access log messages. Value can be “low”,
“medium” or “high”. Default is “medium”.
axi_vif (axi_lite_interface) Handle to axi-lite interface
support_bursts 1 – Support bursts and monitor burst signals
0 – No bursts supported. Burst signals (including WLAST and
RLAST) not monitored. Default value.
fast_mode 1 – Interface timing fixed, address and data cycle started
simultaneously with no delay. Immediate bready and rready
responses
0 – Interface timings, order of address/data cycles and delay of
bready/rready responses randomized. Default value

VIP can be used in passive mode (has_driver = 0) to monitor and log bus traffic.

5 Example testbench
<Insert example TB figure here>
5.1 How to run example test bench
Example test cases are run by using commands below in SIM-directory
VCS:
-Example test case was done using VCS version: syn_vcs_mx_K_2015_09_SP1
-Running analysis, elaboration, simulation (defaults to test case example_test1)
-DEBUG VISIBILITY: gmake -f Makefile_example_env MODE=DEBUG
- NORMAL VISIBILITY: gmake -f Makefile_example_env
Questa:
-Example test case was done using Questa version: mg_questacore_prime10_4d
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-Running analysis, elaboration, simulation (defaults to test case example_test1)
-DEBUG VISIBILITY: gmake -f Makefile_example_env_vsim MODE=DEBUG
- NORMAL VISIBILITY: gmake -f Makefile_example_env_vsim

6 Links to code and bug reporting

6.1 ICManage repository

AXI4 VIP can only be found from ICManage i.e. no SVN repository available
6.1.1 Admin list
Contact one of people in following list to get access to IC verif common repository:
Mika Holappa
Mikko Kemppinen
6.2 JIRA
JIRA is used as issue reporting tool for the VIP: https://jira.inside.nsn.com/browse/VIP
Contact JIRA project owner Antti Rautakoura for VIP JIRA page access.

8 References
[1] FISU agent Guideline reference
https://sharenetims.inside.nokiasiemensnetworks.com/Open/D507907329

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