Study of Non Idealities in ADC and SRAM for IMC Applications AND: OR:

Result Result
Authors-Abhishek Mishra(abhishek22182@iiitd.ac.in), Dr. Anuj Grover(anuj@iiitd.ac.in) Q0 Q1 Output (BL)
Q0 Q1 Output (BL)
1 1 1 1.1849 1 1 1 1.184
Process Step/ IP/ Component 0 1 0 0.877 0 1 1 1.05
1 0 0 0.877 1 0 1 1.05
0 0 0 0.377 0 0 0 0.876
Applicability
In Memory Compute 8T SRAM Array:
Boolean function Implementation:
SRAM-based computing-in-memory architecture • The 8T SRAM cell indeed contains the same 6T SRAM
cell with two additional transistors for read
SRAM-based computing-in-memory (SRAM-CIM) architecture
operations.
is a cutting-edge solution designed to enhance the energy
• We kept 2 Read Word lines on and rest were off.
efficiency of devices at the forefront of technology, such as AI
Then we provided inputs at Q1, Q2, QB1 and QB2 and
edge devices and AIoT. Fig.4 8T SRAM Array implementation (64*1)
kept supply, VDD= 1.2 V.
Energy Efficiency: A core goal of SRAM-CIM to address the
• Both the rows read worldline (RWL) is activated and
energy demands of modern computing. NAND: NOR:
depending on the speed of discharge or no-
Memory-Wall Bottleneck: Tackles the limitations of traditional
discharge, values of NAND and NOR of each bit in Result Result
computing architectures.
column are computed. Q0 Q1 Output (RBL) Q0 Q1 Output (RBL)
 Unified Memory and Processing: Merges memory and
• It can be designed with skew inverters to achieve 1 1 0 0.878
processing tasks to improve performance. 1 1 0 0.42
AND and OR functionality for read and write
 0 1 1 1.0367 0 1 0 0.828
operations.
Impact of Non-Idealities on the Performance Fig.1 Fermi GPU Microarchitecture [1]
Comparison:
1 0 1 1.0367 1 0 0 0.828
Offset Error: A non-zero output even with zero input introduces 0 0 1 1.186 0 0 1 1.1856
a constant bias, leading to inaccurate measurements. Parameters Power Performance Density Trade-offs Comments
Gain Error: Distorted signal representation. The ADC may not
perfectly amplify the input signal, leading to scaling errors.
4+2T SRAM Less poor more Higher write access It easier to perform NAND and NOR
Write/Read Disturbance: Data corruption in adjacent cells.
time, sensitive to operations
Writing or reading data from one cell can interfere with the Process variation
data stored in nearby cells, leading to potential bit errors.
6T SRAM moderate good moderate read noise margin Needs additional circuitry for NAND
Bit Line Noise: Data corruption. Noise on bit lines can cause
degrades and NOR operations.
random bit flips, leading to data integrity issues.

6T SRAM
Fig.2 4+2T SRAM Array implementation(64*1)
8T SRAM more better less Larger size , Two extra transistors, making it easier
• We conducted a discharge analysis across the Bit-line (BL) higher power to perform NAND and NOR operations
to assess whether it effectively performs Boolean NAND: NOR: consumption directly within the cell
operations when given different sets of digital inputs. Result Result
• Analog results . were analysed and compared with digital Conclusion:
Q0 Q1 Output (BL) Q0 Q1 Output (BL)
output.
1 1 0 0.739 1 1 0 0.185 • At the specified PVT condition (TT 25°C, VDD = 1.2V), the result analysis was conducted. At inputs 00, the system
0 1 1 1.0087 0 1 0 0.557
exhibited degradation as the voltage dropped from 1.2V to a range of 0.878V to 0.113V. To address this issue, a sense
4+2T SRAM: amplifier will be introduced in future designs. Once the sense amplifier is added, the results across the bit line (BL) will
1 0 1 1.0087 1 0 0 0.557
Boolean function Implementation: be examined, and if the voltage remains within the acceptable range, the design will be considered correct.
0 0 1 1.19 0 0 1 1.1839
• 4T cell for data storage. The extra 2T search cell enables • The choice between 4+2T, 6T and 8T SRAM cells depends on the specific requirements of the application, such as
efficient searching by utilizing a low-threshold voltage performance, power efficiency, and reliability considerations. Each cell type has its advantages and trade-offs, making
technique. them suitable for different use cases.
• We kept 2 Read Word lines gnd and rest were vdd. Then
we provided inputs at Q1, Q2, QB1 and QB2 and kept
References:
supply, VDD= 1.2 V.
[1] Sparsh Mittal, Gaurav Verma, Brajesh Kaushik, Farooq A. Khanday, A survey of SRAM-based in-memory computing techniques and applications,
6T SRAM: Journal of Systems Architecture, Volume 119, 2021, 102276,ISSN 1383-7621,https://doi.org/10.1016/j.sysarc.2021.102276.
[2] A. Agrawal, A. Jaiswal, C. Lee and K. Roy, "X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories," in IEEE
Boolean function Implementation: Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 12, pp. 4219-4232, Dec. 2018, doi: 10.1109/TCSI.2018.2848999
• We kept 2 Word lines on and rest were off. Then we [3] In Memory Compute for GPUs by Prakhar Shukla Under the supervision of Dr. Anuj Grover
provided inputs at Q1, Q2, QB1 and QB2 and kept supply, [4] A. K. Rajput and M. Pattanaik, "Implementation of Boolean and Arithmetic Functions with 8T SRAM Cell for In-Memory Computation," 2020
International Conference for Emerging Technology (INCET), Belgaum, India, 2020, pp. 1-5, doi: 10.1109/INCET49848.2020.9154137.
VDD= 1.2 V. Fig.3 6T SRAM Array implementation(64*1) [5].Q. Dong et al., "A 0.3V VDDmin 4+2T SRAM for searching and in-memory computing using 55nm DDC technology," 2017 Symposium on VLSI
Circuits, Kyoto, Japan, 2017, pp. C160-C161, doi: 10.23919/VLSIC.2017.8008465.