Study of Non Idealities in ADC and SRAM for IMC Applications i-Razor

Authors-Abhishek Mishra(abhishek22182@iiitd.ac.in), Dr. Anuj Error Detection:

Grover(anuj@iiitd.ac.in) • When M1-M5 is transparent, if Input doesn’t Error Correction:
transitions in this region and M14 is ON (CTL=1), When error is detected , it gives a control signal to
Process Step/ IP/ Component In-situ Error Detection and correction VVSS=0  ERR’ =1 timing control which skips a clock providing the
• Data is given out at Q pipeline with a further clock cycle to resolve
• When M1-M5 is transparent, If input the error.
Applicability Processors transitions in this region and M14 is OFF (CTL=0),
VVSS=1 
ERR’=0

Conventional Razor Scheme:

Error Detection
• Main Flip flop doesn’t latch data and shadow latch which
operates using a delayed clock with respect to main flip
flop latches data.
•By comparing the data of main flip flop and shadow latch an
error signal is generated.

Error Correction: 2 methods

1. Clock Gating: (Simple but slow method)
• When a Razor error is detected in any stage, the entire
pip stalled for one cycle by gating the next global clock
edge.
• The additional cycle allows each stage to recompute its
re the Razor shadow latch as input.

2. Recovery using counter-flow pipelining:.

Erroneous stage's computation is stopped using a "bubble"
signal. Then, a "flush train" is initiated by identifying the
stage that caused the error. The flush train moves through
the pipeline, replacing each affected stage and the one
Comparison
before it with bubbles until it reaches the start of the :
pipeline. Once it reaches the start, the pipeline is restarted
from the instruction after the erroneous one. If multiple
Type Max Energy Area # Razor Maximum Technolo
efficiency overhea cell/ # Total Performance - gy
stages have errors, they will all initiate recovery, but only Razor improvemen d FF Improvemen
the one closest to the end of the pipeline will complete,
while the earlier recoveries will be cancelled by later ones. t t
The pipeline restarts after the erroneous instruction, and Flip-Flop 0.18um
normal operation resumes.
Conventio- based 64.2% @ Not 2408/45661 Not
Error Correction:
Bubble Razor: Adatapath
shadow latch captures data as the main nal Razor 200MHz reported reporte
latch opens. An XOR compares the two A bubble causes a latch to skip its next transparent clock
values and
Error Detection: will flag an error if data arrives late and changes
phase, giving it an additional cycle for correct data to Latch 20% 45nm
arrive.
the value in the main latch. Bubbl base 60% @ 3401/36206 d 22%
e d 363MHz
Razor 13.6% 40nm
Latch 41% @ 1115/12875 34%
I-Razor base 843MHz
d

Resources:
[1] D. Ernst et al., "Razor: a low-power pipeline based on circuit-level timing speculation," Proceedings. 36th Annual IEEE/ACM
International Symposium on Microarchitecture, 2003.
[2] Y. Zhang et al., "iRazor: Current-Based Error Detection and Correction Scheme for PVT Variation in 40-nm ARM Cortex-R4
Processor," in IEEE Journal of Solid-State Circuits,
[3] M. Fojtik et al., "Bubble Razor: An architecture-independent approach to timing-error detection and correction," 2012 IEEE
[4] Fojtik, Matthew. (2013). Architecture Independent Timing Speculation Techniques in VLSI Circuits..
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