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LogicDesign TP01
LogicDesign TP01
• What is design?
• Collection of devices that sense and/or control wires
given a specification of a problem, come up with a way of solving it
choosing appropriately from a collection of available components
that carry a digital value (i.e., a physical quantity that
while meeting some criteria for size, cost, power, beauty, elegance,
can be interpreted as a “0” or “1”)
etc. example: digital logic where voltage < 0.8v is a “0” and > 2.0v is a “1”
• What is logic design?
determining the collection of digital logic components to perform a • Primitive digital hardware devices
specified control and/or data manipulation and/or communication logic computation devices (sense and drive)
function and the interconnections between them are two wires both “1” - make another be “1” (AND)
which logic components to choose? – there are many implementation is at least one of two wires “1” - make another be “1” (OR)
technologies is a wire “1” - then make another be “0” (NOT)
sense
the design may need to be optimized and/or transformed to meet memory devices (store)
design constraints store a value
recall a previously stored value AND drive
sense
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Computation:
This Class : concepts/skills/abilities
abstract vs. implementation
A Z A B
AND
close switch (if A is “1” or asserted) Z = A and B
and turn on light bulb (Z)
Z A
A
open switch (if A is “0” or unasserted) OR
Z = A or B
and turn off light bulb (Z)
Z = A B
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Transistor networks MOS transistors
• Modern digital systems are designed in CMOS • MOS transistors have three terminals: drain, gate,
technology and source
MOS stands for Metal-Oxide on Semiconductor they act as switches in the following way:
C is for complementary because there are both normally-open and if the voltage on the gate terminal is (some amount) higher/lower than
normally-closed switches the source terminal then a conducting path will be established
between the drain and source terminals
S D S D
n-channel p-channel
open when voltage at G is low closed when voltage at G is low
closes when: opens when:
voltage(G) > voltage (S) + voltage(G) < voltage (S) –
X Y
3v
what is the
X what is the relationship
relationship between x, y and z?
between x and y? Z1
3v x y 0v x y z1 z2
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Speed of MOS networks Representation of digital designs
• What influences the speed of CMOS networks? • Physical devices (transistors, relays)
charging and discharging of voltages on wires and gates of • Switches
transistors
• Truth tables
• Capacitors hold charge
• Boolean algebra
capacitance is at gates of transistors and wire material
• Resistors slow movement of electrons • Gates scope of This Class
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Combinational vs.
Logic gates
sequential digital circuits
X Y Z
• A simple model of a digital system is a unit with X 0 0 1
NAND Z 0
inputs and outputs: Y 1 1
1 0 1
X Y 1 1 0
NOT X Y 0 1
1 0
X Y Z
inputs system outputs X 0 0 1
X Y Z Z
0 0 0
NOR 0 1 0
X Y 1 0 0
AND Y Z 0 1 0 1 1 0
1 0 0
• Combinational means "memory-less" 1 1 1
a digital circuit is combinational if its output values X Y Z
X Y Z X 0 0 0
only depend on its input values X 0 0 0 XOR Z 0 1 1
OR Z 0 1 1 Y
Y 1 0 1
1 0 1 1 1 0
1 1 1
X Y Z
X 0 0 1
XNOR Y Z 0 1 0
1 0 0
1 1 1
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Example of combinational and
An example
sequential logic
• Combinational: • Calendar subsystem: number of days in a month (to
input A, B control watch display)
A
wait for clock edge C used in controlling the display of a wrist-watch LCD screen
observe C B
wait for another clock edge inputs: month, leap year flag
observe C again: will stay the same outputs: number of days
• Sequential:
input A, B A
wait for clock edge C
B
observe C
wait for another clock edge
Clock
observe C again: may be different
Implementation as a
Implementation in software
combinational digital system
• Encoding:
integer number_of_days ( month, leap_year_flag) { how many bits for each input/output?
switch (month) { binary number for month
case 1: return (31); four wires for 28, 29, 30, and 31 month leap d28 d29 d30 d31
0000 – – – – –
case 2: if (leap_year_flag == 1) then return (29) • Behavior: 0001 – 0 0 0 1
else return (28); 0010 0 1 0 0 0
combinational
case 3: return (31); 0010 1 0 1 0 0
... truth table 0011 – 0 0 0 1
specification 0100 – 0 0 1 0
case 12: return (31); 0101 – 0 0 0 1
default: return (0); month leap 0110 – 0 0 1 0
0111 – 0 0 0 1
} 1000 – 0 0 0 1
} 1001 – 0 0 1 0
1010 – 0 0 0 1
1011 – 0 0 1 0
1100 – 0 0 0 1
1101 – – – – –
111– – – – – –
d28 d29 d30 d31
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Combinational example (cont’d) Combinational example (cont’d)
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Sequential example (cont’d):
Summary
encoding
• That was what the entire course is about
converting solutions to problems into combinational and sequential
networks effectively organizing the design hierarchically
next
reset new equal state state mux open/closed doing so with a modern set of design tools that lets us handle large
1 – – – 0001 001 0
designs effectively
0 0 – 0001 0001 001 0
0 1 0 0001 0000 – 0 good choice of encoding! taking advantage of optimization opportunities
0 1 1 0001 0010 010 0
0 0 – 0010 0010 010 0 mux is identical to
0 1 0 0010 0000 – 0 last 3 bits of state
0 1 1 0010 0100 100 0
0 0 – 0100 0100 100 0 open/closed is
0 1 0 0100 0000 – 0 identical to first bit
0 1 1 0100 1000 – 1 of state
0 – – 1000 1000 – 1
0 – – 0000 0000 – 0