Digital Logic Design (EEE2135-01)

2nd Midterm Examination Thursday, May 16, 2024

[Problem 1] (10 points) For both 1’s and 2’s complement [Problem 4] (10 points) Given the function
representations, determine the minimum number of bits f  x1 x2 x4  x2 x3 x4  x1 x2 x3 , how many LUTs are
for the signed binary number such that the following
required for an FPGA with 3-input LUTs? Minimize the
computations can be performed without overflow. Then,
obtain the answers by using both 1’s and 2’s complement number of LUTs.
representations. (Show each step in very details.)

(a) 14 + 15 =
[Problem 5] (30 points)
(b) 7 – ( – 21) = (Do not compute 7 + 21.)
(a) Design the fastest 4-bit adder and show the
critical path delay. Use AND, OR, XOR gates
with any number of inputs.
[Problem 2] (5+5+10+10) For the following function
(b) Design 3x4 carry look-ahead fast adder using
f  x2  x1 x3  x1 x2 x4 hierarchical approach using the block designed
in (a). Show the critical path delay.
(a) Optimize the gate level design by using only 2-
(c) Design adder in (a) with the assumption that the
input NAND gates. Then, count total number of
transistors. maximum fan-in for the gates is two.

(b) Design CMOS circuit that minimizes the

number of transistors. Then compare the number
of transistors and its critical path delay with that [Problem 6] (10 points) Design the circuit that convert
of circuit in (a). the 3-bit Gray code to binary code.

(c) Optimize the design using FPGA utilizing 2-

input LUT’s. How many cells are used?

(d) Implement it using 3-to-1 multiplexers only. It

needs to select optimized one after investigating GOOD LUCK!
all possible implementations.

[Problem 3] (10 points) Derive a CMOS complex gate

using minimum number of transistors for the logic

function f   m(0,1, 2, 4,6,8,10,12,14) .

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