Chapter 32

Boot Assist Module (BAM)

This chapter describes the Boot Assist Module (BAM).

32.1 Overview
The Boot Assist Module is a block of read-only memory containing VLE code that is executed according
to the boot mode of the device.
The BAM allows downloading boot code via the FlexCAN or LINFlex interfaces into internal SRAM and
then executing it.

32.2 Features
The BAM provides the following features:
• MPC5604P in static mode if internal flash is not initialized or invalid
• Programmable 64-bit password protection for serial boot mode
• Serial boot loads the application boot code from a FlexCAN or LINFlex bus into internal SRAM
• Censorship protection for internal flash module

32.3 Boot modes

The MPC5604P device supports the following boot modes:
• Single Chip (SC) — the device boots from the first bootable section of the Flash main array.
• Serial Boot (SBL) — the device downloads boot code from either LINFlex or FlexCAN interface
and then execute it1.
If booting is not possible with the selected configuration (e.g., if no Boot ID is found in the selected boot
location) then the device enters the static mode.

32.4 Memory map

The BAM code resides in a reserved 8 KB ROM mapped from address 0xFFFF_C000. The address space
and memory used by the BAM application is shown in Table 32-1.
Table 32-1. BAM memory organization

Parameter Address

BAM entry point 0xFFFF_C000

Downloaded code base address 0x4000_0100

The RAM location where to download the code can be any 4-byte-aligned location starting from the
address 0x4000_0100.

1. Support for the FlexRay interface is planned on future devices.

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32.5 Functional description

32.5.1 Entering boot modes

The MPC5604P detects the boot mode based on external pins and device status. The following sequence
applies (see Figure 32-1):
• To boot either from FlexCAN or LINFlex, the device must be forced into an Alternate Boot Loader
Mode via the FAB (Force Alternate Boot Mode), which must be asserted before initiating the reset
sequence. The type of alternate boot mode is selected according to the ABS (Alternate Boot
Selector) pins (see Table 32-2).
• If FAB is not asserted, the device boots from the lowest Flash sector that contains a valid boot
signature.
• If no Flash sector contains a valid boot signature, the device will go into static mode.

POR or Standby Recovery

Y
00 Serial boot (SBL)
FABM = 1 ABS = ? UART

N
01 Serial boot (SBL)
FlexCAN

Flash Boot-ID Flash boot from

in any 10
boot sector? lowest sector Autobaud scan

no Boot-ID

Static mode

Note: The gray blocks in this figure represent hardware actions; white blocks represent software (BAM) actions.

Figure 32-1. Boot mode selection

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 Table 32-2. Hardware configuration to select boot mode

Standby-RAM
FAB ABS[1:0] Boot ID Boot Mode
Boot Flag

1 00 0 — LINFlex without autobaud

1 01 0 — FlexCAN without autobaud

1 10 0 — Autobaud scan

When autobaud scan is selected by ABS and FAB pins, an autoscan procedure starts. This procedure
listens to the active bus protocol and automatically selects between:
• FlexCAN with autobaud
• LINFlex with autobaud
NOTE
Autobaud boot code feature is not provided when the device is secured.

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32.5.2 Reset Configuration Half Word Source (RCHW)
The MPC5604P Flash is partitioned into boot sectors as shown in Table 32-4.
Each boot sector contains the Reset Configuration Half-Word (RCHW) at offset 0x00.
Address: Base + 0x0000 Access: User read-only
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 VLE BOOT_ID[0:7]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 32-2. Reset Configuration Half Word (RCHW)

Table 32-3. RCHW field descriptions

Field Description

0-6 Reserved

7 VLE Indicator
VLE This bit configures the MMU for the boot block to execute as either Classic Power Architecture
Book E code or as Freescale VLE code.
0 Boot code executes as Classic Power Architecture Book E code
1 Boot code executes as Freescale VLE code
8-15 Is valid if its value is 0x5A, then the sector is considered bootable.
BOOT_ID[0:7]

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 128K

0x0002 0000

32K

0x0001 8000 Boot information

32K

0x0001 0000 Boot information

16K

0x0000 C000 Boot information

Application
16K 0x0000 000C

0x0000 8000 Boot information Application

0x0000 0008

Application start address

32K 0x0000 0004

RCHW
0x0000 0000
0x0000 0000 Boot information

Internal Flash
Figure 32-3. MPC5604P Flash partitioning and RCHW search

Table 32-4. Flash boot sector

Block Address
0 0x0000_0000
1 0x0000_8000
2 0x0000_C000
3 0x0001_0000
4 0x0001_8000

32.5.3 Single chip boot mode

In single chip boot mode, the hardware searches the flash boot sector for a valid boot ID. As soon the
device detects a bootable sector, it jumps within this sector and reads the 32-bit word at offset 0x4. This
word is the address where the startup code is located (reset boot vector).
Then the device executes this startup code. A user application should have a valid instruction at the reset
boot vector address.

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If a valid RCHW is not found, the BAM code is executed. In this case BAM moves the MPC5604P into
static mode.

32.5.3.1 Boot and alternate boot

Some applications require an alternate boot sector in the flash so that the main sector in flash can be erased
and reprogrammed in the field.
When an alternate boot is needed, the user can create two bootable sectors. The low sector is the main boot
sector and the high sector is the alternate boot sector. The alternate boot sector does not need to be
consecutive to the main boot sector.
This ensures that even if one boot sector is erased still there will always be another active boot sector:
• Sector shall be activated (i.e., program a valid BOOT_ID instead of 0xFF as initially programmed).
• Sector shall be deactivated writing to 0 some of the bits BOOT_ID bit field (bit1 and/or bit3, and/or
bit4, and/or bit6).

32.5.4 Boot through BAM

32.5.4.1 Executing BAM

Single chip boot mode is managed by hardware and BAM does not participate in it.
BAM is executed only on these two following cases:
• Serial boot mode has been selected by FAB pin
• Hardware has not found a valid Boot-ID in any Flash boot locations
If one of these conditions is true, the device fetches code at location 0xFFFF_C000 and BAM application
starts.

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32.5.4.2 BAM software flow
Figure 32-4 illustrates the BAM logic flow.

BAM entry
0xFFFF_C000

Save default
configuration
The selected boot mode is verified
by reading the SSCM_STATUS register
(bits BMODE and ABD)

Check
boot mode

Restore
Boot mode
default STATIC mode
valid?
NO configuration

YES

Download new Restore

Execute
and save to default
new code
SRAM configuration

Figure 32-4. BAM logic flow

The first action is to save the initial device configuration. In this way is possible to restore the initial
configuration after downloading the new code but before executing it. This allows the new code being
executed as the device was just coming out of reset.
The BMODE and ABD fields of SSCM_STATUS register (see Section 8.2.2.1, “System Status register
(STATUS)”) indicate which boot has to be executed (see Table 32-5).
If the BMODE field shows either a single chip value (011) or a reserved value, the boot mode is not
considered valid and the BAM pushes the device into static mode.
In all other cases the code of the relative boot is called. Data is downloaded and saved into proper SRAM
location.

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 Table 32-5. Fields of SSCM STATUS register used by BAM

Field Description

BMODE Device Boot Mode

000 FlexRay boot serial boot loader mode (future use)
001 FlexCAN serial boot loader mode
010 SCI serial boot loader mode
011 Single chip mode
100 Expanded chip mode
Other values are reserved.
ABD Autobaud select
0 Autobaud detection is not active.
1 Autobaud detection is active.

Then, the initial device configuration is restored and the code jumps to the address of downloaded code.
At this point BAM has just finished its task.
If an error occurs, (e.g., communication error, wrong boot selected, etc.), the BAM restores the default
configuration and puts the device into static mode. Static mode means the device enters the low power
mode SAFE and the processor executes a wait instruction. This is needed if the device cannot boot in the
selected mode. During BAM execution and after, the mode reported by the field S_CURRENT_MODE of
the register ME_GS in the module ME Module is “DRUN”.

32.5.4.3 BAM resources

BAM uses/initializes the following MCU resources:
• ME and CGM modules to initialize mode and clock sources
• CAN_0, LINFlex_0, and their pads when performing serial boot mode
• SSCM to check the boot mode and during password check (see Table 32-5 and Figure 32-5)
• External oscillator
The following hardware resources are used only when autobaud feature is selected:
• STM to measure the baud rate
• CMU to measure the external clock frequency related to the internal RC clock source
• FMPLL to work with system clock near the maximum allowed frequency (this to have higher
resolution during baud rate measurement).
As already mentioned, the initial configuration is restored before executing the downloaded code.
When the autobaud feature is disabled, the system clock is selected directly from the external oscillator.
Thus the oscillator frequency defines baud rates for serial interfaces used to download the user application
(see Table 32-6).

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 Table 32-6. Serial boot mode without autobaud—baud rates

Crystal frequency LINFlex baud rate FlexCAN bit rate

(MHz) (baud) (bit/s)

fextal fextal / 833 fextal / 40

8 9600 200 K
12 14400 300 K
16 19200 400 K

20 24000 500 K
40 48000 1M

32.5.4.4 Download and execute the new code

From a high level perspective, the download protocol follows these steps:
1. Send message and receive acknowledge message for autobaud or autobit rate selection. (optional
step).
2. Send 64-bit password.
3. Send start address, size of downloaded code in bytes, and VLE bit1.
4. Download data.
5. Execute code from start address.
Each step must be complete before the next step starts.
These steps are correct if autobaud is disabled. Otherwise, to measure the baud rate, some data is sent from
the host to the MCU before step 1 (see Section 32.6.1, “Autobaud feature”).
The communication is done in half duplex manner. Any transmission from the host is followed by the
MCU transmission:
1. Host sends data to MCU and start waiting.
2. MCU echoes to host the data received.
3. MCU verifies if echo is correct.
— If data is correct, the host can continue to send data.
— If data is not correct, the host stops transmitting and the MCU needs to be reset.
All multi-byte data structures are sent MSB first.
A more detailed description of these steps follows.

32.5.4.5 Download 64-bit password and password check

The first 64 received bits represent the password. This password is sent to the Password Check procedure
for verification.
Password check data flow is shown in Figure 32-5 where:
1. Since the device supports only VLE code and does not support Book E code, this flag is used only for backward compatibility.

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 • SSCM_STATUS[SEC] = 1 means flash secured
• SSCM_STATUS[PUB] = 1 means flash with public access.
In case of flash with public access, the received password is compared with the public password
0xFEED_FACE_CAFE_BEEF.
If public access is not allowed but the flash is not secured, the received password is compared with the
value saved on NVPWD0 and NVPWD1 registers.
In uncensored devices, it is possible to download code via LINFlex or FlexCAN (serial boot mode) into
internal SRAM with any 64-bit private password stored in the flash and provided during the boot sequence.
In the previous cases, comparison is done by the BAM application. If it goes wrong, BAM pushes the
device into static mode.
In case of public access not allowed and flash secured, the password is written into SSCM[PWCMPH/L]
registers.
In case of flash secured with public access not allowed (user password configured in the NVPWD0 and NVPWD1 registers), the
user must set the swapped password: NVPWD1 and NVPWD0 to access the device (refer to following examples).

Example 32-1.

In devices with flash secured, registers are programmed:

NVPWD0 = 0x87654321
NVPWD1 = 0x12345678
NVSCI0 = 0x55AA1111
NVSCI1 = 0x55AA1111
To download the code via SLB, the provided password is 0x1234_5678_8765_4321 (swapped
WITH respect to NVPWD0/NVPWD1 —> NVPWD1/NVPWD0).
Example 32-2.

In devices with flash NOT secured, registers are programmed:

NVPWD0 = 0x87654321
NVPWD1 = 0x12345678
NVSCI0 = 0x55AA55AA
NVSCI1 = 0x55AA55AA
To download the code via SLB the provided password is 0x8765_4321_1234_5678 (as expected
from NVPWD0/NVPWD1).
After a fixed time waiting, comparison is done by hardware. Then BAM again verifies the SEC flag in
SSCM_STATUS:
• SEC = 0, flash is now unsecured and BAM continues its task
• SEC = 1, flash is still secured because password was wrong; BAM puts the device into standby
mode.

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This fixed time depends on external crystal oscillator frequency (XOSC). With XOSC of 12 MHz, fixed
time is 350 ms.

SSCM. =1 Comparison with

STATUS. FEEDFACE
PUB CAFEBEEF

=0

SSCM. =0 Comparison with

STATUS. password saved on
SEC NVPWD[0:1]

=1

Write received password to

SSCM.PWCMPH-L

Wait

Verify whether Flash is

unsecured

Figure 32-5. Password check flow

32.5.4.6 Download start address, VLE bit and code size

The next 8 bytes received by the MCU contain a 32-bit Start Address, the VLE mode bit and a 31-bit code
Length as shown in Figure 32-6.
The VLE bit (Variable Length Instruction) indicates which instruction set for which the code has been
compiled. This device family supports only VLE = 1. The bit is used for backward compatibility.
The Start Address defines where the received data will be stored and where the MCU will branch after the
download is finished. The two LSB bits of the Start Address are ignored by the BAM program, such that
the loaded code should be 32-bit word aligned.
The Length defines how many data bytes have to be loaded.

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 START_ADDRESS[31:16]

START_ADDRESS[15:0]

VLE CODE_LENGTH[30:16]

CODE_LENGTH[15:0]

Figure 32-6. Start address, VLE bit and download size in bytes

32.5.4.7 Download data

Each byte of data received is stored into device’s SRAM, starting from the address specified in the
previous protocol step.
The address increments until the number of bytes of data received matches the number of bytes specified
in the previous protocol step.
Since the SRAM is protected by 32-bit wide Error Correction Code (ECC), BAM always writes bytes into
SRAM grouped into 32-bit words. If the last byte received does not fall onto a 32-bit boundary, BAM fills
it with 0 bytes.
Then a “dummy” word (0x0000_0000) is written to avoid ECC error during core prefetch.

32.5.4.8 Execute code

The BAM program waits for the last echo message transmission being completed.
Then it restores the initial MCU configuration and jumps to the loaded code at Start Address that was
received in step 2 of the protocol.
At this point BAM has finished its tasks and MCU is controlled by new code executing from SRAM.

32.5.5 Boot from UART—autobaud disabled

32.5.5.1 Configuration
Boot from UART protocol is implemented by LINFlex_0 module. Pins used are:
• LINFlex_TX corresponds to pin B[2]
• LINFlex_RX corresponds to pin B[3].
When autobaud feature is disabled, the system clock is driven by external oscillator.
LINFlex controller is configured to operate at a baud rate = system clock frequency/833 (see Table 32-6
for baud rate example), using 8-bit data frame without parity bit and 1 stop bit.

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 Byte Field

Start Stop
D0 D1 D2 D3 D4 D5 D6 D7
bit bit

Figure 32-7. LINFlex bit timing in UART mode

32.5.5.2 UART boot mode download protocol

Table 32-7 summarizes the download protocol and BAM action during the UART boot mode.
Table 32-7. UART boot mode download protocol (autobaud disabled)

Protoco
Host sent BAM response
l Action
message message
step

1 64-bit password 64-bit password Password checked for validity and compared against stored
(MSB first) password.
2 32-bit store address 32-bit store address Load address is stored for future use.

3 VLE bit + VLE bit + Size of download is stored for future use.
31-bit number of 31-bit number of Verify if VLE bit is set to 1.
bytes (MSB first) bytes (MSB first)

4 8 bits of raw binary 8 bits of raw binary 8-bit data are packed into 32-bit word. This word is saved
data data into SRAM starting from the “Load address”.
“Load address” increments until the number of data
received and stored matches the size as specified in the
previous step.
5 none none Branch to downloaded code.

32.5.6 Bootstrap with FlexCAN—autobaud disabled

32.5.6.1 Configuration
Boot from FlexCAN protocol is implemented by the FlexCAN_0 module. Pins used are:
• CAN_TX corresponds to pin B[0]
• CAN_RX corresponds to pin B[1].
Boot from FlexCAN with autobaud disabled uses system clock driven by the external oscillator.
The FlexCAN controller is configured to operate at a baud rate equal to the system clock frequency/40 (see
Table 32-6 for examples of baud rate).
It uses the standard 11-bit identifier format detailed in the FlexCAN 2.0A specification.
FlexCAN controller bit timing is programmed with 10 time quanta, and the sample point is 2 time quanta
before the end, as shown in Figure 32-8.

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 NRZ Signal

SYNC_SEG Time Segment 1 Time Segment 2

1 7 2
time quanta time quanta time quanta

1 Bit Time

Transmit Point Sample Point

1 time Quanta = 4 system clock periods

Figure 32-8. FlexCAN bit timing

32.6 FlexCAN boot mode download protocol

Table 32-8 summarizes the download protocol and BAM action during the FlexCAN boot mode. All data
are transmitted bytewise.
Table 32-8. FlexCAN boot mode download protocol (autobaud disabled)

Protoco
Host sent BAM response
l Action
message message
step

1 FlexCAN ID 0x011 + FlexCAN ID 0x001 + Password checked for validity and compared against stored
64-bit password 64-bit password password.

2 FlexCAN ID 0x012 + FlexCAN ID 0x002 + Load address is stored for future use.
32-bit store address 32-bit store address Size of download is stored for future use.
+ VLE bit+ 31-bit + VLE bit + 31-bit Verify if VLE bit is set to 1.
number of bytes number of bytes
3 FlexCAN ID 0x013 + FlexCAN ID 0x003 + 8-bit data are packed into 32-bit words. These words are
8 to 64 bits of raw 8 to 64 bits of raw saved into SRAM starting from the “Load address”.
binary data binary data “Load address” increments until the number of data
received and stored matches the size as specified in the
previous step.

5 none none Branch to downloaded code.

32.6.1 Autobaud feature

The autobaud feature allows boot operation with a wide range of baud rates independent of the external
oscillator frequency.

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32.6.1.1 Configuration
Baud rate is measured by BAM using the System Timer Module (STM), which is driven by the system
clock.
One of the main differences with the previous cases is that system clock is not driven directly by the
external oscillator. Instead, it is driven by the FMPLL output. The reason is that to have an optimum baud
rate measurement resolution, system clock needs to be nearer to the maximum allowed device’s frequency.
This is achieved with the following two steps:
• Using the Clock Monitor Unit (CMU) and the RC oscillator, the external frequency is roughly
measured.
• Using the FMPLL, the system clock is configured to be close to but lower than the maximum
allowed frequency.
The relation between system clock frequency and external clock frequency with FMPLL configuration
value is shown in Table 32-9.
Table 32-9. System clock frequency related to external clock frequency

fosc [MHz] frc/fosc1 fsys [MHz]

4–8 4–2 16–32

8–12 2–4/3 32–48

12–16 4/3–1 36–48

16–24 1–2/3 32–48

> 24 < 2/3 > 24
1
These values and consequently the Fsys suffer from the precision of RC internal oscillator used to
measure Fosc through CMU module.

32.6.1.2 Boot from UART with autobaud enabled

The only difference between booting from UART with autobaud enabled and booting from UART with
autobaud disabled is that a further byte is sent from the host to the MCU when autobaud is enabled. The
value of that byte is 0x00.
This first byte measures the time from falling edge and rising edge. The baud rate can be calculated from
this time.

Time measurement

Start 0x0
bit

Figure 32-9. Baud measurement on UART boot

Initially the UART RX pin is configured as GPIO input and it waits in polling for the first falling edge,
then STM starts. UART RX pin waits again for the first rising. Then STM stops and from its measurement
baud rate is computed.

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The LINFlex module is configured to work in UART mode with the calculated baud rate. Then an
acknowledge byte (0x59, ASCII char “Y”) is sent.
From this point, the BAM follows the normal UART mode boot protocol (see Figure 32-10).

Start

UART_RX
configured as
GPIO input

NO
UART_RX == 0

YES

Start STM

NO
UART_RX == 1

YES

Stop STM
Read elapsed time
Calculate baud rate
UART_RX pin is configured
to work with LINFlex module.
LINFlex module is configured in UART
mode with calculated baud rate.
Baud rate
configuration

Follow normal
UART boot protocol

Figure 32-10. BAM rate measurement flow during UART boot

32.6.1.2.1 Choosing the host baud rate

The calculation of the UART baud rate from the length of the first 0 byte that is received, allows the
operation of the boot loader with a wide range of baud rates. However, to ensure proper data transfer, the
upper and lower limits have to be kept.

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SCI autobaud rate feature operates by polling the LINFlex_RX pin for a low signal. The length of time
until the next low to high transition is measured using the System Timer Module (STM) time base. This
high-low-high transition is expected to be a zero byte: a start bit (low) followed by eight data bits (low)
followed by a stop bit (high).
Upon reception of a zero byte and configuration of the baud rate, an acknowledge byte is returned to the
host using the selected baud rate.
Time base is enabled at reception of first low bit, disabled and read at reception of next high bit. Error
introduced due to polling will be small (typically < 6 cycles).
The following equation gives the relation between baud rate and LINFlex register configuration:

Eqn. 32-1
F cpu
LDIV = --------------------------------
-
16 baudrate

LDIV is an unsigned fixed point number and its mantissa is coded into 13 bits of the LINFlex’s register
LINIBRR.
From this equation and considering that a single UART transmission contains 9 bits, it is possible to obtain
the connection between time base measured by STM and LINIBB register:

Eqn. 32-2
LINIBRR = timebase
-----------------------
144

To minimize errors in baud rate, a large external oscillator frequency value and low baud rate signal are
preferred.
Example 32-3. Baud rate calculation for 24 kBaud signal

Considering a 24 kbaud signal and the device operating with 20 MHz external frequency.
Over 9 bits the STM will measure: (9 × 20 MHz)/24 kbaud = 7497 cycles.
Error expected to be approximately ± 6 cycles due to polling.
Thus, LINIBB will be set to 52 (rounding required). This results in a baud rate of 24.038 kbaud. Error of
< 0.2%.
To maintain the maximum deviation between host and calculated baud rate, recommendations for the user
are listed Table 32-10.
Table 32-10. Maximum and minimum recommended baud rates

Max baud rate for guaranteed Min baud rate for guaranteed
fsys = fxtal (MHz)
< 2.5% deviation < 2.5% deviation

13.4 Kbit/s 30 bit/s

4
(SBR = 19) (SBR = 8192)
26.9 Kbit/s 60 bit/s
8
(SBR = 19) (SBR = 8192)

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 Table 32-10. Maximum and minimum recommended baud rates (continued)

Max baud rate for guaranteed Min baud rate for guaranteed
fsys = fxtal (MHz)
< 2.5% deviation < 2.5% deviation

38.4 Kbit/s 90 bit/s

12
(SBR = 20) (SBR = 8192)

51.2 Kbit/s 120 bit/s

16
(SBR = 20) (SBR = 8192)

64.0 Kbit/s 150 bit/s

20
(SBR = 20) (SBR = 8192)

Higher baud rates high may be used, but the user will be required to ensure they fall within an acceptable
error range. This is illustrated in Figure 32-11, which shows the effect of quantization error on the baud
rate selection.
Baud rate deviation between host and device
10.00

9.00

8.00

7.00

6.00

5.00

4.00

3.00

2.00

1.00

0.00
0 10000 20000 30000 40000 50000
Host baud rate

Figure 32-11. Baud rate deviation between host and MPC5604P

Example 32-4. Baud rate calculation for 250 kBaud signal

Considering reception of a 250kBaud signal from the host and MPC5604P operating with a 4 MHz
oscillator. Over 9 bits the time base will measure: (9 × 4e6)/250e3 = 144 cycles.
Thus, LINIBB is set to 144/144 = 1. This results in a baud rate of exactly 250 kBd.
However, a slower 225 kBd signal operating with 4 MHz XTAL would again result in LINIBB = 1, but
this time with an 11.1% deviation.

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32.6.1.3 Boot from FlexCAN with autobaud enabled
The only difference between booting from FlexCAN with autobaud enabled and booting from FlexCAN
with autobaud disabled is that the following initialization FlexCAN frame is sent for baud measurement
purposes from the host to the MCU when autobaud is enabled:
• Standard identifier = 0x0,
• Data Length Code (DLC) = 0x0.
As all the bits to be transmitted are dominant bits, there is a succession of 5 dominant bits and 1 stuff bit
on the FlexCAN network (see Figure 32-12).
From the duration of this frame, the MCU calculates the corresponding baud rate factor with respect to the
current CPU clock and initializes the FlexCAN interface accordingly.

Start Shift bit Shift bit Shift bit Shift bit

Measured Time

Figure 32-12. Bit time measure

In UART boot mode, the FlexCAN RX pin is first configured to work as a GPIO input. In the end of baud
rate measurement, it switches to work with the FlexCAN module.
The baud rate measurement flow is detailed in Figure 32-13.

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 Start

CAN_0_RX pin
configured as
If CAN is connected, GPIO input
CAN_RX should be at high level

NO
CAN_RX == 1 ERROR

NO
CAN_RX == 0

Start STM

Wait for the first

recessive (HIGH) bit
NO
CAN_RX == 1

YES

There is a glitch if Read STM.

measured time < CAN_GLITCH_WIDTH measured time = STM value

YES
Glitch?

Wait CAN_RX == 1
These steps are
executed 4 times

Wait CAN_RX == 0

Stop STM
Read elapsed time
Calculate baud rate
Baud rate configuration
CAN_RX pin is configured
to work with FlexCAN module.
FlexCAN:
– is configured with calculated baud
– is enabled on the network

Follow normal
CAN boot protocol

Figure 32-13. BAM rate measurement flow during FlexCAN boot

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32.6.1.3.1 Choosing the host baud rate
The calculation of the FlexCAN baud rate allows the operation of the boot loader with a wide range of
baud rates. However, to ensure proper data transfer, the upper and lower limits have to be kept.
Pins are measured until reception of the 5th recessive bit. Thus a total of 29 bit-times are measured (see
Figure 32-12).
When calculating bit times and prescalers, to minimize any errors, ideally operate with the minimum
system clock prescaler divider (CAN_CR[PRESDIV]) and maximum number of time quanta possible.
After measuring the 29 bit times, the results stored in the STM time base are used to select PRESDIV. The
number of time quanta in a FlexCAN bit time is given by:
Bit_time = SYNCSEG + TSEG1 + TESG2
SYNCSEG = Exactly one time quantum.
TSEG1 = PROGPSEG + PSEG1 + 2
TSEG2 = PSEG2 + 1
Time base result = 29 × (Presdiv+1) × (SYNCSEG + TSEG1 + TSEG2)
FlexCAN protocol specifies that the FlexCAN bit timing should comprise a minimum of 8 time quanta
and a maximum of 25 time quanta. Therefore, the available range is:
8 ! 1 + TSEG1 + TESG2 ! 25
For 29 bit times, the possible range in which the result in the time base may lie, accounting for PRESDIV,
is:
(232 × (1 + PRESDIV)) ! time base ! (725 × (1 + PRESDIV))
Therefore, the available values of the time base can be divided into windows of 725 counts.
Table 32-11. Prescaler/divider and time base values

PRESDIV Time base Minimum Time base Maximum

0 232 725
1 726 1450
2 1451 2175
3 2176 2900

In the BAM, the time base is divided by 726, the remainder is discarded. The result provides the
CAN_CR[PRESDIV] to be selected.
To help compensate for any error in the calculated baud rate, the resynchronization jump width will be
increased from its default value of 1 to a fixed value of 2 time quanta.This is the maximum value allowed
that can accommodate all permissible can baud rates. See Table 32-12.

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 .

Table 32-12. FlexCAN standard compliant bit timing segment settings

Time Segment 1 Time Segment 2 RJW

5..10 2 1..2
4..11 3 1..3
5..12 4 1..4
6..13 5 1..4
7..14 6 1..4
8..15 7 1..4
9..16 8 1..4

Timing segment 2 is kept as large as possible to keep sample time within bit time.
Table 32-13. Lookup table for FlexCAN bit timings

Desired number of Time Segment 2 Time segment 1

Time quanta (DTq) PSEG2+1 PSEG1+1 PROPSEG+1

8 to 131 2 2 DTq-5

8 to 132 3 2 DTq-6

14 to 15 3 3 DTq-6
16 to 17 4 4 DTq-7
18 to 19 5 5 DTq-8
20 to 21 6 6 DTq-9
22 to 23 7 7 DTq-10
24 to 25 8 8 DTq-11
1 PRESDIV+1 > 1
2 PRESDIV+1 = 1 (to accommodate information processing time IPT of 3 tq) Note: All TSEG1 and
TSEG2 times have been chosen to preserve a sample time between 70% and 85% of the bit time.

Table 32-14. PRESDIV + 1 = 1

Desired number of time quanta Register contents for CANA_CR

8 0x004A_2001
9 0x004A_2002
10 0x004A_2003
11 0x004A_2004
12 0x004A_2005
13 0x004A_2006

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 Table 32-15. PRESDIV + 1 > 1 (YY = PRESDIV)

Desired number of time quanta Register contents for CANA_CR

8 0xYY49_2002
9 0xYY49_2003
10 0xYY49_2004
11 0xYY49_2005
12 0xYY49_2006
13 0xYY49_2007
14 0xYY52_2007
15 0xYY52_2008
16 0xYY5B_2008
17 0xYY5B_2009
18 0xYY64_2009
19 0xYY64_200A
20 0xYY6D_200A
21 0xYY6D_200B
22 0xYY76_200B
23 0xYY76_200C
24 0xYY7F_200C
25 0xYY7F_200D

Worked examples showing FlexCAN Autobaud rate:

Example 32-5. 8 MHz crystal
Consider case where using an 8 MHz crystal, user attempts to send 1 MB (max permissible baud
rate) FlexCAN message.
— Time base, clocking at crystal frequency, would measure:
— 1MB = 8 clocks/bit => 29 * 8 = 232 clocks
— To calculate PRESDIV = 232/725 =>PRESDIV = 0
— To calculate time quanta requirement:
— Time base result = 29 *(Presdiv+1) * (SYNCSEG + TSEG1 + TSEG2)
— 232 = 29 * 1 * (1 + TSEG1 + TSEG2)
— 1 + TSEG1 + TSEG2 = 8.
— From the lookup table, CANA_CR = 0x004A_2001.
— This give a baud rate of X. This give 0% error.

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 Example 32-6. 20 MHz crystal
Consider case where using a 20 MHz crystal, user attempts to send 62.5 Kb/s FlexCAN message.
— Time base, clocking at crystal frequency, would measure:
— 62.5 Kb/s = 320 clocks/bit => 29 * 320 = 9280 clocks
— To calculate PRESDIV = 9280/725 = 12r580 => PRESDIV = 12
— To calculate time quanta requirement:
— Time base result = 29 x (Presdiv+1) x (SYNCSEG + TSEG1 + TSEG2)
— 9280 = 29 x 13 x (1 + TSEG1 + TSEG2)
— 1 + TSEG1 + TSEG2 = 24.6~ 25 (need to round up - S/W must track remainder)
— From the lookup table, CANA_CR = 0x0C7F_200D.
— This give a baud rate of 61.538k Baud
— This equates to an error of: ~1.6%
This excludes cycle count error introduced due to software polling likely to be ~6 system clocks.

32.6.2 Interrupt
No interrupts are generated by or are enabled by the BAM.

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