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RISC-V Instruction Set Summary
31:25 24:20 19:15 14:12 11:7 6:0 • imm: signed immediate in imm11:0
funct7 rs2 rs1 funct3 rd op R-Type • uimm: 5-bit unsigned immediate in imm4:0
imm11:0 rs1 funct3 rd op • upimm: 20 upper bits of a 32-bit immediate, in imm31:12
I-Type
• Address: memory address: rs1 + SignExt(imm11:0)
imm11:5 rs2 rs1 funct3 imm4:0 op S-Type
data at memory location Address
• [Address]:
imm12,10:5 rs2 rs1 funct3 imm4:1,11 op B-Type • BTA: branch target address: PC + SignExt({imm12:1, 1'b0})
imm31:12 rd op U-Type • JTA: jump target address: PC + SignExt({imm20:1, 1'b0})
imm20,10:1,11,19:12 rd op J-Type • label: text indicating instruction address
fs3 funct2 fs2 fs1 funct3 fd op R4-Type • SignExt: value sign-extended to 32 bits
5 bits 2 bits 5 bits 5 bits 3 bits 5 bits 7 bits • ZeroExt: value zero-extended to 32 bits
• csr: control and status register
Figure B.1 RISC-V 32-bit instruction formats
Table B.1 RV32I: RISC-V integer instructions

op funct3 funct7 Type Instruction Description Operation
0000011 (3) 000 – I lb rd, imm(rs1) load byte rd = SignExt([Address]7:0)
0000011 (3) 001 – I lh rd, imm(rs1) load half rd = SignExt([Address]15:0)
0000011 (3) 010 – I lw rd, imm(rs1) load word rd = [Address]31:0
0000011 (3) 100 – I lbu rd, imm(rs1) load byte unsigned rd = ZeroExt([Address]7:0)
0000011 (3) 101 – I lhu rd, imm(rs1) load half unsigned rd = ZeroExt([Address]15:0)
0010011 (19) 000 – I addi rd, rs1, imm add immediate rd = rs1 + SignExt(imm)
0010011 (19) 001 0000000* I slli rd, rs1, uimm shift left logical immediate rd = rs1 << uimm
0010011 (19) 010 – I slti rd, rs1, imm set less than immediate rd = (rs1 < SignExt(imm))
0010011 (19) 011 – I sltiu rd, rs1, imm set less than imm. unsigned rd = (rs1 < SignExt(imm))
0010011 (19) 100 – I xori rd, rs1, imm xor immediate rd = rs1 ^ SignExt(imm)
0010011 (19) 101 0000000* I srli rd, rs1, uimm shift right logical immediate rd = rs1 >> uimm
0010011 (19) 101 0100000* I srai rd, rs1, uimm shift right arithmetic imm. rd = rs1 >>> uimm
0010011 (19) 110 – I ori rd, rs1, imm or immediate rd = rs1 | SignExt(imm)
0010011 (19) 111 – I andi rd, rs1, imm and immediate rd = rs1 & SignExt(imm)
0010111 (23) – – U auipc rd, upimm add upper immediate to PC rd = {upimm, 12'b0} + PC
0100011 (35) 000 – S sb rs2, imm(rs1) store byte [Address]7:0 = rs27:0
0100011 (35) 001 – S sh rs2, imm(rs1) store half [Address]15:0 = rs215:0
0100011 (35) 010 – S sw rs2, imm(rs1) store word [Address]31:0 = rs2
0110011 (51) 000 0000000 R add rd, rs1, rs2 add rd = rs1 + rs2
0110011 (51) 000 0100000 R sub rd, rs1, rs2 sub rd = rs1 — rs2
0110011 (51) 001 0000000 R sll rd, rs1, rs2 shift left logical rd = rs1 << rs24:0
0110011 (51) 010 0000000 R slt rd, rs1, rs2 set less than rd = (rs1 < rs2)
0110011 (51) 011 0000000 R sltu rd, rs1, rs2 set less than unsigned rd = (rs1 < rs2)
0110011 (51) 100 0000000 R xor rd, rs1, rs2 xor rd = rs1 ^ rs2
0110011 (51) 101 0000000 R srl rd, rs1, rs2 shift right logical rd = rs1 >> rs24:0
0110011 (51) 101 0100000 R sra rd, rs1, rs2 shift right arithmetic rd = rs1 >>> rs24:0
0110011 (51) 110 0000000 R or rd, rs1, rs2 or rd = rs1 | rs2
0110011 (51) 111 0000000 R and rd, rs1, rs2 and rd = rs1 & rs2
0110111 (55) – – U lui rd, upimm load upper immediate rd = {upimm, 12’b0}
1100011 (99) 000 – B beq rs1, rs2, label branch if = if (rs1 == rs2) PC = BTA
1100011 (99) 001 – B bne rs1, rs2, label branch if ≠ if (rs1 ≠ rs2) PC = BTA
1100011 (99) 100 – B blt rs1, rs2, label branch if < if (rs1 < rs2) PC = BTA
1100011 (99) 101 – B bge rs1, rs2, label branch if ≥ if (rs1 ≥ rs2) PC = BTA
1100011 (99) 110 – B bltu rs1, rs2, label branch if < unsigned if (rs1 < rs2) PC = BTA
1100011 (99) 111 – B bgeu rs1, rs2, label branch if ≥ unsigned if (rs1 ≥ rs2) PC = BTA
1100111 (103) 000 – I jalr rd, rs1, imm jump and link register PC = rs1 + SignExt(imm), rd = PC + 4
1101111 (111) – – J jal rd, label jump and link PC = JTA, rd = PC + 4
*
Encoded in instr31:25, the upper seven bits of the immediate field
Table B.2 RV64I: Extra integer instructions
op funct3 funct7 Type Instruction Description Operation
0000011 (3) 011 – I ld rd, imm(rs1) load double word rd = [Address]63:0
0000011 (3) 110 – I lwu rd, imm(rs1) load word unsigned rd = ZeroExt([Address]31:0)
0011011 (27) 000 – I addiw rd, rs1, imm add immediate word rd = SignExt((rs1 + SignExt(imm))31:0)
0011011 (27) 001 0000000 I slliw rd, rs1, uimm shift left logical immediate word rd = SignExt((rs131:0 << uimm)31:0)
0011011 (27) 101 0000000 I srliw rd, rs1, uimm shift right logical immediate word rd = SignExt((rs131:0 >> uimm)31:0)
0011011 (27) 101 0100000 I sraiw rd, rs1, uimm shift right arith. immediate word rd = SignExt((rs131:0 >>> uimm)31:0)
0100011 (35) 011 – S sd rs2, imm(rs1) store double word [Address]63:0 = rs2
0111011 (59) 000 0000000 R addw rd, rs1, rs2 add word rd = SignExt((rs1 + rs2)31:0)
0111011 (59) 000 0100000 R subw rd, rs1, rs2 subtract word rd = SignExt((rs1 — rs2)31:0)
0111011 (59) 001 0000000 R sllw rd, rs1, rs2 shift left logical word rd = SignExt((rs131:0 << rs24:0)31:0)
0111011 (59) 101 0000000 R srlw rd, rs1, rs2 shift right logical word rd = SignExt((rs131:0 >> rs24:0)31:0)
0111011 (59) 101 0100000 R sraw rd, rs1, rs2 shift right arithmetic word rd = SignExt((rs131:0 >>> rs24:0)31:0)
In RV64I, registers are 64 bits, but instructions are still 32 bits. The term “word” generally refers to a 32-bit value. In RV64I, immediate shift instructions use
6-bit immediates: uimm5:0; but for word shifts, the most significant bit of the shift amount (uimm5) must be 0. Instructions ending in “w” (for “word”) operate
on the lower half of the 64-bit registers. Sign- or zero-extension produces a 64-bit result.
Table B.3 RVF/D: RISC-V single- and double-precision floating-point instructions

op funct3 funct7 rs2 Type Instruction Description Operation
1000011 (67) rm fs3, fmt – R4 fmadd fd,fs1,fs2,fs3 multiply-add fd = fs1 * fs2 + fs3
1000111 (71) rm fs3, fmt – R4 fmsub fd,fs1,fs2,fs3 multiply-subtract fd = fs1 * fs2 — fs3
1001011 (75) rm fs3, fmt – R4 fnmsub fd,fs1,fs2,fs3 negate multiply-add fd = —(fs1 * fs2 + fs3)
1001111 (79) rm fs3, fmt – R4 fnmadd fd,fs1,fs2,fs3 negate multiply-subtract fd = —(fs1 * fs2 – fs3)
1010011 (83) rm 00000, fmt – R fadd fd,fs1,fs2 add fd = fs1 + fs2
1010011 (83) rm 00001, fmt – R fsub fd,fs1,fs2 subtract fd = fs1 — fs2
1010011 (83) rm 00010, fmt – R fmul fd,fs1,fs2 multiply fd = fs1 * fs2
1010011 (83) rm 00011, fmt – R fdiv fd,fs1,fs2 divide fd = fs1 / fs2
1010011 (83) rm 01011, fmt 00000 R fsqrt fd,fs1 square root fd = sqrt(fs1)
1010011 (83) 000 00100, fmt – R fsgnj fd,fs1,fs2 sign injection fd = fs1, sign = sign(fs2)
1010011 (83) 001 00100, fmt – R fsgnjn fd,fs1,fs2 negate sign injection fd = fs1, sign = —sign(fs2)
1010011 (83) 010 00100, fmt – R fsgnjx fd,fs1,fs2 xor sign injection fd = fs1,
sign = sign(fs2) ^ sign(fs1)
1010011 (83) 000 00101, fmt – R fmin fd,fs1,fs2 min fd = min(fs1, fs2)
1010011 (83) 001 00101, fmt – R fmax fd,fs1,fs2 max fd = max(fs1, fs2)
1010011 (83) 010 10100, fmt – R feq rd,fs1,fs2 compare = rd = (fs1 == fs2)
1010011 (83) 001 10100, fmt – R flt rd,fs1,fs2 compare < rd = (fs1 < fs2)
1010011 (83) 000 10100, fmt – R fle rd,fs1,fs2 compare ≤ rd = (fs1 ≤ fs2)
1010011 (83) 001 11100, fmt 00000 R fclass rd,fs1 classify rd = classification of fs1
RVF only
0000111 (7) 010 – – I flw fd, imm(rs1) load float fd = [Address]31:0
0100111 (39) 010 – – S fsw fs2,imm(rs1) store float [Address]31:0 = fd
1010011 (83) rm 1100000 00000 R fcvt.w.s rd, fs1 convert to integer rd = integer(fs1)
1010011 (83) rm 1100000 00001 R fcvt.wu.s rd, fs1 convert to unsigned integer rd = unsigned(fs1)
1010011 (83) rm 1101000 00000 R fcvt.s.w fd, rs1 convert int to float fd = float(rs1)
1010011 (83) rm 1101000 00001 R fcvt.s.wu fd, rs1 convert unsigned to float fd = float(rs1)
1010011 (83) 000 1110000 00000 R fmv.x.w rd, fs1 move to integer register rd = fs1
1010011 (83) 000 1111000 00000 R fmv.w.x fd, rs1 move to f.p. register fd = rs1
RVD only
0000111 (7) 011 - – I fld fd, imm(rs1) load double fd = [Address]63:0
0100111 (39) 011 – – S fsd fs2,imm(rs1) store double [Address]63:0 = fd
1010011 (83) rm 1100001 00000 R fcvt.w.d rd, fs1 convert to integer rd = integer(fs1)
1010011 (83) rm 1100001 00001 R fcvt.wu.d rd, fs1 convert to unsigned integer rd = unsigned(fs1)
1010011 (83) rm 1101001 00000 R fcvt.d.w fd, rs1 convert int to double fd = double(rs1)
1010011 (83) rm 1101001 00001 R fcvt.d.wu fd, rs1 convert unsigned to double fd = double(rs1)
1010011 (83) rm 0100000 00001 R fcvt.s.d fd, fs1 convert double to float fd = float(fs1)
1010011 (83) rm 0100001 00000 R fcvt.d.s fd, fs1 convert float to double fd = double(fs1)
fs1, fs2, fs3, fd: floating-point registers. fs1, fs2, and fd are encoded in fields rs1, rs2, and rd; only R4-type also encodes fs3. fmt: precision of computational
instruction (single=002, double=012, quad=112). rm: rounding mode (0=to nearest, 1=toward zero, 2=down, 3=up, 4=to nearest (max magnitude), 7=dynamic).
sign(fs1): the sign of fs1.
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In Praise of Digital Design
and Computer Architecture
RISC-V Edition
Harris and Harris have shown how to design a RISC-V processor from
the gates all the way up through the microarchitecture. Their clear
explanations combined with their comprehensive approach give a full
picture of both digital design and the RISC-V architecture. With the
exciting opportunity that students have to run large digital designs on
modern FPGAs, this approach is both informative and enlightening.
David A. Patterson University of California, Berkeley
What broad fields Harris and Harris have distilled into one book! As
semiconductor manufacturing matures, the importance of digital design
and computer architecture will only increase. Readers will find an
approachable and comprehensive treatment of both topics and will walk
away with a clear understanding of the RISC-V instruction set architecture.
Andrew Waterman SiFive
There are excellent texts for teaching digital design and there are excellent
texts for teaching computer hardware organization - and this textbook does
both! It is also unique in its ability to connect the dots. The writing makes
the RISC-V architecture understandable by building on the basics, and I
have found the exercises to be a great resource across multiple courses.
Roy Kravitz Portland State University
When I first read Harris and Harris’s MIPS textbook back in 2008, I
thought that it was one of the best books I had ever read for teaching
computer architecture. I started using it in my courses immediately.
Thirteen years later, I have had the honor of reviewing this new RISC-V
edition, and my opinion of their books has not changed: Digital Design
and Computer Architecture: RISC-V Edition is an excellent book, very
clear, thorough, with a high educational value, and in line with the
courses that we teach in the areas of digital design and computer archi-
tecture. I look forward to using this RISC-V textbook in my courses.
Daniel Chaver Martinez University Complutense of Madrid
Digital Design and
Computer Architecture
RISC-V Edition
Digital Design and
Computer Architecture
RISC-V Edition
Sarah L. Harris
David Harris
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Contents
Preface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xx
Online Supplements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxi
How to Use the Software Tools in a Course.. . . . . . . . . . . . . . . . xxii
Labs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxiii
RVfpga. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxiii
Bugs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxiv
Acknowledgments.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxiv
About the Authors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxv
Chapter 1 From Zero to One. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 The Game Plan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 The Art of Managing Complexity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2.1 Abstraction�� 2
1.2.2 Discipline�� 3
1.2.3 The Three -Y’s�� 4
1.3 The Digital Abstraction�� 5
1.4 Number Systems�� 7
1.4.1 Decimal Numbers�� 7
1.4.2 Binary Numbers�� 7
1.4.3 Hexadecimal Numbers�� 9
1.4.4 Bytes, Nibbles, and All That Jazz�� 11
1.4.5 Binary Addition�� 12
1.4.6 Signed Binary Numbers�� 13
1.5 Logic Gates�� 17
1.5.1 NOT Gate�� 18
1.5.2 Buffer�� 18
1.5.3 AND Gate�� 18
1.5.4 OR Gate�� 19
1.5.5 Other Two-Input Gates�� 19
1.5.6 Multiple-Input Gates�� 19
1.6 Beneath the Digital Abstraction�� 20
1.6.1 Supply Voltage�� 20
1.6.2 Logic Levels�� 20
1.6.3 Noise Margins�� 21
ix
x Contents
1.6.4 DC Transfer Characteristics�� 22

1.6.5 The Static Discipline�� 22
1.7 CMOS Transistors�� 24
1.7.1 Semiconductors�� 25
1.7.2 Diodes�� 25
1.7.3 Capacitors�� 26
1.7.4 nMOS and pMOS Transistors�� 26
1.7.5 CMOS NOT Gate�� 29
1.7.6 Other CMOS Logic Gates�� 29
1.7.7 Transmission Gates�� 31
1.7.8 Pseudo-nMOS Logic�� 31
1.8 Power Consumption�� 32
1.9 Summary and a Look Ahead�� 34
Exercises�� 36
Interview Questions�� 50
Chapter 2 Combinational Logic Design�� 53
2.1 Introduction�� 53
2.2 Boolean Equations�� 56
2.2.1 Terminology�� 56
2.2.2 Sum-of-Products Form�� 56
2.2.3 Product-of-Sums Form�� 58
2.3 Boolean Algebra�� 58
2.3.1 Axioms�� 59
2.3.2 Theorems of One Variable�� 59
2.3.3 Theorems of Several Variables�� 60
2.3.4 The Truth Behind It All�� 62
2.3.5 Simplifying Equations�� 63
2.4 From Logic to Gates�� 64
2.5 Multilevel Combinational Logic�� 67
2.5.1 Hardware Reduction�� 68
2.5.2 Bubble Pushing�� 69
2.6 X’s and Z’s, Oh My�� 71
2.6.1 Illegal Value: X�� 71
2.6.2 Floating Value: Z�� 72
2.7 Karnaugh Maps�� 73
2.7.1 Circular Thinking�� 74
2.7.2 Logic Minimization with K-Maps�� 75
2.7.3 Don’t Cares�� 79
2.7.4 The Big Picture�� 80
2.8 Combinational Building Blocks�� 81
2.8.1 Multiplexers�� 81
2.8.2 Decoders�� 84
Contents xi
2.9 Timing�� 86
2.9.1 Propagation and Contamination Delay�� 86
2.9.2 Glitches�� 90
2.10 Summary�� 93
Exercises�� 95
Chapter 3 Sequential Logic Design. . . . . . . . . . . . . . . . . . . . . . . . . . 107

3.2 Latches and Flip-Flops�� 107
3.2.1 SR Latch�� 109
3.2.2 D Latch�� 111
3.2.3 D FIip-Flop�� 112
3.2.4 Register�� 112
3.2.5 Enabled Flip-Flop�� 113
3.2.6 Resettable Flip-Flop�� 114
3.2.7 Transistor-Level Latch and Flip-Flop
Designs�� 114
3.2.8 Putting It All Together�� 116
3.3 Synchronous Logic Design�� 117
3.3.1 Some Problematic Circuits�� 117
3.3.2 Synchronous Sequential Circuits�� 118
3.3.3 Synchronous and Asynchronous
Circuits�� 120
3.4 Finite State Machines�� 121
3.4.1 FSM Design Example�� 121
3.4.2 State Encodings�� 127
3.4.3 Moore and Mealy Machines�� 130
3.4.4 Factoring State Machines�� 132
3.4.5 Deriving an FSM from a Schematic�� 135
3.4.6 FSM Review�� 138
3.5 Timing of Sequential Logic�� 139
3.5.1 The Dynamic Discipline�� 140
3.5.2 System Timing�� 140
3.5.3 Clock Skew�� 146
3.5.4 Metastability�� 149
3.5.5 Synchronizers�� 150
3.5.6 Derivation of Resolution Time�� 152
3.6 Parallelism�� 155
Exercises�� 160
xii Contents
Chapter 4 Hardware Description Languages. . . . . . . . . . . . . . . . . . 171

4.1.1 Modules�� 171
4.1.2 Language Origins�� 172
4.1.3 Simulation and Synthesis�� 173
4.2 Combinational Logic�� 175
4.2.1 Bitwise Operators�� 175
4.2.2 Comments and White Space�� 178
4.2.3 Reduction Operators�� 178
4.2.4 Conditional Assignment�� 179
4.2.5 Internal Variables�� 180
4.2.6 Precedence�� 182
4.2.7 Numbers�� 183
4.2.8 Z’s and X’s�� 184
4.2.9 Bit Swizzling�� 186
4.2.10 Delays�� 186
4.3 Structural Modeling�� 188
4.4 Sequential Logic�� 191
4.4.1 Registers�� 191
4.4.2 Resettable Registers�� 192
4.4.3 Enabled Registers�� 194
4.4.4 Multiple Registers�� 195
4.4.5 Latches�� 196
4.5 More Combinational Logic�� 196
4.5.1 Case Statements�� 199
4.5.2 If Statements�� 200
4.5.3 Truth Tables with Don’t Cares�� 203
4.5.4 Blocking and Nonblocking Assignments�� 203
4.6 Finite State Machines�� 207
4.7 Data Types�� 211
4.7.1 SystemVerilog�� 212
4.7.2 VHDL�� 213
4.8 Parameterized Modules�� 215
4.9 Testbenches�� 218
4.10 Summary�� 222
Exercises�� 224
Chapter 5 Digital Building Blocks�� 237

5.2 Arithmetic Circuits�� 237
5.2.1 Addition�� 237
5.2.2 Subtraction�� 244
Contents xiii
5.2.3 Comparators�� 245

5.2.4 ALU�� 247
5.2.5 Shifters and Rotators�� 251
5.2.6 Multiplication�� 253
5.2.7 Division�� 254
5.2.8 Further Reading�� 255
5.3 Number Systems�� 256
5.3.1 Fixed-Point Number Systems�� 256
5.3.2 Floating-Point Number Systems�� 257
5.4 Sequential Building Blocks�� 261
5.4.1 Counters�� 261
5.4.2 Shift Registers�� 262
5.5 Memory Arrays�� 265
5.5.1 Overview�� 265
5.5.2 Dynamic Random Access Memory (DRAM)�� 267
5.5.3 Static Random Access Memory (SRAM)�� 268
5.5.4 Area and Delay�� 268
5.5.5 Register Files�� 269
5.5.6 Read Only Memory (ROM)�� 269
5.5.7 Logic Using Memory Arrays�� 271
5.5.8 Memory HDL�� 272
5.6 Logic Arrays�� 272
5.6.1 Programmable Logic Array (PLA).�� 275
5.6.2 Field Programmable Gate Array (FPGA)�� 276
5.6.3 Array Implementations�� 282
Exercises�� 285
Chapter 6 Architecture�� 299

6.2 Assembly Language�� 300
6.2.1 Instructions�� 301
6.2.2 Operands: Registers, Memory, and Constants�� 302
6.3 Programming�� 308
6.3.1 Program Flow�� 308
6.3.2 Logical, Shift, and Multiply Instructions�� 308
6.3.3 Branching�� 311
6.3.4 Conditional Statements�� 313
6.3.5 Getting Loopy�� 315
6.3.6 Arrays�� 317
6.3.7 Function Calls�� 320
6.3.8 Pseudoinstructions�� 330
xiv Contents
6.4 Machine Language�� 332

6.4.1 R-Type Instructions�� 332
6.4.2 l-Type Instructions�� 334
6.4.3 S/B-Type Instructions�� 336
6.4.4 U/J-Type Instructions�� 338
6.4.5 Immediate Encodings�� 340
6.4.6 Addressing Modes�� 341
6.4.7 Interpreting Machine Language Code�� 342
6.4.8 The Power of the Stored Program�� 343
6.5 Lights, Camera, Action: Compiling, Assembling,
and Loading�� 344
6.5.1 The Memory Map�� 344
6.5.2 Assembler Directives�� 346
6.5.3 Compiling�� 348
6.5.4 Assembling�� 350
6.5.5 Linking�� 353
6.5.6 Loading�� 355
6.6 Odds and Ends�� 355
6.6.1 Endianness�� 355
6.6.2 Exceptions�� 356
6.6.3 Signed and Unsigned Instructions�� 360
6.6.4 Floating-Point Instructions�� 361
6.6.5 Compressed Instructions�� 362
6.7 Evolution of the RISC-V Architecture�� 363
6.7.1 RISC-V Base Instruction Sets and Extensions�� 364
6.7.2 Comparison of RISC-V and MIPS Architectures�� 365
6.7.3 Comparison of RISC-V and ARM Architectures�� 365
6.8 Another Perspective: x86 Architecture�� 366
6.8.1 x86 Registers�� 366
6.8.2 x86 Operands�� 367
6.8.3 Status Flags�� 369
6.8.4 x86 Instructions�� 369
6.8.5 x86 Instruction Encoding�� 371
6.8.6 Other x86 Peculiarities�� 372
6.8.7 The Big Picture�� 373
Exercises�� 375
Chapter 7 Microarchitecture�� 393

7.1.1 Architectural State and Instruction Set�� 393
7.1.2 Design Process�� 394
7.1.3 Microarchitectures�� 396
Contents xv
7.2 Performance Analysis�� 397

7.3 Single-Cycle Processor�� 398
7.3.1 Sample Program�� 399
7.3.2 Single-Cycle Datapath�� 399
7.3.3 Single-Cycle Control�� 407
7.3.4 More Instructions�� 410
7.3.5 Performance Analysis�� 412
7.4 Multicycle Processor�� 415
7.4.1 Multicycle Datapath�� 416
7.4.2 Multicycle Control�� 422
7.4.3 More Instructions�� 432
7.5 Pipelined Processor�� 439
7.5.1 Pipelined Datapath�� 441
7.5.2 Pipelined Control�� 443
7.5.3 Hazards�� 443
7.6 HDL Representation�� 456
7.6.1 Single-Cycle Processor �� 457
7.6.2 Generic Building Blocks�� 461
7.6.3 Testbench�� 464
7.7 Advanced Microarchitecture�� 468
7.7.1 Deep Pipelines�� 468
7.7.2 Micro-Operations�� 469
7.7.3 Branch Prediction�� 470
7.7.4 Superscalar Processors�� 472
7.7.5 Out-of-Order Processor�� 473
7.7.6 Register Renaming�� 476
7.7.7 Multithreading�� 478
7.7.8 Multiprocessors�� 479
7.8 Real-World Perspective: Evolution of
RISC-V Microarchitecture�� 482
Exercises�� 488
Chapter 8 Memory Systems�� 499
8.2 Memory System Performance Analysis�� 503
8.3 Caches�� 505
8.3.1 What Data is Held in the Cache?�� 505
8.3.2 How is Data Found?�� 506
8.3.3 What Data is Replaced?�� 514
8.3.4 Advanced Cache Design�� 515
xvi Contents
8.4 Virtual Memory�� 519

8.4.1 Address Translation�� 522
8.4.2 The Page Table�� 523
8.4.3 The Translation Lookaside Buffer�� 525
8.4.4 Memory Protection�� 526
8.4.5 Replacement Policies�� 527
8.4.6 Multilevel Page Tables�� 527
Epilogue�� 530
Exercises�� 532
Chapter 9 Embedded I/O Systems�� 542
Chapter 9 is available as an online supplement�� 542.e1
9.1 Introduction�� 542.e1
9.2 Memory-Mapped I/O�� 542.e1
9.3 Embedded I/O Systems�� 542.e3
9.3.1 RED-V Board�� 542.e3
9.3.2 FE310-G002 System-on-Chip�� 542.e5
9.3.3 General-Purpose Digital I/O�� 542.e5
9.3.4 Device Drivers�� 542.e10
9.3.5 Serial I/O�� 542.e14
9.3.6 Timers�� 542.e29
9.3.7 Analog I/O�� 542.e30
9.3.8 Interrupts�� 542.e39
9.4 Other Microcontroller Peripherals�� 542.e43
9.4.1 Character LCDs�� 542.e43
9.4.2 VGA Monitor�� 542.e45
9.4.3 Bluetooth Wireless Communication�� 542.e53
9.4.4 Motor Control�� 542.e54
9.5 Summary�� 542.e64
Appendix A Digital System Implementation�� 543
A.1 Introduction�� 543
Appendix A is available as an online supplement�� 543.e1
A.1 Introduction�� 543.e1
A.2 74xx Logic�� 543.e1
A.2.1 Logic Gates�� 543.e2
A.2.2 Other Functions�� 543.e2
Contents xvii
A.3 Programmable Logic�� 543.e2

A.3.1 PROMs�� 543.e2
A.3.2 PLAs�� 543.e6
A.3.3 FPGAs�� 543.e7
A.4 Application-Specific Integrated Circuits�� 543.e9
A.5 Datasheets�� 543.e9
A.6 Logic Families�� 543.e15
A.7 Switches and Light-Emitting Diodes�� 543.e17
A.7.1 Switches�� 543.e17
A.7.2 LEDs�� 543.e18
A.8 Packaging and Assembly�� 543.e19
A.8.1 Packages�� 543.e19
A.8.2 Breadboards�� 543.e20
A.8.3 Printed Circuit Boards�� 543.e20
A.8.4 Putting It All Together�� 543.e23
A.9 Transmission Lines�� 543.e23
A.9.1 Matched Termination�� 543.e24
A.9.2 Open Termination�� 543.e26
A.9.3 Short Termination�� 543.e27
A.9.4 Mismatched Termination�� 543.e27
A.9.5 When to Use Transmission Line Models�� 543.e30
A.9.6 Proper Transmission Line Terminations�� 543.e30
A.9.7 Derivation of Z0�� 543.e32
A.9.8 Derivation of the Reflection Coefficient�� 543.e33
A.9.9 Putting It All Together�� 543.e34
A.10 Economics�� 543.e35
Appendix B RISC-V Instruction Set Summary�� 544
Appendix C C Programming�� 545

C.1 Introduction�� 545
Appendix C is available as an online supplement�� 545.e1

C.1 Introduction�� 545.e1
C.2 Welcome to C�� 545.e3
C.2.1 C Program Dissection�� 545.e3
C.2.2 Running a C Program�� 545.e4
C.3 Compilation�� 545.e5
C.3.1 Comments�� 545.e5
C.3.2 #define�� 545.e5
C.3.3 #include�� 545.e6
xviii Contents
C.4 Variables�� 545.e7

C.4.1 Primitive Data Types�� 545.e8
C.4.2 Global and Local Variables�� 545.e9
C.4.3 Initializing Variables�� 545.e11
C.5 Operators�� 545.e11
C.6 Function Calls�� 545.e15
C.7 Control-Flow Statements�� 545.e16
C.7.1 Conditional Statements�� 545.e17
C.7.2 Loops�� 545.e19
C.8 More Data Types�� 545.e21
C.8.1 Pointers�� 545.e21
C.8.2 Arrays�� 545.e23
C.8.3 Characters�� 545.e27
C.8.4 Strings�� 545.e27
C.8.5 Structures�� 545.e29
C.8.6 typedef�� 545.e31
C.8.7 Dynamic Memory Allocation�� 545.e32
C.8.8 Linked Lists�� 545.e33
C.9 Standard Libraries�� 545.e35
C.9.1 stdio�� 545.e35
C.9.2 stdlib�� 545.e40
C.9.3 math�� 545.e42
C.9.4 string�� 545.e42
C.10 Compiler and Command Line Options�� 545.e43
C.10.1 Compiling Multiple C Source Files�� 545.e43
C.10.2 Compiler Options�� 545.e43
C.10.3 Command Line Arguments�� 545.e44
C.11 Common Mistakes�� 545.e44
Further Reading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547
Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549
Preface
This book is unique in its treatment in that it presents digital logic

design from the perspective of computer architecture, starting at
the beginning with 1’s and 0’s and leading through to the design of a
microprocessor.
We believe that building a microprocessor is a special rite of passage
for engineering and computer science students. The inner workings
of a processor seem almost magical to the uninitiated yet prove to be
straightforward when carefully explained. Digital design in and of itself
is a powerful and exciting subject. Assembly language programming
unveils the inner language spoken by the processor. Microarchitecture is
the link that brings it all together.
The first two versions of this increasingly popular text cover
the MIPS and ARM architectures. As one of the original Reduced
Instruction Set Computing architectures, MIPS is clean and excep-
tionally easy to understand and build. MIPS remains an important
architecture, as it has inspired many of the subsequent architectures,
including RISC-V. The ARM architecture has exploded in popu-
larity over the past several decades because of its efficiency and rich
ecosystem. More than 50 billion ARM processors have been shipped,
and more than 75% of humans on the planet use products with ARM
processors.
Over the past decade, RISC-V has emerged as an increasingly
important architecture, both pedagogically and commercially. As the
first widely used open-source computer architecture, RISC-V offers
the simplicity of MIPS with the flexibility and features of modern
processors.
Pedagogically, the learning objectives of the MIPS, ARM, and
RISC-V editions are identical. The RISC-V architecture has a number of
features, including extendibility and compressed instructions, that con-
tribute to its efficiency but add a small amount of complexity. The three
microarchitectures are also similar, with MIPS and RISC-V architectures
sharing many similarities. We expect to offer MIPS, ARM, and RISC-V
editions as long as the market demands.
xix
xx Preface
FEATURES
Side-by-Side Coverage of SystemVerilog and VHDL
Hardware description languages (HDLs) are at the center of modern
digital design practices. Unfortunately, designers are evenly split between
the two dominant languages, SystemVerilog and VHDL. This book
introduces HDLs in Chapter 4 as soon as combinational and sequential
logic design has been covered. HDLs are then used in Chapters 5 and
7 to design larger building blocks and entire processors. Nevertheless,
Chapter 4 can be skipped and the later chapters are still accessible for
courses that choose not to cover HDLs.
This book is unique in its side-by-side presentation of SystemVerilog
and VHDL, enabling the reader to learn the two languages. Chapter 4
describes principles that apply to both HDLs, and then provides language-
specific syntax and examples in adjacent columns. This side-by-side
treatment makes it easy for an instructor to choose either HDL and
for the reader to transition from one to the other, either in a class or in
professional practice.
RISC-V Architecture and Microarchitecture

Chapters 6 and 7 offer in-depth coverage of the RISC-V architecture and
microarchitecture. RISC-V is an ideal architecture because it is a real
architecture shipped in an increasing number of commercial products, yet
it is streamlined and easy to learn. Moreover, because of its popularity
in the commercial and hobbyist worlds, simulation and development
tools exist for the RISC-V architecture.
Real-World Perspectives
In addition to the real-world perspective in discussing the RISC-V
architecture, Chapter 6 illustrates the architecture of Intel x86 pro-
cessors to offer another perspective. Chapter 9 (available as an online
supplement) also describes peripherals in the context of SparkFun’s
RED-V RedBoard, a popular development board that centers on SiFive’s
Freedom E310 RISC-V processor. These real-world perspective chapters
show how the concepts in the chapters relate to the chips found in many
PCs and consumer electronics.
Accessible Overview of Advanced Microarchitecture

Chapter 7 includes an overview of modern high-performance micro
architectural features, including branch prediction, superscalar, and
out-of-order operation, multithreading, and multicore processors. The
Preface xxi
treatment is accessible to a student in a first course and shows how the

microarchitectures in the book can be extended to modern processors.
End-of-Chapter Exercises and Interview Questions

The best way to learn digital design is to do it. Each chapter ends with
numerous exercises to practice the material. The exercises are followed
by a set of interview questions that our industrial colleagues have asked
students who are applying for work in the field. These questions pro-
vide a helpful glimpse into the types of problems that job applicants will
typically encounter during the interview process. Exercise solutions are
available via the book’s companion and instructor websites.
ONLINE SUPPLEMENTS
Supplementary materials are available online at ddcabook.com or
the publisher’s website: https://www.elsevier.com/books-and-journals/
book-companion/9780128200643. These companion sites (accessible to all
readers) include the following:
▸ Links to video lectures
▸ Solutions to odd-numbered exercises
▸ Figures from the text in PDF and PPTX formats
▸ Links to professional-strength computer-aided design (CAD) tools
from Intel®
▸ Instructions on how to use PlatformIO (an extension of Visual
Studio Code) to compile, assemble, and simulate C and assembly
code for RISC-V processors
▸ Hardware description language (HDL) code for the RISC-V processor
▸ Intel’s Quartus helpful hints
▸ Lecture slides in PowerPoint (PPTX) format
▸ Sample course and laboratory materials
▸ List of errata
The instructor site (accessible to instructors who register at https://

inspectioncopy.elsevier.com) includes the following:
▸ Solutions to all exercises
▸ Laboratory solutions
EdX MOOC
This book also has a companion Massive Open Online Course (MOOC)
through EdX. The course includes video lectures, interactive practice
xxii Preface
problems, and interactive problem sets and labs. The MOOC is divided
into two parts: Digital Design (ENGR 85A) and Computer Architecture
(ENGR85B) offered by HarveyMuddX (on EdX, search for “Digital
Design HarveyMuddX” and “Computer Architecture HarveyMuddX”).
EdX does not charge for access to the videos but does charge for the inter-
active exercises and certificate. EdX offers discounts for students with
financial need.
HOW TO USE THE SOFTWARE TOOLS IN A COURSE

Intel’s Quartus Software
The Quartus software, either Web or Lite Edition, is a free version of
Intel’s professional-strength Quartus™ FPGA design tools. It allows
students to enter their digital designs in schematic or using either the
SystemVerilog or the VHDL hardware description language (HDL).
After entering the design, students can simulate their circuits using the
ModelSim™-Intel FPGA Edition or Starter Edition, which is available
with Intel’s Quartus software. Quartus also includes a built-in logic
synthesis tool that supports both SystemVerilog and VHDL.
The difference between the Web or Lite Edition and the Pro Edition
is that the Web or Lite Edition supports a subset of the most common
Altera FPGAs. The free versions of ModelSim degrade performance
for simulations with more than 10,000 lines of HDL, whereas the
professional version of ModelSim does not.
PlatformIO
PlatformIO, which is an extension of Visual Studio Code, serves as a soft-
ware development kit (SDK) for RISC-V. With the explosion of SDKs for
each new platform, PlatformIO has streamlined the process of program-
ming and using various processors by providing a unified interface for a
large number of platforms and devices. It is available as a free download
and can be used with SparkFun’s RED-V RedBoard, as described in the
labs provided on the companion website. PlatformIO provides access
to a commercial RISC-V compiler and allows students to write both C
and assembly programs, compile them, and then run and debug them on
SparkFun’s RED-V RedBoard (see Chapter 9 and the accompanying labs).
Venus RISC-V Assembly Simulator

The Venus Simulator (available at: https://www.kvakil.me/venus/) is a
web-based RISC-V assembly simulator. Programs are written (or copy/
pasted) in the Editor tab and then simulated and run in the Simulator
tab. Registers and memory contents can be viewed as the program runs.
Preface xxiii
LABS
The companion site includes links to a series of labs that cover topics
from digital design through computer architecture. The labs teach stu-
dents how to use the Quartus tools to enter, simulate, synthesize, and
implement their designs. The labs also include topics on C and assem-
bly language programming using PlatformIO and SparkFun’s RED-V
RedBoard.
After synthesis, students can implement their designs using the
Altera DE2, DE2-115, DE0, or other FPGA board. The labs are written
to target the DE2 or DE-115 boards. These powerful and competitively
priced boards are available from de2-115.terasic.com. The board con-
tains an FPGA that can be programmed to implement student designs.
We provide labs that describe how to implement a selection of designs
on the DE2-115 board using the Quartus software.
To run the labs, students will need to download and install
Intel’s Quartus Web or Lite Edition and Visual Studio Code with the
PlatformIO extension. Instructors may also choose to install the tools
on lab machines. The labs include instructions on how to implement the
projects on the DE2/DE2-115 board. The implementation step may be
skipped, but we have found it of great value. We have tested the labs on
Windows, but the tools are also available for Linux.
RVfpga
RISC-V FPGA, also referred to as RVfpga, is a free two-course sequence
that can be completed after learning the material in this book. The first
course shows how to target a commercial RISC-V core to an FPGA, pro-
gram it using RISC-V assembly or C, add peripherals to it, and analyze
and modify the core and memory system, including adding instructions
to the core. This course uses the open-source SweRVolf system-on-chip
(SoC) (https://github.com/chipsalliance/Cores-SweRVolf), which is based
on Western Digital’s open-source commercial SweRV EH1 core (https://
www.westerndigital.com/company/innovations/risc-v). The course also
shows how to use Verilator, an open-source HDL simulator, and Western
Digital’s Whisper, an open-source RISC-V instruction set simulator (ISS).
RVfpga-SoC, the second course, shows how to build an SoC based on
SweRVolf using building blocks such as the SweRV EH1 core, inter-
connect, and memories. The course then guides the user in loading and
running the Zephyr operating system on the RISC-V SoC. All neces-
sary software and system source code (Verilog/SystemVerilog files) are
free, and the courses may be completed in simulation, so no hardware
is required. RVfpga materials are freely available with registration from
the Imagination Technologies University Programme: https://university.
imgtec.com/rvfpga/.
xxiv Preface
BUGS
As all experienced programmers know, any program of significant com-
plexity undoubtedly contains bugs. So, too, do books. We have taken
great care to find and squash the bugs in this book. However, some
errors undoubtedly do remain. We will maintain a list of errata on the
book’s webpage.
Please send your bug reports to ddcabugs@gmail.com. The first
person to report a substantive bug with a fix that we use in a future
printing will be rewarded with a $1 bounty!
ACKNOWLEDGMENTS
We appreciate the hard work of Steve Merken, Nate McFadden, Ruby
Gammell, Andrae Akeh, Manikandan Chandrasekaran, and the rest of
the team at Morgan Kaufmann who made this book happen. We love
the art of Duane Bibby, whose cartoons enliven the chapters.
We thank Matthew Watkins, who contributed the section on
Heterogeneous Multiprocessors in Chapter 7, and Josh Brake, who
contributed to Chapter 9 on Embedded I/O Systems. We greatly appre-
ciate the work of Mateo Markovic and Geordie Ryder, who reviewed
the book and contributed to the exercise solutions. Numerous other
reviewers also substantially improved the book. They include Daniel
Chaver Martinez, Roy Kravitz, Zvonimir Bandic, Giuseppe Di Luna,
Steffen Paul, Ravi Mittal, Jennifer Winikus, Hesham Omran, Angel Solis,
Reiner Dizon, and Olof Kindgren. We also appreciate the students in our
courses at Harvey Mudd College and UNLV who have given us help-
ful feedback on drafts of this textbook. And last, but not least, we both
thank our families for their love and support.
About the Authors
Sarah L. Harris is an Associate Professor of Electrical and Computer

Engineering at the University of Nevada, Las Vegas. She received her
Ph.D. and M.S. in Electrical Engineering from Stanford University. Sarah
has also worked with Hewlett-Packard, the San Diego Supercomputer
Center, and NVIDIA. Sarah loves teaching, exploring and developing
new technologies, traveling, playing the guitar and various other instru-
ments, and spending time with her family. Her recent research includes
designing bio-inspired prosthetics and implementing machine-learning
algorithms in hardware.
David Harris is the Harvey S. Mudd Professor of Engineering Design

and Associate Department Chair at Harvey Mudd College. He received
his Ph.D. in electrical engineering from Stanford University and his
M.Eng. in electrical engineering and computer science from MIT. Before
attending Stanford, he worked at Intel as a logic and circuit designer on
the Itanium and Pentium II processors. Since then, he has consulted at
Broadcom, Sun Microsystems, Hewlett-Packard, Evans & Sutherland,
and other design companies. David’s passions include teaching, build-
ing chips and airplanes, and exploring the outdoors. When he is not at
work, he can usually be found hiking, flying, and spending time with
his family. David holds about a dozen patents and is the author of three
other textbooks on chip design, as well as seven guidebooks to the
Southern California mountains.
xxv
From Zero to One
1
1. 1 The Game Plan
1. 2 The Art of Managing
Complexity
1. 3 The Digital Abstraction
1. 4 Number Systems
1. 5 Logic Gates
1. 6 Beneath the Digital
1.1 THE GAME PLAN Abstraction
1. 7 CMOS Transistors*
Microprocessors have revolutionized our world during the past three
decades. A laptop computer today has far more capability than a 1. 8 Power Consumption*
room-sized mainframe of yesteryear. A luxury automobile contains 1. 9 Summary and a Look Ahead
about 100 microprocessors. Advances in microprocessors have made Exercises
cell phones and the Internet possible, have vastly improved medicine, Interview Questions
and have transformed how war is waged. Worldwide semiconductor
industry sales have grown from US $21 billion in 1985 to $400 billion
in 2020, and microprocessors are a major segment of these sales.
We believe that microprocessors are not only technically, economi- Application >”hello
cally, and socially important, but are also an intrinsically fascinating Software world!”
human invention. By the time you finish reading this book, you will Operating
know how to design and build your own microprocessor. The skills Systems
you learn along the way will prepare you to design many other digital
systems. Architecture
We assume that you have a basic familiarity with electricity, some
prior programming experience, and a genuine interest in understanding Micro-
what goes on under the hood of a computer. This book focuses on the architecture
design of digital systems, which operate on 1’s and 0’s. We begin with
Logic +
digital logic gates that accept 1’s and 0’s as inputs and produce 1’s and
0’s as outputs. We then explore how to combine logic gates into more
Digital
complicated modules, such as adders and memories. Then, we shift gears Circuits
to programming in assembly language, the native tongue of the micro-
processor. Finally, we put gates together to build a microprocessor that Analog +
Circuits −
runs these assembly language programs.
A great advantage of digital systems is that the building blocks are
quite simple: just 1’s and 0’s. They do not require grungy mathematics or Devices
a profound knowledge of physics. Instead, the designer’s challenge is to
combine these simple blocks into complicated systems. A microprocessor Physics
may be the first system that you build that is too complex to fit in your
Digital Design and Computer Architecture, RISC-V Edition. DOI: 10.1016/B978-0-12-820064-3.00001-5 1

Copyright © 2022 Elsevier Inc. All rights reserved.
2 CHAPTER ONE From Zero to One
head all at once. One of the major themes woven through this book is
how to manage complexity.
1.2 THE ART OF MANAGING COMPLEXITY

One of the characteristics that separates an engineer or computer scien-
tist from a layperson is a systematic approach to managing complexity.
Modern digital systems are built from millions or billions of transistors.
No human being could understand these systems by writing equations
describing the movement of electrons in each transistor and solving all
of the equations simultaneously. You will need to learn to manage com-
plexity to understand how to build a microprocessor without getting
mired in a morass of detail.
1 . 2 . 1 Abstraction
The critical technique for managing complexity is abstraction: hid-
ing details when they are not important. A system can be viewed from
many different levels of abstraction. For example, American politicians
abstract the world into cities, counties, states, and countries. A county
contains multiple cities and a state contains many counties. When a
politician is running for president, the politician is mostly interested in
Application >”hello how the state as a whole will vote rather than how each county votes, so
world!” Programs
Software the state is the most useful level of abstraction. On the other hand, the
Operating Device Census Bureau measures the population of every city, so the agency must
Systems Drivers consider the details of a lower level of abstraction.
Instructions Figure 1.1 illustrates levels of abstraction for an electronic computer
Architecture
Registers system, along with typical building blocks at each level. At the lowest
Micro- Datapaths
level of abstraction is the physics, the motion of electrons. The behav-
architecture Controllers ior of electrons is described by quantum mechanics and Maxwell’s
equations. Our system is constructed from electronic devices such as
+ Adders
Logic
Memories transistors (or vacuum tubes, once upon a time). These devices have
well-defined connection points called terminals and can be modeled by
Digital AND Gates
Circuits NOT Gates the relationship between voltage and current as measured at each termi-
nal. By abstracting to this device level, we can ignore the individual elec-
Analog + Amplifiers
Circuits − Filters trons. The next level of abstraction is analog circuits, in which devices
are assembled to create components such as amplifiers. Analog circuits
Transistors
Devices
Diodes
input and output a continuous range of voltages. Digital circuits, such as
logic gates, restrict the voltages to discrete ranges, which we will use to
Physics Electrons indicate 0 and 1. In logic design, we build more complex structures, such
as adders or memories, from digital circuits.
Figure 1.1 Levels of abstraction Microarchitecture links the logic and architecture levels of abstrac-
for an electronic computing tion. The architecture level of abstraction describes a computer from
system the programmer’s perspective. For example, the Intel x86 architecture
1.2 The Art of Managing Complexity 3
used by microprocessors in most personal computers (PCs) is defined

by a set of instructions and registers (memory for temporarily storing
variables) that the programmer is allowed to use. Microarchitecture
involves combining logic elements to execute the instructions defined
by the architecture. A particular architecture can be implemented by
one of many different microarchitectures with different price/perfor-
mance/power trade-offs. For example, the Intel Core i7, the Intel 80486,
and the AMD Athlon all implement the x86 architecture with different
microarchitectures.
Moving into the software realm, the operating system handles
low-level details, such as accessing a hard drive or managing memory.
Finally, the application software uses these facilities provided by the
operating system to solve a problem for the user. Thanks to the power of
abstraction, your grandmother can surf the Web without any regard for
the quantum vibrations of electrons or the organization of the memory
in her computer.
This book focuses on the levels of abstraction from digital circuits Each chapter in this book
through computer architecture. When you are working at one level of begins with an abstraction
abstraction, it is good to know something about the levels of abstraction icon indicating the focus of
immediately above and below where you are working. For example, a the chapter in deep blue, with
computer scientist cannot fully optimize code without understanding the secondary topics shown in
lighter shades of blue.
architecture for which the program is being written. A device engineer
cannot make wise trade-offs in transistor design without understanding
the circuits in which the transistors will be used. We hope that by the
time you finish reading this book, you can pick the level of abstraction
appropriate to solving your problem and evaluate the impact of your Ford launched the Model T
design choices on other levels of abstraction. with a bold manifesto:
I will build a motor car for

the great multitude. It will be
1 . 2 . 2 Discipline large enough for the family,
Discipline is the act of intentionally restricting your design choices so but small enough for the
individual to run and care
that you can work more productively at a higher level of abstraction.
for. It will be constructed of
Using interchangeable parts is a familiar application of discipline. One the best materials, by the best
of the famous early examples of interchangeable parts was in automo- men to be hired, after the
bile manufacturing. Although the modern gas-powered car dates back to simplest designs that modern
the German Benz Patent-Motorwagen of 1886, early cars were hand- engineering can devise. But
it will be so low in price that
crafted by skilled tradesmen, a time-consuming and expensive process.
no man making a good salary
Henry Ford made a key advance in 1908 by focusing on mass produc- will be unable to own one—
tion with interchangeable parts and moving assembly lines. and enjoy with his family the
The discipline of interchangeable parts revolutionized the indus- blessing of hours of pleasure
try. By limiting the components to a standardized set with well-defined in God’s great open spaces.
[My Life and Work, by
tolerances, cars could be assembled and repaired much faster and with
Samuel Crowther and Henry
less skill. The car builder no longer concerned himself with lower lev- Ford, 1922]
els of abstraction, such as fitting a door to a nonstandardized opening.
The Model T Ford became the most-produced car of its era, selling over
15 million units. Another example of discipline was Ford’s famous say-
ing: “Any customer can have a car painted any color that he wants so
long as it is black.”
In the context of this book, the digital discipline will be very import-
ant. Digital circuits use discrete voltages, whereas analog circuits use
continuous voltages. Therefore, digital circuits are a subset of analog cir-
Model T Ford Photo from cuits and in some sense must be capable of less than the broader class
https://commons.wikimedia. of analog circuits. However, digital circuits are much simpler to design.
org/wiki/File: TModel_
launch_Geelong.jpg. By limiting ourselves to digital circuits, we can easily combine compo-
nents into sophisticated systems that ultimately outperform those built
from analog components in many applications. For example, digital tele-
visions, compact disks (CDs), and cell phones are replacing their analog
predecessors.
1 . 2 . 3 The Three -Y’s

In addition to abstraction and discipline, designers use the three “-y’s” to
manage complexity: hierarchy, modularity, and regularity. These princi-
ples apply to both software and hardware systems.
▸ Hierarchy involves dividing a system into modules, then fur-
ther subdividing each of these modules until the pieces are easy to
understand.
▸ Modularity states that modules have well-defined functions and
interfaces so that they connect easily without unanticipated side
effects.
▸ Regularity seeks uniformity among modules. Common modules are
reused many times, reducing the number of distinct modules that
must be designed.
To illustrate these “-y’s,” we return to the example of automobile

manufacturing. A car was one of the most intricate objects in common
use in the early 20th century. Using the principle of hierarchy, we can
break the Model T Ford into components, such as the chassis, engine,
and seats. The engine, in turn, contained four cylinders, a carburetor, a
magneto, and a cooling system. The carburetor contained fuel and air
intakes, a choke and throttle, a needle valve, and so forth, as shown in
Figure 1.2. The fuel intake was made from a threaded elbow and a cou-
pling nut. Thus, the complex system is recursively broken down into
simple interchangeable components that can be mass produced.
Modularity teaches that each component should have a well-defined
function and interface. For example, the coupling nut has a function of
holding the fuel feed line to the intake elbow in a way that does not
1.3 The Digital Abstraction 5
Figure 1.2 Cutaway view of

Model T fuel system, showing fuel
supply on left and carburetor on
right. (https://en.wikipedia.org/
wiki/Ford_Model_T_engine#/
media/File:Pagé_1917_Model_T_
Ford_Car_Figure_14.png)
leak yet can be easily removed when the feed line needs replacement.
It is of a standardized diameter and thread pitch, tightened to a stan-
dardized torque by a standardized wrench. A car maker can buy the nut
from many different suppliers, as long as the correct size is specified.
Modularity dictates that there should be no side effects: the coupling nut
should not deform the elbow and should preferably be located where it
can be tightened or removed without taking off other equipment in the
engine.
Regularity teaches that interchangeable parts are a good idea. With
regularity, a leaking carburetor can be replaced by an identical part. The
carburetors can be efficiently built on an assembly line instead of being
painstakingly handcrafted.
We will return to these principles of hierarchy, modularity, and regu-
larity throughout the book.
1.3 THE DIGITAL ABSTRACTION

Most physical variables are continuous. For example, the voltage on a
wire, the frequency of an oscillation, or the position of a mass are all
continuous quantities. Digital systems, on the other hand, represent Charles Babbage, 1791–1871
information with discrete-valued variables—that is, variables with a Attended Cambridge University
finite number of distinct values. and married Georgiana
An early digital system using variables with ten discrete values was Whitmore in 1814. Invented
the Analytical Engine, the
Charles Babbage’s Analytical Engine. Babbage labored from 1834 to
world’s first mechanical
1871, designing and attempting to build this mechanical computer. The computer. Also invented the
Analytical Engine used gears with ten positions labeled 0 through 9, cowcatcher and the universal
much like a mechanical odometer in a car. Figure 1.3 shows a prototype postage rate. Interested in lock
of the Analytical Engine, in which each row processes one digit. Babbage picking, but abhorred street
musicians (image courtesy of
chose 25 rows of gears, so the machine has 25-digit precision.
Fourmilab Switzerland, www.
Unlike Babbage’s machine, most electronic computers use a binary fourmilab.ch).
(two-valued) representation in which a high voltage indicates a “1” and
Figure 1.3 Babbage’s Analytical

Engine, under construction at the
time of his death in 1871 (image
courtesy of Science Museum/
Science and Society Picture
Library)
a low voltage indicates a “0,” because it is easier to distinguish between

two voltages than ten.
The amount of information D in a discrete valued variable with N
distinct states is measured in units of bits as
D = log 2 N bits (1.1)

A binary variable conveys log22 = 1 bit of information. Indeed, the
word bit is short for binary digit. Each of Babbage’s gears carried log210 =
3.322 bits of information because it could be in one of 23.322 = 10 unique
positions. A continuous signal theoretically contains an infinite amount
of information because it can take on an infinite number of values. In
practice, noise and measurement error limit the information to only 10
to 16 bits for most continuous signals. If the measurement must be made
rapidly, the information content is lower (e.g., 8 bits).
This book focuses on digital circuits using binary variables: 1’s and
0’s. George Boole developed a system of logic operating on binary vari-
George Boole, 1815–1864
Born to working-class parents ables that is now known as Boolean logic. Each of Boole’s variables
and unable to afford a formal could be TRUE or FALSE. Electronic computers commonly use a pos-
education, Boole taught itive voltage to represent “1” and zero volts to represent “0.” In this
himself mathematics and book, we will use the terms “1,” “TRUE,” and “HIGH” synonymously.
joined the faculty of Queen’s
Similarly, we will use “0”, “FALSE,” and “LOW” interchangeably.
College in Ireland. He wrote
An Investigation of the Laws The beauty of the digital abstraction is that digital designers can
of Thought (1854), which focus on 1’s and 0’s, ignoring whether the Boolean variables are physically
introduced binary variables represented with specific voltages, rotating gears, or even hydraulic fluid
and the three fundamental logic levels. A computer programmer can work without needing to know the
operations: AND, OR, and intimate details of the computer hardware. On the other hand, under-
NOT (image courtesy of the
American Institute of Physics). standing the details of the hardware allows the programmer to optimize
the software better for that specific computer.
1.4 Number Systems 7
An individual bit doesn’t carry much information. In the next sec-

tion, we examine how groups of bits can be used to represent numbers.
In later chapters, we will also use groups of bits to represent letters and
programs.
1.4 NUMBER SYSTEMS

You are accustomed to working with decimal numbers. In digital sys-
tems consisting of 1’s and 0’s, binary or hexadecimal numbers are often
more convenient. This section introduces the various number systems
that will be used throughout the rest of the book.
1 . 4 . 1 Decimal Numbers
In elementary school, you learned to count and do arithmetic in
decimal. Just as you (probably) have ten fingers, there are ten decimal
digits: 0, 1, 2, …, 9. Decimal digits are joined together to form longer
decimal numbers. Each column of a decimal number has ten times the
weight of the previous column. From right to left, the column weights
are 1, 10, 100, 1000, and so on. Decimal numbers are referred to as
base 10. The base is indicated by a subscript after the number to pre-
vent confusion when working in more than one base. For example,
Figure 1.4 shows how the decimal number 974210 is written as the
sum of each of its digits multiplied by the weight of the correspond-
ing column.
An N-digit decimal number represents one of 10N possibilities: 0, 1,
2, 3, …, 10N − 1. This is called the range of the number. For example,
a three-digit decimal number represents one of 1000 possibilities in the
range of 0 to 999.
1 . 4 . 2 Binary Numbers
Bits represent one of two values, 0 or 1, and are joined together to form
binary numbers. Each column of a binary number has twice the weight
of the previous column, so binary numbers are base 2. In binary, the col-
umn weights (again, from right to left) are 1, 2, 4, 8, 16, 32, 64, 128,
1000's column
100's column
10's column
1's column
Figure 1.4 Representation of a

decimal number
974210 = 9 × 10 + 7 × 10 + 4 × 10 + 2 × 10
3 2 1 0
nine seven four two

thousands hundreds tens ones
256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536, and so on. If
you work with binary numbers often, you’ll save time if you remember
these powers of two up to 216.
An N-bit binary number represents one of 2N possibilities: 0, 1, 2,
3, …, 2N − 1. Table 1.1 shows 1-, 2-, 3-, and 4-bit binary numbers and
their decimal equivalents.
Example 1.1 BINARY TO DECIMAL CONVERSION
Convert the binary number 101102 to decimal.
Solution Figure 1.5 shows the conversion.
Table 1.1 Binary numbers and their decimal equivalent
1-Bit 2-Bit 3-Bit 4-Bit

Binary Binary Binary Binary Decimal
Numbers Numbers Numbers Numbers Equivalents
0 00 000 0000 0
1 01 001 0001 1
10 010 0010 2
11 011 0011 3
100 0100 4
101 0101 5
110 0110 6
111 0111 7
1000 8
1001 9
1010 10
1011 11
1100 12
1101 13
1110 14
1111 15
16's column
8's column
4's column
2's column
1's column
Figure 1.5 Conversion of a binary
number to decimal
10110 2 = 1 × 24 + 0 × 23 + 1 × 22 + 1 × 21+ 0 × 2 0 = 2210
one no one one no
sixteen eight four two one
Example 1.2 DECIMAL TO BINARY CONVERSION
Convert the decimal number 8410 to binary.
Solution Determine whether each column of the binary result has a 1 or a 0. We

can do this starting at either the left or the right column.
Working from the left, start with the largest power of 2 less than or equal to
the number (in this case, 64). 84 ≥ 64, so there is a 1 in the 64’s column, leaving
84 − 64 = 20. 20 < 32, so there is a 0 in the 32’s column. 20 ≥ 16, so there is a 1
in the 16’s column, leaving 20 − 16 = 4. 4 < 8, so there is a 0 in the 8’s column.
4 ≥ 4, so there is a 1 in the 4’s column, leaving 4 − 4 = 0. Thus, there must be 0 s
in the 2’s and 1’s column. Putting this all together, 8410 = 10101002.
Working from the right, repeatedly divide the number by 2. The remainder goes in
each column. 84/2 = 42, so 0 goes in the 1’s column. 42/2 = 21, so 0 goes in the
2’s column. 21/2 = 10 with the remainder of 1 going in the 4’s column. 10/2 = 5,
so 0 goes in the 8’s column. 5/2 = 2 with the remainder of 1 going in the 16’s
column. 2/2 = 1, so 0 goes in the 32’s column. Finally, 1/2 = 0 with the remain-
der of 1 going in the 64’s column. Again, 8410 = 10101002.
1 . 4 . 3 Hexadecimal Numbers
Hexadecimal, a term coined
Writing long binary numbers becomes tedious and prone to error. A group by IBM in 1963, derives from
of four bits represents one of 24 = 16 possibilities. Hence, it is sometimes the Greek hexi (six) and Latin
decem (ten). A more proper
more convenient to work in base 16, called hexadecimal. Hexadecimal term would use the Latin
numbers use the digits 0 to 9 along with the letters A to F, as shown in sexa (six), but sexadecimal
Table 1.2. Columns in base 16 have weights of 1, 16, 162 (or 256), 163 sounded too risqué.
(or 4096), and so on.
Example 1.3 HEXADECIMAL TO BINARY AND DECIMAL CONVERSION
Convert the hexadecimal number 2ED16 to binary and to decimal.
Solution Conversion between hexadecimal and binary is easy because each hexa-
decimal digit directly corresponds to four binary digits. 216 = 00102, E16 = 11102
and D16 = 11012, so 2ED16 = 0010111011012. Conversion to decimal requires
the arithmetic shown in Figure 1.6.
Table 1.2 Hexadecimal number system
Hexadecimal Digit Decimal Equivalent Binary Equivalent

0 0 0000
1 1 0001
2 2 0010
3 3 0011
4 4 0100
5 5 0101
6 6 0110
7 7 0111
8 8 1000
9 9 1001
A 10 1010
B 11 1011
C 12 1100
D 13 1101
E 14 1110
F 15 1111
256's column
16's column
1's column
Figure 1.6 Conversion of a

hexadecimal number to decimal
2ED 16 = 2 × 16 2 + E × 16 1 + D × 16 0 = 74910
two fourteen thirteen
two hundred sixteens ones
fifty six's
Example 1.4 BINARY TO HEXADECIMAL CONVERSION
Convert the binary number 11110102 to hexadecimal.
Solution Again, conversion is easy. Start reading from the right. The four least signifi
cant bits are 10102 = A16. The next bits are 1112 = 716. Hence, 11110102 = 7A16.
Example 1.5 DECIMAL TO HEXADECIMAL AND BINARY CONVERSION
Convert the decimal number 33310 to hexadecimal and binary.
Solution Like decimal to binary conversion, decimal to hexadecimal conversion

can be done from the left or the right.
Working from the left, start with the largest power of 16 less than or equal to
the number (in this case, 256). 256 goes into 333 once, so there is a 1 in the
256’s column, leaving 333 − 256 = 77. 16 goes into 77 four times, so there is a
4 in the 16’s column, leaving 77 − 16 × 4 = 13. 1310 = D16, so there is a D in the
1’s column. In summary, 33310 = 14D16. Now it is easy to convert from hexadec-
imal to binary, as in Example 1.3. 14D16 = 1010011012.
Working from the right, repeatedly divide the number by 16. The remainder
goes in each column. 333/16 = 20, with the remainder of 1310 = D16 going in the
1’s column. 20/16 = 1, with the remainder of 4 going in the 16’s column. 1/16 = 0,
with the remainder of 1 going in the 256’s column. Again, the result is 14D16.
1 . 4 . 4 Bytes, Nibbles, and All That Jazz

A group of eight bits is called a byte. It represents one of 28 = 256 pos-
sibilities. The size of objects stored in computer memories is customarily
measured in bytes rather than bits.
A group of four bits, or half a byte, is called a nibble. It represents
one of 24 = 16 possibilities. One hexadecimal digit stores one nibble and
two hexadecimal digits store one full byte. Nibbles are no longer a com-
monly used unit, but the term is cute.
Microprocessors handle data in chunks called words. The size A microprocessor is a
of a word depends on the architecture of the microprocessor. When processor built on a single
this chapter was written in 2021, most computers had 64-bit proces- chip. Until the 1970’s,
processors were too
sors, indicating that they operate on 64-bit words. At the time, older
complicated to fit on one
computers handling 32-bit words were also widely available. Simpler chip, so mainframe processors
microprocessors, especially those used in gadgets such as toasters, use were built from boards
8- or 16-bit words. containing many chips.
Within a group of bits, the bit in the 1’s column is called the Intel introduced the first
4-bit microprocessor, called
least significant bit (lsb), and the bit at the other end is called the
the 4004, in 1971. Now,
most significant bit (msb), as shown in Figure 1.7(a) for a 6-bit even the most sophisticated
binary number. Similarly, within a word, the bytes are identified as supercomputers are built
least significant byte (LSB) through most significant byte (MSB), as using microprocessors.
shown in Figure 1.7(b) for a 4-byte number written with eight hexa- We will use the terms
microprocessor and processor
decimal digits.
interchangeably throughout
By handy coincidence, 210 = 1024 ≈ 103. Hence, the term kilo this book.
(Greek for thousand) indicates 210. For example, 210 bytes is one
101100 DEAFDAD8
Figure 1.7 Least and most most least most least
significant bits and bytes significant significant significant significant
bit bit byte byte
(a) (b)
To distinguish between powers

kilobyte (1 KB). Similarly, mega (million) indicates 220 ≈ 106, and giga
of ten and powers of two, a (billion) indicates 230 ≈ 109. If you know 210 ≈ 1 thousand, 220 ≈ 1 mil-
naming convention specific to lion, 230 ≈ 1 billion, and remember the powers of two up to 29, it is easy
powers of two has emerged: 210 to estimate any power of two in your head.
is called a kibi (Ki), 220 mebi
(Mi), 230 gibi (Gi), 240 tebi (Ti),
250 pebi (Pi), 260 exbi (Ei), and
Example 1.6 ESTIMATING POWERS OF TWO
so on. For example, 230 bytes is
a gibibyte (GiB). Find the approximate value of 224 without using a calculator.
Solution Split the exponent into a multiple of ten and the remainder.
224 = 220 × 24. 220 ≈ 1 million. 24 = 16. So, 224 ≈ 16 million. Technically, 224 =
16,777,216, but 16 million is close enough for marketing purposes.
On-chip memory and RAM 1024 bytes is called a kilobyte (KB) or kibibyte (KiB). 1024 bits is
is measured in powers of two, called a kilobit (Kb or Kbit) or kibibit (Kib or Kibit). Similarly, MB / MiB,
but hard drives are measured Mb/Mib, GB/GiB, and Gb/Gib are used for millions and billions of bytes and
in powers of ten. For example,
32 GB (GiB) of RAM is
bits. Memory capacity is usually measured in bytes. Communication speed
actually 34,359,738,368 bytes is usually measured in powers of ten bits/second. For example, the maximum
of memory, whereas 32 GB speed of a dial-up modem is usually 56 kbits/sec, which is 56,000 bits/sec.
on a hard drive is 32,000,000
bytes of memory.
1 . 4 . 5 Binary Addition
Binary addition is much like decimal addition but easier, as shown in
Figure 1.8. As in decimal addition, if the sum of two numbers is greater
than what fits in a single digit, we carry a 1 into the next column. Figure
1.8 compares addition of decimal and binary numbers. In the rightmost
column of Figure 1.8(a), 7 + 9 = 16, which cannot fit in a single digit
because it is greater than 9. So, we record the 1’s digit, 6, and carry the
10’s digit, 1, over to the next column. Likewise, in binary, if the sum of
two numbers is greater than 1, we carry the 2’s digit over to the next
column. For example, in the rightmost column of Figure 1.8(b), the sum
11 carries 11
Figure 1.8 Addition examples 4277 1011
showing carries: (a) decimal + 5499 + 0011
(b) binary 9776 1110
(a) (b)
1 + 1 = 210 = 102 cannot fit in a single binary digit. So, we record the 1’s
digit (0) and carry the 2’s digit (1) of the result to the next column. In
the second column, the sum is 1 + 1 + 1 = 310 = 112. Again, we record
the 1’s digit (1) and carry the 2’s digit (1) to the next column. For obvi-
ous reasons, the bit that is carried over to the neighboring column is
called the carry bit.
Example 1.7 BINARY ADDITION 111

0111
Compute 01112 + 01012. + 0101
1100
Solution Figure 1.9 shows that the sum is 11002. The carries are indicated in
blue. We can check our work by repeating the computation in decimal. 01112 = Figure 1.9 Binary addition
710. 01012 = 510. The sum is 1210 = 11002. example
Digital systems usually operate on a fixed number of digits. Addition is said

to overflow if the result is too big to fit in the available digits. A 4-bit number,
for example, has the range [0, 15]. 4-bit binary addition overflows if the result
exceeds 15. The fifth bit of the sum is discarded, producing an incorrect result in
the remaining four bits. Overflow can be detected by checking for a carry out of
the most significant column.
Example 1.8 ADDITION WITH OVERFLOW
Compute 11012 + 01012. Does overflow occur? 11 1

1101
Solution Figure 1.10 shows that the sum is 100102. This result overflows the + 0101
range of a 4-bit binary number. If it must be stored as four bits, the most signif- 10010
icant bit is discarded, leaving the incorrect result of 00102. If the computation Figure 1.10 Binary addition
had been done using numbers with five or more bits, the result 100102 would example with overflow
have been correct.
1 . 4 . 6 Signed Binary Numbers

So far, we have considered only unsigned binary numbers that represent
positive quantities. We will often want to represent both positive and
negative numbers, requiring a different binary number system. Several
schemes exist to represent signed binary numbers. The two most widely
employed are called sign/magnitude and two’s complement.
Sign/Magnitude Numbers
Sign/magnitude numbers are intuitively appealing because they match
our custom of writing negative numbers with a minus sign followed
by the magnitude. An N-bit sign/magnitude number uses the most
The $7 billion Ariane 5 rocket, significant bit as the sign and the remaining N − 1 bits as the magnitude
launched on June 4, 1996, (absolute value). A sign bit of 0 indicates positive and a sign bit of 1
veered off course 40 seconds indicates negative.
after launch, broke up, and
exploded. The failure was
caused when the computer Example 1.9 SIGN/MAGNITUDE NUMBERS
controlling the rocket
overflowed its 16-bit range Write 5 and −5 as 4-bit sign/magnitude numbers.
and crashed.
Solution Both numbers have a magnitude of 510 = 1012. Thus, 510 = 01012 and
The code had been extensively
tested on the Ariane 4 rocket. −510 = 11012.
However, the Ariane 5 had a
faster engine that produced larger
values for the control computer, Unfortunately, ordinary binary addition does not work for sign/
leading to the overflow. magnitude numbers. For example, using ordinary addition on −510 + 510
gives 11012 + 01012 = 100102, which is nonsense.
An N-bit sign/magnitude number spans the range [−2N−1 + 1, 2N−1 − 1].
Sign/magnitude numbers are slightly odd in that both +0 and −0 exist.
Both indicate zero. As you may expect, it can be troublesome to have
two different representations for the same number.
Two’s Complement Numbers

Two’s complement numbers are identical to unsigned binary num-
bers except that the most significant bit position has a weight of −2N−1
instead of 2N−1. They overcome the shortcomings of sign/magnitude
numbers: zero has a single representation, and ordinary addition works.
In two’s complement representation, zero is written as all zeros:
00…0002. The most positive number has a 0 in the most significant
position and 1’s elsewhere: 01…1112 = 2N−1 − 1. The most negative
number has a 1 in the most significant position and 0’s elsewhere:
10…0002 = −2N−1. And −1 is written as all ones: 11…1112.
Notice that positive numbers have a 0 in the most significant posi-
Photograph courtesy of ESA/ tion and negative numbers have a 1 in this position, so the most signif-
CNES/ARIANESPACE- icant bit can be viewed as the sign bit. However, the overall number is
Service Optique CS6.
interpreted differently for two’s complement numbers and sign/magni-
tude numbers.
The result of inverting the The sign of a two’s complement number is reversed (e.g., from +5 to
bits in a number is called the −5 or from −17 to +17) by inverting the bits in the number and then
one’s complement of that adding 1 to the least significant bit position. This process is called the
number. For example, the
reversing the sign method. It is useful in finding the representation of a
one’s complement of 0110111
is 1001000. It is called the negative number or determining the magnitude of a negative number.
one’s complement because
when you add the numbers
together, you get all 1’s. For Example 1.10 T
WO’S COMPLEMENT REPRESENTATION
example, 0110111 + 1001000 OF A NEGATIVE NUMBER
= 1111111.
Find the representation of −210 as a 4-bit two’s complement number.
Solution Start by representing the magnitude: +210 = 00102. To get −210, reverse
The process of reversing the
the sign by inverting the bits and adding 1. Inverting 00102 produces 11012. sign has historically been
11012 + 1 = 11102. So, −210 is 11102. called “taking the two’s
complement.” However,
we have found that this
Example 1.11 VALUE OF NEGATIVE TWO’S COMPLEMENT NUMBERS terminology sometimes makes
people think that they always
Find the decimal value of the 4-bit two’s complement number 0x9 (i.e., 10012). have to “take the two’s
complement” when working
Solution 10012 has a leading 1, so it must be negative. To find its magnitude, with two’s complement
reverse the sign by inverting the bits and adding 1. Inverting 10012 = 01102. numbers, but that is not true!
01102 + 1 = 01112 = 710. Hence, 10012 = −710. This process of reversing the
sign is only sometimes used
when working with negative
Two’s complement numbers have the compelling advantage that two’s complement numbers.
addition works properly for both positive and negative numbers. Recall
that when adding N-bit numbers, the carry out of the Nth bit (i.e., the
N + 1th result bit) is discarded.
Example 1.12 ADDING TWO’S COMPLEMENT NUMBERS
Compute (a) −210 + 110 and (b) −710 + 710 using two’s complement numbers.
Solution (a) −210 + 110 = 11102 + 00012 = 11112 = −110. (b) −710 + 710 = 10012 +
01112 = 100002. The fifth bit is discarded, leaving the correct 4-bit result 00002.
Subtraction is performed by taking the two’s complement of the sec-

ond number, then adding.
Two’s complement numbers

Example 1.13 SUBTRACTING TWO’S COMPLEMENT NUMBERS earned their name from the
fact that creating the complement
Compute (a) 510 − 310 and (b) 310 − 510 using 4-bit two’s complement numbers.
(negative) of a number is found
Solution (a) 310 = 00112. Take its two’s complement to obtain −310 = 11012. by subtracting it from 2N
(referred to by its base: two’s)—
Now, add 510 + (−310) = 01012 + 11012 = 00102 = 210. Note that the carry out
thus, the two’s complement.
of the most significant position is discarded because the result is stored in four For example, to create the
bits. (b) Take the two’s complement of 510 to obtain −510 = 1011. Now, add 310 + 4-bit complement of 7 (i.e., −7),
(−510) = 00112 + 10112 = 11102 = −210. we perform: 24 − 7 = 10000 −
0111 = (1111 + 1) − 0111 =
(1111 − 0111) + 1 = 1000 +
1 = 1001. This is the 4-bit
The two’s complement of 0 is found by inverting all the bits two’s complement representation
(producing 11…1112) and adding 1, which produces all 0’s, disregarding of −7. Notice that the final
the carry out of the most significant bit position. Hence, zero is always step was the same as the
reversing the sign method,
represented with all 0’s. Unlike the sign/magnitude system, the two’s
that is, invert the bits of 0111
complement system has no separate −0. Zero is considered positive (to 1000) and add 1.
because its sign bit is 0.
Like unsigned numbers, N-bit two’s complement numbers represent

one of 2N possible values. However, the values are split between positive
and negative numbers. For example, a 4-bit unsigned number represents
16 values: 0 to 15. A 4-bit two’s complement number also represents
16 values: −8 to 7. In general, the range of an N-bit two’s complement
number spans [−2N−1, 2N−1 − 1]. It should make sense that there is one
more negative number than positive number because there is no −0. The
most negative number 10…0002 = −2N−1 is sometimes called the weird
number. Its two’s complement is found by inverting the bits (producing
01…1112) and adding 1, which produces 10…0002, the weird number,
again. Hence, this negative number has no positive counterpart.
Adding two N-bit positive numbers or negative numbers may cause
overflow if the result is greater than 2N−1 − 1 or less than −2N−1. Adding
a positive number to a negative number never causes overflow. Unlike
unsigned numbers, a carry out of the most significant column does not
indicate overflow. Instead, overflow occurs if the two numbers being
added have the same sign bit and the result has the opposite sign bit.
Example 1.14 A
DDING TWO’S COMPLEMENT NUMBERS
WITH OVERFLOW
Compute 410 + 510 using 4-bit two’s complement numbers. Does the result
overflow?
Solution 410 + 510 = 01002 + 01012 = 10012 = −710. The result overflows the
range of 4-bit positive two’s complement numbers, producing an incorrect neg-
ative result. If the computation had been done using five or more bits, the result
010012 = 910 would have been correct.
When a two’s complement number is extended to more bits, the sign

bit must be copied into the most significant bit positions. This process is
called sign extension. For example, the numbers 3 and −3 are written as
4-bit two’s complement numbers 0011 and 1101, respectively. They are
sign-extended to seven bits by copying the sign bit into the three new
upper bits to form 0000011 and 1111101, respectively, which are 7-bit
representations of 3 and –3.
Comparison of Number Systems

The three most commonly used binary number systems are unsigned,
two’s complement, and sign/magnitude. Table 1.3 compares the range
of N-bit numbers in each of these three systems. Two’s complement
numbers are convenient because they represent both positive and neg-
ative integers and because ordinary addition works for all numbers.
Subtraction is performed by negating the second number (i.e., reversing
1.5 Logic Gates 17
Table 1.3 Range of N-bit numbers
System Range
Unsigned [0, 2N – 1]
Two’s Complement [–2N–1, 2N–1 – 1]
Sign/Magnitude [–2N–1 + 1, 2N–1 – 1]
–8 –7 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Unsigned 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 Two's Complement
0000
1111 1110 1101 1100 1011 1010 1001
1000
0001 0010 0011 0100 0101 0110 0111 Sign / Magnitude
Figure 1.11 Number line and 4-bit binary encodings
the sign), and then adding. Unless stated otherwise, assume that all
signed binary numbers use two’s complement representation.
Figure 1.11 shows a number line indicating the values of 4-bit num-
bers in each system. Unsigned numbers span the range [0, 15] in reg-
ular binary order. Two’s complement numbers span the range [−8, 7].
The nonnegative numbers [0, 7] share the same encodings as unsigned
numbers. The negative numbers [−8, −1] are encoded such that a larger
unsigned binary value represents a number closer to 0. Notice that the
weird number, 1000, represents −8 and has no positive counterpart.
Sign/magnitude numbers span the range [−7, 7]. The most significant
bit is the sign bit. The positive numbers [1, 7] share the same encodings
as unsigned numbers. The negative numbers are symmetric but have the
sign bit set. 0 is represented by both 0000 and 1000. Thus, N-bit sign/
magnitude numbers represent only 2N − 1 integers because of the two
representations for 0. N-bit unsigned binary or two's complement num-
bers represent 2N integers.
1.5 LOGIC GATES

Now that we know how to use binary variables to represent information,
we explore digital systems that perform operations on these binary vari-
ables. Logic gates are simple digital circuits that take one or more binary
inputs and produce a binary output. Logic gates are drawn with a symbol
showing the input (or inputs) and the output. Inputs are usually drawn
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Bavaria.) Furthermore, this Conservative of high position would
prefer to see the King become Emperor of Prussia. (A matter of
taste.) Under the other arrangement Prussia will be lost in Germany,
and that arouses scruples in his mind. Löwinsohn also reported that
the Crown Prince is very indignant at certain correspondents who
compared Châteaudun to Pompeii, and drew lively pictures of the
devastation of the country owing to the war. I suggested to
Löwinsohn that he should deal with the subject of the new French
loan and that of “Chaudordy and Garibaldi’s ear-clippers” in the
Indépendance Belge, with which he is connected. He promised to do
this to-morrow.
An article for the Kölnische Zeitung on the new French loan was
accordingly despatched in the following form:—
“Yet another loan! With wicked unconcern the gentlemen who
now preside over the fortunes of France and who are plunging her
deeper and deeper into moral and material ruin, are also trying to
exploit foreign countries. This was to be anticipated for some time
past, and we are therefore not surprised at it. We would, however,
call the attention of the financial world to the very obvious dangers
accompanying the advantages which will be offered to them. We will
indicate there in a few words, in order to make the matter clear. High
interest and a low rate of issue may be very tempting. But, on the
other hand, the Government which makes this loan is recognised
neither by the whole of France nor by a single European Power.
Moreover, it should be remembered that we have already stated our
intention that measures would be taken to prevent the repayment of
certain loans which French municipalities tried to raise for the
purposes of the war. We imagine that is a sufficient hint that the
same principle might be applied on a larger scale. The French
Government which concludes peace with Prussia and her allies (and
that will presumably not be the present Government) will in all
probability be bound, among other conditions of peace, not to
recognise as binding the engagements for payment of interest and
redemption of loans made by MM. Gambetta and Favre. The
Government referred to will unquestionably have the right to do this,
as those gentlemen, although it is true they speak in the name of
France, have received no mission and no authority from the country.
People should therefore be on their guard.”
Wollmann came up to me after 10 o’clock, and said that the
deputation from the Reichstag had arrived. Their chairman, Simson,
was now with the Chief, who would doubtless inform him of the
King’s disinclination to receive them before all the Princes had sent
letters declaring their approval. These letters would go first to the
King of Bavaria, who would afterwards send them to our King. All the
Princes had already telegraphed their approval—only Lippe still
appeared to entertain scruples. Probably in consequence of this
postponement it will be necessary for a few members of the
deputation to fall ill.
Saturday, December 17th.—In the course of the forenoon I wrote
a second paragraph on the new French loan.
In the afternoon wrote another article on the ever-increasing
instances of French officers breaking their parole and absconding
from the places where they were interned, and returning to France to
take service against us again. Over fifty of these cases have
occurred up to the present. They include officers of all ranks, and
even three generals—namely, Ducrot, Cambriel, and Barral. After the
battle of Sedan we could have rendered the army that was shut up in
that fortress harmless by destroying it. Humanity, however, and faith
in their pledged word induced us to forgo that measure. The
capitulation was granted, and we were justified in considering that all
the officers had agreed to its terms and were prepared to fulfil the
conditions which it imposed. If that was not the case we ought to
have been informed of the fact. We should then have treated those
exceptions in an exceptional way, that is to say, not accorded to the
officers in question the same treatment that was granted to the
others. In other words, they would not have been allowed the liberty
which they have now abused in such a disgraceful manner. It is true
that the great majority of the captive officers have kept their word,
and one might therefore have dismissed the matter with a shrug of
the shoulders. But the affair assumes another aspect when the
French Provisional Government approves this breach of their
pledged word by reappointing such officers to the regiments that are
opposing us in the field. Has there been a single case in which one
of these deserters was refused readmission to the ranks of the
French army? Or have any French officers protested against the
readmission of such comrades into their corps? It is, therefore, not
the Government alone, but also the officers of France, who consider
this disgraceful conduct to be correct. The consequence, however,
will be that the German Governments will feel bound in duty to
consider whether the alleviation of their imprisonment hitherto
accorded to French officers is consistent with the interests of
Germany. And further, we must ask ourselves the question whether
we shall be justified in placing confidence in any of the promises of
the present French Government when it wants to treat with
Germany, without material guarantees and pledges.
We were joined at dinner by Herr Arnim-Krochlendorff, a brother-
in-law of the Chief, a gentleman of energetic aspect, and apparently
a little over fifty. The Minister was in very good humour, but the
conversation this time was not particularly interesting. It chiefly
turned upon the bombardment, and the attitude assumed towards
that question by a certain party at headquarters. Arnim related that
when Grävenitz spoke to the Crown Prince on the matter, the latter
exclaimed: “Impossible! nothing to be done; it would be to no
purpose,” and when Grävenitz ventured to argue the point, the
Prince declared: “Well, then, if you know better, do it! Bombard it
yourself!” To which Grävenitz replied: “Your Royal Highness, I can
only fire a feu de joie (ich kann nur Victoria schiessen).” The Chief
remarked: “That sounds very equivocal.” The Crown Prince told me
the same thing, viz., if I thought the bombardment would be
successful, I had better take over the command. I replied that I
should like to very much—for twenty-four hours, but not longer. He
then added in French, doubtless on account of the servants: “For I
do not understand anything about it, although I believe I know as
much as he does, for he has no great knowledge of these matters.”
Sunday, December 18th.—At 2 o’clock the Chief drove off to the
Prefecture for the purpose of introducing the deputation of the
Reichstag to the King. The Princes residing in Versailles were in
attendance upon his Majesty. After 2 o’clock the King, accompanied
by the Heir Apparent and Princes Charles and Adalbert, entered the
reception room where the other Princes, the Chancellor of the
Confederation, and the Generals grouped themselves around him.
Among those present were the Grand Dukes of Baden, Oldenburg
and Weimar, the Dukes of Coburg and Meiningen, the three
Hereditary Grand Dukes, Prince William of Würtemberg and a
number of other princely personages. Simson delivered his address
to the King, who answered very much in the sense that had been
anticipated. A dinner of eighty covers, which was given at 5 o’clock,
brought the ceremony to a close.
On our way back from the park Wollmann told me that the Chief
had recently written to the King requesting to be permitted to take
part in the councils of war. The answer, however, was that he had
always been called to join in councils of a political nature, as in 1866,
that a similar course would also be followed in future, and that he
ought to be satisfied with that. (This story is probably not quite
correct, for Wollmann is incapable of being absolutely accurate.)
Monday, December 19th.—I again wrote calling attention to the
international revolution which arrays its guerilla bands and heroes of
the barricades against us. The article was to the following effect. We
understood at first that we were only fighting with France, and that
was actually the case up to Sedan. After the 4th of September
another power rose up against us, namely the universal Republic, an
international association of cosmopolitan enthusiasts who dream of
the United States of Europe, &c.
In the afternoon I took a walk in the park, in the course of which I
twice met the Chief driving with Simson, the President of the
Reichstag. The Minister was invited to dine with the Crown Prince at
7 o’clock, but first joined our table for half an hour. He spoke of his
drive with Simson: “The last time he was here was after the July
Revolution in 1830. I thought he would be interested in the park and
the beautiful views, but he showed no sign of it. It would appear that
he has no feeling for landscape beauty. There are many people of
that kind. So far as I am aware, there are no Jewish landscape
painters, indeed no Jewish painters at all.” Some one mentioned the
names of Meyerheim and Bendemann. “Yes,” the Chief replied,
“Meyerheim; but Bendemann had only Jewish grandparents. There
are plenty of Jewish composers—Mendelssohn, Halevy—but
painters! It is true that the Jew paints, but only when he is not
obliged to earn his bread thereby.”
Abeken alluded to the sermon which Rogge preached yesterday
in the palace church, and said that he had made too much of the
Reichstag deputation. He then added some slighting remarks about
the Reichstag in general. The Chief replied: “I am not at all of that
opinion—not in the least. They have just voted us another hundred
millions, and in spite of their doctrinaire views they have adopted the
Versailles treaties, which must have cost many of them a hard
struggle. We ought to place that, at least, to their credit.”
Abeken then talked about the events at Ems which preceded the
outbreak of the war, and related that on one occasion, after a certain
despatch had been sent off, the King said, “Well, he” (Bismarck) “will
be satisfied with us now!” And Abeken added, “I believe you were.”
“Well,” replied the Chancellor, laughing, “you may easily be
mistaken. That is to say I was quite satisfied with you. But not quite
as much with our Most Gracious, or rather not at all. He ought to
have acted in a more dignified way—and more resolutely.” “I
remember,” he continued, “how I received the news at Varzin. I had
gone out, and on my return the first telegram had been delivered. As
I started on my journey I had to pass our pastor’s house at Wussow.
He was standing at his gate and saluted me. I said nothing, but
made a thrust in the air—thus” (as if he were making a thrust with a
sword). “He understood me, and I drove on.” The Minister then gave
some particulars of the wavering and hesitation that went on up to a
certain incident, which altered the complexion of things, and was
followed by the declaration of war. “I expected to find another
telegram in Berlin answering mine, but it had not arrived. In the
meantime I invited Moltke and Roon to dine with me that evening,
and to talk over the situation, which seemed to me to be growing
more and more unsatisfactory. Whilst we were dining, another long
telegram was brought in. As I read it to them—it must have been
about two hundred words—they were both actually terrified, and
Moltke’s whole being suddenly changed. He seemed to be quite old
and infirm. It looked as if our Most Gracious might knuckle under
after all. I asked him (Moltke) if, as things stood, we might hope to be
victorious. On his replying in the affirmative, I said, ‘Wait a minute!’
and seating myself at a small table I boiled down those two hundred
words to about twenty, but without otherwise altering or adding
anything. It was Abeken’s telegram, yet something different—shorter,
more determined, less dubious. I then handed it over to them, and
asked, ‘Well, how does that do now?’ ‘Yes,’ they said, ‘it will do in
that form.’ And Moltke immediately became quite young and fresh
again. He had got his war, his trade. And the thing really succeeded.
The French were fearfully angry at the condensed telegram as it
appeared in the newspapers, and a couple of days later they
declared war against us.”
The conversation then wandered back to Pomerania, and if I am
not mistaken to Varzin, where the Chief had, he said, taken much
interest in a Piedmontese who had remained behind after the great
French wars. This man had raised himself to a position of
consequence, and although originally a Catholic, had actually
become a vestryman. The Minister mentioned other people who had
settled and prospered in places where they had been accidentally
left behind. There were also Italians taken as prisoners of war to a
district in Further Pomerania, where they remained and founded
families whose marked features still distinguish them from their
neighbours.
The Minister did not return from the Crown Prince’s until past ten
o’clock, and we then heard that the Crown Prince was coming to
dine with us on the following evening.
Tuesday, December 20th.—On the instructions of the Chief I
wrote two articles for circulation in Germany.
The first was as follows: “We have already found it necessary on
several occasions to correct a misunderstanding or an intentional
garbling of the words addressed by King William to the French
people on the 11th of August last. We are now once more confronted
with the same attempt to falsify history, and to our surprise in a
publication by an otherwise respectable French historian. In a
pamphlet entitled La France et la Prusse devant l’Europe, M.
d’Haussonville puts forward an assertion which does little credit to
his love of truth, or let us say his scientific accuracy. The whole
pamphlet is shallow and superficial. It is full of exaggerations and
errors, and of assertions that have no more value than mere
baseless rumours. Of the gross blunders of the writer, who is
obviously blinded by patriotic passion, we will only mention that,
according to him, King William was on the throne during the Crimean
War. But apart from this and other mistakes, we have here only to
deal with his attempt to garble the proclamation issued to the French
in August last, which, it may be observed, was written in French as
well as in German, so that a misunderstanding would appear to be
out of the question. According to M. d’Haussonville the King said: ‘I
am only waging war against the Emperor and not at all against
France.’ (Je ne fais la guerre qu’à l’Empereur, et nullement à la
France.) As a matter of fact, however, the document in question
says: ‘The German nation, which desired and still desires to live in
peace with France, having been attacked at sea and on land by the
Emperor Napoleon, I have taken the command of the German
armies for the purpose of repelling this aggression. Owing to the
course taken by the military operations, I have been led to cross the
French frontier. I wage war against the soldiers and not against the
citizens of France.’ (L’Empereur Napoléon ayant attaqué par terre et
par mer la nation allemande, qui désirait et désire encore vivre en
paix avec le peuple français, j’ai pris le commandement des armées
allemandes pour repousser l’agression, et j’ai été amené par les
événements militaires à passer les frontières de la France. Je fais la
guerre aux soldats, et non aux citoyens français.) The next sentence
excludes all possibility of mistake as to the meaning of the foregoing
statement: ‘They (the French citizens) will accordingly continue to
enjoy complete security of person and property so long as they
themselves do not deprive me of the right to accord them my
protection by acts of hostility against the German troops.’ (Ceux-ci
continueront, par conséquent, à jouir d’une complète sécurité pour
leur personnes et leur biens, aussi longtemps qu’ils ne me priveront
eux-mêmes par des entreprises hostiles contre les troupes
allemandes du droit de leur accorder ma protection.) There is, in our
opinion, a very obvious difference between d’Haussonville’s
quotation and the original proclamation, and no obscurity can
possibly be discovered in the latter to excuse a mistake.”
The second item ran thus: “The Delegation from the Government
of National Defence, which is at present in Bordeaux, has satisfied
itself that further resistance to the German forces is useless, and it
would, with the approval even of M. Gambetta, be prepared to
conclude peace on the basis of the demands put forward by
Germany. It is understood, however, that General Trochu has
decided to continue the war. The Delegation entered into an
engagement from Tours with General Trochu not to negotiate for
peace without his consent. According to other reports General
Trochu has had provisions for several months stored in the fortress
of Mont Valérien, so that he may fall back upon that position after
Paris has had to capitulate with a sufficient force to exercise
influence upon the fate of France after the conclusion of peace. His
object, it is believed, is to promote the interests of the Orleans family,
of which General Trochu is understood to be an adherent.”
On my taking these paragraphs into the office to have them sent
off, Keudell told me the Chief had agreed that henceforth all State
papers received and despatched should be shown to me if I asked
for them.
The Crown Prince and his aide-de-camp arrived shortly after six
o’clock. The former had on his shoulder straps the badges of his new
military rank as field-marshal. He sat at the head of the table, with
the Chief on his right and Abeken on his left. After the soup the
conversation first turned on the subject which I had this morning
worked up for the press, namely, that according to a communication
from Israel, the secretary of Laurier, who acts as agent for the
Provisional Government in London, Gambetta no longer believed in
the possibility of successful resistance, and was disposed to
conclude peace on the basis of our demands. Trochu was the only
member of the Government who wished to continue the struggle, but
on his undertaking the defence of Paris, the others had bound
themselves to act in concert with him in this respect.
The Chancellor observed: “He is understood to have had Mont
Valérien provisioned for two months, so that he may fall back upon
that position with the regular troops when it becomes necessary to
surrender the city—probably in order to influence the conclusion of
peace.” He then continued: “Indeed, I believe that France will break
up into several pieces—the country is already split up into parties.
There are great differences of opinion between the different districts.
Legitimists in Brittany, Red Republicans in the south, and Moderate
Republicans elsewhere, while the regular army is still for the
Emperor, or at least the majority of the officers are. It is possible that
each section will follow its own convictions, one being Republican,
another Bourbon, and a third Orleanist, according to the party that
happens to have the most adherents, and then Napoleon’s people—
tetrarchies of Judea, Galilee, &c.”
The Crown Prince said it was believed that Paris must have a
subterranean communication with the outer world. The Chief thought
so too, and added: “But they cannot get provisions in that way,
although, of course, they can receive news. I have been thinking
whether it might not be possible to flood the catacombs from the
Seine, and thus inundate the lower parts of the city. Of course the
catacombs go under the Seine.”
The Chief then said that if Paris could be taken now it would
produce a good effect upon public opinion in Bavaria, whence the
reports were again unsatisfactory. Bray was not to be trusted, had
not the interests of Germany at heart, inclined to the Ultramontanes,
had a Neapolitan wife, felt happiest in his memories of Vienna,
where he lived for a long time, and seemed disposed to tack about
again. “The King is, after all, the best of them all in the upper circles,”
said the Chancellor, “but he seems to be in bad health and eccentric,
and nobody knows what may yet happen.” “Yes, indeed,” said the
Crown Prince. “How bright and handsome he was formerly—a little
too slight, but otherwise the very ideal of a young man. Now his
complexion is yellow, and he looks old. I was quite shocked when I
saw him.” “The last time I saw him,” said the Chancellor, “was at his
mother’s at Nymphenburg, in 1863, when the Congress of Princes
was being held. Even at that time he had a strange look in his eyes. I
remember that, when dining, he on one occasion drank no wine, and
on another took eight or ten glasses—not at intervals, but hastily,
one glass after another, at one draught, so that the servant scarcely
liked to keep on filling his glass.”
The conversation then turned on the Bavarian Prince Charles,
who was said to be strongly anti-Prussian, but too old and feeble to
be very dangerous to the cause of German unity. Some one
remarked: “Nature has very little to do with him as it is.” “That
reminds me of old Count Adlerberg,” said the Minister, “who was also
mostly artificial—hair, teeth, calves, and one eye. When he wanted
to get up in the morning all his best parts lay on chairs and tables
near the bed. You remember the newly-married man in the Fliegende
Blätter who watched his bride take herself to pieces, lay her hair on
the toilet table, her teeth on the chimney-piece, and other fragments
elsewhere, and then exclaimed, ‘But what remains for me?’”
Moreover, Adlerberg, he went on to say, was a terrible bore, and it
was owing to him that Countess Bismarck once fainted at a
diplomatic dinner where she was seated between him and Stieglitz.
“She always faints when she is exceptionally bored, and for that
reason I never take her with me to diplomatic dinners.” “That is a
pretty compliment for the diplomats,” observed the Crown Prince.
The Chief then related that one evening, not long ago, the sentry
on guard at the Crown Prince’s quarters did not want to let him go in,
and only agreed to do so on his addressing him in Polish. “A few
days ago I also tried to talk Polish with the soldiers in the hospital,
and they brightened up wonderfully on hearing a gentleman speak
their mother tongue. It is a pity that my vocabulary was exhausted. It
would, perhaps, be a good thing if their commander-in-chief could
speak to them.” “There you are, Bismarck, coming back to the old
story,” said the Crown Prince, smiling. “No, I don’t like Polish and I
won’t learn it. I do not like the people.” “But, your Royal Highness,
they are, after all, good soldiers and honest fellows when they have
been taught to wash themselves and not to pilfer.” The Crown
Prince: “Yes, but when they cast off the soldier’s tunic they are just
what they were before, and at bottom they are and still remain
hostile to us.” The Chief: “As to their hostility, that only applies to the
nobles and their labourers, and all that class. A noble, who has
nothing himself, feeds a crowd of people, servants of all sorts, who
also belong to the minor nobility, although they act as his domestics,
overseers, and clerks. These stand by him when he rises in
rebellion, and also the Komorniks, or day labourers.... The
independent peasantry does not join them, however, even when
egged on by the priests, who are always against us. We have seen
that in Posen, when the Polish regiments had to be removed merely
because they were too cruel to their own fellow countrymen.... I
remember at our place in Pomerania there was a market, attended,
on one occasion, by a number of Kassubes (Pomeranian Poles). A
quarrel broke out between one of them and a German, who refused
to sell him a cow because he was a Pole. The Kassube was mortally
offended, and shouted out: ‘You say I’m a Polack. No, I’m just as
much a Prussack as yourself;’ and then, as other Germans and
Poles joined in, it soon developed into a beautiful free fight.”
The Chief then added that the Great Elector spoke Polish as well
as German, and that his successors also understood that language.
Frederick the Great was the first who did not learn it, but then he
also spoke better French than German. “That may be,” said the
Crown Prince, “but I am not going to learn Polish. I do not like it.
They must learn German.” With this remark the subject was allowed
to drop.
At dessert the Crown Prince, after asking if he might smoke a
pipe, pulled out a short one with a porcelain bowl, on which an eagle
was painted, while the rest of us lit our cigars.
After dinner the Crown Prince and the Minister retired with the
Councillors to the drawing-room, where they took coffee. Later on we
were all sent for, and formally presented to the future Emperor by the
Chief. We had to wait for about a quarter of an hour while the
Chancellor was deep in conversation with the Crown Prince. His
august guest stood in the corner near one of the windows. The Chief
spoke to him in a low tone, with his eyes mostly cast down, while the
Crown Prince listened with a serious and almost sullen look.
After the presentation I returned to the bureau, where I read the
diplomatic reports and drafts of the last few days, amongst others
the draft of the King’s reply to the Reichstag deputation. This had
been prepared by Abeken, and greatly altered by the Chief. Then an
instruction from the Minister to the Foreign Office to the effect that if
the Provinzial-Correspondenz should again contain a commendation
of Gambetta’s energy or anything of that kind, every possible means
should be immediately employed to prevent the publication. Also a
report from Prince Reuss to the effect that Gortschakoff had replied
in a negative sense to a sentimental communication of Gabriac’s,
adding that all the Russian Cabinet could do for the French at
present was to act as letter-carrier in conveying their wishes to the
Prussian Government.
At tea Hatzfeldt told me he had been trying to decipher a Dutch
report from Van Zuylen, which had been brought out with
Washburne’s mail, and had succeeded, though there were still a few
doubtful points. He then showed it to me, and together we contrived
to puzzle out some more of it. The despatch seems to be based
throughout on good information, and to give a faithful account of the
situation.
At 10.30 p.m. summoned to the Chief, who wants the Moniteur to
mention Gambetta’s inclination to forgo further resistance and
Trochu’s plan respecting Mont Valérien.
Wednesday, December 21st.—At dinner the Chief spoke of his
great-grandfather, who, if I rightly understood him, fell at Czaslau.
“The old people at our place often described him to my father. He
was a mighty hunter before the Lord, and a great toper. Once in a
single year he shot 154 red deer, a feat which Prince Frederick
Charles will scarcely emulate, although the Duke of Dessau might. I
remember being told that when he was stationed at Gollnow, the
officers messed together, the Colonel presiding over the kitchen. It
was the custom there for five or six dragoons to march in and fire a
volley from their carbines at each toast. Altogether they had very
curious customs. For instance, instead of a plank bed they had as a
punishment a so-called wooden donkey with sharp edges, upon
which the men who had been guilty of any breach of discipline were
obliged to sit, often for a couple of hours—a very painful punishment.
On the birthday of the Colonel or of other officers, the soldiers
always carried this donkey to the bridge and threw it into the river.
But a new one was invariably provided. The Burgomaster’s wife told
my father that it must have been renewed a hundred times. I have a
portrait of this great-grandfather in Berlin. I am the very image of
him, that is to say, I was when I was young—when I saw myself in
the looking-glass.”
The Minister then related that it was owing to a relative of his,
Finanzrath Kerl, that he was sent to Göttingen University. He was
consigned to Professor Hausmann, and was to study mineralogy.
“They were thinking, no doubt, of Leopold von Buch, and fancied it
would be fine for me to go through the world like him, hammer in
hand, chipping pieces off the rocks. Things, however, turned out
differently. It would have been better if I had been sent to Bonn,
where I should have met countrymen of my own. At Göttingen I had
no one from my own part of the country, and so I met none of my
University acquaintances again until I saw a few of them in the
Reichstag.”
Abeken said that after a brisk fire from the forts this morning
there had been a sortie of the Paris garrison, which was principally
directed against the positions occupied by the Guards. It was,
however, scarcely more than an artillery engagement, as the attack
was known beforehand and preparations had been made to meet it.
Hatzfeldt said he should like to know how they were able to discover
that a sortie was going to take place. It was suggested that in the
open country movements of transport and guns could not escape
detection, as large masses of troops could not be concentrated on
the point of attack in one night. “That was quite true,” observed the
Chief, with a laugh; “but often a hundred louis d’ors also form an
important part of this military prescience.”
After dinner I read drafts and despatches, from which I
ascertained, amongst other things, that as early as the 1st of
September, Prussia had intimated in St. Petersburg that she would
put no difficulties in the way of such action in the matter of the Black
Sea as has now been taken.
Later on I arranged that Löwinsohn should deal with the
Gambetta-Trochu question in the Indépendance Belge. Also
informed him that Delbrück would be here again on the 28th inst.
Thursday, December 22nd.—This time there were no strangers
at dinner. The Chief was in excellent spirits, but the conversation
was of no special importance.
A reference was made to yesterday’s sortie, and the Chief
remarked: “The French came out yesterday with three divisions, and
we had only fifteen companies, not even four battalions, and yet we
made nearly a thousand prisoners. The Parisians with their attacks,
now here and now there, remind me of a French dancing master
conducting a quadrille.
“Ma commère, quand je danse
Mon cotillon, va-t-il bien?
Il va de ci, il va de là,
Comme la queue de notre chat.”
Later on the Chief remarked: “Our august master is not at all

pleased at the idea of Antonelli at length deciding to come here. He
is uneasy about it. I am not.” Abeken said: “The newspapers express
very different opinions about Antonelli. At one time he is described
as a man of great intelligence and acumen; then again as a sly
intriguer, and shortly afterwards as a stupid fellow and a blockhead.”
The Chief replied: “It is not in the press alone that you meet with
such contradictions. It is the same with many diplomats. Goltz and
our Harry (von Arnim). We will leave Goltz out of the question—that
was different. But Harry—to-day this way and to-morrow that! When I
used to read a number of his reports together at Varzin, I found his
opinion of people change entirely a couple of times every week,
according as he had met with a friendly or unfriendly reception. As a
matter of fact, he sent different opinions by every post, and often by
the same post.”
Afterwards read reports from Rome, London, and Constantinople,
and the replies sent to them. According to Arnim’s despatch,
Monsignor Franchi informed him that the Pope and Antonelli wished
to send a mission to Versailles to congratulate the King on his
accession to the imperial dignity, and at the same time to induce the
French clergy to promote the liberation of the country from
Gambetta, and the negotiation of peace with us on the basis of a
cession of territory. In certain circumstances Antonelli himself would
undertake the task, in which the Archbishop of Tours had failed, of
securing an acceptable peace. In reply to this communication Arnim
was informed that it was still uncertain whether Bavaria would agree
to the scheme of Emperor and Empire. We should, nevertheless,
carry it through. But, in that case, its chief support having been found
in public opinion, the (mainly Ultramontane) elements of resistance
would be in still more marked opposition to the new Germany.
Bernstorff reports that the former Imperial Minister, Duvernois, had
called upon him at Eugénie’s instance and suggested a cession of
territory to us equal in extent to that acquired by the Empire in Nice
and Savoy. The Empress wished to issue a proclamation. Persigny
was of a different opinion, as he considered the Empress to be
impossible. Bonnechose, the Archbishop of Rouen, expressed a
similar opinion to Manteuffel. The reply sent to Bernstorff was that
we could not negotiate with the Empress (who, moreover, does not
appear to be reliable or politically capable), unless Persigny was in
agreement with her, and that Duvernois’ overture was unpractical.
Aali Pasha is prepared to agree to the abolition of the neutrality of
the Black Sea, but demands in compensation the full sovereignty of
the Porte over the Bosphorus and the Dardanelles. This was
telegraphed by us to St. Petersburg, and there agreed to; whereupon
Brunnow (the Russian Ambassador in London) received the
necessary instructions in the matter.
Friday, December 23rd.—It was mentioned at dinner that General
von Voigts-Rhetz was outside Tours, the inhabitants having offered
so much resistance that it was found necessary to shell the town.
The Chief added, “He ought not to have stopped firing when they
hoisted the white flag. I would have continued to shell them until they
sent out four hundred hostages.” He again condemned the leniency
of the officers towards civilians who offer resistance. Even notorious
treachery was scarcely punished as it ought to be, and so the French
imagined that they could do what they liked against us. “Here is, for
instance, this Colonel Krohn,” he continued. “He first has a lawyer
tried for aiding and abetting franctireurs, and then, when he sees him
condemned, he sends in first one and then another petition for
mercy, instead of letting the man be shot, and finally despatches the
wife to me with a safe conduct. Yet he is generally supposed to be
an energetic officer and a strict disciplinarian, but he can hardly be
quite right in his head.”
From the discussion of this foolish leniency the conversation
turned on General von Unger, Chief of the Staff to the 7th Army
Corps, who had gone out of his mind, and had to be sent home. He
is, it seems, generally moody and silent, but occasionally breaks out
into loud weeping. “Yes,” sighed the Chief, “officers in that position
are terribly harassed. Constantly at work, always responsible, and
yet unable to get things done, and hampered by intrigue. Almost as
bad as a Minister. I know that sort of crying myself. It is over-
excitement of the nerves, hysterical weeping. I, too, had it at
Nikolsburg, and badly. A Minister is just as badly treated—all sorts of
worries—an incessant plague of midges. Other things can be borne,
but one must be properly treated. I cannot endure shabby treatment.
If I were not treated with courtesy, I should be inclined to throw my
riband of the Black Eagle into the dustbin.”
The Versailles Moniteur having been mentioned, the Chief
observed: “Last week they published a novel by Heyse, the scene of
which is laid in Meran. Such sentimental twaddle is quite out of place
in a paper published at the cost of the King, which after all this one
is. The Versailles people do not want that either. They look for
political news and military intelligence from France, from England, or,
if you like, from Italy, but not such namby-pamby trash. I have also a
touch of poetry in my nature, but the first few sentences of that stuff
were enough for me.” Abeken, at whose instance the novel was
published, stood up for the editor, and said the story had been taken
from the Revue des Deux Mondes, an admittedly high-class
periodical. The Chief, however, stuck to his own opinion. Somebody
remarked that the Moniteur was now written in better French. “It may
be,” said the Minister, “but that is a minor point. However, we are
Germans, and as such we always ask ourselves, even in the most
exalted regions, if we please our neighbours and if what we do is to
their satisfaction. If they do not understand, let them learn German. It
is a matter of indifference whether a proclamation is written in a good
French style or not, so long as it is otherwise adequate and
intelligible. Moreover, we cannot expect to be masters of a foreign
language. A person who has only used it occasionally for some two
and a half years cannot possibly express himself as well as one who
has used it for fifty-four years.” Steinmetz’s proclamation then
received some ironical praise, and a couple of extraordinary
expressions were quoted from it. Lehndorff said: “It was not first-
class French, but it was, at any rate, intelligible.” The Chief: “Yes, it is
their business to understand it. If they cannot, let them find some
one to translate it for them. Those people who fancy themselves
merely because they speak good French are of no use to us. But
that is our misfortune. Whoever cannot speak decent German is a
made man, especially if he can murder English. Old —— (I
understood: Meyendorff) once said to me: ‘Don’t trust any
Englishman who speaks French with a correct accent.’ I have
generally found that true. But I must make an exception in favour of
Odo Russell.”
The name of Napoleon III. then came up. The Chief regarded him
as a man of limited intelligence. “He is much more good-natured and
much less acute than is usually believed.” “Why,” interrupted
Lehndorff, “that is just what some one said of Napoleon I.: ‘a good
honest fellow, but a fool.’” “But seriously,” continued the Chief,
“whatever one may think of the coup d’état he is really good-natured,
sensitive, even sentimental, while his intellect is not brilliant and his
knowledge limited. He is a specially poor hand at geography,
although he was educated in Germany, even going to school there,
—and he entertains all sorts of visionary ideas. In July last he spent
three days shilly-shallying without being able to come to a decision,
and even now he does not know what he wants. People would not
believe me when I told them so a long time ago. Already in 1854–55
I told the King, Napoleon has no notion of what we are. When I
became Minister I had a conversation with him in Paris. He believed
there would certainly be a rising in Berlin before long and a
revolution all over the country, and in a plebiscite the King would
have the whole people against him. I told him then that our people
do not throw up barricades, and that revolutions in Prussia are only
made by the Kings. If the King could only bear the strain for three or
four years he would carry his point. Of course the alienation of public
sympathy was unpleasant and inconvenient. But if the King did not
grow tired and leave me in the lurch I should not fail. If an appeal
were made to the population, and a plebiscite were taken, nine-
tenths of them would vote for the King. At that time the Emperor said
of me: ‘Ce n’est pas un homme sérieux.’ Of course I did not remind
him of that in the weaver’s house at Donchery.”
Somebody then mentioned that letters to Favre began “Monsieur
le Ministre,” whereupon the Chief said: “The next time I write to him I
shall begin Hochwohlgeborner Herr!” This led to a Byzantine
discussion of titles and forms of address, Excellenz,
Hochwohlgeboren, and Wohlgeboren. The Chancellor entertained
decidedly anti-Byzantine views. “All that should be dropped,” he said.
“I do not use those expressions any longer in private letters, and
officially I address councillors down to the third class as
Hochwohlgeboren.”
Abeken, a Byzantine of the purest water, declared that diplomats
had already resented the occasional omission of portions of their
titles, and that only councillors of the second class were entitled to
Hochwohlgeboren. “Well,” said the Chief, “I want to see all that kind
of thing done away with as far as we are concerned. In that way we
waste an ocean of ink in the course of the year, and the taxpayer has
good reason to complain of extravagance. I am quite satisfied to be
addressed simply as ‘Minister President Count von Bismarck.’”
Saturday, December 24.—Bucher told us at lunch he had heard
from Berlin that the Queen and the Crown Princess had become
very unpopular, owing to their intervention on behalf of Paris; and

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Digital Design and Computer

Architecture: RISC-V Edition Sarah

Digital design and computer architecture. ARM Edition

CISSP Practice Exams, Fourth Edition Shon Harris -

Engineering Ethics: Concepts and Cases 6 ed. Edition

Quantitative Chemical Analysis 9th Edition by Daniel C.

CISSP All-in-One Exam Guide 7th edition Edition Harris

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(eBook PDF) Computer Organization & Architecture:

Table B.1 RV32I: RISC-V integer instructions

Table B.3 RVF/D: RISC-V single- and double-precision floating-point instructions

AMSTERDAM • BOSTON • HEIDELBERG • LONDON

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Copyright © 2022 Elsevier Inc. All rights reserved.

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For Information on all Morgan Kaufmann publications visit our website at

Publisher: Katey Birtcher

Chapter 1 From Zero to One. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.6.4 DC Transfer Characteristics������������������������� 22

Chapter 3 Sequential Logic Design. . . . . . . . . . . . . . . . . . . . . . . . . . 107

Chapter 4 Hardware Description Languages. . . . . . . . . . . . . . . . . . 171

Chapter 5 Digital Building Blocks������������������������������ 237

5.2.3 Comparators������������������������������������� 245

Chapter 6 Architecture���������������������������������������� 299

6.4 Machine Language��������������������������������������� 332

Chapter 7 Microarchitecture���������������������������������� 393

7.2 Performance Analysis������������������������������������� 397

8.4 Virtual Memory������������������������������������������ 519

A.3 Programmable Logic����������������������������������� 543.e2

Appendix B RISC-V Instruction Set Summary������������������ 544

Appendix C C Programming����������������������������������� 545

Appendix C is available as an online supplement������������� 545.e1

C.4 Variables���������������������������������������������� 545.e7

Further Reading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547

This book is unique in its treatment in that it presents digital logic

RISC-V Architecture and Microarchitecture

Accessible Overview of Advanced Microarchitecture

treatment is accessible to a student in a first course and shows how the

End-of-Chapter Exercises and Interview Questions

The instructor site (accessible to instructors who register at https://

HOW TO USE THE SOFTWARE TOOLS IN A COURSE

Venus RISC-V Assembly Simulator

Sarah L. Harris is an Associate Professor of Electrical and Computer

David Harris is the Harvey S. Mudd Professor of Engineering Design

Digital Design and Computer Architecture, RISC-V Edition. DOI: 10.1016/B978-0-12-820064-3.00001-5 1

1.2 THE ART OF MANAGING COMPLEXITY

used by microprocessors in most personal computers (PCs) is defined

I will build a motor car for

1 . 2 . 3 The Three -Y’s

To illustrate these “-y’s,” we return to the example of automobile

Figure 1.2 Cutaway view of

1.3 THE DIGITAL ABSTRACTION

Figure 1.3 Babbage’s Analytical

a low voltage indicates a “0,” because it is easier to distinguish between

D = log 2 N bits (1.1)

An individual bit doesn’t carry much information. In the next sec-

1.6.4 DC Transfer Characteristics�� 22

Chapter 5 Digital Building Blocks�� 237

5.2.3 Comparators�� 245

Chapter 6 Architecture�� 299

6.4 Machine Language�� 332

Chapter 7 Microarchitecture�� 393

7.2 Performance Analysis�� 397

8.4 Virtual Memory�� 519

A.3 Programmable Logic�� 543.e2

Appendix B RISC-V Instruction Set Summary�� 544

Appendix C C Programming�� 545

Appendix C is available as an online supplement�� 545.e1

C.4 Variables�� 545.e7

1.2 THE ART OF MANAGING COMPLEXITY

1 . 2 . 3 The Three -Y’s

1.3 THE DIGITAL ABSTRACTION

1.4 NUMBER SYSTEMS

1 . 4 . 4 Bytes, Nibbles, and All That Jazz

1 . 4 . 6 Signed Binary Numbers

1.5 LOGIC GATES