Enhancing Real-Time Clock with an

Ultra-Low-Power Crystal Oscillator

1 Dr. C. Padmini 2 B. Sathwika 3 V. Aakash Chandra
Dept. of ECE Dept. of ECE Dept. of ECE
Vardhaman College of Engineering Vardhaman College of Engineering Vardhaman College of Engineering
Hyderabad Hyderabad Hyderabad
c.padmini@vardhaman.org sathwikab2001@gmail.com aakashchandra2002@gmail.com

4 B. Laxminarayana
Dept. of ECE
Vardhaman College of Engineering
Hyderabad
laxminarayanalucky231@gmail.com

Abstract—A real-time clock is shown with a 32 kHz crystal
oscillator with a power consumption of 3.245 nW performing at a
0.6 V. A precise Schmitt trigger replaces the traditional amplifier
circuit within a crystal oscillator circuit, incorporating power
minimization blocks. The MTCMOS technique is employed in
constructing the low-power crystal oscillator. The timing of
the pulse is accurately generated through the utilization of
a Delay-Locked Loop (DLL). The switched capacitor network
(SCN) generates various supply levels on-chip from a single
supply source. The recorded power consumption demonstrates
a minimal value of 3.24 nW over a supply of 0.6 V-1.2 V
Index Terms—Crystal Oscillators, Real-Time Clock, Wire-
less Sensor Nodes, low power
I. I NTRODUCTION
rystal oscillators play a pivotal role in electronic
C circuits, particularly where precise frequency stability
is essential, even when operating within low voltage supply
conditions. Wireless sensor Nodes, Remote Monitoring
Systems, Smart Agriculture, Health Monitoring, etc. depend
on crystal oscillators because of their precise timing, stability,
and low power consumption for reliable operation and
communication. [1]
In wireless sensor nodes the communication between
nodes plays a vital role. To avoid mismatch due to random
jitter, frequency instability, and power consumption issues
crystal oscillators are introduced inside the circuit. When
compared to silicon-based timers, the sensor node system’s
incredibly low power consumption contrasts with the crystal
oscillators consistently stable frequency, albeit at the expense
of higher power consumption. [3]
When certain applications demand wireless sensor
nodes, 32kHz crystal oscillators that run on a 0.6V to 1.8V
supply are employed. We constructed and characterized
two implementations for various crystals utilizing a Schmitt
trigger circuit. The circuits are small and made in 130nm.
The oscillators have a low power consumption of 2.26 nW
and 15 nW, respectively. [3]
A 24-MHz complementary Colpitts crystal oscillator
with ultralow power and low phase noise is employed in
a few wireless sensor node applications. With the updated
circuit, the oscillator is continuously biased in the weak-
inversion zone, allowing it to operate in Class-C mode. A
Langasite-type CTGS crystal resonator, which differs from
conventional quartz (SiO2) in several ways, is used to cut the
starting time down to less than 1 ms. To further accelerate
the oscillation, an injected gm-booster is added. Both CTGS
and quartz resonators were used to test prototype chips in
65-nm CMOS. [2]
However for some applications, Real-time clock
generation is featured for establishing proper communication
between wireless sensor nodes. An RTC module contains an
inbuilt 32KHz crystal oscillator with extremely low power
consumption. To significantly reduce power usage, a power
injection strategy is devised that takes advantage of oscillation
amplitude and load capacitance scaling in conjunction with a
power injection mechanism in the resonator. It is stated that
the oscillator uses 10nW of electricity at 1V.
Ultra-low-power silicon-based Real-Time Clocks (RTCs),
able to operate at sub-nW levels (660pW, for example), face
the challenge of high-frequency instability. Although they
have a more stable frequency, crystal oscillators (XOs)
usually use more power—between mW and hundreds of
nW. Low-power XO research in the past has mostly focused
on reducing oscillation amplitude, which lowers energy
loss per cycle and necessitates less energy replenishment to
maintain oscillation. But this method also causes the voltage
amplitude at the driver circuit’s input to decrease. It becomes
more difficult to maintain steady oscillation as a result of
the driver circuit’s exponential weakening as it approaches
the sub-threshold zone. Increased power consumption is
also a result of the circuit’s continuous bias current. Using
this technology, the lowest documented power usage for a
32.768kHz crystal oscillator is 27nW. [8]
A Real-time clock consists of various insider blocks.
The front-end block consists of a body-biased inverter and
generator, A DLL block which is made with current-starved
inverters that minimize the leakage, Switched Capacitor
Networks modify various voltage supply pairs for different
requirements), and Level Converter converts to the high
voltage supply levels for low ON-resistance. It resulted in
5.58nW of overall power consumption with 0.94-1.82V
supply voltage for a crystal-generated frequency of 32KHz
by adding a power injection scheme realized by DLL. [5]
The previous works contain the schematics for the DLL
and FE [5]. The FE functions similarly to earlier research [6].
By dynamically altering the NMOS and PMOS body bias, it
can transfer the oscillation generated by the various voltage
areas between low and medium levels, making it robust
to process variations. The main unit of the bias-adjusting
circuit consists of three inverter stages with input and output
levels centered between medium-voltage level areas. With
a maximum drift of 10uV/s at 85°C, a precise stabilizing
capacitor is used in quick corner simulation to minimize bias
drift when the circuit is idle. A transistor stack connected by
diodes internally provides the reference voltage (Vref).
Based on the results of the simulations, the FE typically
modifies its switching threshold to the midpoint between
VDD-M and VSS-M. There will be a power usage of about
0.3nW with this change. To minimize the amount of delay
cells and power consumption, the DLL uses an odd number
of stages to guarantee that the last stage is 180° out of phase
from the first stage. To save power, the DLL occasionally
deactivates the charge pump and BAC. Furthermore, by using
simplified Flip-Flops rather than regular D Flip-Flops, edge
detection reduces the number of transistors, which reduces
the power consumption to more than half of other works
attributed to D Flip-flops. [6]
Voltage scaling has been employed aggressively in
modern microsystems to achieve reduced power consumption.
The insensitivity of crystal oscillators to changes in non-
supply and temperature makes them a popular choice for
frequency reference. A timer that uses gate leakage is
shown to lower active power as of [7]. The temperature
self-compensation program-and-hold timer is now available.
There exist analytical formulas that explain how the
Schmitt trigger functions as an amplifier. In the case where
there is no hysteresis, transistor aspect ratios that maximize
voltage gain can be found. In principle, the Schmitt Trigger
may produce a voltage gain more than unity at standard
temperatures, using a supply voltage as low as 31 mV. This
result is different from other studies that stated a threshold of
35 mV, which was higher. [9]
Considering the highlighted concerns and pertinent
findings, there is an evident demand for an improved crystal
oscillator tailored to meet specific application requirements.
This paper introduces a cutting-edge crystal oscillator
design that integrates precise frequency control and power
consumption reduction techniques across all circuits, thereby
enabling ultra-low power operation. Instead of conventional
amplifier circuits, a modified Pseudo-NMOS Schmitt Trigger
is employed, complemented by the integration of sleep
transistors to introduce the MTCMOS technique into the
circuitry. Additionally, an external power minimization block,
incorporating precise RLC values, is introduced through the
utilization of a bond wire, resulting in a significant reduction
in power consumption. [3].
II. E XISTING A PPROACH
This clock circuit uses a crystal oscillator and special
drivers instead of a regular amplifier. The drivers produce
pulses precisely timed by a Delay-Locked Loop (DLL). These
pulses are low-power and maintain a stable oscillation with a
very small voltage of 160 mV. Additional supply voltages, one
lower and one higher, help keep the operation reliable. These
voltages are created on the chip using a special network.
The circuit has been tested under different conditions and
consumes very little power, about 5.58 nW. It’s also stable
over different supply voltages and temperatures, from -20°C
to 80°C. It has been confirmed to work well as a real-time
clock with high accuracy.
A novel design for a crystal oscillator (XO) was
Fig. 1. Block Diagram
showcased. It uses a lower voltage to reduce oscillation; for
more powerful drivers, it uses a higher voltage. It is the first
to employ pulsed input to sustain the oscillation generated by
the crystal using a Delay-Locked Loop (DLL). As a result,
power usage drops to just 5.58 nW, which is about five times
less than what was used in earlier technologies. It exhibits
consistency across a broad range of supply voltages and is
unaffected by temperature variations in the crystal’s frequency
performance. Testing confirms that it satisfies the stability
criteria for Wireless Sensor Network (WSN) applications.
 III. P ROPOSED A PPROACH
To enhance the power efficiency of a Crystal Oscillator,
we present a novel circuit topology incorporating a bond
wire to reduce power consumption. Additionally, a Schmitt
trigger was used, along with sleep transistors, to reduce power
consumption. A Schmitt trigger with sleep transistors was
included, which greatly reduced the crystal oscillator design’s
power usage. Sleep transistors can be used to selectively turn
down particular circuit components while they’re not in use,
which will minimize power loss. The Schmitt trigger was Fig. 3. Equivalent Crystal Circuit
used to introduce hysteresis to the circuit, which enhanced
noise immunity and preserved constant oscillations. A Pierce
crystal with carefully chosen capacitance (C) and inductance
(L) values is used in the circuit.
The best transistor aspect ratios for maximizing voltage
gain can be found in situations without hysteresis. In addition
to having a larger gain, Schmitt triggers have a lower depen-
dence on process variables than conventional inverters, which
makes them especially useful in ultra-low voltage applications.
However, utilizing Schmitt triggers instead of standard circuits
in such applications comes with the trade-off of larger area
requirements and slower response times.
Here, Figure 2 illustrates the Crystal Oscillator circuit Fig. 4. Bond wire and package model used for simulations

TABLE I
E QUIVALENT C RYSTAL AND B ONDWIRE CIRCUIT VALUES

Parameters Oscillator Bondwire

Type ABS07W- NA
32.768kHz
Frequency [Hz] 32 K NA
Capacitance [F] C=4.68 f C1=200f,
C2=200f, C3=5p
Inductance [H] L=5048.571 H L1= 2n, L2=500p
Resistance [Ω] R=38.194K R1=20m,
R2=200m
R3=1K, R4=1K

Fig. 2. 32 kHz Crystal Oscillator Circuit

operating at a frequency of 32 kHz. Bond wire blocks are

included in the circuit after an equivalent circuit of the crystal
coupled to a biased Schmitt trigger circuit. The accompanying
table contains the exact values of the crystal’s comparable
circuit components.
The crystal’s comparable circuit is shown in Figure 3.
The necessary 32 kHz frequency is represented by a passive
network of crystal circuits using estimated L and C values, as Fig. 5. Biased Schmitt Trigger Circuit
indicated in Table 1. The amplifier circuit is connected to the
crystal circuit using a Pierce-type topology.
Figure 5. The circuit was also changed to a pseudo-Nmos with
a sleep transistor circuit to reduce the number of transistors
It is discovered that the crystal oscillator in conjunction as shown in Figure 6.
with the Schmitt trigger has a lower voltage need and a higher The front end block consists of a generator and a body-
power consumption efficiency when compared to conventional biased inverter. It converts sine wave oscillations into square
amplifier circuits. The 6-T Schmitt trigger circuit, which has wave input for the DLL block. using a body-biased inverter
been biased, is coupled to the crystal oscillator circuit as of to raise the sine wave voltage. The body-biased generator
 viding the crystal frequency by eight times yield a 4.096kHz
signal, which powers the SCN, as shown in Figure 9. SCN-1
combines the high and low-voltage supply pairs to create the
medium-voltage supply pair. Subsequently, SCN-2 forms the
low-voltage supply couple using the medium-voltage supply.
By reconfiguring SCN-1 and SCN-2, six distinct division ratios
are anticipated to be accessible, as seen in Figure10.
A 100 pF, 36 pF capacity capacitor is used to decouple
each supply-voltage node. Each of the test results in the
following section was obtained using an SCN-1 split ratio of
two to one and an SCN-2 split ratio of three to one. Using
a clock signal of 4.096 kHz in this configuration, the SCN
consumes 0.463 nW. Operating at 32.768 kHz, it consumes
about 3 nW of power.
Fig. 6. Schmitt-Trigger with Sleep Transistors approach The SCN requires an independent clock source before
the crystal oscillates to set the required output voltage levels
at startup. To do this, a simple ring-type oscillator that serves
as a clock for starting up and isn’t part of the test chip can be
used. This allows for minimal leakage while power-gating it.

Fig. 7. Biased Schmitt Trigger Output

dynamically adjusts the body bias to set the voltage as needed.

Current-starved inverters are used in the construction of DLL
blocks to minimize leakage. two DLL outputs are chosen by
Fig. 8. Front End block
the MUX for the ensuing Pulse Generator block. We have
replaced Flip Flops with custom cells to reduce the number of
transistors in the Edge Detector and Charge Pump for DLL
blocks. They don’t always work and are only used when
lowering the overall power usage is essential (double stacking
is needed).
Level converter circuits are used to convert high-voltage
supply levels to low ON resistance. The medium-voltage
supply of the preceding block produces an up-converted pulse.
When the NMOS driver is switched to high voltage, its
maximum voltage is increased to Vddh. For the PMOS driver,
the minimum voltage needs to be decreased to Vssh. Parasitic
components are considered to attain high SCN efficiency and
lessen the effects of increasing supply voltage ripple. SCN-
1 creates a medium-voltage supply 9 from two high-voltage
supplies, and SCN-2 transforms two medium-voltage supplies
into a low-voltage supply. The use of a triple well reduced the Fig. 9. SCN-1
amount of electricity used, and it runs on an external clock.
Level-converting to a high-voltage supply level and di-
 a 32kHz frequency wave.
SCN is configured to produce VDDM - VSSM = 0.47
V and VDDL - VSSL = 0.16 V at the moment. In the initial
testing, VDDM - VSSM = 0.54 V and VDDL - VSSL =
0.18 V were used with a VDDH input supply voltage of
1.08 V, which produced an unloaded power consumption of
9.05 nW. This arrangement was used for further tests, such
as a temperature sweep. Because each supply voltage pair is
centered about half of the VDDH voltage, the unloaded values
of VDDM, VDDL, VSSL, and VSSM are, respectively, 0.81
V, 0.63 V, 0.45 V, and 0.27 V. The recorded frequency in this
arrangement was 32 KHz.
Fig. 10. SCN-2

TABLE II
IV. R ESULTS AND D ISCUSSIONS C OMPARISON OF DIFFERENT APPROACHES

The proposed circuit was created using CMOS Parameters [4] [1] [6] Proposed
Work
technology at 180 µm. 3.245 nW of minimum power, with Technology CMOS CMOS CMOS CMOS
a voltage fluctuation of 0.9 V to 1.8 V, is the total circuit’s 180nm 130nm 180nm 180nm
power consumption, which includes the SCN’s on-chip Load C1=5.2pF C1=C2=6pF NA C1=C2=6pF
Capacitance C2=3.9pF
voltage generation.
Capacitance C=3.5fF C1=3.5fF NA C1=4.68fF
Inductance L=6740.193H L=6740.193H NA L=5048.571H
Frequency 32KHz 32KHz 32 KHz 32KHz
Voltage 0.4 to 5.5V 0.6 to 1 0.9 to 1.8V 0.9 to 1.8V
Bond Wire No No No Yes
Architecture Timers Traditional Pulsed Schmitt
Based Amplifier Driver trigger
Based Based based
Power Con- 10nW 2.26nW 5.58nW 3.245nW
sumption

V. C ONCLUSION AND F UTURE S COPE

Fig. 11. Real-Time Clock Waveform(X axis-µs and Y axis- V)
Here are the findings of the simulation, measurements,
and architectural design of the crystal oscillator. A stable
frequency of 32 kHz is generated with ultra-low power
consumption and voltage levels. With an amplifier that is
a modified Schmitt trigger, the crystal oscillator displays a
67.55% reduction in total power as compared to [4]. The
power consumption was reduced by 55% in the DLL block
by reducing the transistor count. In SCN-1 and SCN-2
blocks, decoupling capacitors are used to minimize power,
also voltage scaling is used to select the less complex circuit
in SCN blocks. It can be further modified with a pseudo-
randomized approach in SCN to reduce power consumption.
When compared to [6], there was a reduction of almost 40%
in power usage in the Real-Time clock generator circuit
which is suitable for the wireless sensor node applications.

Fig. 12. Power analysis of Crystal Oscillator (X axis-ns and Y axis- V)
At this point, the crystal oscillator is employed
with the crystal values Resistance (R)=38.194kΩ and
inductance(L)=5048.571 H and capacitance (C)=4.68 fF gives
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