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…esting PSRR with High-Frequency Ripple

By Anoop Joshi, Cadence Design Systems

Power supply rejection ratio (PSRR) is an important parameter for

many electronic systems because it measures system performance,
enabling designers to verify a system meets required performance
specification. This white paper discusses how to drive high-
frequency sinusoidal ripple over capacitive loads for PSRR testing

Introduction

This white paper discusses a method for driving high-frequency sinusoidal

ripple over capacitive loads for power supply rejection ratio (PSRR) testing,
an important performance parameter for many electronic systems such as RF
and wireless systems, power management systems, data converters,
clocking systems, and high-speed serial interface systems. PSRR measures
how well a circuit rejects ripple coming from input power supply at various
frequencies, measuring system performance with a ripple (e.g., sinusoidal
ripple) of specific amplitude and frequency added to the power supply, and
verifying that it meets the required performance specifications.

One key factor while adding supply ripple is the presence of a decoupling
capacitor at the supply pin. Systems usually have decoupling capacitors on
all their supplies to decouple the power supply from the switching noise
caused by switching currents across the PCB trace inductance. As the ripple
frequencies increase, the shunt impedance to ground presented by the
decoupling capacitors decreases and the current required to achieve a
specific ripple amplitude across the capacitor increases. For example, for a
0.1μF decoupling capacitor, the impedance for a 1MHz ripple frequency is
about 1/(Cω)=1.59Ω, which is fairly low. To achieve a 200mVpp
(70.72mVrms) sinusoidal ripple amplitude at the supply pin with the
decoupling capacitor in place requires a root mean square (RMS) current of
70.72mVrms/1.59 Ω, which is nearly 45mArms. As frequencies go even
higher, the currents required will scale up accordingly. This makes the
required ripple amplitudes somewhat difficult to achieve when driven by
normally available signal sources or op-amp-based circuits, and may require

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high-performance components with high current driving capacity, wide signal

bandwidths, and tolerance of high-capacitive loads-which may be expensive.
Even with these components, it may not be easy to achieve the desired
results, and the system may have stability issues due to the capacitance
load, especially in op-amp-based approaches. An easy solution would be to
remove the decoupling capacitors during the PSRR tests, but this may not be
acceptable for highly automated test systems, where all the tests are
supposed to run one after the other at the click of a button without any
interruptions.

The circuits discussed in this white paper use the higher current drive
capability of the DC power supplies by deriving the AC current for generating
the ripple directly from the supplies, and thus isolate the signal source/ op-
amp amplifier from the task of delivering this load current across the
decoupling capacitors. In addition to the basic circuit used to drive a sine/
square supply ripple at a supply pin without the decoupling capacitor in
place, this white paper discusses two enhanced versions, one that drives a
1MHz sinusoidal 200mVpp supply ripple across a 0.1μF decoupling capacitor,
and another that delivers a 30MHz sinusoidal 50mVpp supply ripple across a
0.1μF decoupling capacitor. All circuits have been simulated using Cadence®
OrCAD® PCB Designer with PSPICE® tool.

Circuits

This white paper describes three circuits:

1. Basic circuit for adding supply ripple (no decoupling capacitor)

2. Circuit for adding supply ripple (with decoupling capacitor)
3. Circuit for adding supply ripple at frequencies greater than 10MHz (with
decoupling capacitor)

Circuits 2 and 3 are modified versions of the basic circuit, and are both
capable of driving a supply ripple even when a decoupling capacitor is
present. This approach allows designers to leave the decoupling capacitors
on the board during PSRR testing, saving time during the testing stage and
enabling more automation.

Circuit 1: Basic circuit for adding supply ripple (no decoupling

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capacitor)

Figure 1 shows a basic circuit that drives a sine/square supply ripple without
a decoupling capacitor. This circuit makes use of negative feedback to ensure
that the ripple signal is an exact replica of the signal applied on the non-
inverting terminal of the op-amp. It works well for even square wave ripple
with faster rising edges and for high-ripple frequencies up to 100MHz,
assuming appropriate high-speed op-amps and MOSFETS are chosen.
However, because the output node is part of the negative feedback loop,
supply decoupling capacitors must be removed for testing to avoid instability.

In this circuit, the signal required to be replicated at the supply pin is applied
to the non-inverting input of the op-amp U1. For illustrative purposes,
consider a case where a 1MHz 200mVpp sine/square ripple riding on a 3.63V
DC supply is required. A 1MHz 200mVpp sine/square signal riding on 3.63V

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DC level is applied to the op-amp non-inverting input using a signal

generator. The op-amp output drives the gate terminal of the N-channel
enhancement MOSFET T1. The drain terminal of T1 is connected to a 10V DC
supply (a 5V DC supply may be adequate, depending on the DC level
required at the output). The source terminal of T1 is connected to the
inverting input of U1, with the RC combination (consisting of R2, R3, and C1)
connected between the source terminal and ground. The functionality of R1,
R4, and R5 will be discussed later in this white paper. The final output signal
appears at the source terminal, denoted by node VM1.

Once the required input signal is applied at the non-inverting op-amp input,
the op-amp tries to replicate the same signal on the inverting input by
resorting to negative feedback to reduce the difference or error between the
inverting and non-inverting inputs. In this case, the inverting input is not
directly connected to the op-amp output, but to the source terminal of T1,
and op-amp output is connected to the MOSFET gate terminal. The op-amp
can control how much the MOSFET turns on by setting the gate voltage to
allow the MOSFET to turn on just enough so that the current that flows
across it from drain to source (derived from the 10V DC supply) creates a
voltage across the R2, R3, and C1 combination that closely mimics the
voltage applied on the op-amp non-inverting terminal. Here, the MOSFET
behaves somewhat like a voltage variable resistor controlled by Vgs. Thus,
we replicate this signal at the output node, but the required current is fully
delivered by the 10V DC supply and not by the op-amp or signal source.

When implementing this circuit in hardware, there are practical

considerations that the designer must keep in mind to realize the
performance achieved in simulations, such as choosing the proper
components and reducing of the effects of board parasitics on circuit
operation. Additional considerations are listed below:

• The choice of the op-amp and MOSFET - The op-amp should have
sufficient bandwidth and slew rate to be able to track the input signal
fast enough using negative feedback. The op-amp used in this
particular example has a GBP of 165MHz. The MOSFET should also be
able to respond fast enough to the gate signal variations to ensure the
negative feedback action is good enough. A low threshold voltage and a
low RgCgs time constant-where Rg is the internal series gate resistance

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and Cgs is the internal gate-source capacitance-are desirable traits.

Unity gain stable op-amps may be preferred.
• The op-amp output swing and DC supplies required - This is
dictated by the threshold voltage Vgsth for the MOSFET. Assuming a
Vgsth of 3V, if the required output DC level (which is the same as the
source terminal voltage) is 3.63V, the gate voltage should at least be
6.63V. Therefore, the op-amp and the DC supply levels used need to
support the required output swing.
• Use of R1, R4, and R5 - These are not always strictly necessary, but
can be very helpful. R1 helps to isolate the op-amp output from any
direct capacitive loading (such as the gate-source capacitance of the
MOSFET) and helps maintain stability. R4 helps to reduce ringing in the
output, especially in cases with a square wave ripple or high-frequency
sine wave ripple with fast rising edges. R5 is not strictly required in this
case, but will become more important in the cases to follow.
Nevertheless, it may be useful to leave the option to add a resistance
here so that this circuit can be easily modified in the future.
• Minimize inductance - Be careful to minimize the inductance on the
trace driving the gate signal, as this inductance could form a parasitic
LC circuit with the MOSFET gate-source and gate-drain capacitances
and oscillate. Minimizing the trace length will help.
• Adjust DC drain voltage as necessary - If 10V drain DC voltage is
used, the output may approach 7V for a brief period of 50us after
powering on the circuit before settling to the final value, so it may be
better to connect the output to the chip supply pin after this time, i.e.,
after the output is settled (a relay can be used for this). Alternatively, a
lesser DC drain voltage, e.g., 5V, may be used, as the startup output
overshoot will always be less than this. The series drain resistor value
for T1 may have to be reduced accordingly.

Figure 2 shows the input and output waveforms from simulation for a 1MHz
200mVpp sine and square signal riding on 3.63V DC level. VM1 is the output
and VM2 is the input. The output tracks the input closely, as both signals
overlap almost perfectly in both cases.

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Click to enlarge

Circuit 2: Adding supply ripple (with decoupling capacitor)

Figure 3 shows a circuit that drives a 1MHz 200mVpp sinusoidal supply ripple
across a 0.1μF decoupling capacitor. This circuit does not require designers
to remove the decoupling capacitor for PSRR testing, saving testing time and
enabling more automation.

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Click to enlarge

If a decoupling capacitor is added directly to the T1 source terminal in the

circuit in Figure 1, a capacitor is connected directly to the inverting input of
the op-amp, which contributes to a phase lag within the negative feedback
loop. This affects the loop function and may make the circuit unstable, as
shown in Figure 4. It is also difficult to compensate for this phase lag using
phase lead compensation and other compensation methods, and will
continue to affect the negative feedback operation to some degree.

Click to enlarge

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To prevent the negative feedback loop being affected by the decoupling

capacitor's capacitive load , an extra output stage with a MOSFET T2
identical to T1 is added as shown in Figure 3. The gate terminal of T2 is
shorted to match T1 so that both receive the same gate voltage from the op-
amp. An RC combination consisting of R4 and C2 (which is the decoupling
capacitor) is connected between the source terminal of T2 and ground.

It is not as straightforward as simply shorting the gate signals of the 2

MOSFETS together. For just a DC level, we could use an R4 value that is the
same as R2 and would receive an identical DC output. In this case, for the
AC signal component, the load impedance present at the output of the
second MOSFET is much lower compared to the first one due to the
decoupling capacitor. This is calculated by ~1/(Cω), and is approximately
1.59Ω for a frequency of 1MHz and C=0.1uF. The AC current required to flow
across the MOSFET to get a 100mV amplitude is likewise higher, i.e., a
sinusoidal current of around 45mArms or around 64mA amplitude should
flow across it. To allow for the full swing of this AC current, the DC current
must be biased to a high enough value (at least 64mA) so that the AC
current is not clipped during the negative cycle, as the current across the
MOSFET cannot be negative. The circuit uses a much lower value of 50Ω for
R, so that the DC current bias point is set high enough to allow for the full
range of variation for the AC current. This is critical to make the output stage
MOSFET react well enough to the gate signal to deliver the required AC
current across the output load per the AC excitation, and to improve its
linearity. Ensure R4 has the required power dissipation capability.

In turn, the DC and AC component of the gate excitation for T2 must be

scaled sufficiently higher to achieve the required output. The easiest way to
find the scaling required for the gate voltage's DC and AC components is to
simulate using a simple circuit as shown in Figure 5 and find what DC and AC
signal levels are required at the MOSFET gate to achieve the required DC
and AC levels at the output. For example, for this circuit and components,
the required gate input for a 1MHz 200mVpp sine wave riding on 3.63V DC
level at the output is a 240mVpp sine wave signal of the same

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This is achieved in Circuit 2 by using the indicated values for R2, R3, and R5.
For the DC signal, the feedback point connected to the inverting input is
taken from the junction of the resistive voltage divider formed by R2 and R5.
The AC signal is taken from the junction of the voltage divider, which
consists of R5 at the top and the parallel combination of R2 and R3. (The
impedance of C1 is in series with R3, but at frequencies as high as 1MHz, the
series combination would still be nearly equal to R3 as the capacitive
reactance will be negligible in comparison.) This ensures that the DC and AC
components in the op-amp output are individually scaled by the respective
values required, and this signal is applied to the gates of both MOSFETs.

This architecture will not work well with square waves, as the amount of
switching current required for getting sharp rising edges across the
capacitive load will be too high, and the edges will start to slow down and
become distorted. The scope for this circuit is restricted only to sinusoidal
ripple.

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Figure 6 shows the input and output waveforms from simulation of a 1MHz
200mVpp sinusoidal signal riding on 3.63V DC level. VM1 is the output and
VM2 is the input. The output tracks the input fairly accurately even though
there is a small phase shift, which should not be an issue.

Click to enlarge

Proper thermal management for the MOSFETs is important, because MOSFET

power dissipation can be non-trivial especially at higher ripple frequencies or
higher capacitance load values. MOSFET power dissipation can be calculated
as IDS X VDS , where IDS is the drain to source current of the MOSFET and
VDS is the drain to source voltage differential. Clearly, the choice of a lower
drain voltage (e.g., 5V instead of 10V) can reduce this power dissipation.
Designers should also reduce the MOSFET junction-to-ambient thermal
resistance using good heat-sinking practices to minimize the internal
temperature increases with power dissipation. This is required because
MOSFET operating characteristics can be affected by temperature changes,
and the performance may deviate from expectations if thermal management
is not adequately managed. The goal should be to limit the junction
temperature rise as much as possible for the given ripple
amplitude,frequency specifications and decoupling capacitor value.

Circuit 3: Adding supply ripple at frequencies greater than 10MHz

(with decoupling capacitor)

Figure 7 shows a circuit that drives a 30MHz 50mVpp sinusoidal supply ripple
across a 0.1μF decoupling capacitor This circuit is an enhanced version of
Circuit 2 shown in Figure 3 that is capable of driving comparatively higher
ripple frequencies by using a much faster op-amp.

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Click to enlarge

The Circuit 3 architecture uses a different op-amp than Circuit 2, with a

much higher bandwidth (420MHz) and slew rate. This is required for the
negative feedback to work fast enough to adequately track the input signal.
If a lower bandwidth/slew rate op-amp is used, the input signal applied to
the non inverting op-amp input may need to be scaled up to attain the
desired output ripple amplitude. Also, the values for the R2, R3, and R9
resistors have been changed to set the appropriate scaling ratios for the AC
and DC components of the signal. In addition, an even lower value of 10Ω
has been used for R4 to account for the higher DC biasing current required
to support the higher output swing for the AC current.

Figure 8 shows the simulation input and output waveforms for a 30MHz
50mVpp sinusoidal signal riding on 3.63V DC level. VM1 is the output and
VM2 is the input. The output tracks the input fairly accurately even though
there is a noticeable phase shift, which should not be an issue.

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Click to enlarge

Note that, at high speeds (≥10MHz), the PCB layout, the choice of the
components, and the parasitics of the components?especially the MOSFETs,
trace parasitics, etc.?become extremely important. Also, supplying the right
amount of current to achieve the desired ripple amplitude becomes more
difficult as the speeds increase, because the impedance across which the
ripple voltage is to be generated scales down with the ripple frequency. For
instance, at 30MHz, the load impedance becomes ~53mΩ, so the load
current required to achieve a particular ripple amplitude becomes that much
higher. Also, if you are using a current feedback op-amp as in this case, you
have to carefully follow the circuit recommendations, usually given in the
datasheets for such amplifiers. For example, do not use a feedback resistor
with a value less than the suggested value (in this circuit, R9 can be
considered the feedback resistor), and ensure the board parasitic
capacitance at the op-amp pins is low enough by removing the ground
planes from beneath them. Also make sure that the DC power supply can
drive the required output current.

Conclusion

Affecting PSRR measurements with the decoupling capacitors in place for the
supplies can be challenging. This white paper discusses how to insert high-
frequency ripple on a DC supply to affect PSRR measurements without
removing the decoupling capacitor on the supply pin. This capability is
especially important in highly automated test and measurement systems
where all the tests are run on batches of devices without changing the
hardware setups. With this solution, designers can avoid spending the time
and money required to implement a dedicated PSRR test hardware setup

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without decoupling capacitors. To ensure the most effective circuit, designers

should pay attention to the practical considerations such as optimal
component choice, proper thermal management practices, and reduction of
board parasitics.

References

• Understanding power supply ripple rejection in linear regulators

by John C. Teel, Texas instruments
• Current Feedback (CFB) Op Amps, MT-034 tutorial by Analog
devices
• Driving and Layout Design for Fast Switching Super-Junction
MOSFETS, AN-9005 by Fairchild Semiconductor
• AC Analyses, The Designer?s Guide to SPICE and Spectre by
Kundert

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