EC6504 – Microprocessor and Microcontroller Nov/Dec 2017 - Key

1 List the mode of operation in 8086.

Minimum mode
Maximum mode
2 Define Macros
A number of instructions appearing again & again in the main program can be assigned as a macro
definition (i.e.) a label is assigned to the repeatedly appearing string of instructions. The process of
assigning a label or macro name to the string is called defining a macro. A macro within a macro is
called a nested macro.
3 What is the need of LOCK signal?
This output pin indicates that other system bus masters will be prevented from gaining the system
bus, while the LOCK signal is low. The LOCK signal is activated by the 'LOCK' prefix instruction
and remains active until the completion of the next instruction. This floats to tri-state off during
"hold acknowledge". When the CPU is executing a critical instruction which requires the system
bus, the LOCK prefix instruction ensures that other processors connected in the system will not gain
the control of the bus. The 8086, while executing the prefixed instruction, asserts the bus lock signal
output, which may be connected to an external bus controller.
4 Write some example for advanced processors.
ARM Processor
AMD Processor
5 What are the handshake signals used in Mode02 configuration of 8255?
Port C Upper
Port C Lower
6 How the DMA operation performed with 8086?
Following is the sequence of operations performed by a DMA
 Initially, when any device has to send data between the device and the memory, the
device has to send DMA request (DRQ) to DMA controller.
 The DMA controller sends Hold request (HRQ) to the CPU and waits for the CPU to
assert the HLDA.
 Then the microprocessor tri-states all the data bus, address bus, and control bus. The
CPU leaves the control over bus and acknowledges the HOLD request through HLDA
signal.
 Now the CPU is in HOLD state and the DMA controller has to manage the
operations over buses between the CPU, memory, and I/O devices.
7 How to set 8051 in idle mode?
In Idle Mode, only the clock provided to CPU gets deactivated, whereas peripherals clock will
remain active in this mode. Hence power saved in power down mode is more than in idle mode.

8 Illustrate the DJNZ instruction.

The DJNZ instruction decrements the byte indicated by the first operand and, if the resulting value
is not zero, branches to the address specified in the second operand.

9 List the 8051 interrupts with its priority.

The 8051 microcontroller can recognize five different events that cause the main program to
Interrupt from the normal execution. These five sources of interrupts in 8051are:
1. Timer 0 overflow interrupt- TF0
2. Timer 1 overflow interrupt- TF1
3. External hardware interrupt- INT0
4. External hardware interrupt- INT1
5. Serial communication interrupt- RI/TI
10 Give two examples of sensors and state its uses.
Speed sensor- Sensors used for detecting speed of an object or vehicle is called as Speed sensor.
Temperature sensor- A device which gives temperature measurement as an electrical signal is
called as Temperature sensor. This electrical signal will be in the form of electrical voltage and is
 proportional to the temperature measurement.
PART B/ UNIT I
11.a Draw the architecture and explain the functional units of 8086.
 8086 has two blocks Bus Interfacing Unit(BIU) and ExecutionUnit(EU).
 The BIU performs all bus operations such as instruction fetching,reading and writing
operands for memory and calculating theaddresses of the memory operands. The
instruction bytes aretransferred to the instruction queue.
 EU executes instructions from the instruction system byte queue.
 Both units operate asynchronously to give the 8086 anoverlapping instruction fetch
and execution mechanism which iscalled as Pipelining. This results in efficient use of
the systembus and system performance.
 BIU contains Instruction queue, Segment registers, Instructionpointer, Address
adder.
 EU contains Control circuitry, Instruction decoder, ALU, Pointerand Index
register,Flag register.

Bus Interface Unit:

 It provides a full 16 bit bidirectional data bus and 20 bit address bus. The businterface
unit is responsible for performing all external bus operations. Instruction fetch,
Instruction queuing, Operand fetch and storage, Addressrelocation and Bus control.
 The BIU uses a mechanism known as an instruction streamqueue to implement a
pipeline architecture. This queue permits prefetch of up to six bytesof instruction code.
 Whenever the queue of the BIU is not full, it has room for at leasttwo more bytes and
at the same time the EU is not requesting it to read or write operandsfrom memory, the
BIU is free to look ahead in the program by prefetching the nextsequential instruction.
 These prefetching instructions are held in its FIFO queue. With its16 bit data bus, the
BIU fetches two instruction bytes in a single memory cycle.
 After a byte is loaded at the input end of the queue, it automatically shifts up through
 the FIFO to the empty location nearest the output.
 The EU accesses the queue from the output end. It reads one instruction byte after the
other from the output of the queue. If the queue is full and the EU is not requesting
access to operand in memory.
 These intervals of no bus activity, which may occur between bus cycles are known as
Idle state
 If the BIU is already in the process of fetching an instruction when the EU request it
to read or write operands from memory or I/O, the BIU first completes the
instruction fetch bus cycle before initiating the operand read / write cycle.
 The BIU also contains a dedicated adder which is used to generate the20bit physical
address that is output on the address bus. This address is formed by adding an
appended 16 bit segment address and a 16 bit offset address.
 For example : The physical address of the next instruction to be fetched is formed by
combining the current contents of the code segment CS register and the current
contents of the instruction pointer IP register. The BIU is also responsible for
generating bus control signals such as those for memory read or write and I/O read
or write.
Execution Unit
 The Execution unit is responsible for decoding and executing all instructions. The EU
extracts instructions from the top of the queue in the BIU, decodes them, generates
operands if necessary, passes them to the BIU and requests it to perform the read or
write byte cycles to memory or I/O and perform the operation specified by the
instruction on the operands.
 During the execution of the instruction, the EU tests the status and control flags and
updates them based on the results of executing the instruction.
 If the queue is empty, the EU waits for the next instruction byte to be fetched and
shifted to top of the queue. When the EU executes a branch or jump instruction, it
transfers control to a location corresponding to another set of sequential instructions.
 Whenever this happens, the BIU automatically resets the queue and then begins to
fetch instructions from this new location to refill the queue.
Internal Registers of 8086
 The 8086 has four groups of the user accessible internal registers. They are the
instruction pointer, four data registers, four pointer and index register, four segment
registers
 The 8086 has a total of fourteen 16-bit registers including a 16bit register called the
status register, with 9 of bits implemented for status and control flags. Most of the
registers contain data/instruction
offsets within 64 KB memory segment.
 There are four different 64 KB segments for instructions, stack, data and extra data.
To specify wherein 1 MB of processor memory these 4 segments are located the
processor uses four segment registers:

Code segment
 (CS) is a 16-bit register containing address of 64KB segment with processor
instructions. The processor uses CS segment for all accesses to instructions
referenced by instruction pointer (IP) register. CS register cannot be changed
directly. The CS register is automatically updated during far jump, far call and far
 return instructions.
Stack segment
 (SS) is a 16-bit register containing address of 64KB segment with program stack. By
default, the processor assumes that all data referenced by the stack pointer (SP) and
base pointer (BP)registers is located in the stack segment. SS register can be changed
directly using POP instruction.
Data segment
 (DS) is a 16-bit register containing address of 64KB segment with program data. By
default, the processor assumes that all data referenced by general registers (AX, BX,
CX, DX) and index register (SI, DI) is located in the data segment. DS register can be
changed directly using POP and LDS instructions.
Accumulator
 Register consists of two 8-bit registers AL and AH, which can be combined together
and used as a 16-bit register AX. AL in this case contains the low order byte of the
word, and AH contains the high-order byte. Accumulator can be used for I/O
operations and string manipulation.
Base
 Register consists of two 8-bit registers BL and BH, which can be combined together
and used as a 16-bit register BX. BL in this case contains the low-order byte of the
word, and BH contains the high-order byte. BX register usually contains a data
pointer used for based, based indexed or register indirect addressing.
Count
 Register consists of two 8-bit registers CL and CH, which can be combined together
and used as a 16-bit register CX. When combined, CL register contains the low order
byte of the word, and CH contains the high-order byte. Count register can be used in
Loop, shift/rotate instructions and as a counter in string manipulation,.
Data
 Register consists of two 8-bit registers DL and DH, which can be combined together
and used as a 16-bit register DX. When combined, DL register contains the low order
byte of the word, and DH contains the high-order byte. Data register can be used as a
port number in I/O operations. In integer 32-bit multiply and divide instruction the
DX register contains high-order word of the initial or resulting number.
 The following registers are both general and index registers
Stack Pointer
 (SP) is a 16-bit register pointing to program stack.
Base Pointer
 (BP) is a 16-bit register pointing to data in stack segment. BP register is usually used
for based, based indexed or register indirect addressing.
Source Index
 (SI) is a 16-bit register. SI is used for indexed, based indexed and register indirect
addressing, as well as a source data addresses in string manipulation instructions.
Destination Index
 (DI) is a 16-bit register. DI is used for indexed, based indexed and register indirect
addressing, as well as a destination data addresses in string manipulation
instructions.
Instruction Pointer
 (IP) is a 16-bit register.
 Flags
 Is a 16-bit register containing 9 one bit flags.
Overflow Flag
 (OF) - set if the result is too large positive number, or is too small negative number to
fit into destination operand.
Direction Flag
 (DF) - if set then string manipulation instructions will auto-decrement index
registers. If cleared then the index registers will be auto-incremented.
Interrupt-enable Flag
 (IF) - setting this bit enables mask able interrupts.
Single-step Flag
 (TF) - if set then single-step interrupt will occur after the next instruction.
Sign Flag
 (SF) - set if the most significant bit of the result is set.
Zero Flag
 (ZF) - set if the result is zero.
Auxiliary carry Flag
 (AF) - set if there was a carry from or borrow to bits 0-3 in the AL register.
Parity Flag
 (PF) - Set if parity (the number of "1" bits) in the low-order byte of the result is even.
Carry Flag
 (CF) - set if there was a carry from or borrow to the most significant bit during last
result calculation.
OR
11.b Describe the interrupts of 8086 and explain its types with service routine.
A signal indicating that an event needing immediate attention has occurred
3 Types of Interrupts:
• External - generated outside CPU by other hardware
• Internal - generated within CPU as a result of an instruction or operation
• - x86 has internal interrupts: int, into, Divide Error and Single Step
• - Trap generally means any processor generated interrupt
• - in x86, Trap usually means the Single Step interruptx86 Interrupts:
1) Hardware Interrupt - External Uses INTR and NMI
2) Software Interrupt - Internal - from int or into
3) Processor Interrupt - Traps and 10 Software Interrupts (12 total)
Interrupt Vector Table:
256 different Interrupts Specified by vector, Type vector is pointer in to Interrupt vector
table
Interrupt Acknowledge Cycle
The interrupt number for NMI is 2 so the location in the IVT for the NMI ISR address is 4+2
= 0X0008h. Upon receipt of interrupt cycle 8086 executes a two special bus cycle called
Interrupt Acknowledge Cycle. It is used to fetch the interrupt vector number from the
interrupting device via D&-D0 lines
The Operation of an Interrupt sequence on the 8086 Microprocessor:
1. External interface sends an interrupt signal, to the Interrupt Request (INTR) pin, or
an internal interrupt occurs.
2. The CPU finishes the present instruction (for a hardware interrupt) and sends
Interrupt Acknowledge (INTA) to hardware interface.
3. The interrupt type N is sent to the Central Processor Unit (CPU) via the Data bus
from the hardware interface.
4. The contents of the flag registers are pushed onto the stack.
5. Both the interrupt (IF) and (TF) flags are cleared. This disables the INTR pin and
the trap or single-step feature.
6. The contents of the code segment register (CS) are pushed onto the Stack.
7. The contents of the instruction pointer (IP) are pushed onto the Stack.
8. The interrupt vector contents are fetched, from (4 x N) and then placed into the IP
and from (4 x N +2) into the CS so that the next instruction executes at the interrupt service
procedure addressed by the interrupt vector.
9. While returning from the interrupt-service routine by the Interrupt Return (IRET)
instruction, the IP, CS and Flag registers are popped from the Stack and return to their state
prior to the interrupt.
Multiple Interrupts
If more than one device is connected to the interrupt line, the processor needs to know to
which device service routine it should branch to. The identification of the device requesting
service can be done in either hardware or software, or a combination of both.

The three main methods are:

 Software Polling,
Hardware Polling, (Daisy Chain),
Hardware Identification (Vectored Interrupts).
12.a Explain the system bus structure of 8086. Draw the timing diagram for interrupt
acknowledgement cycle.
System Design using 8086: Maximum mode 8086 system and timings
In the maximum mode, the 8086 is operated by strapping the MN/MX* pin to ground. In
this mode, the processor derives the status signals S2*, S1* and S0*. Another chip called bus
controller derives the control signals using this status information. In the maximum mode,
there may be more than one microprocessor in the system configuration.
The basic functions of the bus controller chip IC8288, is to derive control signals like RD*
and WR* (for memory and I/O devices), DEN*, DT/R*, ALE, etc. using the information
made available by the processor on the status lines. The bus controller chip has input lines
S2*, S1* and S0* and CLK. These inputs to 8288 are driven by the CPU. It derives the
outputs ALE, DEN*, DT/R*, MWTC*, AMWC*, IORC*, IOWC* and AIOWC*. The AEN*,
IOB and CEN pins are especially useful for multiprocessor systems. AEN* and IOB are
generally grounded. CEN pin is usually tied to +5V.

The significance of the MCE/PDEN* output depends upon the status of the IOB pin. If IOB
is grounded, it acts as master cascade enable to control cascaded 8259A; else it acts as
peripheral data enable used in the multiple bus configurations. INTA* pin is used to issue
two interrupt acknowledge pulses to the interrupt controller or to an interrupting device.
IORC*, IOWC* are I/O read command and I/O write command signals respectively. These
signals enable an IO interface to read or write the data from or to the addressed port. The
MRDC*, MWTC* are memory read command and memory write command signals
respectively and may be used as memory read and write signals. All these command
signals instruct the memory to accept or send data from or to the bus. For both of these
write command signals, the advanced signals namely AIOWC* and AMWTC* are available.
They also serve the same purpose, but are activated one clock cycle earlier than the IOWC*
and MWTC* signals, respectively.
The maximum mode system timing diagrams are also divided in two portions as read
(input) and write (output) timing diagrams. The address/data and address/status timings
are similar to the minimum mode. ALE is asserted in T1, just like minimum mode. The only
difference lies in the status signals used and the available control and advanced command
signals. The figures shows the maximum mode timings for the read operation while the
figures shows the same for the write operation.
 OR
12.b Explain the Loosely coupled configuration with neat diagram.
A loosely coupled configuration provides the following advantages:

1. High system throughput can be achieved by having more than one CPU.

2. The system can be expanded in a modular form. Each bus master module is an
independent unit and normally resides on a separate PC board. Therefore, a bus
master module can be added or removed without affecting the other modules in the
system.
3. A failure in one module normally does not cause a breakdown of the entire
system and the faulty module can be easily detected and replaced.

4. Each bus master may have a local bus to access dedicated memory or I/O devices
so that a greater degree of parallel processing can be achieved. More than one bus
master module may have access to the shared system bus

Extra bus control logic must be provided to resolve the bus arbitration problem. The extra
logic is called bus access logic and it is its responsibility to make sure that only one bus
master at a time has control of the bus. Simultaneous bus requests are resolved on a priority
basis:
There are three schemes for establishing priority:
1. Daisy chaining.
2. Polling.
3. Independent requesting.
Loosely coupled configuration consists of the number of modules of the microprocessor
based systems, which are connected through a common system bus. Each module consists
of their own clock generator, memory, I/O devices and are connected through a local bus.

Block Diagram of Loosely Coupled Configuration

 Advantages
 Having more than one processor results in increased efficiency.
 Each of the processors have their own local bus to access the local memory/I/O
devices. This makes it easy to achieve parallel processing.
 The system structure is flexible, i.e. the failure of one module doesn’t affect the whole
system failure; faulty module can be replaced later.
13.a Draw and explain the functional diagram of 8251.
The 8251 is a USART (Universal Synchronous Asynchronous Receiver Transmitter) for
serial data communication. As a peripheral device of a microcomputer system, the
8251receives parallel data from the CPU and transmits serial data after conversion. This
device also receives serial data from the outside and transmits parallel data to the CPU after
conversion.
2 Control Words
There are two types of control word.
ü Mode instruction (setting of function)
ü Command (setting of operation)
1) Mode Instruction
Mode instruction is used for setting the function of the 8251. Mode instruction will be in
"wait for write" at either internal reset or external reset. That is, the writing of a control
word after resetting will be recognized as a "mode instruction."
Items set by mode instruction are as follows:
ü Synchronous/asynchronous mode
ü Stop bit length (asynchronous mode)
ü Character length
ü Parity bit
ü Baud rate factor (asynchronous mode)
ü Internal/external synchronization (synchronous mode)
ü Number of synchronous characters (Synchronous mode)
The bit configuration of mode instruction is shown in Figures 3.8 and 3.9. In the case of
synchronous mode, it is necessary to write one-or two byte sync characters. If sync
characters were written, a function will be set because the writing of sync characters
constitutes part of mode instruction.
Asynchronous:

Synchronous:
 2) Command
Command is used for setting the operation of the 8251. It is possible to write a command
Whenever necessary after writing a mode instruction and sync characters.
Items to be set by command are as follows:
Transmit Enable/Disable
Receive Enable/Disable
DTR, RTS Output of data.
Resetting of error flag.
Sending to break characters
Internal resetting
Hunt mode (synchronous mode)

OR
13.b Draw and explain functional diagram of keyboard and display controller.
The disadvantages of interfacing keyboard and display with 8086 using 8255 are that
the processor has to refresh the display and check the status of the keyboard periodically
using polling technique. Thus a considerable amount of CPU time is wasted, reducing the
system operating speed.
Intel’s 8279 is a general purpose keyboard display controller that simultaneously drives the
display of a system and interfaces a keyboard with the CPU, leaving it free for its routine
task.
ARCHITECTURE AND SIGNAL DESCRIPTIONS OF 8279:
• The keyboard display controller chip 8279 provides:
a) A set of four scan lines and eight return lines for interfacing keyboards
b) A set of eight output lines for interfacing display.
The Fig shows the functional block diagram of 8279 followed by its brief description.
I/O Control and Data Buffers:
The I/O control section controls the flow of data to/from the 8279. The data buffers
interface the external bus of the system with internal bus of 8279.
The I/O section is enabled only if CS is low. The pins A0, RD and WR select the command,
status or data read/write operations carried out by the CPU with 8279.

Control and Timing Register and Timing Control:

These registers store the keyboard and display modes and other operating conditions
programmed by CPU.
The registers are written with A0=1 and WR=0.
The Timing and control unit controls the basic timings for the operation of the circuit.
Scan counter divide down the operating frequency of 8279 to derive scan keyboard and
scan display frequencies.
Scan Counter:
The scan counter has two modes to scan the key matrix and refresh the display.
In the encoded scan mode, the counter provides binary count that is to be externally
decoded to provide the scan lines for keyboard and display (Four externally decoded scan
lines may drive up to 16 displays).
In the decoded scan mode, the counter internally decodes the least significant 2 bits and
provides a decoded 1 out of 4 scan on SL0-SL3 (Four internally decoded scan lines may
drive up to 4 displays).
The keyboard and display both are in the same mode at a time.

Return Buffers and Keyboard Debounce and Control:

If a key closer is detected, the keyboard debounce unit debounces the key entry (i.e. wait for
10 ms).
After the debounce period, if the key continues to be detected.
The code of key is directly transferred to the sensor RAM along with SHIFT and CONTROL
key status.

FIFO/Sensor RAM and Status Logic:

In keyboard or strobed input mode, this block acts as 8-byte first-in-first-out (FIFO) RAM.
Each key code of the pressed key is entered in the order of the entry and in the mean time
read by the CPU, till the RAM become empty.
The status logic generates an interrupt after each FIFO read operation till the FIFO is empty.
In scanned sensor matrix mode, this unit acts as sensor RAM. Each row of the sensor RAM
is loaded with the status of the corresponding row of sensors in the matrix. If a sensor
changes its state, the IRQ line goes high to interrupt the CPU.

Display Address Registers and Display RAM:

The display address register holds the address of the word currently being written or read
by the CPU to or from the display RAM.
The contents of the registers are automatically updated by 8279 to accept the next data entry
by CPU.

PIN DESCRIPTION:
• DB0-DB7: These are bidirectional data bus lines. The data and command words to and
from the CPU are transferred on these lines.
• CLK: This is a clock input used to generate internal timing required by 8279.
• RESET: This pin is used to reset 8279. A high on this line reset 8279. After resetting 8279,
its in sixteen 8-bit display, left entry encoded scan, 2-key lock out mode. The clock prescaler
is set to 31.
• CS: Chip Select – A low on this line enables 8279 for normal read or write operations.
Other wise, this pin should remain high.
• A0: A high on this line indicates the transfer of a command or status information. A low
on this line indicates the transfer of data. This is used to select one of the internal registers
of 8279.
• RD, WR (Input/Output) READ/WRITE – These input pins enable the data buffers to
receive or send data over the data bus.
• IRQ: This interrupt output lines goes high when there is a data in the FIFO sensor RAM.
The interrupt lines goes low with each FIFO RAM read operation but if the FIFO RAM
further contains any key-code entry to be read by the CPU, this pin again goes high to
generate an interrupt to the CPU.
• Vss, Vcc: These are the ground and power supply lines for the circuit.
• SL0-SL3-Scan Lines: These lines are used to scan the key board matrix and display digits.
These lines can be programmed as encoded or decoded, using the mode control register.
• RL0 - RL7 - Return Lines: These are the input lines which are connected to one terminal
of keys, while the other terminals of the keys are connected to the decoded scan lines. These
are normally high, but pulled low when a key is pressed.
• SHIFT: The status of the shift input lines is stored along with each key code in FIFO, in
scanned keyboard mode. It is pulled up internally to keep it high, till it is pulled low with a
key closure.
• BD – Blank Display: This output pin is used to blank the display during digit switching
or by a blanking closure.
• OUT A0 – OUT A3 and OUT B0 – OUT B3 – These are the output ports for two 16*4 or
16*8 internal display refresh registers. The data from these lines is synchronized with the
scan lines to scan the display and keyboard. The two 4-bit ports may also as one 8-bit port.
• CNTL/STB- CONTROL/STROBED I/P Mode: In keyboard mode, this lines is used as a
control input and stored in FIFO on a key closure. The line is a strobed line that enters the
data into FIFO RAM, in strobed input mode. It has an interrupt pull up. The lines are pulled
down with a key closer.
14.a Describe the architecture of 8051, with its neat diagram.
In the following diagram, the system bus connects all the support devices to the CPU. The
system bus consists of an 8-bit data bus, a 16-bit address bus and bus control signals. All
other devices like program memory, ports, data memory, serial interface, interrupt control,
timers, and the CPU are all interfaced together through the system bus.

OR
14.b Describe the ports and its circuits of 8051.
8051 microcontrollers have 4 I/O ports each of 8-bit, which can be configured as input or
output. Hence, total 32 input/output pins allow the microcontroller to be connected with
the peripheral devices.

 Pin configuration, i.e. the pin can be configured as 1 for input and 0 for output as
per the logic state.

o Input/Output (I/O) pin − All the circuits within the microcontroller must be
connected to one of its pins except P0 port because it does not have pull-up
resistors built-in.

o Input pin − Logic 1 is applied to a bit of the P register. The output FE

transistor is turned off and the other pin remains connected to the power
supply voltage over a pull-up resistor of high resistance.

 Port 0 − The P0 (zero) port is characterized by two functions −

o When the external memory is used then the lower address byte (addresses
A0A7) is applied on it, else all bits of this port are configured as
input/output.

o When P0 port is configured as an output then other ports consisting of pins

with built-in pull-up resistor connected by its end to 5V power supply, the
pins of this port have this resistor left out.

Input Configuration
If any pin of this port is configured as an input, then it acts as if it “floats”, i.e. the input has
unlimited input resistance and in-determined potential.

Output Configuration
When the pin is configured as an output, then it acts as an “open drain”. By applying logic
0 to a port bit, the appropriate pin will be connected to ground (0V), and applying logic 1,
the external output will keep on “floating”.

In order to apply logic 1 (5V) on this output pin, it is necessary to build an external pullup
resistor.

Port 1
P1 is a true I/O port as it doesn’t have any alternative functions as in P0, but this port can
be configured as general I/O only. It has a built-in pull-up resistor and is completely
compatible with TTL circuits.

Port 2
P2 is similar to P0 when the external memory is used. Pins of this port occupy addresses
 intended for the external memory chip. This port can be used for higher address byte with
addresses A8-A15. When no memory is added then this port can be used as a general
input/output port similar to Port 1.

Port 3
In this port, functions are similar to other ports except that the logic 1 must be applied to
appropriate bit of the P3 register.
15.a Illustrate the serial communication in 8051, with its special function register.
There are 21 Special function registers (SFR) in 8051 micro controller and this includes
Register A, Register B, Processor Status Word (PSW), PCON etc etc. There are 21 unique
locations for these 21 special function registers and each of these register is of 1 byte size.
Some of these special function registers are bit addressable (which means you can access 8
individual bits inside a single byte), while some others are only byte addressable. Let’s take
a look at them in detail.
Register A/Accumulator
The most important of all special function registers, that’s the first comment
about Accumulator which is also known as ACCor A. The Accumulator (sometimes
referred to as Register A also) holds the result of most of arithmetic and logic operations.
ACC is usually accessed by direct addressing and its physical address is E0H. Accumulator
is both byte and bit addressable.You can understand this from the figure shown below. To
access the first bit (i.e bit 0) or to access accumulator as a single byte (all 8 bits at once), you
may use the same physical address E0H. Now if you want to access the second bit (i.e bit 1),
you may use E1H and for third bit E2H and so on.

Register B

The major purpose of this register is in executing multiplication and division. The 8051
micro controller has a single instruction for multiplication (MUL) and division (DIV). If you
are familiar with 8085, you may now know that multiplication is repeated addition,
whereas division is repeated subtraction. While programming 8085, you may have written a
loop to execute repeated addition/subtraction to perform multiplication and division. Now
here in 8051 you can do this with a single instruction.

Ex: MUL A,B – When this instruction is executed, data inside A and data inside B is
multiplied and answer is stored in A.
For MUL and DIV instructions, it is necessary that the two operands must be in A and B.

Follow this link if you are interested in knowing about differences between a
microprocessor and microcontroller.

Register B is also byte addressable and bit addressable. To access bit o or to access all 8 bits
(as a single byte), physical address F0 is used. To access bit 1 you may use F1 and so on.
Please take a look at the picture below.

Note: Register B can also be used for other general purpose operations.
Port Registers
As you may already know, there are 4 ports for 8051. If you are unfamiliar of the
architecture of 8051 please read the following article:- The architecture of 8051
So 4 Input/Output ports named P0, P1, P2 and P3 has got four corresponding port registers
with same name P0, P1, P2 and P3. Data must be written into port registers first to send it
out to any other external device through ports. Similarly any data received through ports
must be read from port registers for performing any operation. All 4 port registers are bit as
well as byte addressable. Take a look at the figure below for a better understanding of port
registers.
 From the figure:-
 The physical address of port 0 is 80
 The physical address of port 1 is 90
 And that of port 2 is A0
 And that of port 3 is B0
Stack Pointer
Known popularly with an acronym SP, stack pointer represents a pointer to the the system
stack. Stack pointer is an 8 bit register, the direct address of SP is 81H and it is only byte
addressable, which means you cant access individual bits of stack pointer. The content of
the stack pointer points to the last stored location of system stack. To store something new
in system stack, the SP must be incremented by 1 first and then execute the “store”
command. Usually after a system reset SP is initialized as 07H and data can be stored to
stack from 08H onwards. This is usually a default case and programmer can alter values of
SP to suit his needs.
Power Management Register (PCON)
Power management using a microcontroller is something you see every day in mobile
phones. Haven’t you noticed and got wondered by a mobile phone automatically going into
stand by mode when not used for a couple of seconds or minutes ? This is achieved by
power management feature of the controller used inside that phone.
As the name indicates, this register is used for efficient power management of 8051 micro
controller. Commonly referred to as PCON register, this is a dedicated SFR for power
management alone. From the figure below you can observe that there are 2 modes for this
register :- Idle mode and Power down mode.

Setting bit 0 will move the micro controller to Idle mode and Setting bit 1 will move the
micro controller to Power down mode.
Processor Status Word (PSW)
Commonly known as the PSW register, this is a vital SFR in the functioning of micro
controller. This register reflects the status of the operation that is being carried out in the
processor. The picture below shows PSW register and the way register banks are selected
using PSW register bits – RS1 and RS0. PSW register is both bit and byte addressable. The
physical address of PSW starts from D0H. The individual bits are then accessed using D1,
D2 … D7. The various individual bits are explained below.

OR
15.b Interface the ADC convertor with 8051 and explain with neat diagram.
ADC (Analog to digital converter) forms a very essential part in many embedded projects
and this article is about interfacing an ADC to 8051 embedded controller. ADC 0804 is the
ADC used here and before going through the interfacing procedure, we must neatly
understand how the ADC 0804 works.
ADC 0804.
ADC0804 is an 8 bit successive approximation analogue to digital converter from National
semiconductors. The features of ADC0804 are differential analogue voltage inputs, 0-5V
input voltage range, no zero adjustment, built in clock generator, reference voltage can be
externally adjusted to convert smaller analogue voltage span to 8 bit resolution etc. The pin
out diagram of ADC0804 is shown in the figure below.

ADC0804 pinout
The voltage at Vref/2 (pin9) of ADC0804 can be externally adjusted to convert smaller
input voltage spans to full 8 bit resolution. Vref/2 (pin9) left open means input voltage span
is 0-5V and step size is 5/255=19.6V. Have a look at the table below for different Vref/2
voltages and corresponding analogue input voltage spans.
Circuit diagram.

Interfacing ADC to 8051

The figure above shows the schematic for interfacing ADC0804 to 8051. The circuit initiates
 the ADC to convert a given analogue input , then accepts the corresponding digital data
and displays it on the LED array connected at P0. For example, if the analogue input
voltage Vin is 5V then all LEDs will glow indicating 11111111 in binary which is the
equivalent of 255 in decimal. AT89s51 is the microcontroller used here. Data out pins (D0 to
D7) of the ADC0804 are connected to the port pins P1.0 to P1.7 respectively. LEDs D1 to D8
are connected to the port pins P0.0 to P0.7 respectively. Resistors R1 to R8 are current
limiting resistors. In simple words P1 of the microcontroller is the input port and P0 is the
output port. Control signals for the ADC (INTR, WR, RD and CS) are available at port pins
P3.4 to P3.7 respectively. Resistor R9 and capacitor C1 are associated with the internal clock
circuitry of the ADC. Preset resistor R10 forms a voltage divider which can be used to apply
a particular input analogue voltage to the ADC. Push button S1, resistor R11 and capacitor
C4 forms a debouncing reset mechanism. Crystal X1 and capacitors C2,C3 are associated
with the clock circuitry of the microcontroller.
ii. Write the assembly language program to execute the ADC conversion.

ORG 00H
MOV P1,#11111111B // initiates P1 as the input port
MAIN: CLR P3.7 // makes CS=0
SETB P3.6 // makes RD high
CLR P3.5 // makes WR low
SETB P3.5 // low to high pulse to WR for starting conversion
WAIT: JB P3.4,WAIT // polls until INTR=0
CLR P3.7 // ensures CS=0
CLR P3.6 // high to low pulse to RD for reading the data from ADC
MOV A,P1 // moves the digital data to accumulator
CPL A // complements the digital data (*see the notes)
MOV P0,A // outputs the data to P0 for the LEDs
SJMP MAIN // jumps back to the MAIN program
END
Part C
16.a Develop a 8086 based system with 128 RAM and 4K ROM, to display the word HAPPY
for every 2 ms in the common anode seven segment LED diplay. Explain the delay
timings.
7 – SEGMENT DISPLAY INTERFACING:
Here common anode seven segment display is used because the output current of the
microprocessor is not sufficient enough to drive the LED’s. The circuit diagram shows the
connections of seven segment to the processor. The pins ‘a’ to ‘g’ of the Seven Segment are
connected to the Port B of the microprocessor. The common pin of the seven segment is
connected to Vcc.
The 7447 converts a BCD code applied to its inputs to the pattern of lows required to
display the number represented by the BCD code. This circuit connection is referred to as a
static display because current is being passed through the display at all times.
DATA SEGMENT
PORTA EQU 120H
PORTB EQU 121H
PORTC EQU 122H
CWRD EQU 123H
TABLE DB 8CH,0C7H,86H,89H
DATA ENDS
CODE SEGMENT
ASSUME CS:CODE, DS:DATA
START: MOV AX, DATA; initialize data segment
MOV DS,AX
MOV AL, 80H; initialize 8255 port-b and port-c as o/p
MOV DX,CWRD
OUT DX,AL
MOV BH, 04; BH = no of digitsto be displayed
LEA SI, TABLE; SI = starting address of lookup table
NEXTDIGIT:MOV CL, 08; CL = no of segments = 08
MOV AL,[SI]
NEXTBIT: ROL AL,01
MOV CH, AL; save al
MOV DX, PORTB; one bit is sent out on portb
OUT DX,AL
MOV AL,01
MOV DX, PORTC; one clock pulse sent on pc0
OUT DX,AL
DEC AL
MOV DX,PORTC
OUT DX,AL
MOV AL,CH; get the seven segment code back in al
DEC CL; send all 8 bits, thus one digit is displayed
 JNZ NEXTBIT
DEC BH
INC SI; display all the four digits
JNZ NEXTDIGIT
MOV AH, 4CH; exit to dos
INT 21H
CODE ENDS
END START
HAPPY DISPLAY:
Memory d c b a dp g f e Hex LED DISPLAY
address code
4500 1 0 0 1 1 0 0 0 98H H
4501 1 0 0 0 1 0 0 0 88H A
4502 0 1 1 1 1 1 0 0 7CH P
4503 0 1 1 1 1 1 0 0 7CH P
4504 0 0 0 1 1 0 0 1 19H Y
16.b Design a circuit to generate 12 Mhz frequency for a system. Write a program for
generation of unipolar square waveform of 1 KHZ frequency using Timer 0 of 8051 in
mode 0.
Square waves of any frequency (limited by the controller specifications) can be generated
using the 8051 timer. The technique is very simple. Write up a delay subroutine with delay
equal to half the time period of the square wave. Make any port pin high and call the delay
subroutine. After the delay subroutine is finished, make the corresponding port pin low
and call the delay subroutine gain. After the sub routine is finished, repeat the cycle again.
The result will be a square wave of the desired frequency at the selected port pin. The
circuit diagram is shown below and it can be used for any square wave, but the program
has to be accordingly. Programs for different square waves are shown below the circuit
diagram.
MOV P1,#00000000B
MOV TMOD,#00000001B
MAIN: SETB P1.0
ACALL DELAY
CLR P1.0
ACALL DELAY
SJMP MAIN
DELAY: MOV TH0,#0FEH
MOV TL0,#00CH
SETB TR0
HERE: JNB TF0,HERE
CLR TR0
CLR TF0
SETB P1.0
RET
END