9 - CH06 - Main Memory Organization

Computer Organization and Architecture
Designing for Performance

11th Edition
Chapter 6
Internal Memory
Copyright © 2019, 2016, 2013 Pearson Education, Inc. All Rights Reserved
Memory Hierarchy
• Memory Hierarchy is to obtain the highest possible access
speed while minimizing the total cost of the memory system
• Memory Hierarchy
Figure 6.20: Nonvolatile RAM within the
Memory Hierarchy
Increasing performance
and endurance
SRAM
STT-RAM
DRAM
PCRAM
NAND FLASH
ReRAM
HARD DISK
Decreasing cost
per bit,
increasing capacity
or density
Main Memory
• Main Memory: Relatively large and fast memory to store
programs and data during execution.
• RAM Chips: Static Dynamic
• Flip flops to store binary • Charge on capacitor to store
information binary information
• Volatile • Volatile
• Does not need refresh • Needs to be periodically
recharged (refreshed)
• Faster read and write • Slower read and write
• Larger size per bit • Smaller size per bit
• Expensive (cost/bit) • Less expensive (cost/bit)
• Used to build memory with • Used to build memory with
4
small capacity large capacity
Main Memory
• Main Memory: RAM and ROM chip
• Typical RAM chip
• Typical ROM chip
Memory Address Map
• Example:
 Assume that a computer system needs 512 bytes of RAM and
512 bytes of ROM, using the chips shown in previous slides:
 Address space assignment to each memory chip
– We need four 128x8bits RAM’s and a 512x8bits ROM
Connection of
Memory to
CPU
Memory Connection to CPU
•Memory connection to CPU
–RAM and ROM chips are connected to a CPU through
the data and address buses
–The low-order lines in the address bus select the byte
within the chips and other lines in the address bus select
a particular chip through its chip select inputs
Figure 6.1: Memory Cell Operation
Control Control
Select Data in Select Sense

Cell Cell
(a) Write (b) Read
Table 6.1: Semiconductor Memory Types
Write
Memory Type Category Erasure Volatility
Mechanism
Read-write Electrically,
Random-access memory (RAM) Electrically Volatile
memory byte-level
Read-only memory (ROM) Read-only Masks
Not possible
Programmable ROM (PROM) memory
UV light,
Erasable PROM (EPROM)
chip-level
Nonvolatile
Electrically Erasable PROM Read-mostly Electrically, Electrically
(EEPROM) memory byte-level
Electrically,
Flash memory
block-level
© 2016 Pearson Education, Inc.,
Hoboken, NJ. All rights reserved.
dc voltage
Address line T3 T4
T5 C1 C2 T6
Transistor
Storage
capacitor
T1 T2
Bit line Ground

Ground
B
Bit line Address Bit line

B line B
(a) Dynamic RAM (DRAM) cell (b) Static RAM (SRAM) cell
Figure 5.2 Typical Memory Cell Structures
RAS CAS WE OE
Timing and Control
Refresh
Counter MUX
Row Row Memory array

Address De- (2048 2048 4)
A0 coder
A1 Buffer
Data Input
A10 Column Buffer D1
Address D2
Refresh circuitry D3
Buffer Data Output D4
Buffer
Column Decoder
Figure 5.3 Typical 16 Megabit DRAM (4M 4)

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
© 2016 Pearson Education, Inc.,
Hoboken, NJ. All rights reserved.
A19 1 32 Vcc Vcc 1 24 Vss
1M 8 4M 4
A16 2 31 A18 D0 2 23 D3
A15 3 30 A17 D1 3 22 D2
A12 4 29 A14 WE 4 21 CAS
A7 5 28 A13 RAS 5 20 OE
A6 6 27 A8 NC 6 19 A9
A5 7 26 A9 A10 7 24 Pin Dip 18 A8
A4 8 25 A11 A0 8 17 A7
0.6"
A3 9 32 Pin Dip 24 Vpp A1 9 16 A6
A2 10 23 A10 A2 10 15 A5
0.6"
A1 11 22 CE A3 11 14 A4
A0 12 21 D7 Vcc 12 13 Vss
Top View
D0 13 20 D6
D1 14 19 D5
D2 15 18 D4
Vss 16 17 D3
Top View
(a) 8 Mbit EPROM (b) 16 Mbit DRAM
Figure 5.4 Typical Memory Package Pins and Signals

Dynamic RAM (DRAM) & Static RAM (SRAM)
• RAM technology is divided into two technologies:
– Dynamic RAM (DRAM)
– Static RAM (SRAM)
DRAM
• Made with cells that store data as charge on capacitors
• Presence or absence of charge in a capacitor is interpreted as a binary 1 or 0
• Requires periodic charge refreshing to maintain data storage
• The term dynamic refers to tendency of the stored charge to leak away, even with
power continuously applied
SRAM
• Digital device that uses the same logic elements used in the processor
• Binary values are stored using traditional flip-flop logic gate configurations
• Will hold its data as long as power is supplied to it
SRAM versus DRAM
• Both volatile
– Power must be continuously supplied to the memory to preserve the bit
values
• Dynamic cell
– Simpler to build, smaller
– More dense (smaller cells = more cells per unit area)
– Less expensive
– Requires the supporting refresh circuitry
– Tend to be favored for large memory requirements
– Used for main memory
• Static
– Faster
– Used for cache memory (both on and off chip)
+
Error Correction
 Hard Failure
 Permanent physical defect
 Memory cell or cells affected cannot reliably store data but become
stuck at 0 or 1 or switch erratically between 0 and 1
 Can be caused by:
 Harsh environmental abuse
 Manufacturing defects
 Wear
 Soft Error
 Random, non-destructive event that alters the contents of one or more
memory cells
 No permanent damage to memory
 Can be caused by:
 Power supply problems
 Alpha particles

Error Signal
Data Out M
Corrector
Data In M M K
f
Memory Compare
K K
f
Figure 5.7 Error-Correcting Code Function

(a) A B (b) A B
1 1 1 0
1 1
1 0 1 0
0
C C
(c) A B (d) A B
1 1 0 1 1 0
1 1
0 0 0 0
0 0
C C
Figure 5.8 Hamming Error-Correcting Code

Single-Error Correction Single-Error Correction/
Double-Error Detection
Data Bits Check Bits % Increase Check Bits % Increase
8 4 50 5 62.5
16 5 31.25 6 37.5
32 6 18.75 7 21.875
64 7 10.94 8 12.5
128 8 6.25 9 7.03
256 9 3.52 10 3.91
Table 5.2
Increase in Word Length with Error Correction

Bit
12 11 10 9 8 7 6 5 4 3 2 1
Position
Position
1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001
Number
Data
D8 D7 D6 D5 D4 D3 D2 D1
Bit
Check
C8 C4 C2 C1
Bit
Figure 5.9 Layout of Data Bits and Check Bits

Bit
12 11 10 9 8 7 6 5 4 3 2 1
position
Position
1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001
number
Data bit D8 D7 D6 D5 D4 D3 D2 D1
Check
C8 C4 C2 C1
bit
Word
stored 0 0 1 1 0 1 0 0 1 1 1 1
as
Word
fetched 0 0 1 1 0 1 1 0 1 1 1 1
as
Position
1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001
Number
Check
0 0 0 1
Bit
Figure 5.10 Check Bit Calculation

(a) (b) (c)
0 0 0 1 1 0 1
1 1 0
1 0 1 0 1 0
0 0
1 1
(d) (e) (f)
1 0 1 1 0 1 1 0 1
0 0 0
1 0 1 1 1 1
0 0 0
1 1 1
Figure 5.11 Hamming SEC-DED Code

Associative Memory
• Accessed by the content of the data rather than by an address
• Also called Content Addressable Memory (CAM)
• HW organization
Content-addressable memory
(CAM) is a special type of
computer memory used in
certain very-high-speed
searching applications.
• Compare each word in CAM in parallel

• with the content of A (Argument Reg.)
• If CAM Word[i] = A, M(i) = 1
• Read sequentially accessing CAM for CAM Word(i) for M(i) = 1
• K(Key Register) provides a mask for choosing a particular field or key in
the argument in A
– (only those bits in the argument that have 1’s in their corresponding
position of K are compared)
23
Associative Memory
• Example:
• Suppose that the argument register A and the key
register K have the shown bit configuration. Only the
three most bits are compared with memory words,
because K has 1’s in these positions.
•A 101 111100
•K 111 000000
• Word 1 100 111100 (no match)
• Word 2 101 000001 (match)
24
Organization of CAM
• Organization of CAM
• Internal organization of a
typical cell Cij
• Associative memory of m
word, n cells per word.
One cell of associative memory
25
Read Only Memory (ROM)
• Contains a permanent pattern of data that cannot be changed or
added to
• No power source is required to maintain the bit values in memory
• Data or program is permanently in main memory and never needs
to be loaded from a secondary storage device
• Data is actually wired into the chip as part of the fabrication
process
– Disadvantages of this:
▪ No room for error, if one bit is wrong the whole batch of ROMs must be thrown
out
▪ Data insertion step includes a relatively large fixed cost
Programmable ROM (PROM)
• Less expensive alternative
• Nonvolatile and may be written into only once
• Writing process is performed electrically and may be performed by
supplier or customer at a time later than the original chip
fabrication
• Special equipment is required for the writing process
• Provides flexibility and convenience
• Attractive for high volume production runs
Double Data Rate SDRAM (DDR SDRAM)
• Developed by the JEDEC Solid State Technology

Association (Electronic Industries Alliance’s semiconductor-
engineering-standardization body)
• Numerous companies make DDR chips, which are widely
used in desktop computers and servers
• DDR achieves higher data rates in three ways:
– First, the data transfer is synchronized to both the rising and falling edge of
the clock, rather than just the rising edge
– Second, DDR uses higher clock rate on the bus to increase the transfer rate
– Third, a buffering scheme is used
Embedded DRAM (eDRAM)
• eDRAM is a DRAM integrated on the same chip or
MCM(Multiple Chip Modules) of an application-specific
integrated circuit (ASIC) or microprocessor
• For a number of metrics, eDRAM is intermediate between on-
chip SRAM and off-chip DRAM
– For the same surface area, eDRAM provides a larger size memory
than SRAM but smaller than off-chip DRAM
– eDRAM’s cost-per-bit is higher when compared to equivalent stand-
alone DRAM chips used as external memory, but it has a lower cost-
per-bit than SRAM
– Access time to eDRAM is greater than SRAM but, because of its
proximity and the ability to use wider busses, eDRAM provides faster
access than DRAM
• Fundamentally eDRAMs use the same designs and

architectures as DRAM
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Computer Organization and Architecture

Designing for Performance

• Typical ROM chip

Select Data in Select Sense

(a) Write (b) Read

Bit line Ground

Bit line Address Bit line

Figure 5.2 Typical Memory Cell Structures

Timing and Control

Row Row Memory array

Figure 5.3 Typical 16 Megabit DRAM (4M 4)

(a) 8 Mbit EPROM (b) 16 Mbit DRAM

Figure 5.4 Typical Memory Package Pins and Signals

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

Figure 5.7 Error-Correcting Code Function

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

Figure 5.8 Hamming Error-Correcting Code

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

Figure 5.9 Layout of Data Bits and Check Bits

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

Figure 5.10 Check Bit Calculation

Figure 5.11 Hamming SEC-DED Code

• Compare each word in CAM in parallel

One cell of associative memory

• Developed by the JEDEC Solid State Technology

• Fundamentally eDRAMs use the same designs and

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