The Ultimate Optimization Solution Based On

Sign-Off timing ECO Tool

Kadan Hiba
Oren Kol
Intel

Silicon Valley
Israel

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 Agenda

ECO solution Historical View

Clock Tree Optimization
Summary

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 ECO Solution Historical View

• 2013.12
– Physical aware mode
• 2014.12
– Significant improvement of run time and hold violation fixing rate.
– MIM support
• 2015.12
Dynamic
– Improved power fixing (buffers removal, PBA guard band) Power
DRC
– Improved physical aware efficiency (check eco)
Debug
– Reduce ECO feature
capabilities Setup
• 2016.12
– Enabling clock network ECOs Clock
Optimization Hold
– Improved setup fixing (downside side loads)
• 2017.06 Leakage
Power
– Dynamic (and Leakage) Power Optimization based on SAIF.
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 Clock Tree Optimization Background

• Setup violation is demonstrated in the image

– L1 delay causing setup violation. R1 L1 R2 L2 R3

– L2 delay have high positive margin.

– In early design stage - retiming.
– In optimization stage – “Useful skew”
• Useful skew – set a none zero skew between different pipe stages in order to
resolve timing violations.
– In current example - delay R2 clock arrival time to resolve L1 setup violation.
• Risks
– Hold/Setup violation might be created (L1 hold, L2 setup)
• Some can be fixed by additional buffer insertion.
• Some are unresolvable (setup/hold violation on the same path).
– Transparent (latch) paths might appear, or worse by creating new sequential loops.
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 Automatic Clock Tree Optimization
• New “Clock ECO” allow DRC fixing on clock network and automatic timing
violation fixing using “useful skew” technique.
R1 R2
• The main capabilities are: R1 R2
R1
R1
R1 R2
R2
R2

– Clock tree sizing and buffer insertion.

– Physical aware mode (only).
– Define clock_fixes_per_change, in order to allow a single clock network change.
– Define clock_max_level_from_reg that clock opt can touch.
• Some points to notice:
– Use “clock_fixes_per_change” wisely to minimize changes on clock tree.
– Slack fixing window should be well defined while fixing clock network.
• Resolve slack of “-34567” by using useful skew is not realistic even if it is possible.
– Hold slack guard band have huge impact on setup fixing rate.
– Different buffers lists for different clock types.
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 Different Approaches of Clock Optimization

Reference flow • Fix clock (post setup) –

– On case of unfixed setup violations, allow touching clock network
to resolve leftovers.
Fix Clock (pre setup)
– Cost of clock vs. data fixing might vary according to design nature
fix_eco_timing -setup • Fix clock (pre setup) –
– Early optimization of clock network at “high ROI” points to reduce
Fix Clock (post setup) amount of changes during “fix_eco_timing -setup” on data.
• Data/clock interleave fixing (in loops)
Fix Clock (pre hold) – Showed low to none benefit, with a run time hit.
• “Fix Clock” method can be either size or buffer insertion.
fix_eco_timing -hold
• Same clock stages for hold fixing as well.
Fix Clock (post hold)

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 Hold Guard Band Sweep During Setup Fixing
• The following graphs show Setup fixing rate while allow different hold margin
degradation (from 0 down to -500), followed by hold fixing optimization.

Design A – Un-converged setup start point Design B – Converged setup start point
100.00% 60 100.00% 30

90.00%
90.00%
50 25
80.00%

70.00% 80.00%
40 20
60.00%
70.00%
50.00% 30 15
60.00%
40.00%
20 10
30.00% 50.00%
20.00%
10 5
40.00%
10.00%

0.00% 0 30.00% 0
0 50 100 150 200 250 300 350 400 450 500 0 50 100 150 200 250 300 350 400 450 500

Setup TNS Improvment Hold TNS Improvment # Clk Sized Cells # Clk Buffers Setup TNS Improvment Hold TNS Improvment # Clk Sized Cells # Clk Buffers

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 Setup Fixing rate Using Different Strategies

88.07%
88.03%

88.02%
88.00%
88.00%
90.00%

81.73%
80.00%

70.00%

59.16%
60.00%

49.75%

49.74%
49.72%

49.72%

48.36%
45.03%
50.00% 35.13%

40.00%
29.11%
28.82%
28.81%

25.58%
24.53%

23.72%

23.55%
30.00%

15.90%
15.89%

15.84%

20.00%
12.88%

12.24%
12.20%

12.20%
10.92%

10.70%

10.00%
DESIGN-A DESIGN-B DESIGN-C DESIGN-D DESIGN-E DESIGN-F

SNUG 2017 NoClkOpt Sizer0 Sizer250 Bfr0 Bfr250 8

 Setting clock_fixes_per_change=1
During Clock Optimization
• Setup TNS improvement (in %) and additional inserted clock buffers (in Ratio),
comparing using clock_fixes_per_change of 1 vs 4.

20.0%
x11.1
11
16.4%
x9.6

15.0% 9

10.0%

5.0% x2.7 3
3.6%
x1.9
x1.6
x1.0
0.6% 1
0.2%
0.0%
0.0%
-1

-3.1%
-5.0% -3
Additional Improvement Additional Clock Buffers Ratio
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 Clock-ECO Back Annotate Recommendations

• Physical aware is a must and open_site is highly recommended.

– Minimize changes on clock network during back annotation.
– The importance of it increase on cases of high density designs.
• As ECO change list contain both clock and data changes:
– Should legalization of clock/data cells have the same priority?
– Should a single route-eco resolve both clock and data nets?
– Does clock nets need special attribute manipulation (Clock/User-Signal)?
– Does your clock network contain special routing constraints (CTS vs. MS-CTS)?
• Back Annotate Flow recommendations:
– Follow Minimum Physical Impact (MPI) guidelines.
– Reduce to minimum special routing constraints (ex: layer constraints)
– In order to minimize DRC on highly congested areas, avoid in advance performing ECO on
those areas.
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 Summary

• Latest ECO solution deliver almost a full span of capabilities to efficiently

resolve all optimization domains (Timing, Power, DRC, etc.)
• The new clock network optimization bring those capabilities to a new level.
– Clock cells sizing has a significant lower impact vs. buffer insertion solution.
– Efficient setup fixing requires (recoverable) hold degradations.
– The “cost” of clock ECOs comparing to data optimization should be wisely set.

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 Thank You

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