AS362016ENGRR34

VERIFICATION OF VERILOG MODEL OF
NEURAL NETWORKS USING SYSTEM VERILOG
As
SC
A thesis submitted to the faculty of
San Francisco State University
EtiGtR In partial fulfillment of
the requirements for
. 'RSH- the Degree
Master of Science
In
Engineering: Embedded Electrical and Computer Systems
by
Prashis Raghuwanshi
San Francisco, California
August 2016
Copyright by
Prashis Raghuwanshi
2016
CERTIFICATION OF APPROVAL
I certify that I have read “ Verification o f Verilog Model o f neural Networks using System
Verilog” by Prashis Raghuwanshi, and that in my opinion this work meets the criteria for
approving a thesis submitted in partial fulfillment of the requirement for the degree
Master of Science in Engineering: Embedded Electrical and Computer Systems at San
Francisco State University.
Professor of Electrical and Computer
Engineering
3 1> v a * - j
Xiaorong Zhang
Professor of Electrical Engineering
VERIFICATION OF VERILOG MODEL
OF NEURAL NETWORKS USING SYSTEMVERILOG
Prashis Raghuwanshi
San Francisco, California
2016
Developing hardware to mimic neural networks in the brain is becoming more realizable
as technology advances and improves. In this research, a model of neural networks for
visual edge detection is analyzed. The various challenges in verifying the models of a
neuron and a complex cell are taken into consideration. The research presents a
verification model for the neuron and complex cell hardware using Verilog as well as
System Verilog
I certify that the abstract is a correct representation of the content of this Thesis
Date
ACKNOWLEDGEMENT
I would like to acknowledge Professor Hamid Mahmoodi for being my graduate advisor
and providing the software and hardware tools necessary to complete my research. I
would also like to thank Professor Xiaorong Zhang for being on my committee for my
Master’s thesis oral defense.
V
TABLE OF CONTENTS
List o f Figures............................................................................................................................... vii
List o f Figures...............................................................................................................................viii
Introduction.....................................................................................................................................1
Background Design of Neuron M o d el.......................................................................................9
Integrater....................................................................................................................... 11
S u m T h resh o ld.............................................................................................................. 18
Ganglion Cell M odel.................................................................................................................. 27
Verification Model using System Verilog................................................................................. 38
Neuron Model using System V erilo g ...................................................................40
Conclusion......................................................................................................................................48
Future Scope.................................................................................................................................. 49
References...................................................................................................................................... 50
Appendix.........................................................................................................................................51
VI
LIST OF FIGURES
Figures Page
I. Code Snippet showing plasticity logic............................................................................4
2.1ntegrater waveform displaying integrated values.........................................................1
3. Snippet o f SystemVerilog code of Integrater..............................................................13
4. Self Checking o f the design............................................................................................14
5. Interface module of Integrater DUT............................................................................. 15
6. Functional coverage of integrater DUT........................................................................ 16
7. Snippet o f Sum Threshold Verilog M odule................................................................ 18
8. Code Snippet o f Scoreboard...........................................................................................19
9. Scoreboard in Sum Threshold M odule......................................................................... 19
10. Self checking o f Sum Threshold module...................................................................20
II. Functional coverage o f S u m T h resh o ld.................................................................... 22
12. Simulation waves in Verilog........................................................................................ 23
13. Zoomed in version o f Sum threshold w aves............................................................. 24
14. Simulation of Sum threshold module in SystemVerilog......................................... 25
15. Receptive Field of a Biological Ganglion/ Concentric Circle C ell........................27
16. Receptive Field of a Pixelated Ganglion/Concentric Circle Cell........................... 27
17. Code Snippet o f Ganglion C ell.....................................................................................28
18. Simulation of Complex Cell using Verilog................................................................29
VII
19. Simulation o f Complex Cell using SystemVerilog.................................................. 30
20. Simulation o f Complex Cell using SystemVerilog.................................................... 31
21. Function Coverage o f Complex Cell............................................................................ 32
22. Functional Coverage o f Complex Cell with bins....................................................... 33
23. Randomization logic in SystemVerilog testbench..................................................... 34
24. Scoreboard o f Ganglion C ell........................................................................................ 34
25. Self checking code Snippet............................................................................................ 35
26. Functional Coverage code Snippet in SystemVerilog............................................... 36
27. The testbench - design connection............................................................................ 37
28 Testbench Environment................................................................................................... 38
29. Neuron M odel...................................................................................................................39
30. Scoreboard for N euron....................................................................................................41
31. Scoreboard for Neuron Model.......................................................................................41
32. Snippet of Scoreboard for Neuron M odel.................................................................... 42
33. Self checking module o f N euron.................................................................................. 43
34. Simulation of Neuron Model in Verilog......................................................................44
35. Simulation o f Neuron Model using SV testbench......................................................45
36. Zoomed in figure of Simulation o f Neuron model using SV................................... 46
VIII
1.INTRODUCTION
As the hardware becomes more complex, as more transistors can be packed into a single
chip , the verification of complex designs is becoming increasingly important.
Verification consumes 60% to 75% of the total design cycle and is on the critical path in
the design flow o f billion gate Application Specific Integrated Circuits. The best and
easiest way to verify design is to write a test bench. A test bench is mimic o f the
environment in which the design resides. A good test bench is one that verifies the design
performs every function that it is supposed to perform. There are different methods to
write a good test bench which are also known as Methodologies. In this Research,
different methodologies have been used to verify the design o f Neuron Model and a
Complex Cell. One of the methodology is of the self checking test bench. In self
checking test bench, the expected output is checked against the actual outputs. The
technique o f self checking reduces the amount o f effort needed to check design again
after DUT has been modified. Debugging time is reduced significantly by useful error
tracking information that can be built into the Test bench to show where a design fails .
Self checking test bench consists of Input and Output blocks. Input block consist o f
stimulus and driver to drive the stimulus to DUT. The System verilog provides an object
- oriented programming model. In System verilog, classes support a single - inheritance
model. The polymorphism features are similar to those o f C++. Features like
Encapsulation and data hiding is accomplished using the local and protected keywords.
The System Verilog new features include various C type data types
a) int
b) typedef
c) struct
d) union
2
e) enum=
System Verilog supports different data types like struct, classes , dynamic queues ,
dynamic arrays. In our thesis , all the features of SystemVerilog has been used in writing
the Testbench .
3
II.BACKGROUND DESIGN OF NEURON MODEL
The Neuron Model is a proto type of proposed feed forward network model by Hubei
and Weisel's. In this model, the integrate and fire neurons are used to model the simple
and complex cells for light orientation detection.
In Neuron Model, multiple synapses are used as inputs and one axon signal for the
neuron output . Each are one bit wide. The neuron model receives input in the form o f
digital pulses and integrates the pulses over a period o f time and updates an integrated
value for that input. When a neuron input receives a pulse within a clock cycle , the
integrated value increases by a constant preset value representing the weight o f a synapse.
The Neuron Model consists of two main modules
• Integrator
• Sum Threshold
Integrator
The input is given to Integrator in form of a digital pulse. It can take the value o f wither
0 or 1. The Integrator block consists of flip flops and gates. The logic for synaptic weight
is included in the Integrator block. There are two reset blocks included in the Integrator.
The add plasticity and subtract plasticity can be manually set . It is a 7 bit value. The
values can range from 0 to 255.
In this neuron schematic, note that any input alone can make the neuron fire provided
that that input fires frequently enough to produce an integrated value higher than the
threshold.
4
In both neuron models, integrated values are reset whenever the threshold in the
neuron is reached. Also note that this model does not update its synaptic weights since
there is no learning mechanism used in this neural network. Networks used in pattern
recognition or learning use models that update their synaptic weights, but in this model,
the updating o f synaptic weights is not required so they remain constant.
alw ays#fposedg e c lo c k )
beg in
if (r e s e t ~~ r b l j | re set_tw o = r b l)
in te g ra te d _ v a lu e ~ S;
e ls e i f (e d g e _ d e te c te d == r b l ) / / add to in t e r g r a t io n v a lu e on an o u tp u t neuron edge
begin
if (iin te g r a te d _ v a lu e + a d d _ p la s t ic it y ) >- m a x j/a lu e )
in te g ra te d _ v a lu e •- m ax_value
e ls e
in te g ra te d _ v a lu e in te q ra te d _ v a lu e t a d d _ p la s t ic it y
end
e ls e
begin
if >s u b t r a c t _ p la s t ic it y in te g ra te d _ v a lu e )
in te g ra te d _ v a lu e <= f);
e ls e
in te g ra te d _ v a lu e <= in te g ra te d _ v a lu e s u b t r a c t _ p la s t ic it y ;
end
end
Figure 1: Code Snippet showing plasticity logic

Figure 2: Integrater waveform displaying integrated values
In figure 2, the selected blue line shows the Integrated values at every clock cycle. The
first wave in the figure is the Neuron Input which tracks the Inputs given to our Design.
At When the reset and reset two are set to low ,the DUT starts showing the output. Then
last threshold input is the register that stores the output. The last threshold input is low
for the clock cycles for which edge detected is high
In the Integrator model, the logic for add plasticity , subtract plasticity, maximum value ,
integrated value is defined. We have two reset in the Integrator block.
Initially both the resets are high. In this condition Integrated value is set to zero. The
module starts working when both resets are set to zero. If the edge is detected, the
module starts working.
6
The edge is detected for the clock cycles at which neuron input becomes high and last
neuron input is low. The last neuron input s a register which stores the input to neuron.
The max value is a preset parameter which takes the value up to 255. The Integrated
value gives the 7 bit output which would be given as Input to the Sum Threshold module.
Generating Random Stimulus Using Integrater
logic neuron_input = 6 ;
logic reset;
logic reset_two ;
logic {7:©J add_plasticity;
logic 17:©3 subtract_.plasticity ;
logic [7:6] integrated_value;
logic 17.6] new_value;
int i,count;
lnt edge_detected =©;
int max value * 255;
int output_value = 0;
covergroup funct; //Functional Coverage for neuron input

cove r p o m t In teg rate r _if.add_plasticlty
{option. auto_bin_max » 4; }
endgroup
covergroup funct2; //Functional Coverage for input add plasticity

coverpoint Integrate r J L f .subtractjplasticity
( o p t i o n .auto J>injnax = 4;>
endgroup
/*
class good_sum;
rand bitll:0] neuron_input;
constraint c_ range i neuron_input inside{l i:©]}; 3; V
// constraint Limit {neuron ji.nput. s i z e O = » 2 ; }

// constraint Limit{neuron_input. sizet) inside{{1;0)};};
task edg e _ d e t e c t { );
Integrater_if reset * 1;
In teg rate r _ i f .re set_two * 1,
*10 Inte g r a t e r _ i f .reset = 0;

#1© Integ r a t e r j i f ,resetstwo = O;
I n t e g r a t e r _ i f ,addjjlasticity « 10;
In t e g r a t e r _ i f .subtractjplasticity * 4;
*10 Integraterîf>add_plasticity = 12;
*10 Integrater__if, subtractjjlasticity « 3; |
*26 I n t e grater_if.add_plasticity = $urandom_range(©, 128};
*20 In t e g r a t e r _ i f .subtract_plasticity = $urandom_range CO,128);
Figure 3: The figure shows the snippet o f System Verilog code o f Integrates
In the figure , the code the test bench o f System Verilog is displayed. The logic data type
is used to define inputs and output ports. The covergroup function are defined for
coverpoints. The data would be sampled before the posedge clock. The add plasticity and
7
subtract plasticity are randomized to get (0,128) data bytes. The $urandom is used to
generate uniformed data.
Self Checking
i f (n ew ..value i» teg » at«td ,.ya V «« ) j

begin
Sdi ssf/U yrit i s not a watch

«<d
e ls e
o u tfit value x l<it«*9fat.er_ i f . integrated,vatu*;

Sdi splay (*Outputn*alti* i s %d* ; <>«tpwt_vaiu« j ;
S d is p 'U y C it is a w atcirh
e« d task : s« tf_ c h * ek
fiirtct functadd p l a s t i c i t y - nawit,

fu n ct2 f«Hlcr»ut)triK:t_j>V»*tt< l ty - new'.):
i n i t i a l ta y m
repeat< lets?
be g in
d r iv « r ( ) ;
wjge d o t« c t{ > ;
s e lf c h ec M i ;
«nd
rep e at <88>|N I« te g r a t* r .c b )
iwsgii'
e d g « _ d e t« tt? };
d r i v e r ! );
8
Figure 4 : Self Checking o f the design
Figure 4 shows the Self checking logic and self checking report o f the Integrater module.
The self checking o f the design is a automatic result validation feature. In the Integrater
DUT, if new value is equal to the output integratedvalue, the self check is successful
and message is printed, “Self Check Successful” else “Not Successful”
The self checking for Integrater is successfully implemented for thousand cycles. In the
scoreboard, the expected output logic was build using plasticity. The plasticity is added
and subtracted in accordance with the condition that threshold reached is true or false.
For the self checking of the Integrater module, we ran it for 1000 cycles.
Integrator M odport:
Mtyortamjestklockingcb^tpyt utfjratenwet, outputttiiffljRtpit, inputiitwlHow, input utjialwjw, inputiatjatyttrft, inputintjalaefotir, inputmtjaluejive.inputiiâltiniuptiatjrali»-sw«/ iapat int.
valwtt#, \ m ifitjalyejsiae, input i»tjalMj«f input tUnsholdjnliie);
endirtterfac*
Figure 5 : Interface module of Integrater DUT
In figure 5 , the modport is used for giving directions to signals. This is a better technique
as the output signals and input signals to the DUT are clearly defined
Functional Coverage: To measure Functional coverage, we begin with verification plan
and write an executable version of it for simulation. In the System Verilog testbench, we
sample the values o f variables and expressions. These sample locations are known as
coverage points. Multiple cover points that are sampled at the same time (such as when a
transaction completes) are placed together in a cover group.
Dashboard
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D m : TuwApr 19 01:22 51 2016

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10
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T o ta l G r o u p s C o v e r a g e S u m m a ry
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d a s h b o a rd | hierarchy I modfcst i g r o u p s | t e s t s j asserts
a n g g M m s m msmrn so% p % ?o** m % ,w** 100%
Figure 6: Functional Coverage o f Integrater DUT in Systemverilog
The figure shows the Functional coverage report generated for Integrater mnodule. The
functional coverage report is generated after simulating the waves and running following
commands on UNIX Shell
vcs -sverilog -n tb opts dtm filename.sv
urg -d ir simv.vdb
The report would be generated in the urg directory The directory should be downloaded
to the computer and run with default browser. This process is known as Extraction o f
Coverage Report
We got 100% functional coverage o f an Integrater. The cover groups were defined on
the add plasticity and subtract plasticity. Both are 8 bit Inputs which are randomized and
varied after certain clock cycles. The two cover groups were defined and each cover
group had one cover point
Sum Threshold
In the proposed Neuron Model , sum is done in the Sum Threshold block. Each input to
the Sum Threshold block is o f 7 bits. The summation o f 10 Integrators is the Neuron
Output.
The Neuron output value is compared with the threshold reached value. If the Neuron
output value is greater than the threshold reached value, the proposed model gives the
output. The logic is the implementation o f Hubei’s and WeisePs model. This logic is
used for firing a Neuron when the Neuron output value crosses the value o f action
potential.
there are ten Integrators . The output of each Integrator is sent to Sum Threshold. The
summation o f 10 Integrators
The threshold reached is calculated by given equation
Threshold reached = in tv a lu e o n e + int value two + int value three + int value four +
in tv a lu e f iv e + in tv a lu e s ix + in tv a lu e s e v e n + in tv a lu e e ig h t + in tv a lu e n in e +
int value ten > threshold value
In the Verilog M o d el, the threshold value is p re se t. In the testbench o f Verilog m o d e l,
the threshold value is varied after certain period o f clock cycles. The threshold value is
varied among clock cycles to check against possible failures.

12
Threshold Logic :
threshold__reached » int_valuejone + int_value_jtwo + int value three + int value four ♦ int value five + int v<
Figure 7: Snippet o f Sum Threshold Verilog module
In the figure 7, the logic o f thresholdreached is shown. The thresholdreached is
calculated by addition o f all inputs given to Sum Threshold. After the addition , the final
value is calculated by comparing the final value with the threshold value
Scoreboard :
Scoreboard is responsible for the comparison purpose. It is used for comparing whether
the expected output matches with the actual o u tp u t.
tasfc scoreboardU,
begin
g is tm f.c b );
begin
estimated_val«t « upvalue,, one + ii»t_vaiue_two t int_valu«_three <■ u pv alue Jour + w t_«lue_five ♦ u»t_valu«_six + wt_value_seven * int_val««_eight ♦ in tja lu e ju n e + int_value_ten j
ifiestLaatedjalue tb f«sho reachedI
$display{*Stor«d values matches the expected output * ,estiiaated value?;
else
$display{*stored values does not match the expected output: %d*,esti$ated_val«eS;
if!thfeshold_reached s* thresholdjalue)
$dtsplay(‘ £sti«ated output from Scoreboard is tf.threshold value},
else
Sdisplayi*Estimated output trm Scoreboard is \3\su*ji,threshold_vaU ie) :
end
end
wdtask , sto»e;»ard
Figure 8: Code snippet o f Scoreboard

13
Threshold reached 100

Stored values matches the expected output 0
Estimated output from Scoreboard is 100
It is a match. Self checking of design is done
randomized1 threshold_value 1GG
Figure 9: Scoreboard in Sum Threshold Module checks for the threshold conditions and
displays the results
In the figure 8 , the estimated value is the estimate o f the outputs coming from the DUT.
If the threshold reached is greater than threshold value, the estim ateoutput is displayed.
The scoreboard is used to keep the scores o f the estimated output from the DUT. It is a
14
good way of estimating expected outputs as the designer and verification engineer has
sense o f the expected output values
In figure 9, the proposed Scoreboard in Sum Threshold Module checks for the threshold
conditions and displays the results
Self C h eck er:
task self_check();
begin
sum_if,cb);
begin
if (estimated,,value ==th resholdm reached)
begin
SdisplayClt is a match. Self checking of design is done”');
end
else
begin
Sdisplay(‘Test cases does not match1 @ \t", $ realtime);
end
end
end
endtask : self_check
Figure 10: Self checking o f Sum T hreshold module in Systemverilog
In figure 10, the self checking logic snippet is shown. If the threshold reached is equal to
the estimated value which is output from scoreboard , the text message is printed ,”It is a
match” else message is printed, “Not a match” .

15
Functional Coverage : Functional coverage is a measure of which design features have
been exercised by the tests. We start with the design specifications and create a
verification! plan with a detail list o f when to test and how. The coverage tools gather
information during simulation and then postprocess it to produce a coverage report.
Functional coverage is tied to the design intent and is also known as Specification
coverage.
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16
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Figure 11: Functional coverage o f Sum Threshold
In the figure I I , the functional coverage reports are displayed. To get 100% coverage,
we run more simulation cycles and tried using new randomization techniques. As we can
see from this figure, SystemVerilog automatically creates bins for cover points. It looks
at the domain o f the sampled expression to determine the range o f possible values. The
cover group option auto-binrnax specify the maximum number of bins to automatically
create, with a default of 64 bins. It looks at the domain of the sampled expression to
determine the range of possible values. For an expression that is N bit wide, there are 2 to
power N possible values.

17
Sum Threshold Simulated Waveforms :
Sim:1715
t D-int_valuejightj?:0]
+ D-int_value_nine[7:0]
+ D-int_value_ten[7:0]
+ D-threshold_value[11:0]
(-►clock
-Dneuron_output
■.^-thresholdjeached
Figure 12: Simulation waves in Verilog
Simulation o f Sum threshold waves in Verilog is shown in figure 12. The values for
input are in tv a lu e o n e to int-value_ten. The values are given manually after delay o f 5
nanosecond clock cycles. In this case, the clock period is 5 nanoseconds. By increasing
the clock period, the frequency of clock would decrease. It is better to keep the clock
period low to attain the better frequency for clock.
18
+ £>-int_value_one[7 0]
♦ £>int_value_two[7:0]
+ D-int_value_three(7:0]
+ d - int_v al ue _four[7:0]
+ D-int_value_five[7:0J
+ D-int_value_six|7:0]
+ D-int_value_eight(7 0]
-i- D-int_value_nine[7 0]
+ D-int_value_tenp:0]
+ D-threshold_value[11:0)
■-o-clocK
-D integraterjeset
-E>neuron_output
n.thresholdjeached
• I lastjhreshold
■New Group
Figure 13: Zoomed in version o f Sum Threshold waves in Verilog
As shown in figure 13, the int value one to int value ten are shown. The values are
Set manually in Verilog. The threshold reached becomes high for clock cycles for
which the threshold is reached which is computed in the logic shown in figure.
We ran the simulation for 1000 cycles and then ran it for 2000 cycles. By running for
more cycles, the functional coverage was improved.
■
19
Figure 14: Simulation of Sum Threshold module in SystemVerilog
As shown in figure 14, the int values one to in tv a lu e s te n are randomized using the
random() function in SystemVerilog. The last threshold is a register that stores the
values of inputs given to the design.
20
III. Ganglion Cell Model
The output from ganglion cells in the eye and concentric cells from the LGN best respond
to dots of light stimuli. The receptive field for this construct is a circular field (figure 15)
with an antagonistic response between the center and its surround, somewhat resembling
the picture o f a target. In biology, the ganglion cell and concentric cell’s output is a
measure of the difference in illumination between the circular center and it’s surround o f
the receptive field. A higher difference in illumination between the center and its
surround results in a greater frequency o f action potentials produced by the ganglion cell
and vice versa. The biological ganglion cell is also specialized in detecting rapid changes
in light but that feature is not modeled in the digital model.
In this digital model (figure 16), a ganglion cell takes a grayscale value o f a pixel and
compares the average o f the grayscale values of all neighboring pixels. The greater the
difference between the center grayscale value and its average o f the surrounding
grayscale values results in a greater frequency o f digital pulses output for that pixel. This
sort o f abstraction is used to mimic the concentric circle receptive field in the eye for this
model. The digital model of the ganglion cell and concentric circle cell is essentially an
indicator of the difference in grayscale values between a pixel and its surround average.
This model uses off-center ganglion cells which respond best to illumination (or high
21
grayscale values, white) on the surround and darkness (or low grayscale values, black) on
the center. The greater the difference between the surround grayscale average and the
grayscale center results in a higher frequency of pulses output from the
ganglion/concentric circle cell.
Biological Ganglion Cell Receptive

Field
O ff Center On Center
Figure 15: Receptive Field of a Biological Ganglion/ Concentric Circle Cell
Digital Ganglion Cell Receptive Field
On Center O ff Center
— — — + + +
— + mmmmm — +
+
— — — + + +
22
Figure 16: Receptive Field of a Pixelated Ganglion/Concentric Circle Cell
In figure 15, the Receptive fields are turned on and off in the digital model. The ‘+ ’ signs
denotes on and denoted off.
In the Verilog model o f Ganglion C e ll, there were different oscillations. Each oscillation
is varied by addition of values to the surround sum as shown in figure 16.
always@(posedge clock)
begin
if ((middle_center * 8) > {surround_sum + 25))// max fast oscillation
counter_threshold_on <= 0;
else if ((middle_center * 8) > {surround_sum + 20))// ultra fast oscillation
else if ((middle_center * 8) > (surround_sum + 15))// super fast oscillation
else if ((middle_center * 8) > (surround_sum + 10))// very fast oscillation
else if ((middle_center * 8) > (surround_sum + 5))// fast oscillation
else if ((middle_center * 8) > surround_sum)// normal oscillation
else //if (surround_sum == (middle_center * 8))// slow oscillation
begin
if {oscillation_counter_off >= counter_threshold_off)
begin
oscillation_counter_off <= 0;
ganglion_output_off <= ~ganglion_output_off;
end
else
begin
oscillation_counter_off <= oscillation_counter_off + 1;
ganglion_output_off <= ganglion_output_off;
end
end
Figure 17 -: Code Snippet o f Ganglion Cell Module
In figure 17, the Verilog code o f Ganglion cell is shown. In this figure, the different
values o f middle centre is compared with surround sum. Based on those values, the rate
23
od oscillation is decided. The counter-threshold is also computed with respect to the rate
o f oscillation.
RESULTS OF COMPLEX CELL
>to p _ le ip
D-t3p_center(7 0|
D-topjigp]
D-PiiSdlejeftJ? 0|
D-nijdlejefp
1050->MZ9
Figure 18: Simulation o f Complex Cell using Verilog
As seen in figure 18, the simulated waves o f Ganglion-cell are shown. Each input to
G anglionC ell DUT is o f 7 bits. The counter threshold is calculated for each value o f
24
these inputs as inputs change after clock periods. Based on the computation, the state o f
counter threshold is decided. The counter threshold has two states
a) counter threshold on
b) counter threshold off
|"iT;TFTT^^W'?T6F(T37pT7^^(^lTYr65yi7yir(Hijfir);Ti3)W^T^'3rfr66jl~flTi c6
198->230 ; ■ - : ■ : '■
196->230 : . - . : .
♦ B-wddle.centeffl MTTJ21}79*MO(^221(253|'i7]'2F]r50%,98(w^13?^122S1k)23 |7if]|11CJ'59f14nO?fU4J2DDfTTm>44\53}**3!20«{97'(202!27fwf

4 D-middle_nghl|/ 0| 205->206 |l23yr^£4ay2TfeTfT~yF5YB^| jTTFfi6?f^TTT),2oTyTFjTsFfiir^llgy^TysFyTFgITyTeFyioF.rsF{'IF^TTTfTTTfTio'^llF^T?Tj^^TaTjTo?(IT?T4eT^
4 D-5D»0«l_le(tl Oj |~^Ti4y23y55~j[7TfiTfi66)[T93^1^^[:lTyv^(T^friT)(l23^^ f3rfTFf737n3X5r)[HoyiSSy7r][T54^0iyTTr|T99~fTl5 ;Ti3yi26'in
4d-DD«om_m:oolepC] 153->236 ^l^TEqT 36)[^(Tr](Tr(^(ir)[t^3|2 ^ e ^T^^^^^T6C^T^Tr][Tir(TTr^3rj(ir][Ta2jl^T2l)f2FyT66^^
♦ B-Dottomjigh(70j
JiEiDGi)L3iKE)IDin^^
clock
: -oginglion.ctfputjlf
- -oganghon_CLlput_Dn
innn_JUL_Jinnjuui_nnfliuiii ;
♦ • Jurround_'tfB[100| 106M 429H B
4- G oscHlaaon_ccijnter_offI6 0]
♦ C :ounter_tnreshold_cfl(6 3|
f CDscill3llon_ccinter.on;e 0|
wiLLtM
4 0 CDunler_tn'esnold_cr|60|
-New Group
Figure 19: Simulation o f Complex Cell using System Verilog
As shown in figure 19, the SystemVerilog testbench of ganglion cell is simulated. Each
input is of 7 bits. We have randomized each input. At every posedge clock cycle, the
randomized data is driven to the DUT using task driver. We have randomized each input
25
so as to test the DUT for maximum number of test cases. This method tests the DUT for
maximum possible test cases.
J........ 127 1& '4> 9 ▼| b: i .j s b b

b1 , . . ,
; ® @ -a ®-.®l J i
01:19950
r REF
Name Value (17500 . 118000 (18500 . [19000 , (19500
I...I— t— .1 1... j ....l i i 1 i i r i 1 i » t t 1 t t t i I i. i i i 1 i i i i 1 i i i t 1 i i i i I i i t -
iroupl
Lt>topjelll?:0] 8'h01->8'h05 j
i- o-top_center[7:OJ 8’h01->8'h03 01 J 04 J 01 J 06 J 01 J 06 | 01 | 04 J 01 j 07 j 01 J 07 | 01 J 06 J 01 f 00 j 01 \ 00 | 01 J 07 J 01
[ D-top_right(7:0| 8'hQ1->8'h00 01 | 02 { 01 I 05 | 01 { 03 J 01 | 03 J 01 { 03 J 01 f 00 | 01 J 07 J 01 J 07 J 01 f 02 J 01 | 04 J 01
►t>middlejeft(7:0] 8'h01->8'h07 01 ][ 04 | 01 j 05 J 01 j( 07 J 01 J 06 J 01 J 07 j 01 \07 J 01 | 03 J 01 | 04 | 01 J 05 [ 01 ( 06 \01

f D-middle_center[7 0] 8'h01->8'ti07 01 | 02 } 01 J 06 | 01 { 00 | 01 J 03 { 01 J 06 { 01 J 03 | 01 j 00 \01 | 07 J 01 J 00 ( 01 | 06 j 01 | 03 J 01
Id-middlejight[7:0] 8'h01->8'h06
f D-bottomJell(7:0J 8'h01->8‘h05 01 | 05 J 01 J 06 J 01 J 04 | 01 J 06 | 01 f 03 J 01 J 04 j 01 j 07 J 01 J 07 J 01 | 06 J 01 J 05 { 01 J 02 J 01 I
I d-bottom_middle[7:0] 8'h01->8‘h05
i-D-bottoiiijighl{7:0] 8'h01->8'h04
" D - clock StO->St1
• -d ganglion_output_off St1->StO : i r i n ............ r
-o ganglion_outpul_on sto _ _ . . . . . . . . . . . . . . . : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . :. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ .. _
i-n . surround_sump0:0] 11’h008->11'h023
\-0 oscillation_counter_ofT[6:0] 7'h03->7'h00 o o o o o i 'o i ii o H o t a o o o f f a f f a o o t a o 'o o 't a o 'i ii
• DcounterJhresholdjtl[6:0] 3->127 127 I3 | 127 | O f 127 J 3 J 1271 2 \ 127 j 2 |l2 7 | 0 | 127 { 0 J 127 J 3 I
[-0 oscillationjounterjn{6... 7'h01->7'h02 D o a o a a i a a a a a a a a a a o a a a a Q a o a

►- Dcounterjhreshold_on[6:0] 127
LNewGroup
m poo 4000 jouuo pooo .10000 .12000 .14000 mm poo m
p i * * 11It 11 i H i l l f t t l f It t t 1f t t 1t 1t t I »{ f it 1 I t 11t I i 1111M i l l 1I U 1t t H { 1111t t 11. 11 It M t I t 1f 1f 1l 111I t 1 1fflL
<| 1 >1 1 1 |« l IM <
ganglion_top.dutciock St1 (|| » finished: ganglionjop 19950s " If jB U H n

.. 1 • ,/V OTj M
Figure 20: Simulation o f Complex Cell using System Verilog
As seen in the figure, each o f the input is randomized for every clock cycle in
SystemVerilog testbench. All signals before the signal clock are our input. All output
signals are arranged after the clock signal.
26
FUNCTIONAL COVERAGE OF COMPLEX CELL
dashboard | hierarchy) modlist | groups | tests | asserts
Total Groups Coverage Summary

SCORE W EIG HT
100.00 1
Total groups in report: 1
SCORE W EIGHT GOAL NAME
100.00 1 100 ganglion_top.t::funct
dashboard | hierarchy | modlist | groups | tests | asserts
liM t liM — E ? 40% 50% 60% 70% 60% 90% 100%
Figure 21: Functional Coverage o f Complex Cell
In the research, we got 100 percent functional coverage for the complex cell module.
There were eight cover groups defined. Each cover group contained one cover point.
Each cover point is a 8 bit value which is randomized and taking random value at each
clock cycle.
27
Group : ganglion_top.t::funct
SCORE W E IG H T GOAL
100.00 1 100
S u m m a ry fo r G ro u p g a n g lio n _ to p .t::fu n c t
CATEGORY EXPECTED UN COVERED COVERED PERCENT

Variables 4 0 4 100.00
V aria b le s fo r G ro u p g a n g lio n _ to p .t::fu n c t

V A R IA B LE E X P E C T E D U N C O V E R E D C O V E R E D P E R C E N T G O A L W E IG H T
ganglion Jf.to p J e ft 4 0 4 100.00 100 1
G o to top
S u m m a ry fo r V a ria b le g a n g lio n J f.t o p J e f t
CATEG O RY EXPECTED UNCOVERED COVERED PERCENT
Automatically G enerated Bins 4 0 4 100.00
A u to m a tic a lly G e n e ra te d B ins fo r g a n g lio n jf .t o p je f t
B ins
NAME COUNT AT LEAST
auto[0:63j 2916 1
auto[64:127] 2728 1
auto[128;191] 278 2 1
auto[192:255] 274 2 1
G o to top
d a s h b o a rd | hierarchy | modlist | g ro u p s j tes ts | asserts
Figure 22: Functional Coverage o f Complex Cell with bins
In Figure 22, Functional Coverage o f Complex Cell showing various generated auto bins
The Ganglion cell responds to the stimulus o f light in a particular orientation.

In the digital model of Ganglion c e ll, they are used for the purpose o f edge detection.
The edges are detected at 0 , 90 , 135 and 180 degrees
28
Generating Random Stimulus for Ganglion Cell
b eg in
g a n g li o n _ i f . t o p _ i e f t = $ u ra n d o m _ ra n g e (0 ,2 5 5 );
g a n g li o n ^ i f , to p ^ c e n te r ~ S u ran d o m ^ran g e lO ,2 5 5 );
g a n g lio n J .f . to p _ r i g h t = $u ran dom_ range to , 2 5 5 );
g a n g lio n ^ if m id d le ^ le f t - $ u ra n d o fn _ ra n g e {0 ,2 5 5 );
g a n g lio n _ if ,}D id d le _ c e n te r = $u ran dom_ range (6 /2 5 5 ) ;
g a n g li o n j if . m i d d l e _ r i g h t = $ u ra n d o m _ ra n g e {0 ,2 5 5 );
g a n g li o n _ i f .b o t t o m J .e f t = lu ra n d o in _ ra n g e (d ,255) ;
g a n g l i o n j i f . b o tto m jm d d le = $u ran dom_ ran g e ( 0 ,2 5 5 ) ;
g a n g lio n j i f . b o t t o m / i g h t » $u ran d o m _ ran g e(0 ,2 5 5 ) ;
end
Figure 23: Randomization logic in SystemVerilog testbench
As shown in the figure, we randomize each of the inputs in the Ganglion Cell DUT.
Each input is randomized for range o f (0,255) as the inputs are o f 7 bits. We use
g a n g lio n if as it is the name of our instance from the Interface module. For every in p u t,
we use ganglion if as this is the connectivity technique used with interface in
Systemverilog. The $urandom is used for randomizing the data between the range 0 to
255 in uniform way.
Scoreboard for Ganglion Cell in Systemverilog

29
task s c o r e b o a r d O ;
begin
£ ( ganglion_if.cb);
begin
i f { o s c iL la tio n jc o u n te rjo n > - new_valu*_on)
begin
oscillation counter on <- 8,
ganglion ôutput on <= ~ganglion_output_on
end
else
begin
o s c i l l a t i o n c o u n t e r o n <- o s c i l l a t i o n c o u n t e r o n *• lj
ganglion_output_on <= ganglion_ou tpu t_on;
end
end
begm
if (oscillation_counter_off >~ new_value_pff}
begin
oscillation_count*r_off <~ 0;
ganglion_Gutput_off ~ganglion_output_off;
end
else
begin
oscillation _ c o u n t e r o f f <= oscillation counter off + 1;
ganglian_Qutputj>ff <= ganglionjjutputjsff;
end
end
end
endtask : scoreboard
Figure 24: Scoreboard o f Ganglion Cell
As shown in the figure, for building the scoreboard, we create a new dynamix array and
name it as new value. This new-value is compared with the oscialltion counter on and
o scillationcounteroff. If new_value-on is less than oscillation counter on , then the
signal ganglion_output-on would be activated. Similarly , for the oscillation counter off
condition, if new value off is less than oscilaation counter off, the oscillation-
counter off condition is activated. For all other conditions, the values o f oscillation-
counter would be xero.
30
Self Checking of Ganglion Cell
task s e l f ,ch«ckO i
b e g in
# < g a n g U o n _ if.c b );
begin
i f { (n«w_v»lu«_on ~~ court ter_th re shold_on) {new_valu«_off cou n ter_thresii0ld _ o f f )}
begin
$ d isp l«y< ‘Expected value matches with actu al output* # s>t*4$ real tim e);
end
e ls e
begin
$ d isp lay(*n o i t i s flat a match! f \ t * ,S r e a ltim e );
end
end
end
endtask , s e lfje h e c k
i n i t i a l begin
repeat(2600 (g a n g lio n _if.cb•
begin
i n i t i a l i z e * ),
d riv er O ;
e k .in s t ,s a m p le O ;
sco reboa rdO;
s e l f checkO ;
j « J ♦ »i
end
end
endprogram
Figure 25: Self checking code Snippet
As shown in figure, the self check is defined as a task in SystemVerilog testbench. In the
self check task, we compare the new value with counter-threshold value. If both the
values are equal, the self check task prints the message that, “Expected values matches
with the actual output”. If the two values does not match , it prints the message ,” it is not
a match”.
Functional Coverage Code in SystemVerilog Testbench
covergroup fu n ct; /'/F u n ctio n a l Coverage f o r in p u t a

co v e rpoin t neu r o n i f , inpu t ja n e
{ o p tio n , au to _ b in j» a x = 4 ; }
endgroup
covergroup fu n ct2 ; //F u n c t io n a l Coverage fo r inp u t b

c o v e r p o m t neuron _ if. input, two
{ o p tio n .a u t o jb in ja a x - 4 ; }
endgroup
31
covergroup covport ;
to p p le ft ; coverpoint g an g lio ftjL f. to p _ le ft {
b ins low range = {(©:255]>;
>
to p jc e n te r : coverpoint to p jr e n te r {
b in s low range = {1Q;255)>;
>
to p _ rig h t : coverpoint t o p r i g h t {
b in s low_range - {10:2551};
>
m id d le_ ieft : coverpoint m id d ie_ left {
b in s low^range = {[0:255]};
>
fluddle_center : coverpoint middlemen t e r {
b in s lo w ran g e » {{0:2551};
>
middle^ rig h t ; coverpoint m id d le^rig h t {
b in s low_range » {I0:255j>;
}
endgroup
Figure 26: Functional Coverage code Snippet in SystemVerilog
As shown in the figure, the coverage points are defined at the inputs of the DUT. Each
input to the ganglion Cell DUT is the cover point. These cover points are merged
together in the Covergroups. It is the novel technique of merging the cover points which
we discovered through reading Research papers.
In our thesis, we implemented and verified the design by building verification

environment and simulating the design.
32
IV. Verification Model using System Verilog
The layered testbench is the key concept in modern verification methodology. This
technique makes the task easier by dividing the code into smaller pieces that can be
developed separately.
The testbench creates constrained random stimulus, and gathers functional coverage.
There are several steps needed to verify a design:
Generate stimulus, capture responses, determine correctness and measure progress.
Testbench
Design
inputs outputs
Under
Test
Figure 27: The testbench - design connection
The testbench should be connected to the design as shown (in figure 27).
Modern Designs have become very complex. To model this, 1 use the interface construct
that is similar to an intelligent bundle of wires. They contain the connectivity,
synchronization and the functionality of the communication between two or more
blocks. The thesis concentrates on interfaces that connect design blocks and testbenches.
In this Research, 1 use a point-to-point connection scheme with no signal directions in the
interface. The modport construct in an interface allows to group signals and specify
directions. The Monitor Modport allows to connect a monitor module.
33
An interface block uses a clocking block to specify the timing of synchronous signals
relative to the clocks. Any signal in a clocking block is sampled synchronously. Clocking
blocks are mainly used by testbenches but also allow verification engineer to create
abstract synchronous models.
Figure 28: Testbench Environment
In this research, the design is complicated and non traditional , the sophisticated
testbench is build using the testbench environment shown in figure 28.
In this research, we have optimized the testbench environment. The reason for
optimization is the testbench does not require all the protocols. In our verification
environment, the different protocols play different roles . The Generator is used to
generate the inputs. The Driver is responsible for driving the inputs to our DUT. The
34
Scoreboard is used to display the number of cycles for which the design output matches
with the expected output. For the expected output, the novel algorithm is proposed which
is discussed later in detail.
As our top level DUT is complex and consists o f several connected DUT’s ,in order to
check the design for maximum correctness , we build several System Verilog test
benches
V. Neuron Model using System Verilog
In the Verilog model of Neuron, the top level Neuron consists of Integraters and Sum
Threshold. The approach which we follow for verification purpose is to build basic
Verilog testbench for each module. In the verification model of Neuron, we build basic
Verilog testbench for Integrater and Sum Threshold, we instantiate the testbench o f
Integrater and Sum Threshold.
35
Neuron Model
) Intearater -h
Intearater +
Inputs Sum, Output

^ Integrater ------
Threshold.
Pulser Block
Integrater —
Figure 29: Neuron Model
After, the modules of the Neuron model have been verified by simulation, we continue to
second approach of the thesis. In the second approach, we build the Design Verification
environment, using the System Verilog. In the verification environment, we start by
building systemverilog testbench for Integrator. After simulating the System Verilog
testbench of Integrator, we build the testbench for Sum Threshold. During the
compilation stage, we connect the Integrator DUT with the Sum Threshold DUT. The
reason for doing this is that the outputs from the Integrator DUT’s are the inputs to the
Sum Threshold DUT. After debugging and simulating the Sum Threshold DUT, the top
level systemverilog model for Neuron is build. In the Top level Systemverilog testbench,
we make use o f function Surandom in the generator. The $urandom generates the uniform
range o f data .The top level testbench o f Neuron Model consists o f various tasks such as
Initialization Generator , Driver , Scoreboard and Self Checker. In the top level Verilog
model, we instantiate ten different Integraters and Sum Threshold.
Proposed Scoreboard for Neuron

36
t3sk scoreboardO;
fcegis
b&gif!
StOftOUtfllt = 8;
5tor«_diitp«t swtegraadjalwowt int^ratedjalii^tw ♦ wt^ritdvatotjiire* + ii?t«grated_vaiue_fouf ♦ wttgfat^.wl#fji« ♦ iategratedâiwsi* + u?t<grated_vaUie_seven + iM«gfit«djalw6i$t + wtMratedjakejifie * integri
ated.val«t«;
tdisplaytrate value m is W\jjrt«gf9tedj«UMMi;

Idis^layrIntegrated valse t« is ld\ Migrated
Wispitayl’stoftd values ii array' are VJ\stor*%?piit),
esd
esd
er.dtask: store&oard
Figure 30: Scoreboard for Neuron
As shown in figure 30, the Scoreboard is built for the top level module. This scoreboard
stores the integrated values from the Integrater in the dynamic array store_output and
performs addition of those values. The store output is a dynamic array type in
SystemVerilog that can store large number of similar integers.
37
illic it sic icvjt unc 13 iU£

Integrated value two is 158 #160 lieui
stored values in array are 488 *106 neui
integrate value one is 69 #166 neui
Integrated value two is 248 1106 neut
stored values m array are 493
it is a match
#100 neui
*166 neui
integrate value one is 69
[integrated value two is 248
stored values in array are 493 end
integrate value one is 96 end
Integrated value two is 222 endtask
stored values in array are 494
it is a natch
task scof
Integrated value two is 222
begin
integrate value one is 53 $(neuron_
Integrated value two is 121 begin
stored values in array are 359 storeout
it is a siatch storeout
integrate value one is 53 atedvaU
Sdisplayi
Integrated value two is 45 Sdisplayi
stored values in array are 371 display!
it is a match end
integrate value one is 158 end
Integrated value two is 45 endtask :
$finish at simulation time 2899950000999890.0ns
task self
VCS S i m u l a t i o n R e p o r t
begin
Time: 2899958
CPU Tine: 9.660 seconds; Data structure size: 8.9$ @(neuron_
Sat Apr 16 17:39:55 2916 begin
CPU tine: .268 seconds to compile + .948 seconds to elab + .263 seconds to link + .817 seconds in simulation if (th re
[engr852-19@hafez neuj$ | Sdisplayi
Figure 31: Scoreboard for Neuron Model
Our proposed Scoreboard successfully stored and displayed match for different values
As shown in figure 31, the Scoreboard for Neuron displays the stored values in the array
created for storing all the outputs is displayed. We have 10 Integraters instantiated for
building the top level module Neuron. So each integrated value is shown. Then , the self
checking message is displayed as whether the actual output values matches with the
stored values
38
.stored values in array are 286

i t is a match
i t is a watch
i t is a match
i t is a match
i t is a match
i t is a match
REGISTERED VERSION - Please support Hob&Xterm by subscribing to the profcssenal edition here: htip://TsiGisajiterm.rndsatefc.net
Figure 32: Snippet o f Scoreboard for Neuron Module
As shown in figure 32 , we show a second part o f Scoreboard output from the Neuron
DUT. Since we ran simulation for more than 1000 cycles, then for 2000 cycles, we get
vast Scoreboard values.
In this case,the Scoreboard for Neuron displays the stored values in the array created for
storing all the outputs is displayed. We have 10 Integraters instantiated for building the
top level module Neuron. So each integrated value is shown. Then , the self checking
message is displayed as whether the actual output values matches with the stored values
39
S e l f - Checking
task self ..checM);

teg i n
if.cb);
begin
i f t storeoutput »~ threshold.value M> bin ran. output ----- H
begin
idisplayt"‘tfes! i t is a match"j,
end
else
begin
Mi splay J*it is not a switch*); |
end
if{store output *= threshold value SA Heuronoutput “ 6)
begin
(display{’ Yes i t is a s m th ');
end
else
begin
tdisplayC i t is not atastth'};
end
Sdi sp t «y<“i.nt eg r <»te value one is %d’ ,int:egr*t«d_»alu«..ofte);

4disp1ay{"In teg f ated value two is %d*, i«t*grated„v<»tiie_tw©) j
$display(*stored values i« array are %d*> store ..output);
end
end
endtasK i self_checK
fu n c t fu n c t iflp u t .one = new*. >;

r u n c ti' f t m c t in p u t . two « new i t ,
Figure 33: Self checking module of Neuron
In the self checking module of Neuron, as shown in figure 33, the store-output is a
dynamic array type which is defined in beginning o f Systemverilog testbench. For self
checking, the storeoutput is compared with threshold value and also neuronoutput
state is checked.
Based on store output condition and state of neuron output, the message is printed
whether selfchecking is successful or selfchecking is not successful.
40
Neuron Module Results
;D-inputjne
rD-inputJwo
D-input_three
;oinpuljour
r-D-inputJive
D-inpuljix
\D-input_seven
;D-input_eight
|D-input_nine
:D-iripulJen Sti
+ D-add_plasticity[7:0] 8'h0a->8'h0c
+ D-sublract_plaslicity[7:0) 8'h04->8'h03
+ D-threshold_value[11:0] 12'h00a->12'hOOc
D-clocfc StO->St1
ID -re se t s to -> sti

-oneuron_output s to :
New Group
Figure 34: Simulation o f Neuron Model in Verilog
As shown in figure 34, the basic Verilog testbench is simulated. The input-one to
input ten are the inputs from different Integraters. For the Verilog testbench, we give
manual inputs varying the clock period with fixed value. By this technique, more number
o f testing and validating cases are covered. If we fed value for clock frequency at
20MHZ , then increase it with 5 MHZ , we can check clock for different frequencies , say
25 MHZ , 30 MHZ , 35 MHZ upto whatever upper limit of the clock we desire for our
DUT.
41
N airte V alue
P l i z J
p . m m t . poooo , pm. p m . 1120000, p4oooo, mm , *
[•-D -inputJW Q Sll j

IIIIHMIIIHIIIWIIIIIIHIIIIIIII l l l l l l l l l l .......I l l l l l l i m m
| h D - in p u tJ ire e S ll:
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . m i
j •-•D -inputjour Stl 1
j j-D -in p u tJiv e Stl
; j-D -in p u L six Stl j
j-D -in p u tje v e n S tl;
j-D -in p u L e ig h t S tl;B S o S ilH B n B
| j-D -in p irtn in e S t l !; M M i i i i i i i i i i i M i i M i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i j i i i i i i i i i i i i
1 - D -in p u tJ e n S tl.
j 4 -D -addj)lasticity[7:01 8'h O Z :
1
|i-lh r e s h o l(j_ v a lu e p i:0 | 12 *
j j-D -C lQ Ck S tl;
| b D -re se t Sto
D n e u io n ju tp u t sto
j j - n . th re s h o ld je s e t
i i: n intflwatofl ualuo nnoI7fll
sto
ft'hnn I
tm B S ^ S K B B S S S
Figure 35: Simulation of Neuron Model using System Verilog Testbench
As shown in figure 35, the SystewmVerilog testbench for Neuron module is simulated.
We are running Simulating for 1000 plus clock cycles so clock signal is seen in the
yellow color.
42
1203298 Ids
i>threshold_value[11 0J
D -clock
& -reset
Figure 36: Zoomed in figure of Simulation of Neuron Model using System Verilog
As shown in figure 36, the SystemVerilog testbench for Neuron. The input one to input-
ten are randomized. The threshold-reached is the 11 bit value.
43
IX. CONCLUSION
In this thesis, we proposed a Simulation Framework for the verification o f Verilog model
of Neuron model and a complex cell. We successfully simulated the complex and non
traditional design o f Verilog using System Verilog. The thesis also met all the parameters
required for the verification of the complex cell. The successful generation of Random
Stimulus , building o f Scoreboard and the self checking of design by building various
checkers for each design. We also proposed an algorithm for the scoreboard of the top
level of Neuron model. In this research, we successfully got hundred percent functional
coverage for each of the design.
44
X. FUTURE SCOPE
In this research, the simulation framework using System Verilog was successfully
implemented. The research can be continued by building the simulation framework using
UVM methodology. This methodology has inbuilt feature of the monitor which monitors
the outputs coming from the DUT at every clock cycle. The Neuron model of this thesis
can be used for purpose of Image Recognition by implementing it in MATLAB and
training the Neuron using learning algorithms. As the amount of online videos is
growing, the Neuron model can be trained in MATLAB and applied for purpose of
searching and recognizing the images from online videos.
45
XI: REFERENCES
[1] Kandel, James Schwartz, and Thomas Jessell. “Central Visual Pathways.” Principles
o f N eural Science. 4th Edition. New York: McGraw-Hill 2000. 507-545. Print.
[2] Michael Gee Yin Chan thesis. “ Hardware Modeling and Implementation of Neural
Network for Orientation Selectivity of Eye”.
[3] Chris Spear.”SystemVerilog for Verification. A Guide to Learning the Testbench

Language Features”.Second Edition.Springer 2008. 5 - 245.Print
[4] w w w.Testbench.in
[5] w w w .asic-w orld.com
[6] Zhili Zhou,Zheng Xie,Xinan Wang and Teng Wang. “ Development of verification
environment for SPI master interface using SystemVerilog.” IEEE 11th International
Conference on Signal Processing(ICSP) 2012.Volume:3.2188 - 2192
[7] Hadingham and Jennifer S. Lund. “A Visual Cortex Circuit Model for Orientation
Specificity.” IEEE International Conference on Neural Networks, November 1995
46
APPENDIX
VERILOG CODE :
IN TEG RA TER:
module Integrate^
neuroninput,
reset,
resettw o ,
add_plasticity,
subtractplasticity,
clock,
integratedvalue
);
i/ = = = = = = = = = = = = = = =
II PORT declarations
input neuroninput;
input reset;
input resettw o ;
input [7:0] add_plasticity;
input [7:0] subtract_plasticity;
input clock;
output reg [7:0] integrated value;
/ / = = = = =
// REG/WIRE declarations
/ / = = = = = _ _ _
reg la stn e u ro n in p u t;
wire edgedetected;
parameter [7:0] max value = 255;
assign edge detected = (llast neuron input && neuron input) ? l'bl : 1'bO;
47
begin
if (reset == l'bl || reset_two == l'b l)
integratedvalue <= 0;
else if (edge detected == l'b l) // add to intergration value on an output
neuron edge
begin
if ((integrated value + addplasticity) >= m ax v alu e)
integrated value <= max value;
else
integrated value <= integrated value +
addplasticity;
end
else
begin
if (subtractplasticity >= integrated value)
integrated value <= 0;
else
integrated value <= integrated value -
subtractplasticity;
end
end
begin
la s tn e u r o n in p u t <= neuron input;
end
initial
begin
integratedvalue = 0;
la s tn e u ro n in p u t = 0;
end
endmodule
SUM THRESHOLD
module Sum_Threshold(
in t v a lu e o n e ,
int_value_two,
in tv a lu e th r e e ,
i n t v a lu e s i x ,
in tv a lu e s e v e n ,
in tv a lu e e ig h t,
i n tv a lu e n in e ,
in t v a lu e t e n ,
thresholdvalue, //2A12 bits wide
clock,
integraterreset,
neuronoutput
);
// I/O ports
input [7:0] nt_value_one;
input [7:0] n tv a l u e t w o ;
input [7:0] n tv a lu e th r e e ;
input [7:0] n tv a lu e f o u r ;
input [7:0] n tv a lu e f iv e ;
input [7:0] n t v a l u e s i x ;
input [7:0] n tv a lu e s e v e n ;
input [7:0] n tv a lu e e ig h t;
input [7:0] n tv a lu e n in e ;
input [7:0] nt_value_ten;
input [11:0] threshold value;
input clock;
output integrater reset;
output reg neuron output;
// WIRE/REG Declarations
wire thresholdreached;
reg lastthreshold;
wire su m o n e ;
wire s u m tw o ;
wire sum three;
wire s u m fo u r;
wire su m fiv e;
wire su m s ix ;
wire sum seven;
wire sum eight;
wire sum n in e ;
49
wire s u m te n ;
assign thresholdreached = ((int value one + in t v a l u e t w o + in t v a lu e t h r e e +

i n t v a l u e f o u r + i n t v a lu e f i v e + i n t v a l u e s i x + in tv a lu e s e v e n + i n t v a lu e e ig h t +
i n t v a lu e n i n e + i n t v a lu e t e n ) >= thresholdvalue) ? l'bl : I'bO;
/*
assign sum one = (int_value_one > 0) ? l'bl : I'bO;
assign sum_two = (int value two > 0) ? l'bl : I'bO;
assign sum three = (int value three > 0) ? l'bl : I'bO;
assign sum four = (int value four > 0) ? l'bl : I'bO;
assign sum five = (int value fiv e> 0) ? l'bl : I'bO;
assign sum six = (int_value_six > 0) ? l'bl : I'bO;
assign sum seven = (int value seven > 0) ? l'bl : I'bO;
assign sum eight = (int value eight > 0) ? l'bl : I'bO;
assign sum nine = (int value nine > 0) ? l'bl : I'bO;
assign sum ten = (int value ten > 0) ? l'bl : I'bO;
assign threshold reached = ((sum one + sum two + sum three + sum four + sum five
+ sum six + sum seven + sum eight + sum nine + sum ten) >= threshold value) ? l'bl
: I'bO;
*/
assign integrater reset = threshold reached;
begin
neuron output <= (Ilast threshold && threshold reached);
end
//always@(posedge clock)
// begin
// neuron output <= 1;
// end
begin
last_threshold <= threshold reached;
end
50
initial
begin
lastthreshold = 0;
neuronoutput = 0;
end
endmodule
NEURON VERILOG CODE
module Neuron(
inputone,
inputtw o,
inputthree,
inputfour,
inputfive,
inputsix,
inputseven,
inputeight,
inputnine,
inputten,
addplasticity,
subtractplasticity,
thresholdvalue,
clock,
reset,
neuronoutput
);
input inputone;
input inputtw o;
input inputthree;
input inputfour;
input inputfive;
input inputsix;
input inputseven;
input inputeight;
input inputnine;
51
input inputten;
input [7:0] add plasticity;
input [7:0] subtract plasticity;
input [11:0] threshold value;
input clock;
input reset;
output neuronoutput;
wire threshold_reset;
wire [7:0] nte gratedv alu eo ne;
wire [7:0] ntegratedval u e tw o ;
wire [7:0] ntegratedvaluethree;
wire [7:0] ntegratedvalu efou r;
wire [7:0] ntegrated valuefive;
wire [7:0] nteg rated v alu esix ;
wire [7:0] ntegrated_val u e s e v e n ;
wire [7:0] ntegratedvalueeight;
wire [7:0] ntegratedval u e n ine;
wire [7:0] nteg ra ted v alu ete n ;
wire [12:0] store output;
Integrater ul (input one,reset, thresholdreset, add plasticity, subtract plasticity, clock,

integ rated valu eo ne);
Integrater u2 (input two, reset, threshold reset, add plasticity, subtract plasticity, clock,
in teg ratedvaluetw o );
Integrater u3 (input three, reset, threshold reset, add plasticity, subtract plasticity,
clock, integrated value three);
Integrater u4 (input four, reset, threshold reset, add plasticity, subtract plasticity, clock,
integratedvaluefour);
Integrater u5 (input five, reset, threshold reset, add_plasticity, subtract plasticity, clock,
integratedvaluefive);
Integrater u6 (inputsix, reset, threshold reset, add_plasticity, subtract plasticity, clock,
integrated valu esix);
Integrater u7 (input seven, reset, threshold reset, add plasticity, subtract plasticity,
clock, integrated value seven);
Integrater u8 (input eight, reset, threshold reset, add plasticity, subtract plasticity,
clock, integrated value eight);
Integrater u9 (input nine, reset, threshold reset, add plasticity, subtract plasticity, clock,
integratedva Iue_n ine);
Integrater ulO (input ten, reset, threshold reset, add plasticity, subtract_plasticity, clock,
integ ratedv alueten);
52
always@(posedge clock);
assign storeoutput = integ rate d v alu eo n e + in teg rate d v alu etw o +
integ ratedvaluethree + in teg rated v alu efo u r + in teg rate d v alu efiv e +
in teg ra te d v a lu e six + integratedvalueseven + integrated valueeight +
in teg rated v alu en in e + in teg ratedvalueten;
Sum Threshold thres 1(integrated value one, integrated value two,

integrated value three, integrated value four, integrated value five,
integrated value six, integrated value seven, integrated value eight,
integrated value nine, integrated value ten, threshold value, clock, thresholdreset,
neuronoutput);
endmodule
SYSTEM VERILOG CODE
SUM THRESHOLD
program automatic test(neuron_if.neuron_test neuron);
logic input o n e ;
logic input two ;
logic input three ;
logic input fo u r ;
logic input five ;
logic input six;
logic input seven ;
logic input e ig h t;
logic input n in e ;
logic input ten ;
logic [7:0] add plasticity ;
logic [7:0] subtract plasticity ;
logic [11:0] threshold value ;
logic clock;
logic re s e t;
logic neuron o u tp u t;
logic threshold reset;

logic edgedetected;
logic la stn e u ro n in p u t;
53
logic [7:0] ntegrated_value_one ;

logic [7:0] ntegrated value two ;
logic [7:0] ntegrated value th re e ;
logic [7:0] ntegrated_value_four;
logic [7:0] ntegrated value five ;
logic [7:0] ntegrated_value_six ;
logic [7:0] ntegrated value seven ;
logic [7:0] ntegrated value eight ;
logic [7:0] ntegrated value n in e ;
logic [7:0] ntegrated value ten ;
logic [12:0] store output = 0 ;
logic thresholdreached;
logic lastthreshold;
integer estimatedoutput;
covergroup funct; //Functional Coverage for input a
coverpoint n eu ro n if.in p u to n e
{ o p tio n .au to b in m ax = 4;}
endgroup
covergroup funct2; //Functional Coverage for input b

coverpoint n e u ro n if.in p u ttw o
{ o p tio n .au to b in m ax = 4;}
endgroup
task initialize();
begin
@(neuron_if.cb);
begin
neuronif.reset = 0;
neuronif.thresholdreset = 0;
// n eu ro n if.in te g ra te d v a lu e tw o = 0;
// neuron if.integrated value two <= n eu ro n if.in teg rate d v alu etw o +
neuron if.add plasticity ;
integrated value one = $urandom_range(0,255);
in teg rate d v alu etw o = $urandom_range(0,255);
integratedv aluethree = 3;
in teg rate d v alu efo u r = 0;
in teg rate d v alu efiv e = 5;
in teg rate d v alu esix = 0;
integratedv alueseven = 78;
in teg ratedvalu eeigh t = 90;
in teg rate d v alu en in e = 0;
54
in te g rate d v alu eten = 0;
n e u ro n if.in p u to n e = $urandom_range(0,l);
n e u ro n if.in p u ttw o = $urandom_range(0,l);
n e u ro n if.in p u tth ree = $urandom_range(0,1);
n eu ro n if.in p u tfo u r = $urandom_range(0,l);
n eu ro n if.in p u tfiv e = $urandom_range(0,l);
n e u ro n if.in p u tsix = $urandom_range(0,l);
neu ro n if.in p u tse v en = $urandom_range(0,l);
n eu ro n if.in p u teig h t = $urandom_range(0,1);
n eu ro n if.in p u tn in e = $urandom_range(0,l);
n e u ro n if.in p u tte n = $urandom_range(0,1);
neuronif.addplasticity = 13;
neuronif.subtractplasticity = 3;
neuronif.thresholdvalue = 12;
neuronif.reset = 1;
end
end
endtask
task driver();
begin
@(neuron_if.cb);
begin
n eu ro n if.in te g ra te d v a lu e tw o = 0;
neuron if.integrated value two <= neuron if.integrated value two +
functinput_one.sample();
functinput_two.sample();
neuronif.reset = 1;
#50 integrated value one = 123;
#50 neuron if.input one = $urandom_range(0,1);
#50 neuron if.input two = $urandom_range(0,1);
#50 neuron if.input three = $urandom_range(0,l);
#50 neuron if.input four = $urandom_range(0,l);
#50 neuron if.input five = $urandom_range(0,l);
#50 neuron if.input six = $urandom_range(0,l);
55
#50 n eu ro n if.in p u tse v en = $urandom_range(0,1);

#50 n eu ro n if.in p u teig h t = $urandom_range(0,1);
#50 n eu ro n if.in p u tn in e = $urandom_range(0,l);
#50 n e u ro n if.in p u tte n = $urandom_range(0,1);
#50 neuronif.addplasticity = 10;
#50 neuron_if.subtract_plasticity = 3;
#50 neuron_if.threshold_value = 9;
#50 neuronif.reset = 0;
#50 neuronif.thresholdreset = 1;
// #200 n e u ro n if.re s e ttw o = 0;
#100 threshold reset = 0;
#100 neuron if. reset = 0;
#100 n eu ro n if.in p u to n e = $urandom_range(0,l);
#100 neuron if.input two = $urandom_range(0,l);
#100 neuron if.input four = $urandom_range(0,l);
#100 neuron if.input five = $urandom_range(0,1);
#100 neuron if.input seven = $urandom_range(0,l);
#100 neuron if.input eight = $urandom_range(0,l);
#100 neuron if.input nine = $urandom_range(0,1);
#100 neuron if.input ten = $urandom_range(0,1);
#100 neuron_if.add_plasticity = 12;
#100 neuron if.subtract plasticity = 4;
#100 neuron if.threshold value = 10;
end
end
endtask
task scoreboard();
begin
@(neuron_if.cb);
begin
store_output = 0;
sto reoutput = integ rate d v alu eo n e + in teg rate d v alu etw o + integ rate d v alu eth ree +
in te g rate d v alu efo u r + integratedv aluefiv e + in teg rate d v alu esix +
integratedv alueseven + in tegratedvalueeigh t + in teg rate d v alu en in e +
integratedva 1u e t e n ;
56
$display("integrate value one is %d",integrated_value_one);

$display("lntegrated value two is %d",integrated_value_two);
$display("stored values in array are %d",store_output);
end
end
task self_check();
begin
@(neuron_if.cb);
begin
if(store_output >= threshold value && neuron output == 1)
begin
$display("Yes, it is a match");
end
else
begin
$display("it is not a match");
end
if(store_output <= threshold value && neuron output == 0)
begin
$display(" Yes it is a match");
end
else
begin
$display(" it is not a match");
end

$display("Integrated value two is %d",integrated_value_two);
end
end
endtask : self check
funct functinputone = new();

funct2 functinput two = new();
initial begin
57
repeat( 1000)
@(neuron_if.cb)
begin
driver();
initialize();
scoreboard();
self_check();
end
end
INTERFACE MODPORT
modport ganglion_test(clocking cb,output ganglionoutputoff,output

ganglion_output_on,input top left, input topcenter,input to p rig h t, input
middle_left,input middlecenter,input middle right,input bottom left, input
bottommiddle,input bottomright);
INTEGRATER
program automatic test(Integrater_if.Integrater_test Integrater);
logic neuron input = 0 ;

logic reset;
logic reset t w o ;
logic [7:0] add plasticity;
logic [7:0] subtract plasticity ;
logic [7:0] integrated value;
logic [7:0] new value;
int i,count;
int edgedetected =0;
int max value = 255;
int output value = 0;
covergroup funct; //Functional Coverage for neuron input

coverpoint Integrater if.add plasticity
{op tio n .au to b in m ax = 4;}
endgroup
covergroup funct2; //Functional Coverage for input add plasticity

coverpoint Integrater if.subtract plasticity
58
{option.auto_bin_max = 4;}
endgroup
/*
class good_sum;
rand bit[l:0] neuron input;
constraint c range { neuron input inside{[l */
// constraint Limitlneuron input.sizeO^^;}

// constraint Limit{neuron_input.size() inside{[ 1:0]};};
task edge_detect();
Integraterif.reset = 1;
Integ raterif.resettw o = 1;
NEURON FILE
program automatic test(neuron_if.neuron_test neuron);
logic input o n e ;
logic input two ;
logic input three ;
logic input f o u r ;
logic input five ;
logic input six;
logic input seven ;
logic input e ig h t;
logic input nine ;
logic input ten ;
logic [7:0] add plasticity ;
logic [7:0] subtract plasticity;
logic [11:0] threshold value ;
logic clock;
logic re s e t;
logic neuron o u tp u t;
logic threshold reset;

logic edgedetected;
logic la stn e u ro n in p u t;
logic [7:0] integrated value one ;
logic [7:0] integrated value two ;
logic [7:0] integrated value three ;
logic [7:0] integratedvalue f o u r;
logic [7:0] integrated value five ;
logic [7:0] integrated value six ;
logic [7:0] integrated value seven ;
logic [7:0] integrated value eight ;
logic [7:0] integrated value n in e ;
logic [7:0] integrated va ten ;
logic [12:0] store output =
logic thresholdreached;
logic lastthreshold;
integer estimatedoutput;
covergroup funct; //Functional Coverage for input a
coverpoint neuron if.input one
endgroup
covergroup funct2; //Functional Coverage for input b

coverpoint neuron if.input two
endgroup
task initialize();
begin
@(neuron_if.cb);
begin
neuronif.reset = 0;
neuronif.thresholdreset = 0;
// neuron if.integrated value two
// neuron if.integrated value two £= neuron if.integrated value two +
in teg rate d v alu eo n e = $urandom range(0,255);
in teg rate d v alu etw o = $urandom range(0,255);
integ ratedvaluethree = 3;
in te g rate d v alu efo u r = 0;
in teg rate d v alu efiv e = 5;
in teg rate d v alu esix = 0;
integratedv alueseven = 78;
integrated valu eeigh t = 90;
in teg rate d v alu en in e = 0;
in te g rate d v alu eten = 0;
60
n e u ro n if.in p u to n e = $urandom_range(0,l);
n e u ro n if.in p u ttw o = $urandom_range(0,1);
n e u ro n if.in p u tth ree = $urandom_range(0,1);
n e u ro n if.in p u tfo u r = $urandom_range(0,l);
n e u ro n if.in p u tfiv e = $urandom_range(0,l);
n e u ro n if.in p u tsix = $urandom_range(0,1);
neu ro n if.in p u tse v en = $urandom_range(0,1);
n eu ro n if.in p u teig h t = $urandom_range(0,1);
n e u ro n if.in p u tn in e = $urandom_range(0,1);
n e u ro n if.in p u tte n = $urandom_range(0,l);
neuron_if.add_plasticity = 13;
neuronif.subtractplasticity = 3;
neuron_if.threshold_value = 12;
neuronif.reset = 1;
end
end
endtask
task driver();
begin
@(neuron_if.cb);
begin
n e u ro n if.in te g ra te d v a lu e tw o = 0;
neuron if.integrated value two <= neuron if.integrated value two +
functinput_one.sample();
functinput_two.sample();
neuronif.reset = 1;
#50 integrated value one = 123;
#50 neuron if.input one = $urandom_range(0,1);
#50 neuron_if.input_two = $urandom_range(0,1);
#50 neuron if.input four = $urandom_range(0,1);

#50 neuron if.input seven = $urandom_range(0,l);
61
#50 n eu ro n if.in p u tn in e = $urandom_range(0,l);

#50 n e u ro n if.in p u tte n = $urandom_range(0,1);
#50 neuronif.addplasticity = 10;
#50 neuron_if.subtract_plasticity = 3;
#50 neuronif.thresholdvalue = 9;
#50 neuronif.thresholdreset = 1;
// #200 neuron_if.reset_two = 0;
#100 threshold reset = 0;
#100 neuron_if.reset = 0;
#100 neuron if.reset = 0;
#100 neuron if.input one = $urandom_range(0,l);
#100 neuron if.input two = $urandom_range(0,l);
# 100 neuron if.input four = $urandom_range(0,1);
#100 neuron_if.input_seven = $urandom_range(0,1);
#100 neuron if.input nine = $urandom_range(0,l);
#100 neuron if.input ten = $urandom_range(0,l);
#100 neuron_if.add_plastieity = 12;
#100 neuron if.subtract plasticity = 4;
#100 neuron if.threshold value = 10;
end
end
endtask
task scoreboard();
begin
@(neuron_if.cb);
begin
storeoutput = 0;
storeoutput = in teg rated v alu eo n e + in teg rate d v alu etw o + in teg rate d v alu eth ree +
in teg rate d v alu efo u r + integratedv aluefiv e + in teg rate d v alu esix +
integrated valu eseven + in tegratedv alueeig ht + in teg rated v alu en in e +
in teg rated valu eten;

$display("Integrated value two is %d",integrated_value_two);
end
end
task self_check();
begin
@(neuron_if.cb);
begin
if(store_output >= threshold value && neuron output == 1)
begin
$display("Yes, it is a match");
end
else
begin
$display("it is not a match");
end
if(store_output <= threshold value && neuron output == 0)
begin
$display(" Yes it is a match");
end
else
begin
$display(" it is not a match");
end

$display("lntegrated value two is %d",integrated_value_two);
end
end
funct functinput one = new();

funct2 functinput two = new();
initial begin
repeat( 1000)
@(neuron_if.cb)
63
begin
driver();
initialize();
scoreboard();
self_check();
end
end
endprogram
GANGLION CELL TESTBENCH
program automatic test(ganglion_if.gang!ion_test ganglion);

log c [7:0] t o p l e f t ;
log c [7:0] top center = 1;
log c [7:0] top right = 1;
log c [7:0] middle left = 1;
log c [7:0] middle center = 1;
log c [7:0] middle right = 1;
log c [7:0] bottom_left= 1;
log c [7:0] bottom middle = 1;
log c [7:0] bottom right = 1;
log c clock;
log c [6:0] oscillation counter off = 0;
log c [6:0] counter threshold off = 16;
log c [6:0] oscillation counter on = 0;
log c [6:0] counter threshold on = 16;
log c [10:0] surround sum;
log c ganglion output off;
log c ganglion output on;
log c [6:0] new value on = 16;
log c [6:0] new_value_off = 16;
int j = 0;
covergroup covport;
top l e f t : coverpoint ganglion if.top left {
bins low range = {[0:255]};
}
to p c e n te r : coverpoint to p c e n te r {
bins low_range= {[0:255]};
}
t o p r i g h t : coverpoint to p r ig h t {
bins lo w ran g e = {[0:255]};
m i d d l e l e f t : coverpoint m iddleleft {
bins low range = {[0:255]};
}
middle center : coverpoint middle_center {

bins low_range = {[0:255]};
}
m i d d le r i g h t: coverpoint m iddleright {
bins low_range = {[0:255]};
}
endgroup
/* coverpoint g anglion if.to pleft;

coverpoint ganglionif.topcenter;
coverpoint ganglion if.top right;
coverpoint ganglion if.middle left;
coverpoint ganglionif.m iddlecenter;
coverpoint ganglionif.m iddleright;
coverpoint ganglion if.bottom left;
coverpoint ganglion if. bottom middle;
coverpoint ganglion if.bottom right
{ o p tion .au tob inm ax = 16;}
*/
covport ck inst = new();
task initialize();
begin
65
begin
end
end
endtask : initialize
task driver();
begin
@(ganglion_if.cb);
begin
g an g lio n if.to p le ft = $urandom_range(0,255);
g a n g lio n if.to p cen ter = $urandom_range(0,255);
g an g lio n if.to p rig h t = $urandom_range(0,255);
g ang lio n if.m id d leleft = $urandom_range(0,255);
gang lionif.m iddlecenter = $urandom_range(0,255);
gang lion if.m idd leright = $urandom_range(0,255);
gang lionif.b otto m left = $urandom_range(0,255);
ganglionif.bottom m iddle = $urandom_range(0,255);
g anglio nif.b ottom righ t = $urandom_range(0,255);
end
end
endtask : driver
task scoreboard();
begin
@(ganglion_if.cb);
begin
if (oscillation counter on >= new value on)
begin
oscillation counter on <= 0;
ganglion output on <= -ganglion output on;
end
else
begin
oscillation counter on <= oscillation counter on + 1;
ganglion output on <= ganglion output on;
end
end
begin
if (o scillatio n co u n tero ff >= n e w v a lu e o f f )
66
begin
o s c illatio n co u n te ro ff <= 0;
g a n g lio n o u tp u to f f <= - g a n g lio n o u tp u to ff ;
end
else
begin
oscillatio n co u n te ro ff <= o scillatio n co u n te ro ff + 1;
g a n g lio n o u tp u to f f <= g an g lio n o u tp u to ff;
end
end
end
task self_check();
begin
@(ganglion_if.cb);
begin
if((new_value_on == cou n terth resh o ld o n ) && (new value off ==
co un terthresho ld off))
begin
$display("Expected value matches with actual output! @ %t",$realtime);
end
else
begin
$display("no it is not a match! @ %t ",$realtime);
end
end
end
initial begin
repeat(2000)@(ganglion_if.cb)
begin
initialize();
driver();
ck_inst.sample();
scoreboard();
self_check();
j = j +1;
end
end
endprogram

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VERIFICATION OF VERILOG MODEL OF

NEURAL NETWORKS USING SYSTEM VERILOG

Engineering: Embedded Electrical and Computer Systems

San Francisco, California

Master of Science in Engineering: Embedded Electrical and Computer Systems at San

Francisco State University.

Professor of Electrical and Computer

OF NEURAL NETWORKS USING SYSTEMVERILOG

List o f Figures............................................................................................................................... vii

Background Design of Neuron M o d el.......................................................................................9

Ganglion Cell M odel.................................................................................................................. 27

Verification Model using System Verilog................................................................................. 38

Neuron Model using System V erilo g ...................................................................40

I. Code Snippet showing plasticity logic............................................................................4

2.1ntegrater waveform displaying integrated values.........................................................1

3. Snippet o f SystemVerilog code of Integrater..............................................................13

4. Self Checking o f the design............................................................................................14

5. Interface module of Integrater DUT............................................................................. 15

6. Functional coverage of integrater DUT........................................................................ 16

7. Snippet o f Sum Threshold Verilog M odule................................................................ 18

8. Code Snippet o f Scoreboard...........................................................................................19

9. Scoreboard in Sum Threshold M odule......................................................................... 19

10. Self checking o f Sum Threshold module...................................................................20

II. Functional coverage o f S u m T h resh o ld.................................................................... 22

12. Simulation waves in Verilog........................................................................................ 23

13. Zoomed in version o f Sum threshold w aves............................................................. 24

14. Simulation of Sum threshold module in SystemVerilog......................................... 25

15. Receptive Field of a Biological Ganglion/ Concentric Circle C ell........................27

16. Receptive Field of a Pixelated Ganglion/Concentric Circle Cell........................... 27

17. Code Snippet o f Ganglion C ell.....................................................................................28

18. Simulation of Complex Cell using Verilog................................................................29

20. Simulation o f Complex Cell using SystemVerilog.................................................... 31

21. Function Coverage o f Complex Cell............................................................................ 32

22. Functional Coverage o f Complex Cell with bins....................................................... 33

23. Randomization logic in SystemVerilog testbench..................................................... 34

24. Scoreboard o f Ganglion C ell........................................................................................ 34

25. Self checking code Snippet............................................................................................ 35

26. Functional Coverage code Snippet in SystemVerilog............................................... 36

27. The testbench - design connection............................................................................ 37

29. Neuron M odel...................................................................................................................39

30. Scoreboard for N euron....................................................................................................41

31. Scoreboard for Neuron Model.......................................................................................41

32. Snippet of Scoreboard for Neuron M odel.................................................................... 42

33. Self checking module o f N euron.................................................................................. 43

34. Simulation of Neuron Model in Verilog......................................................................44

35. Simulation o f Neuron Model using SV testbench......................................................45

36. Zoomed in figure of Simulation o f Neuron model using SV................................... 46

II.BACKGROUND DESIGN OF NEURON MODEL

The Neuron Model consists of two main modules

the updating o f synaptic weights is not required so they remain constant.

Figure 1: Code Snippet showing plasticity logic

for the clock cycles for which edge detected is high

Generating Random Stimulus Using Integrater

covergroup funct; //Functional Coverage for neuron input

covergroup funct2; //Functional Coverage for input add plasticity

// constraint Limit {neuron ji.nput. s i z e O = » 2 ; }

*10 Inte g r a t e r _ i f .reset = 0;

generate uniformed data.

i f (n ew ..value i» teg » at«td ,.ya V «« ) j

Sdi ssf/U yrit i s not a watch

o u tfit value x l<it«*9fat.er_ i f . integrated,vatu*;

fiirtct functadd p l a s t i c i t y - nawit,

Figure 4 : Self Checking o f the design

and message is printed, “Self Check Successful” else “Not Successful”

o u tfit value x l<it«9fat.er_ i f . integrated,vatu;

SCCflS vS€tCT OW. tl*M£

a n g g M m s m msmrn so% p % ?o m % ,w 100%

_m ;eo». m m «> 100*

io% m» «eo. .-res w ** «xm