Lab 12 Keypad

NATIONAL UNIVERSITY OF TECHNOLOGY (NUTECH)
Main IJP Road, Sector I-12, Islamabad

Telephone: 051-5476768/4576809, Fax: 051-
5476769 Website: www.nutech.edu.pk
DEPARTMENT OF ELECTRICAL ENGINEERING
EXPERIMENT 12:
Implementation of Keypad Controller for Keypad Scanning using Verilog HDL
Keypad
Keypad Controller for Keypad Scanning is a digital circuit designed to interface with a keypad,
scan its matrix of keys, and detect when a key is pressed. This type of controller is commonly
used in various electronic devices that require user input, such as calculators, security systems,
and electronic locks.
WORKINHG:
The Anvyl keypad has 16 labeled keys (0-F). It is set up as a matrix in which each row of buttons
from left to right are tied to a row pin, and each column from top to bottom is tied to a column
pin. This gives the user four row pins and four column pins to address a button push. When a
button is pressed, the pins corresponding to that button’s row and column are connected.
To read a button’s state, the column pin in which the button resides must be driven low while the
other three column pins are driven high. This enables all of the buttons in that column. When a
button in that column is pushed, the corresponding row pin will read logic low.
The state of all 16 buttons can be determined in a four-step process by enabling each of the four
columns one at a time. This can be accomplished by rotating an “1110” pattern through the
column pins. During each step, the logic levels of the row pins correspond to the state of the
buttons in that column. To allow simultaneous button presses in the same row, instead configure
the column pins as bi-directional with internal pull-up resistors and keep the columns not
currently being read at high impedance.
Telephone: 051-5476768/4576809, Fax: 051-
VERILOG CODE:
module keypad(
input [3:0] read_1_in, //row select
input clk,
output reg [3:0] cscan, //col scan
output reg AN, //segment select anode an
output [6:0] disp //seg out
);
reg [6:0] disp1;
reg [3:0] read1;

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always @(posedge clk)
begin
AN =1;
end
initial
cscan = 4'b0010;
always @(posedge clk)
begin
case(cscan)
4'b0001:
begin
if (read_1_in[0]) disp1 = 7'b1111110; //0
else if (read_1_in[1]) disp1 = 7'b0110011; //4

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else if (read_1_in[3]) disp1 = 7'b1001110; //12==C
end
4'b0010:
begin
if (read_1_in[0]) disp1 = 7'b0110000; //1
else if (read_1_in[3]) disp1 = 7'b0111101; //13==D
end
4'b0100:
begin
if (read_1_in[0]) disp1 = 7'b1101101; //2
else if (read_1_in[2]) disp1 = 7'b1110111; //10==A
else if (read_1_in[3]) disp1 = 7'b1001111; //14==E
end
4'b1000:
begin
if (read_1_in[0]) disp1 = 7'b1101101; //3

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else if (read_1_in[2]) disp1 = 7'b1110111; //11==B
else if (read_1_in[3]) disp1 = 7'b1001111; //15==F
end
endcase
// Shift cscan after reading the keys
cscan = {cscan[2:0],cscan[3]};
end
endmodule
TEST bENCH:
`timescale 1ns / 1ps
module keypad_controller_tb;
// Define parameters
parameter CLK_PERIOD = 10; // Clock period in ns
// Declare signals
reg clk;
reg rst;
reg [3:0] row;
wire [3:0] col;
wire [7:0] seg;
// Instantiate the keypad controller

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Keypad_Controller dut (
.clk(clk),
.rst(rst),
.row(row),
.col(col),
.seg(seg)
);
// Clock generation
always #((CLK_PERIOD)/2) clk = ~clk;
// Reset generation
initial begin
clk = 0;
rst = 1;
#10;
rst = 0;
#1000;
$finish;
end
// Stimulus
initial begin
// Press Key 1
row = 4'b1110;
#50;
row = 4'b1111;
#50;
row = 4'b1110;
#50;
row = 4'b1111;
#50;
// Press Key 2
row = 4'b1101;
#50;
row = 4'b1111;
#50;
row = 4'b1101;
#50;
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row = 4'b1111;
#50;
// Press Key 3
row = 4'b1011;
#50;
row = 4'b1111;
#50;
row = 4'b1011;
#50;
row = 4'b1111;
#50;
// Press Key 4
row = 4'b0111;
#50;
row = 4'b1111;
#50;
row = 4'b0111;
#50;
row = 4'b1111;
#50;
end
endmodule
Telephone: 051-5476768/4576809, Fax: 051-
USER CONSTRAINT FILE:
## This file is a general .ucf for the Anvyl board

## To use it in a project:
## - uncomment the lines corresponding to used pins
## - rename the used signals according to the project
##Clock Signal 100MHz

NET CLK LOC=D11 | IOSTANDARD = "LVCMOS33";
#NET "CLK" TNM_NET = sys_clk_pin;
#TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz;
##Switches
NET "read_1_in[0]" LOC= V5 | IOSTANDARD=LVCMOS18;
#Bank = 3, pin name = IO_L13N_3, Sch name = SW0
NET "read_1_in[1]" LOC= U4 | IOSTANDARD=LVCMOS18;
#Bank = 3, pin name = IO_L18P_3, Sch name = SW1
NET "read_1_in[2]" LOC= V3 | IOSTANDARD=LVCMOS18;
NET "read_1_in[3]" LOC= P4 | IOSTANDARD=LVCMOS18;
#NET "SW[4]" LOC= R4 | IOSTANDARD=LVCMOS18;
#NET "SW[5]" LOC= P6 | IOSTANDARD=LVCMOS18;
Telephone: 051-5476768/4576809, Fax: 051-

## Buttons
#NET "BTN[0]" LOC = E6 | IOSTANDARD=LVCMOS18;
#Bank = 3, pin name = IO_L82P_3, Sch name = BTN0
#NET "BTN[1]" LOC = D5 | IOSTANDARD=LVCMOS18;
#Bank = 3, pin name = IO_L82N_3, Sch name = BTN1
#NET "BTN[2]" LOC = A3 | IOSTANDARD=LVCMOS18;
#Bank = 3, pin name = IO_L83P_3, Sch name = BTN2
#NET "BTN[3]" LOC = AB9 | IOSTANDARD=LVCMOS33;
## 7 Segment Display
NET "disp[0]" LOC=AA21 | IOSTANDARD=LVCMOS33;
#Bank = 1, pin name = IO_L63P_1, Sch name = 7SD-AA
NET "disp[1]" LOC=AA22 | IOSTANDARD=LVCMOS33;
#Bank = 1, pin name = IO_L63N_1, Sch name = 7SD-AB
NET "disp[2]" LOC=Y22 | IOSTANDARD=LVCMOS33;
#Bank = 1, pin name = IO_L59N_1, Sch name = 7SD-AC
NET "disp[3]" LOC=N15 | IOSTANDARD=LVCMOS33;
#Bank = 1, pin name = IO_L60P_1, Sch name = 7SD-AD
NET "disp[4]" LOC=AB19 | IOSTANDARD=LVCMOS33;
#Bank = 1, pin name = IO_L65P_1, Sch name = 7SD-AE
NET "disp[5]" LOC=P20 | IOSTANDARD=LVCMOS33;
Telephone: 051-5476768/4576809, Fax: 051-
#Bank = 1, pin name = IO_L64N_1, Sch name = 7SD-AF

NET "disp[6]" LOC=Y21 | IOSTANDARD=LVCMOS33;
#Bank = 1, pin name = IO_L59P_1, Sch name = 7SD-AG
#NET dp LOC=P15 | IOSTANDARD=LVCMOS33;

#Bank = 1, pin name = IO_L62P_1, Sch name = 7SD-DP
#NET "disp_cnt[1]" LOC = P16 | IOSTANDARD=LVCMOS33;

#Bank = 1, pin name = IO_L62N_1, Sch name = 7SD-C1
#NET "disp_cnt[0]" LOC = M17 | IOSTANDARD=LVCMOS33;
#NET "disp_cnt[3]" LOC = N16 | IOSTANDARD=LVCMOS33;
#NET "disp_cnt[2]" LOC = P19 | IOSTANDARD=LVCMOS33;
#Bank = 1, pin name = IO_L64P_1, Sch name = 7SD-C4
#NET "disp_cnt[5]" LOC = AA20 | IOSTANDARD=LVCMOS33;
#Bank = 1, pin name = IO_L61P_1, Sch name = 7SD-C5
#NET "disp_cnt[4]" LOC = AB21 | IOSTANDARD=LVCMOS33;
## Keypad
NET "cscan[0]" LOC = H8 | IOSTANDARD=LVCMOS18;
#Bank = 3, pin name = IO_L58P_3, Sch name = COL1
NET "cscan[1]" LOC = J7 | IOSTANDARD=LVCMOS18;
#Bank = 3, pin name = IO_L58N_3, Sch name = COL2
Telephone: 051-5476768/4576809, Fax: 051-
NET "cscan[2]" LOC = K8 | IOSTANDARD=LVCMOS18;

#Bank = 3, pin name = IO_L59P_3, Sch name = COL3
NET "cscan[3]" LOC = K7 | IOSTANDARD=LVCMOS18;
#Bank = 3, pin name = IO_L59N_3, Sch name = COL4
NET "read_1_in[0]" LOC = E4 | IOSTANDARD=LVCMOS18;

#Bank = 3, pin name = IO_L60P_3, Sch name = ROW1
NET "read_1_in[1]" LOC = F3 | IOSTANDARD=LVCMOS18;
#Bank = 3, pin name = IO_L60N_3, Sch name = ROW2
NET "read_1_in[2]" LOC = G8 | IOSTANDARD=LVCMOS18;
#Bank = 3, pin name = IO_L73P_3, Sch name = ROW3
NET "read_1_in[3]" LOC = G7 | IOSTANDARD=LVCMOS18;
#Bank = 3, pin name = IO_L73N_3, Sch name = ROW4

Lab 12 Keypad

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Lab 12 Keypad

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NATIONAL UNIVERSITY OF TECHNOLOGY (NUTECH)

Main IJP Road, Sector I-12, Islamabad

Implementation of Keypad Controller for Keypad Scanning using Verilog HDL

input [3:0] read_1_in, //row select

output reg [3:0] cscan, //col scan

output reg AN, //segment select anode an

output [6:0] disp //seg out

reg [6:0] disp1;

reg [3:0] read1;

always @(posedge clk)

always @(posedge clk)

if (read_1_in[0]) disp1 = 7'b1111110; //0

else if (read_1_in[1]) disp1 = 7'b0110011; //4

else if (read_1_in[2]) disp1 = 7'b1111111; //8

else if (read_1_in[3]) disp1 = 7'b1001110; //12==C

if (read_1_in[0]) disp1 = 7'b0110000; //1

else if (read_1_in[1]) disp1 = 7'b1011011; //5

else if (read_1_in[2]) disp1 = 7'b1111011; //9

else if (read_1_in[3]) disp1 = 7'b0111101; //13==D

if (read_1_in[0]) disp1 = 7'b1101101; //2

else if (read_1_in[1]) disp1 = 7'b1011111; //6

else if (read_1_in[2]) disp1 = 7'b1110111; //10==A

else if (read_1_in[3]) disp1 = 7'b1001111; //14==E

if (read_1_in[0]) disp1 = 7'b1101101; //3

else if (read_1_in[1]) disp1 = 7'b1011111; //7

else if (read_1_in[2]) disp1 = 7'b1110111; //11==B

else if (read_1_in[3]) disp1 = 7'b1001111; //15==F

// Shift cscan after reading the keys

// Instantiate the keypad controller

USER CONSTRAINT FILE:

## This file is a general .ucf for the Anvyl board

##Clock Signal 100MHz

#Bank = 3, pin name = IO_L22P_3, Sch name = SW5

#Bank = 1, pin name = IO_L64N_1, Sch name = 7SD-AF

#NET dp LOC=P15 | IOSTANDARD=LVCMOS33;

#NET "disp_cnt[1]" LOC = P16 | IOSTANDARD=LVCMOS33;

NET "cscan[2]" LOC = K8 | IOSTANDARD=LVCMOS18;

NET "read_1_in[0]" LOC = E4 | IOSTANDARD=LVCMOS18;

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