FAKULTI TEKNOLOGI DAN KEJURUTERAAN

ELEKTRONIK DAN KOMPUTER

UNIVERSITI TEKNIKAL MALAYSIA MELAKA

VLSI DESIGN & FABRICATION

BEEC4804 SEMESTER 2 SESI 2023/2024

LAB 5: DESIGNING MULTIPLEXER – LAYOUT AND VERIFICATION

NO. STUDENTS' NAME MATRIC. NO.

1. AHMAD HAZIQ BIN AHMAD LATFI B082110321

2. MUHAMMAD HAIKAL BIN MOHD RIDZUAN B082110221

3.

PROGRAMME 3 BERC

SECTION /
S1/1
GROUP

DATE 21/5/2024

1. DR.MOHD SYAFIQ BIN MISPAN

NAME OF
INSTRUCTOR(S)
2.

EXAMINER’S COMMENT(S) TOTAL MARKS

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1.0 OBJECTIVES

1. To familiar with VLSI design software.

2. To design the layout of the basic CMOS logic circuit.
3. To run physical verification on the layout design.
4. To work effectively in given task in group.

2.0 EQUIPMENT

1. Personal Computer / desktop.

2. Mentor Graphics software.

3.0 SYNOPSIS & THEORY

This Lab is concerned with the use of VLSI design software in order to create the layout design of
a logic circuits based on CMOS. It will be focusing on designing the layout and running the
physical verification of the circuit.

In this Lab, the layout for CMOS Gate will be created by using Mentor Graphics Software. After
layout design completed, Design Rule Check (DRC), Layout Versus Schematic and Parasitic
Extraction will be run. Once designed and violation free, the design with the parasitic data will
then be verified through simulation.

3.1 Layout Design

Integrated circuit layout, also known IC layout, IC mask layout, or mask design, is the
representation of an integrated circuit in terms of planar geometric shapes which correspond to
the patterns of metal, oxide, or semiconductor layers that make up the components of the
integrated circuit.
When using a standard process, where the interaction of the many chemical, thermal, and
photographic variables are known and carefully controlled, the behavior of the final integrated
circuit depends largely on the positions and interconnections of the geometric shapes. Using a
computer-aided layout tool, the layout engineer or layout technician places and connects all of the
components that make up the chip such that they meet certain criterion. Typically we will focus on
the performance, size, density, and manufacturability. This practice is often subdivided between
two primary layout disciplines: Analog and Digital.

The generated layout must pass a series of checks in a process known as physical verification.
When all verification is complete, the data is translated into an industry standard format, typically
GDSII, and sent to a semiconductor foundry. The process of sending this data to the foundry is
called tapeout due to the fact the data used to be shipped out on a magnetic tape. The foundry
converts the data into another format and uses it to generate the photomasks used in a
photolithographic process of semiconductor device fabrication.

In the earlier, simpler, days of IC design, layout was done by hand using opaque tapes and films,
much like the early days of PCB design. Modern IC layout is done with the aid of IC layout editor
software, mostly automatically using EDA tools, including place and route tools or schematic
driven layout tools. The manual operation of choosing and positioning the geometric shapes is
informally known as "polygon pushing".

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3.2 Design Rule Check (DRC)

DRC is a verification of the process design rules and supplementary rules. Basically, it verifies
whether all the polygons and layers from the layout database meet all of the manufacturing
process rules. Fundamentally, these design rule represent the physical limits of the manufacturing
process.

3.3 Layout Versus Schematic (LVS)

LVS is to verify whether physical layout is correctly matched with reference to the schematic. In
LVS, the following is verified:
1. Electrical connectivity of all signals (input, output and power) to their corresponding devices.
2. Devices size: transistor, resistor, capacitor…
3. Identification of any extra components and signals which is not found in the schematic.

3.4 Parasitics Extraction (PEX)

Extraction process of the parasitics from a completed layout. Simulation is done on the extracted
netlist to ensure the design is function within the specification.

4.0 PROCEDURES

PART A: PYXIS LAYOUT DESIGN

Create Schematic Driven Layout (SDL)
1. Open the new terminal on Linux OS.
2. Go to your lab4 project folder and open the Pyxis Design Manager, by typing:
dmgr_ic &
3. Select your “mux21” cell on the Project Navigator. Then click on the “New Layout” icon
to create a new layout sheet. Click “OK” to continue with the default setting.

4. Pyxis Layout will be invoked automatically with all files setting retrieved from the sil013_kit
design kit. Click on “option” to setup library file an do as follows:

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1 2

5. After setup the library file, New layout window should look as below and click on “OK” to
confirm with the layout setting.

Layout Design
6. Pyxis Layout will automatically create a Schematic Driven Layout (SDL) with both
schematic and layout sheet is display at the same time. On logic window, click on
“AutoInst” to auto-place the standard cells.
7. Pyxis Layout will automatically insert the layout with Schematic Driven Layout (SDL)
components in schematic as shown below:

8. With the layout view open as above, under IC Palettes, click on Plan & Place, then click
on “Autofp” under Floorplanner to perform auto-floorplanning and let the option as
default. Click OK. The floorplan will be generated.

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 9. Click on “StdCell” at the Auto placement, to insert all component cells into floorplan. The
standard cells components will be inserted into floorplan.
10. Click on “Feed” at the Auto placement and click OK with default setup, to align standard
cells and insert feed cell if needed.
11. Use peek area stroke command (hold MMB (middle-mouse-button) > drag to the right
> drag downward > release MMB) to view standard cells internal layout and unpeek
area stroke to switch off (hold MMB > drag to the right > drag upward > release MMB)

12. On logic window, click “Port” to insert port into layout window. Use the number 3 and 4 to
increase or decrease Metal Layer number, paste the port near to the connection node.
Use Metal 2 for A, SEL, B and X port.

Layout Routing
13. Use the hotkey “I” intelligent route command to route from node to node. Number 3 and 4
can be used to increase or decrease routing layer.
*You may use the hotkey “H” to view the available hotkeys for IRoute in the IRoute
Single Path Hotkeys window.
14. Complete all routing.
15. To label the ports, first select the M2.TEXT layer on the Layer Palette.
16. Click on “Add Text” icon on the toolbar or use the hotkey “T” to add the text to the ports.
Use the hotkey “Q” to change the Attribute of the text in the Add text window.
*Value = X; Text Height = 0.2/0.3
17. Move the Add Text window aside and paste the text (X) to the input port.
18. Repeat steps above to add the text for B, A, SEL, VDD and VSS port.
*Use M2.TEXT for A, SEL, B and X. Use M1.TEXT for VDD and VSS port.

PART B: VERIFICATION
Design Rule Check (DRC)
1. From the menu bar, select “Tools > Calibre > Run DRC”. To invoke the Calibrate
nmDRC.
2. Click on “Run DRC” to start the DRC checking.
3. RVE (Result Viewing Environment) window shows DRC errors.
4. On the Calibre RVE window, click on “down arrow” to find the errors in the report.
5. If there are errors, click on the error to see the details. Double click on the coordinate to
locate the error in layout window.
6. Fix the layout and run the DRC again until all errors are solved.
7. Close the RVE and Calibre DRC windows.

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 Layout Versus Schematic (LVS)
8. In Pyxis layout, invoke Calibre nmLVS by selecting “Tool > Calibre > Run LVS” from the
menu bar.
9. Click on “Setup” on the menubar of the nmLVS window to enable the LVS Options.
10. On the LVS Options, key in VDD and VSS at the Power nets: and Ground nets:
respectively to define the power and ground net of the layout.
11. Click on “Run LVS” to perform the LVS checking.
12. Once the LVS checking process is done, a LVS checking report will display the LVS
results. Similarly, if error occurred, you may need to fix all the errors before proceed to the
next stage; else close the report and exit the LVS checking.
13. After modifying the layout, remember to run DRC again. Make sure your layout is DRC
and LVS clean.

Parasitic extraction
14. Click on “Tools > Calibre > Run PEX” and Calibre PEX window pops up
15. Click on the “Inputs” tab. Select “Netlist” tab and check the “Export from schematic
viewer” option. Change the Top Cell of the netlist to “mux21”, and then click “OK”.

16. Click on “Outputs” and under the “Netlist” tab, select “DSPF” as the format instead of
“ELDO”.

17. Click on “Setup” and enable the “PEX Options”.

18. Under the “LVS Options” tab, key in VDD as the Power nets and VSS as the Ground
nets.
19. Click on “Run PEX”. This will start RC extraction.
20. A new netlist with parasitic will be generated e.g “mux21.pex.netlist”

Re-simulate the design with the parasitic data.

21. Open the “mux21_tb > default” on the Pyxis Design Manager to invoke the Pyxis
Schematic to enter to the simulation mode of the testbench directly.

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 22. Select the “MUX211” instant symbol and click on “Tools > Parasitics > Add DSPF” to
include the parasitic netlist for simulation.
23. Browse the previously generated parasitics netlist in the Choose DSPF column to
“$PROJECT/component/mux21/mux21.cal/mux21.pex.netlist” and select on “DSPF”
in the “Simulate using devices from:” option and click “OK”.
24. The parasitic netlist will be displayed on the schematic once the parasitic netlist is
included.
25. Click on “Run Simulator” on the toolbar to re-simulate the design with the parasitic data.

26. Once the simulation is completed, click on EZwave View Waves on the toolbar to
view the simulation result.
27. Click on the TRAN folder to view all the waveforms. You may double clicks on the node to
view the waveform in time domain.
28. You can compare with the original simulation waveform (pre-layout lab4) with the output
waveform with parasitic. Complete Table 5.1.

PART C: PYXIS LAYOUT DESIGN, VERIFICATION, AND SIMULATION

1. Repeat all the steps in PART A and B for mux21A design. Complete Table 5.1.

5.0 RESULTS

1. Multiplexer layout in PART A:

a. Complete layout – peek and unpeek.

2. DRC, LVS & PEX results for PART A.

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DRC

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LVS

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PEX

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3. Multiplexer layout in PART C:
a. Complete layout – peek and unpeek.
4. Testbench schematic PART A and C.
Part A

Part C

5. Simulation result with measured value of tpLH (PART A and C)

Part A

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 Part C

6. Low-to-high propagation delay comparison:

Table 5.1 : Low-to-high propagation delay comparison.
Design tPLH (ns) – tPLH (ns) –
post-layout pre-layout
Design in PART A – mux21 25.183 20.142
Design in PART C – mux21A 25.099 25.099

7. Total area consumption comparison:

Table 5.2 : Area comparison.
Design W x L (um2)
Design in PART A – mux21 12.010 x7.680
Design in PART C – mux21A 11.265 x 7.700

6.0 DISCUSSION
Discuss the findings from the experiment versus the theory.
 Explain your observation of propagation delay difference in Table 5.1.
 Explain your observation of total area consumption difference in Table 5.2.
 Based on your learning experience in Lab 5, suggest the best mutliplexer design for
low speed application.

7.0 CONCLUSION
Conclude what you have learned in this lab session.

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