S32G2RSERDESRM

NXP Semiconductors Document identifier: S32G2SERDESRM
Reference Manual Rev. 6, 8 Nov 2022
S32G2 SerDes Subsystem Reference Manual

NXP Semiconductors
Contents
Chapter 1 Introduction to the Subsystem...............................................................5
1.1 Copyright and permissions........................................................................................................ 5
1.2 Block diagram............................................................................................................................5
1.3 Subsystem working modes........................................................................................................6
1.4 Selecting a working mode......................................................................................................... 6
1.5 Enabling 2.5G SGMII with PCIe on SerDes lane 0................................................................... 6
1.6 Requirements for Split Reference Independent Spread Spectrum (SRIS)................................8
1.7 PLL usage................................................................................................................................. 8
Chapter 2 SerDes_SS register descriptions........................................................ 10

2.1 SS memory map......................................................................................................................10
2.2 PCIe PHY General Control (PCIE_PHY_GEN_CTRL)............................................................ 13
2.3 PCIe PHY Loopback Control (PCIE_PHY_LPBK_CTRL)........................................................16
2.4 PCIe PHY SRAM Control And Status (PCIE_PHY_SRAM_CSR)........................................... 17
2.5 PCIe PHY MPLLA Control (PCIE_PHY_MPLLA_CTRL)......................................................... 18
2.6 PCIe PHY MPLLB Control (PCIE_PHY_MPLLB_CTRL)......................................................... 19
2.7 PCIe PHY Setting External Control (PCIE_PHY_EXT_CTRL_SEL)........................................21
2.8 PCIe PHY Boundary Scan Control (PCIE_PHY_EXT_BS_CTRL).......................................... 21
2.9 PCIe Reference Clock Control (PCIE_PHY_REF_CLK_CTRL).............................................. 22
2.10 PCIe PHY MPLLA Control 1 (PCIE_PHY_EXT_MPLLA_CTRL_1)....................................... 24
2.13 PCIe PHY MPLLB Control 1 (PCIE_PHY_EXT_MPLLB_CTRL_1)....................................... 27
2.16 PCIe PHY RX Equalization Control 1 For Gen1 Speed
(PCIE_PHY_EXT_RX_EQ_CTRL_1A)...................................................................................... 31
(PCIE_PHY_EXT_RX_EQ_CTRL_1B)...................................................................................... 33
(PCIE_PHY_EXT_RX_EQ_CTRL_1C)......................................................................................34
2.28 PCIe PHY Calibration Control For Gen1 Speed (PCIE_PHY_EXT_CALI_CTRL_1)............. 43
S32G2 SerDes Subsystem Reference Manual , Rev. 6, 8 Nov 2022

Reference Manual 2 / 990
NXP Semiconductors
Contents

2.32 PCIe PHY Miscellaneous Control 1 (PCIE_PHY_EXT_MISC_CTRL_1)............................... 47
2.33 PCIe PHY Miscellaneous Control 2 (PCIE_PHY_EXT_MISC_CTRL_2)............................... 49
2.34 PCIe PHY TX Equalization Control For Gen1 Speed (PCIE_PHY_EXT_TX_EQ_CTRL_1)..50
2.37 PCIe PHY XPCS_0 Rx Override Control (PCIE_PHY_XPCS0_RX_OVRD_CTRL).............. 53
2.38 PCIe PHY XPCS_1 Rx Override Control (PCIE_PHY_XPCS1_RX_OVRD_CTRL).............. 54
2.39 Subsystem Read-Only Register 0 (SS_RO_REG_0)............................................................ 55
2.43 Subsystem Read/Write Register 0 (SS_RW_REG_0)........................................................... 61
2.49 PCIe Subsystem Version (PCIE_SUBSYSTEM_VERSION).................................................70
2.50 Link Interrupt Control And Status (LINK_INT_CTRL_STS)................................................... 71
2.51 PCIe Controller 0 General Control 1 (PE0_GEN_CTRL_1)...................................................73
2.55 PCIe Controller 0 PM Control (PE0_PM_CTRL)................................................................... 79
2.56 PCIe Controller 0 PM Status (PE0_PM_STS)....................................................................... 81
2.57 PCIe Controller 0 Transmit Message Header 1 (PE0_TX_MSG_HDR_1).............................83
2.60 PCIe controller 0 transmit message header 4 (PE0_TX_MSG_HDR_4)............................... 87
2.61 PCIe Controller 0 Transmit Message Request (PE0_TX_MSG_REQ)..................................88
2.62 PCIe Controller 0 Receive Message Header 1 (PE0_RX_MSG_HDR_1)............................. 90
2.66 PCIe Controller 0 Receive Message Status (PE0_RX_MSG_STS)...................................... 94
2.67 PCIe Controller 0 Receive Message Capture Control (PE0_RX_MSG_CAP_CTRL)............96
2.68 PCIe Controller 0 Receive Message Interrupt Control (PE0_RX_MSG_INT_CTRL).............98
2.69 PCIe Controller 0 Link Debug 1 (PE0_LINK_DBG_1)......................................................... 100
2.70 PCIe Controller 0 Link Debug 2 (PE0_LINK_DBG_2)......................................................... 101
2.71 PCIe Controller 0 AXI Master Debug 1 (PE0_AXI_MSTR_DBG_1).................................... 105
2.72 PCIe Controller 0 AXI Master Debug 2 (PE0_AXI_MSTR_DBG_2).................................... 106
2.73 PCIe Controller 0 AXI Slave Debug 1 (PE0_AXI_SLV_DBG_1)..........................................107
2.74 PCIe Controller 0 AXI Slave Debug 2 (PE0_AXI_SLV_DBG_2)..........................................108
2.75 PCIe Controller 0 Error Status (PE0_ERR_STS)................................................................ 109
2.76 PCIe Controller 0 Error Interrupt Control (PE0_ERR_INT_CTRL).......................................114
2.77 PCIe Controller 0 Interrupt Status (PE0_INT_STS).............................................................117
2.78 PCIe Controller 0 MSI Generation Control (PE0_MSI_GEN_CTRL)................................... 120
2.79 PCIe Controller 0 FSM Track 1 (PE0_FSM_TRACK_1)...................................................... 120
2.80 PCIe Controller 0 FSM Track 2 (PE0_FSM_TRACK_2)...................................................... 122
2.81 APB Bridge Timeout Control (APB_BRIDGE_TO_CTRL)................................................... 124
2.82 PHY Register Address (PHY_REG_ADDR)........................................................................ 125
2.83 PHY Register Data (PHY_REG_DATA).............................................................................. 126

NXP Semiconductors
Contents
2.84 Reset Control (RST_CTRL).................................................................................................127
Chapter 3 PCIe Controller..................................................................................129

3.1 Introduction............................................................................................................................129
3.2 Features................................................................................................................................ 132
3.3 Modes of operation................................................................................................................135
3.4 External (link interface) signal descriptions........................................................................... 135
3.5 Register configuration space overview†................................................................................ 137
3.6 BAR details†.......................................................................................................................... 141
3.7 PCIE_EP register descriptions.............................................................................................. 146
3.8 PCIE_RC register descriptions.............................................................................................. 426
3.9 Functional description............................................................................................................718
3.10 Initialization/application information.....................................................................................795
3.11 Embedded direct-memory access (DMA) controller............................................................796
Chapter 4 PHY...................................................................................................890
4.1 PHY features......................................................................................................................... 890
4.2 Interfaces...............................................................................................................................890
4.3 Approximating low-swing operation.......................................................................................890
4.4 Code examples......................................................................................................................891
4.5 Accessing PHY registers....................................................................................................... 892
4.6 SerDes_PHY register descriptions........................................................................................ 892
Chapter 5 XPCS................................................................................................ 906

5.1 XPCS features.......................................................................................................................906
5.2 Accessing XPCS registers.....................................................................................................906
5.3 Switching the PHY to 1G speed†...........................................................................................907
5.4 Switching the PHY to 2.5G speed†........................................................................................908
5.5 Switching the SGMII speed................................................................................................... 910
5.6 XPCS reset priority................................................................................................................ 911
5.7 SerDes_XPCS register descriptions......................................................................................912
Chapter 6 Revision History................................................................................ 987

Back page.................................................................................................................................................................................. 0
Legal information................................................................................................................................................................................... 988

NXP Semiconductors
Chapter 1
Introduction to the Subsystem
The SerDes subsystem on this chip includes the following components:
Table 1. Subsystem components
Component Description See section
One PCIe controller Provides a solution to implement a PCIe PCIe Controller

port for a PCIe root complex or endpoint
application
One PHY Supports various PCIe and Ethernet PHY

operation modes (also see Subsystem
working modes)
Two Ethernet Physical Coding Sublayer Provide an interface between the Media XPCS
(XPCS) controllers Access Control (MAC) and Physical
Medium Attachment Sublayer (PMA)
through a media-independent interface
to support serial-GMII transmit/receive
Subsystem-level registers Control and configure the overall SerDes_SS register descriptions
subsystem
You can use the SerDes interfaces for both PCI Express and SGMII applications.
NOTE
This document describes relative offsets for the registers and memory-mapped areas of the components
mentioned in the table above. See the chip reference manual for the absolute base addresses of the subsystem
and components.
1.1 Copyright and permissions

Throughout this document, the dagger character (†) notates: "Portions Copyright (C) 2017 Synopsys, Inc. Used with permission.
All rights reserved. Synopsys & DesignWare are registered trademarks of Synopsys, Inc."
1.2 Block diagram

The following figure shows a block diagram of the subsystem:

NXP Semiconductors
AXI slave
PCIe controller
AXI master
PHY (serves as SerDes)

Subsystem-level registers
SerDes lanes
GMII
ENET MAC XPCS0
GMII
ENET MAC XPCS1
Interrupt
SerDes subsystem
Legend:
Subsystem component Other external logic
Figure 1. Subsystem block diagram†
1.3 Subsystem working modes

The SerDes subsystem components work together to support different working modes. See the chip-specific SerDes information
in the chip reference manual for a summary of the available working modes.
1.4 Selecting a working mode

To select a subsystem working mode, perform the procedure in the following table. If you need to enable 2.5G SGMII with PCIe
on SerDes lane 0, also perform the procedure in Enabling 2.5G SGMII with PCIe on SerDes lane 0.
Table 2. Selecting a working mode
Step Action
1 Start a reset of the SerDes subsystem. See the chip-specific SerDes information in the chip reference manual for
the exact steps to do this.
2 Program SS_RW_REG_0[SUBSYS_MODE] with the desired mode number.
3 If you are using an internal reference clock, write 1 to SS_RW_REG_0[CLKEN].
4 Wait for at least 10 μs.
5 Finish the reset of the SerDes subsystem. See the chip-specific SerDes information in the chip reference manual for
1.5 Enabling 2.5G SGMII with PCIe on SerDes lane 0

In the table below, all XPCS registers are for XPCS_1.

NXP Semiconductors
Table 3. Enabling 2.5G SGMII with PCIe on SerDes lane 0
Step Action
1 If you are using the internal reference clock, write 1 to VR_MII_DIG_CTRL1[BYP_PWRUP].
2 Write 1 to VR_MII_DIG_CTRL1[EN_2_5G_MODE].
3 In VR MII MMD Debug Control (VR_MII_DBG_CTRL):

• Write 1 to SUPRESS_LOS_DET.
• Write 1 to RX_DT_EN_CTL.
4 In PCIe PHY Miscellaneous Control 2 (PCIE_PHY_EXT_MISC_CTRL_2):

• Write 3h to EXT_TX_VBOOST_LVL.
• Write 4h to EXT_TX_TERM_CTRL.
5 Write 1 to PCIE_PHY_EXT_CTRL_SEL[EXT_PHY_CTRL_SEL].
6 In PCIe Reference Clock Control (PCIE_PHY_REF_CLK_CTRL):

• Write 0 to REF_CLK_MPLLB_DIV2_EN.
• Write 0 to REF_CLK_DIV2_EN.
• Write 11b to REF_RANGE.
7 In PCIe PHY MPLLB Control 2 (PCIE_PHY_EXT_MPLLB_CTRL_2):

• Write 0, then 27h, to EXT_MPLLB_MULTIPLIER.
• Write 414h to EXT_MPLLB_FRACN_CTRL.
• Do not overwrite the reset value of the reserved field at bits 24–26.

• Write 5h to EXT_MPLLB_TX_CLK_DIV.
• Write 0 to EXT_MPLLB_WORD_DIV2_EN.
• Do not overwrite the reset value of the reserved fields at bits 0–11 and 16–24.

• Write 66h to EXT_MPLLB_BANDWIDTH.
• Write 1 to EXT_MPLLB_DIV10_CLK_EN.
• Write 0 to EXT_MPLLB_DIV8_CLK_EN.
• Write 0 to EXT_MPLLB_DIV_CLK_EN.
• Write 0 to EXT_MPLLB_DIV_MULTIPLIER.
10 In PCIe PHY XPCS_1 Rx Override Control (PCIE_PHY_XPCS1_RX_OVRD_CTRL):

• Write 2Bh to XPCS1_RX_REF_LD_VAL.
• Write 540h to XPCS1_RX_VCO_LD_VAL.
11 In PCIe PHY Boundary Scan Control (PCIE_PHY_EXT_BS_CTRL):

• Write Bh to EXT_BS_RX_LEVEL.
Table continues on the next page...

NXP Semiconductors
Table 3. Enabling 2.5G SGMII with PCIe on SerDes lane 0 (continued)
Step Action
• Write 1 to EXT_BS_RX_BIGSWING.
• Write 0 to EXT_BS_TX_LOWSWING.
12 Write 2h to PCIE_PHY_EXT_MISC_CTRL_1[EXT_RX_LOS_THRESHOLD].
13 Write 1 to VR_MII_Gen5_12G_16G_TX_GENCTRL2[TX0_WIDTH].
14 Write 1 to VR_MII_Gen5_12G_16G_TX_GENCTRL1[VBOOST_EN_0].
15 Write 1 to VR_MII_Gen5_12G_16G_MPLL_CMN_CTRL[MPLLB_SEL_0].
16 Write 0 to VR_MII_Gen5_12G_16G_TX_RATE_CTRL[TX0_RATE].
17 Write 1 to VR_MII_Gen5_12G_16G_RX_RATE_CTRL[RX0_RATE].
18 In VR MII PHY Rx CDR Control (VR_MII_Gen5_12G_16G_RX_CDR_CTRL):

• Write 0 to CDR_SSC_EN_0.
• Write 1 to VCO_LOW_FREQ_0.
20 Write 1, then 0, to RST_CTRL[COLD_RST].
21 Write 1 to VR_MII_Gen5_12G_16G_TX_GENCTRL2[TX_REQ_0], then read this field until it returns to 0.
22 Write 1 to VR_MII_Gen5_12G_16G_RX_GENCTRL2[RX_REQ_0], then read this field until it returns to 0.
23 Write 1 to VR_MII_Gen5_12G_16G_TX_GENCTRL1[TX_CLK_RDY_0].
24 Write 1 to VR_MII_DIG_CTRL1[INIT], then read this field until it returns to 0.
1.6 Requirements for Split Reference Independent Spread Spectrum (SRIS)

To use SRIS, you must meet the following requirements:
• Do not configure SRIS in conjunction with any SGMII mode on the same SerDes subsystem.
• Write 1 to PE0_GEN_CTRL_1[SRIS_MODE].
• Write 1 to PCIE_PHY_GEN_CTRL[RX_SRIS_MODE].
1.7 PLL usage

Table 4 shows which PLL each protocol and speed uses.
Table 4. PLL as a function of protocol and speed
Protocol and speed PLL used
PCIe Gen1 MPLLA
PCIe Gen2 MPLLA
PCIe Gen3 MPLLB
SGMII 1G MPLLA
SGMII 2.5G MPLLB

NXP Semiconductors
After SerDes reset is released, PCIE_PHY_MPLLA_CTRL[MPLL_STATE] becomes 1 within a certain amount of time, indicating
that the PHY is operational. Table 5 shows this time as a function of PHY reference-clock frequency.
Table 5. MPLL_STATE transition time
PHY reference clock frequency Time between SerDes reset and MPLL_STATE = 1
100 MHz Within 3.4 ms
125 MHz Within 5.2 ms

NXP Semiconductors
Chapter 2
SerDes_SS register descriptions
This section presents the subsystem-level registers.†
2.1 SS memory map

SerDes_SS relative offset: 8_0000h
Offset Register Width Access Reset value
(In bits)
0h PCIe PHY General Control (PCIE_PHY_GEN_CTRL) 32 RW 0003_0C00h
4h PCIe PHY Loopback Control (PCIE_PHY_LPBK_CTRL) 32 RW 0000_0000h
8h PCIe PHY SRAM Control And Status (PCIE_PHY_SRAM_CSR) 32 RW 0000_0001h
10h PCIe PHY MPLLA Control (PCIE_PHY_MPLLA_CTRL) 32 RW 0000_0000h
14h PCIe PHY MPLLB Control (PCIE_PHY_MPLLB_CTRL) 32 RW 0000_0000h
18h PCIe PHY Setting External Control (PCIE_PHY_EXT_CTRL_SEL) 32 RW 0000_0000h
1Ch PCIe PHY Boundary Scan Control (PCIE_PHY_EXT_BS_CTRL) 32 RW 0000_0029h
20h PCIe Reference Clock Control (PCIE_PHY_REF_CLK_CTRL) 32 RW 0000_001Ah
30h PCIe PHY MPLLA Control 1 (PCIE_PHY_EXT_MPLLA_CTRL_1) 32 RW 0001_0165h
40h PCIe PHY MPLLB Control 1 (PCIE_PHY_EXT_MPLLB_CTRL_1) 32 RW 0004_0076h
50h PCIe PHY RX Equalization Control 1 For Gen1 Speed 32 RW 00E7_0000h

(PCIE_PHY_EXT_RX_EQ_CTRL_1A)
54h PCIe PHY RX Equalization Control 2 For Gen1 Speed 32 RW 0000_0000h

(PCIE_PHY_EXT_RX_EQ_CTRL_1B)

(PCIE_PHY_EXT_RX_EQ_CTRL_1C)
60h PCIe PHY RX Equalization Control 1 For Gen2 Speed 32 RW 00E7_0000h




NXP Semiconductors
Table continued from the previous page...
(In bits)
70h PCIe PHY RX Equalization Control 1 For Gen3 Speed 32 RW 00E7_000Fh



80h PCIe PHY RX Equalization Control 1 For Gen4 Speed 32 RW 00E7_000Fh



90h PCIe PHY Calibration Control For Gen1 Speed 32 RW 001B_0546h

(PCIE_PHY_EXT_CALI_CTRL_1)
94h PCIe PHY Calibration Control For Gen2 Speed 32 RW 001B_0546h

98h PCIe PHY Calibration Control For Gen3 Speed 32 RW 0022_0550h

9Ch PCIe PHY Calibration Control For Gen4 Speed 32 RW 0022_0550h

A0h PCIe PHY Miscellaneous Control 1 32 RW 5100_0012h

(PCIE_PHY_EXT_MISC_CTRL_1)
A4h PCIe PHY Miscellaneous Control 2 32 RW 0203_00FFh

(PCIE_PHY_EXT_MISC_CTRL_2)
B0h PCIe PHY TX Equalization Control For Gen1 Speed 32 RW 0294_0044h

(PCIE_PHY_EXT_TX_EQ_CTRL_1)


C0h PCIe PHY XPCS_0 Rx Override Control 32 RW 0546_1B01h

(PCIE_PHY_XPCS0_RX_OVRD_CTRL)
D0h PCIe PHY XPCS_1 Rx Override Control 32 RW 0546_1B01h

(PCIE_PHY_XPCS1_RX_OVRD_CTRL)
E0h Subsystem Read-Only Register 0 (SS_RO_REG_0) 32 RO 0000_0006h

NXP Semiconductors
(In bits)
ECh Subsystem Read-Only Register 3 (SS_RO_REG_3) 32 RO 0000_0000h
F0h Subsystem Read/Write Register 0 (SS_RW_REG_0) 32 RW 0000_0000h
FCh Subsystem Read/Write Register 3 (SS_RW_REG_3) 32 RW 0000_0000h
100h Subsystem Read/Write Register 4 (SS_RW_REG_4) 32 RW 0000_0000h
104h Subsystem Read/Write Register 5 (SS_RW_REG_5) 32 RW 0000_0000h
1000h PCIe Subsystem Version (PCIE_SUBSYSTEM_VERSION) 32 RO 500A_0000h
1040h Link Interrupt Control And Status (LINK_INT_CTRL_STS) 32 RW 0000_0000h
1050h PCIe Controller 0 General Control 1 (PE0_GEN_CTRL_1) 32 RW 0000_0000h
105Ch PCIe Controller 0 General Control 4 (PE0_GEN_CTRL_4) 32 RW 0000_0000h
1060h PCIe Controller 0 PM Control (PE0_PM_CTRL) 32 RW 0028_0000h
1064h PCIe Controller 0 PM Status (PE0_PM_STS) 32 W1C 0000_0004h
1070h PCIe Controller 0 Transmit Message Header 1 32 RW 0000_0000h

(PE0_TX_MSG_HDR_1)

(PE0_TX_MSG_HDR_2)

(PE0_TX_MSG_HDR_3)
107Ch PCIe controller 0 transmit message header 4 32 RW 0000_0000h

(PE0_TX_MSG_HDR_4)
1080h PCIe Controller 0 Transmit Message Request (PE0_TX_MSG_REQ) 32 RW 0000_0000h
1090h PCIe Controller 0 Receive Message Header 1 32 RO 0000_0000h

(PE0_RX_MSG_HDR_1)

(PE0_RX_MSG_HDR_2)

(PE0_RX_MSG_HDR_3)
109Ch PCIe Controller 0 Receive Message Header 4 32 RO 0000_0000h

(PE0_RX_MSG_HDR_4)
10A0h PCIe Controller 0 Receive Message Status (PE0_RX_MSG_STS) 32 W1C 0000_0000h

NXP Semiconductors
(In bits)
10A4h PCIe Controller 0 Receive Message Capture Control 32 RW 0000_0000h

(PE0_RX_MSG_CAP_CTRL)
10A8h PCIe Controller 0 Receive Message Interrupt Control 32 RW 0000_0000h

(PE0_RX_MSG_INT_CTRL)
10B0h PCIe Controller 0 Link Debug 1 (PE0_LINK_DBG_1) 32 RO 0000_0000h
10B4h PCIe Controller 0 Link Debug 2 (PE0_LINK_DBG_2) 32 RO 0100_0800h
10C0h PCIe Controller 0 AXI Master Debug 1 (PE0_AXI_MSTR_DBG_1) 32 RO 0000_0000h
10C4h PCIe Controller 0 AXI Master Debug 2 (PE0_AXI_MSTR_DBG_2) 32 RO 0000_0000h
10D0h PCIe Controller 0 AXI Slave Debug 1 (PE0_AXI_SLV_DBG_1) 32 RO 0000_0000h
10D4h PCIe Controller 0 AXI Slave Debug 2 (PE0_AXI_SLV_DBG_2) 32 RO 0000_0000h
10E0h PCIe Controller 0 Error Status (PE0_ERR_STS) 32 W1C 0000_0000h
10E4h PCIe Controller 0 Error Interrupt Control (PE0_ERR_INT_CTRL) 32 RW 0000_0000h
10E8h PCIe Controller 0 Interrupt Status (PE0_INT_STS) 32 W1C 0000_0000h
10ECh PCIe Controller 0 MSI Generation Control (PE0_MSI_GEN_CTRL) 32 RW 0000_0000h
10F0h PCIe Controller 0 FSM Track 1 (PE0_FSM_TRACK_1) 32 RW 0000_0000h
10F4h PCIe Controller 0 FSM Track 2 (PE0_FSM_TRACK_2) 32 RO 0000_0000h
3000h APB Bridge Timeout Control (APB_BRIDGE_TO_CTRL) 32 RW 0064_0082h
3008h PHY Register Address (PHY_REG_ADDR) 32 RW 0000_0000h
300Ch PHY Register Data (PHY_REG_DATA) 32 RW 0000_0000h
3010h Reset Control (RST_CTRL) 32 RW 0000_0000h
2.2 PCIe PHY General Control (PCIE_PHY_GEN_CTRL)
Offset
Register Offset
PCIE_PHY_GEN_CTRL 0h

NXP Semiconductors
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PHY_
R Reserved Reserved
RTU... REF_U REF_R
PHY_ SE... EP...
W
RTU...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserv
R Reserved RX1_T RX0_T RX_S Reserved CR_P EXT_P
ed
ER... ER... RIS... ARA... CL...
W
Reset 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-26 Reserved
25 Resistor Tune Status

PHY_RTUNE_S Reports the status of the manual resistor tuning in PCIe mode.
TS
0b - Tuning has not started or completed
1b - Tuning completed
24 Resistor Tune Request

PHY_RTUNE_R Controls the value of PMA's rtune_req signal in PCIe mode.
EQ
0b - Driven to 0
1b - Driven to 1
23-18 Reserved
17 Reference Is From External Pad

REF_USE_PAD Controls the value of PHY's ref_use_pad signal in PCIe mode.
0b - Driven to 0
1b - Driven to 1
16 Repeat Reference Clock Enable

REF_REPEAT_ Controls the value of PMA's ref_repeat_clk_en signal in PCIe mode.
CLK_EN
0b - Driven to 0
1b - Driven to 1

NXP Semiconductors
Field Function
15-12 Reserved
11 Receiver Termination Control For Rx1

RX1_TERM_AC Controls the value of PMA's rx1_term_acdc signal in PCIe mode.
DC
0b - Driven to 0
1b - Driven to 1
10 Receiver Termination Control For Rx0

RX0_TERM_AC Controls the value of PMA's rx0_term_acdc signal in PCIe mode.
DC
0b - Driven to 0
1b - Driven to 1
9 SRIS Enable, As Defined In PCIe ECN

RX_SRIS_MOD Enables PHY's SRIS mode in PCIe mode. See Requirements for Split Reference Independent Spread
E Spectrum (SRIS).
0b - Disables
1b - Enables
8-3 Reserved
2 CR Parallel Clock Divider Control

CR_PARA_CLK Controls the PMA cr_para_clk frequency.
_DIV2_EN
0b - Same as PHY ref_dig_fr_clk
1b - Half of ref_dig_fr_clk
1 Reserved
0 pipeP_pclk Required By External Logic

EXT_PCLK_RE Controls the value of PHY's ext_pclk_req signal in PCIe mode.
Q
0b - Driven to 0
1b - Driven to 1

NXP Semiconductors
2.3 PCIe PHY Loopback Control (PCIE_PHY_LPBK_CTRL)
Offset
Register Offset
PCIE_PHY_LPBK_CTRL 4h
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserved LANE1 LANE1 LANE0 LANE0
W _R... _T... _R... _T...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-4 Reserved
3 Lane1 Parallel (RX To TX) Loopback Enable

LANE1_RX2TX Controls the value of PMA's lane1_rx2tx_par_lb_en signal in PCIe mode.
_PAR_LB_EN
0b - Driven to 0
1b - Driven to 1
2 Lane1 Analog Serial Loopback Control

LANE1_TX2RX Controls the value of PHY's pcs_lane1_tx2rx_loopbk signal in PCIe mode.
_LOOPBK
0b - Driven to 0
1b - Driven to 1
1 Lane0 Parallel (RX to TX) Loopback Enable

LANE0_RX2TX Controls the value of PMA's lane0_rx2tx_par_lb_en signal in PCIe mode.
_PAR_LB_EN
0b - Driven to 0
1b - Driven to 1
0 Lane0 Analog Serial Loopback Control

Controls the value of PHY's pcs_lane0_tx2rx_loopbk signal in PCIe mode.

NXP Semiconductors
Field Function
LANE0_TX2RX 0b - Driven to 0
_LOOPBK
1b - Driven to 1
2.4 PCIe PHY SRAM Control And Status (PCIE_PHY_SRAM_CSR)
Offset
Register Offset
PCIE_PHY_SRAM_CSR 8h
Function
Used to:
• Control whether to bypass updating PHY firmware from SRAM
• Indicate when PCIe hardware completes initializing PHY SRAM
• Control when firmware completes updating PHY SRAM
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R Reserved
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRAM
R Reserved SRAM SRAM
_IN...
_EX... _BY...
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
1. The reset value may change after another module on the chip asserts a PCIe reset.
Fields
Field Function
31-3 Reserved
2 SRAM Initialization Done

NXP Semiconductors
Field Function
SRAM_INIT_D Provides the value of PMA's sram_init_done signal in PCIe mode.

ONE 0b - 0
1b - 1
1 SRAM External Load Done

SRAM_EXT_LD Controls the value of PMA's sram_ext_ld_done signal in PCIe mode.
_DONE
0b - Driven to 0
1b - Driven to 1
0 SRAM Bypass
SRAM_BYPAS Controls the value of PMA's sram_bypass signal in PCIe mode.
S
0b - Driven to 0
1b - Driven to 1
2.5 PCIe PHY MPLLA Control (PCIE_PHY_MPLLA_CTRL)
Offset
Register Offset
PCIE_PHY_MPLLA_CTR 10h
L
Function
Used to:
• Force MPLLA Enable
• Monitor MPLL lock state
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MPLLA MPLL_
R Reserved
_S... ST...
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserved Reserv MPLLA
W ed _F...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
Fields
Field Function
31 MPLLA State Indicator

MPLLA_STATE Indicates the state of the phy0_mplla_state signal.
0b - 0
1b - 1
30 MPLLA or MPLLB State Indicator

MPLL_STATE Indicates the state of the phy0_mplla_state and phy0_mpllb_state signals. See PLL usage for more
information.
0b - phy0_mplla_state and phy0_mpllb_state are 0
1b - phy0_mplla_state or phy0_mpllb_state is 1
29-2 Reserved
1 Reserved
0 MPLLA Force Enable

MPLLA_FORC Controls the value of PHY's phy0_mplla_force_en signal in PCIe mode.
E_EN
0b - Driven to 0
1b - Driven to 1
2.6 PCIe PHY MPLLB Control (PCIE_PHY_MPLLB_CTRL)
Offset
Register Offset
PCIE_PHY_MPLLB_CTR 14h
L
Function
Used to:
• Force MPLLB Enable
• Monitor MPLL lock state

NXP Semiconductors
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MPLLB MPLL_
R Reserved
_S... ST...
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserved Reserv MPLLB
W ed _F...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31 MPLLB State Indicator

MPLLB_STATE Indicates the state of the phy0_mpllb_state signal.
0b - 0
1b - 1
30 MPLLA or MPLLB State Indicator

MPLL_STATE Indicates the state of the phy0_mplla_state and phy0_mpllb_state signals.
0b - phy0_mplla_state and phy0_mpllb_state are 0
1b - phy0_mplla_state or phy0_mpllb_state is 1
29-2 Reserved
1 Reserved
— If you enable 2.5G SGMII mode for lane 0 (see Enabling 2.5G SGMII with PCIe on SerDes lane 0), do
not write to this field. It must remain at its reset value.
0 MPLLB Force Enable

MPLLB_FORC Controls the value of PHY's phy0_mpllb_force_en signal in PCIe mode.
E_EN
0b - Driven to 0
1b - Driven to 1

NXP Semiconductors
2.7 PCIe PHY Setting External Control (PCIE_PHY_EXT_CTRL_SEL)
Offset
Register Offset
PCIE_PHY_EXT_CTRL_ 18h
SEL
Function
Control whether to use external control registers to override PCIe PHY parameters.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserved EXT_P
W HY...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-1 Reserved
0 External Control Of PHY Setting

EXT_PHY_CTR Controls the value of PHY's phy_ext_ctrl_sel signal in PCIe mode.
L_SEL
0b - Driven to 0
1b - Driven to 1
2.8 PCIe PHY Boundary Scan Control (PCIE_PHY_EXT_BS_CTRL)
Offset
Register Offset
PCIE_PHY_EXT_BS_CT 1Ch
RL

NXP Semiconductors
Function
Overrides boundary-scan parameters when external control of PHY settings is enabled.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserved EXT_B EXT_B

EXT_BS_RX_LEVEL
W S_... S_...
Reset 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1
Fields
Field Function
31-7 Reserved
6 TX Boundary Scan Low Swing

EXT_BS_TX_L Controls the value of PHY's protocol0_ext_bs_rx_lowswing signal in PCIe mode.
OWSWING
0b - Driven to 0
1b - Driven to 1
5 RX Boundary Scan Big Swing

EXT_BS_RX_BI Controls the value of PHY's protocol0_ext_bs_rx_bigswing signal in PCIe mode.
GSWING
0b - Driven to 0
1b - Driven to 1
4-0 ACJTAG Receiver Sensitivity Level Control

EXT_BS_RX_L Controls the value of PHY's protocol0_ext_bs_rx_level signal in PCIe mode.
EVEL
2.9 PCIe Reference Clock Control (PCIE_PHY_REF_CLK_CTRL)
Offset
Register Offset
PCIE_PHY_REF_CLK_C 20h
TRL

NXP Semiconductors
Function
Overrides reference clock parameters when external control of PHY settings is enabled.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserved REF_C REF_C REF_C

REF_RANGE
W LK... LK... LK...
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0
Fields
Field Function
31-6 Reserved
5-3 Input Reference Clock frequency Range

REF_RANGE Controls the value of PHY's protocol0_ext_ref_range signal in PCIe mode.
2 Input Reference Clock Divider Control

REF_CLK_DIV2 Controls the value of PHY's protocol0_ext_ref_clk_div2_en signal in PCIe mode.
_EN
0b - Driven to 0
1b - Driven to 1
1 MPLLB Reference Clock Divider Control

REF_CLK_MPL Controls the value of PHY's protocol0_ext_ref_clk_mpllb_div2_en signal in PCIe mode.
LB_DIV2_EN
0b - Driven to 0
1b - Driven to 1
0 MPLLA Reference Clock Divider Control

REF_CLK_MPL Controls the value of PHY's protocol0_ext_ref_clk_mplla_div2_en signal in PCIe mode.
LA_DIV2_EN
0b - Driven to 0
1b - Driven to 1

NXP Semiconductors
2.10 PCIe PHY MPLLA Control 1 (PCIE_PHY_EXT_MPLLA_CTRL_1)
Offset
Register Offset
PCIE_PHY_EXT_MPLLA 30h
_CTRL_1
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R Reserved EXT_ EXT_ EXT_ EXT_

EXT_MPLLA_DIV_MULTIPLIER
W MPL... MPL... MPL... MPL...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
EXT_MPLLA_BANDWIDTH
W
Reset 0 0 0 0 0 0 0 1 0 1 1 0 0 1 0 1
Fields
Field Function
31-24 MPLLA Output Frequency Multiplier Control

EXT_MPLLA_DI Controls the value of PHY's protocol0_ext_mplla_div_multiplier signal in PCIe mode.
V_MULTIPLIER
23-20 Reserved
19 MPLLA Divide Clock Enable

EXT_MPLLA_DI Controls the value of PHY's protocol0_ext_mplla_div_clk_en signal in PCIe mode.
V_CLK_EN
0b - Driven to 0
1b - Driven to 1
18 MPLLA Divide by 8 Enable

EXT_MPLLA_DI Controls the value of PHY's protocol0_ext_mplla_div8_clk_en signal in PCIe mode.
V8_CLK_EN
0b - Driven to 0
1b - Driven to 1
17 MPLLA Divide by 16.5 Enable

Controls the value of PHY's protocol0_ext_mplla_div16p5_clk_en signal in PCIe mode.

NXP Semiconductors
Field Function
EXT_MPLLA_DI 0b - Driven to 0
V16P5_CLK_E
1b - Driven to 1
N
16 MPLLA Divide by 10 Enable

EXT_MPLLA_DI Controls the value of PHY's protocol0_ext_mplla_div10_clk_en signal in PCIe mode.
V10_CLK_EN
0b - Driven to 0
1b - Driven to 1
15-0 MPLLA Bandwidth Control

EXT_MPLLA_B Controls the value of PHY's protocol0_ext_mplla_bandwidth signal in PCIe mode.
ANDWIDTH
Offset
Register Offset
_CTRL_2
Function
Overrides MPLLA parameters when external control of PHY settings is enabled.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserv Reserv Reserv

R
ed Reserved ed Reserved ed EXT_MPLLA_FRACN_CTRL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserved
EXT_MPLLA_FRACN_CTRL EXT_MPLLA_MULTIPLIER
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1

NXP Semiconductors
Fields
Field Function
31 Reserved
30-28 Reserved
27 Reserved
26-24 Reserved
23 Reserved
22-12 MPLLA Fractional Control

EXT_MPLLA_F Controls the value of PHY's protocol0_ext_mplla_fracn_ctrl signal in PCIe mode.
RACN_CTRL
11-8 Reserved
7-0 MPLLA Frequency Multiplier Control

EXT_MPLLA_M Controls the value of PHY's protocol0_ext_mplla_multiplier signal in PCIe mode.
ULTIPLIER
Offset
Register Offset
_CTRL_3
Function
Overrides MPLLA parameters when external control of PHY settings is enabled.

NXP Semiconductors
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R EXT_M EXT_MPLLA_TX_CLK_D Reserved

Reserved
W PL... IV
Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserved
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31 MPLLA Word Clock Divide by 2

EXT_MPLLA_W Controls the value of PHY's protocol0_ext_mplla_word_div2_en signal in PCIe mode.
ORD_DIV2_EN
0b - Driven to 0
1b - Driven to 1
30-28 MPLLA Tx Clock Divide

EXT_MPLLA_T Controls the value of PHY's protocol0_ext_mplla_tx_clk_div signal in PCIe mode.
X_CLK_DIV
27-25 Reserved
24-16 Reserved
15-12 Reserved
11-0 Reserved
2.13 PCIe PHY MPLLB Control 1 (PCIE_PHY_EXT_MPLLB_CTRL_1)
Offset
Register Offset
PCIE_PHY_EXT_MPLLB 40h
_CTRL_1

NXP Semiconductors
Function
Overrides MPLLB parameters when external control of PHY settings is enabled.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserv
R Reserved EXT_ EXT_ EXT_
EXT_MPLLB_DIV_MULTIPLIER ed
MPL... MPL... MPL...
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
EXT_MPLLB_BANDWIDTH
W
Reset 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 0
Fields
Field Function
31-24 MPLLB Output Frequency Multiplier Control

EXT_MPLLB_DI Controls the value of PHY's protocol0_ext_mpllb_div_multiplier signal in PCIe mode.
V_MULTIPLIER
23-20 Reserved
19 MPLLB Divide Clock Enable

EXT_MPLLB_DI Controls the value of PHY's protocol0_ext_mpllb_div_clk_en signal in PCIe mode.
V_CLK_EN
0b - Driven to 0
1b - Driven to 1
18 MPLLB Divide by 8 Enable

EXT_MPLLB_DI Controls the value of PHY's protocol0_ext_mpllb_div8_clk_en signal in PCIe mode.
V8_CLK_EN
0b - Driven to 0
1b - Driven to 1
17 Reserved
16 MPLLB Divide by 10 Enable

EXT_MPLLB_DI Controls the value of PHY's protocol0_ext_mpllb_div10_clk_en signal in PCIe mode.
V10_CLK_EN
0b - Driven to 0
1b - Driven to 1

NXP Semiconductors
Field Function
15-0 MPLLB Bandwidth Control

EXT_MPLLB_B Controls the value of PHY's protocol0_ext_mpllb_bandwidth signal in PCIe mode.
ANDWIDTH
Offset
Register Offset
_CTRL_2
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserv Reserv Reserv

R
ed Reserved ed Reserved ed EXT_MPLLB_FRACN_CTRL
W
Reset 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserved
EXT_MPLLB_FRACN_CTRL EXT_MPLLB_MULTIPLIER
W
Reset 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0
Fields
Field Function
31 Reserved
30-28 Reserved
27 Reserved

NXP Semiconductors
Field Function
26-24 Reserved
23 Reserved
22-12 MPLLB Fractional Control

EXT_MPLLB_F Controls the value of PHY's protocol0_ext_mpllb_fracn_ctrl signal in PCIe mode.
RACN_CTRL
11-8 Reserved
7-0 MPLLB Frequency Multiplier Control

EXT_MPLLB_M Controls the value of PHY's protocol0_ext_mpllb_multiplier signal in PCIe mode.
ULTIPLIER
Offset
Register Offset
_CTRL_3
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R EXT_M EXT_MPLLB_TX_CLK_D Reserved

Reserved
W PL... IV
Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserved
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
Fields
Field Function
31 MPLLB Word Clock Divide by 2

EXT_MPLLB_W Controls the value of PHY's protocol0_ext_mpllb_word_div2_en signal in PCIe mode.
ORD_DIV2_EN
0b - Driven to 0
1b - Driven to 1
30-28 MPLLB Tx Clock Divide

EXT_MPLLB_T Controls the value of PHY's protocol0_ext_mpllb_tx_clk_div signal in PCIe mode.
X_CLK_DIV
27-25 Reserved
24-16 Reserved
15-12 Reserved
11-0 Reserved

Offset
Register Offset
PCIE_PHY_EXT_RX_EQ 50h
_CTRL_1A
Function
Overrides receiver equalization settings for PCIe Gen1 speed when external control of PHY settings is enabled.

NXP Semiconductors
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
EXT_RX_EQ_CTLE_POLE_G1 EXT_RX_EQ_CTLE_BOOST_G1
W
Reset 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserved EXT_RX_ADAP EXT_RX_ADAP

EXT_RX_EQ_ATT_LVL_G1
W T_DF... T_AF...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-26 RX Equalization CTLE Pole

EXT_RX_EQ_C Controls the value of PHY's protocol0_ext_rx_eq_ctle_pole_g1 signal in PCIe mode.
TLE_POLE_G1
25-16 RX Equalization CTLE Boost

EXT_RX_EQ_C Controls the value of PHY's protocol0_ext_rx_eq_ctle_boost_g1 signal in PCIe mode.
TLE_BOOST_G
1
15-10 Reserved
9-4 RX Equalization Attenuation Level

EXT_RX_EQ_A Controls the value of PHY's protocol0_ext_rx_eq_att_lvl_g1 signal in PCIe mode.
TT_LVL_G1
3-2 RX DFE Enable

EXT_RX_ADAP Controls the value of PHY's protocol0_ext_rx_adapt_dfe_en_g1 signal in PCIe mode.
T_DFE_EN_G1
1-0 RX Adaptation Enable

EXT_RX_ADAP Controls the value of PHY's protocol0_ext_rx_adapt_afe_en_g1 signal in PCIe mode.
T_AFE_EN_G1

NXP Semiconductors

Offset
Register Offset
_CTRL_1B
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
EXT_RX_EQ_VGA2_GAIN_G1 EXT_RX_EQ_VGA1_GAIN_G1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
EXT_RX_EQ_DFE_TAP1_G1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-24 RX Equalization VGA Gain 2

EXT_RX_EQ_V Controls the value of PHY's protocol0_ext_rx_eq_vga2_gain_g1 signal in PCIe mode.
GA2_GAIN_G1

GA1_GAIN_G1
15-0 RX Equalization DFE Tap1

EXT_RX_EQ_D Controls the value of PHY's protocol0_ext_rx_eq_dfe_tap1_g1 signal in PCIe mode.
FE_TAP1_G1

NXP Semiconductors

Offset
Register Offset
_CTRL_1C
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserved
EXT_RX_EQ_DELTA_IQ_G1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-8 Reserved
7-0 RX Equalization DELTA IQ

EXT_RX_EQ_D Controls the value of PHY's protocol0_ext_rx_eq_ctle_pole_g1 signal in PCIe mode.
ELTA_IQ_G1

Offset
Register Offset
_CTRL_2A

NXP Semiconductors
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

W T_DF... T_AF...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function

TLE_POLE_G2

TLE_BOOST_G
2
15-10 Reserved

TT_LVL_G2
3-2 RX DFE Enable

T_DFE_EN_G2

T_AFE_EN_G2

NXP Semiconductors

Offset
Register Offset
_CTRL_2B
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function

GA2_GAIN_G2

GA1_GAIN_G2

FE_TAP1_G2

NXP Semiconductors

Offset
Register Offset
_CTRL_2C
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-8 Reserved

ELTA_IQ_G2

Offset
Register Offset
_CTRL_3A

NXP Semiconductors
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

W T_DF... T_AF...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
Fields
Field Function

TLE_POLE_G3

TLE_BOOST_G
3
15-10 Reserved

TT_LVL_G3
3-2 RX DFE Enable

T_DFE_EN_G3

T_AFE_EN_G3

NXP Semiconductors

Offset
Register Offset
_CTRL_3B
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function

GA2_GAIN_G3

GA1_GAIN_G3

FE_TAP1_G3

NXP Semiconductors

Offset
Register Offset
_CTRL_3C
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1
Fields
Field Function
31-8 Reserved

ELTA_IQ_G3

Offset
Register Offset
_CTRL_4A

NXP Semiconductors
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

W T_DF... T_AF...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
Fields
Field Function

TLE_POLE_G4

TLE_BOOST_G
4
15-10 Reserved

TT_LVL_G4
3-2 RX DFE Enable

T_DFE_EN_G4

T_AFE_EN_G4

NXP Semiconductors

Offset
Register Offset
_CTRL_4B
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function

GA2_GAIN_G4

GA1_GAIN_G4

FE_TAP1_G4

NXP Semiconductors

Offset
Register Offset
_CTRL_4C
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1
Fields
Field Function
31-8 Reserved

ELTA_IQ_G4
2.28 PCIe PHY Calibration Control For Gen1 Speed (PCIE_PHY_EXT_CALI_CTRL_1)
Offset
Register Offset
PCIE_PHY_EXT_CALI_ 90h
CTRL_1
Function
Overrides receiver calibration settings for PCIe Gen1 speed when external control of PHY settings is enabled.

NXP Semiconductors
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R Reserved
EXT_RX_REF_LD_VAL_G1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserved
EXT_RX_VCO_LD_VAL_G1
W
Reset 0 0 0 0 0 1 0 1 0 1 0 0 0 1 1 0
Fields
Field Function
31-22 Reserved
21-16 RX VCO Calibration Reference Load Value

EXT_RX_REF_ Controls the value of PHY's protocol0_ext_rx_ref_ld_val_g1 signal in PCIe mode.
LD_VAL_G1
15-13 Reserved
12-0 RX VCO Calibration Load Value

EXT_RX_VCO_ Controls the value of PHY's protocol0_ext_rx_vco_ld_val_g1 signal in PCIe mode.
LD_VAL_G1
Offset
Register Offset
CTRL_2
Function

NXP Semiconductors
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserved
W
Reset 0 0 0 0 0 1 0 1 0 1 0 0 0 1 1 0
Fields
Field Function
31-22 Reserved

LD_VAL_G2
15-13 Reserved

LD_VAL_G2
Offset
Register Offset
CTRL_3
Function

NXP Semiconductors
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserved
W
Reset 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 0
Fields
Field Function
31-22 Reserved

LD_VAL_G3
15-13 Reserved

LD_VAL_G3
Offset
Register Offset
PCIE_PHY_EXT_CALI_ 9Ch
CTRL_4
Function

NXP Semiconductors
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserved
W
Reset 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 0
Fields
Field Function
31-22 Reserved

LD_VAL_G4
15-13 Reserved

LD_VAL_G4
2.32 PCIe PHY Miscellaneous Control 1 (PCIE_PHY_EXT_MISC_CTRL_1)
Offset
Register Offset
PCIE_PHY_EXT_MISC_ A0h
CTRL_1
Function
Overrides miscellaneous PHY settings when external control of PHY settings is enabled.

NXP Semiconductors
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R Reserved EXT_RX_LOS_PWR_UP
EXT_RX_TERM_CTRL EXT_RX_VREF_CTRL
W _CNT
Reset 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserv
R EXT_R
EXT_RX_LOS_PWR_UP_CNT ed EXT_RX_LOS_THRESHOLD
X_...
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0
Fields
Field Function
31-29 RX Term Control

EXT_RX_TERM Controls the value of PHY's protocol0_ext_rx_term_ctrl signal in PCIe mode.
_CTRL
28-24 RX Biasing Current Control

EXT_RX_VREF Controls the value of PHY's protocol0_ext_rx_vref_ctrl signal in PCIe mode.
_CTRL
23-19 Reserved
18-8 Receiver LOS Power Up Counter

EXT_RX_LOS_ Controls the value of PHY's protocol0_ext_rx_los_pwr_up_cnt signal in PCIe mode.
PWR_UP_CNT
7 Reserved
6-1 Receiver LOS Threshold

EXT_RX_LOS_ Controls the value of PHY's protocol0_ext_rx_los_threshold signal in PCIe mode.
THRESHOLD
0 Receiver LOS LFPS Enable

EXT_RX_LOS_ Controls the value of PHY's protocol0_ext_rx_los_lfps_en signal in PCIe mode.
LFPS_EN
0b - Driven to 0
1b - Driven to 1

NXP Semiconductors
2.33 PCIe PHY Miscellaneous Control 2 (PCIE_PHY_EXT_MISC_CTRL_2)
Offset
Register Offset
PCIE_PHY_EXT_MISC_ A4h
CTRL_2
Function
Overrides miscellaneous PHY settings when external control of PHY settings is enabled.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R Reserved Reserved
EXT_TX_TERM_CTRL EXT_TX_VBOOST_LVL
W
Reset 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserved
EXT_TX_IBOOST_LVL
W
Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Fields
Field Function
31-27 Reserved
26-24 Tx Term Control

EXT_TX_TERM Controls the value of PHY's protocol0_ext_tx_term_ctrl signal in PCIe mode.
_CTRL
23-19 Reserved
18-16 TX Voltage Boost Maximum Level

EXT_TX_VBOO Controls the value of PHY's protocol0_ext_tx_vboost_lvl signal in PCIe mode.
ST_LVL
15-8 Reserved
7-0 Transmitter Current Boost Level

NXP Semiconductors
Field Function
EXT_TX_IBOO Controls the value of PHY's protocol0_ext_tx_iboost_lvl signal in PCIe mode.

ST_LVL
2.34 PCIe PHY TX Equalization Control For Gen1 Speed (PCIE_PHY_EXT_TX_EQ_CTRL_1)
Offset
Register Offset
PCIE_PHY_EXT_TX_EQ B0h
_CTRL_1
Function
Overrides transmitter equalization settings for PCIe Gen1 speed when external control of PHY settings is enabled.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R Reserved EXT_TX_EQ_O Reserved

EXT_TX_EQ_MAIN_G1
W VRD_...
Reset 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
EXT_TX_EQ_PRE_G1 EXT_TX_EQ_POST_G1
W
Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0
Fields
Field Function
31-30 Reserved
29-28 TX Equalization Override Enable

EXT_TX_EQ_O Controls the value of PHY's protocol0_ext_tx_eq_ovrd_g1 signal in PCIe mode.
VRD_G1
27-26 Reserved
25-16 TX Equalization Amplitude Adjustment Control

NXP Semiconductors
Field Function
EXT_TX_EQ_M Controls the value of PHY's protocol0_ext_tx_eq_main_g1 signal in PCIe mode.

AIN_G1
15-8 TX Equalization Pre-Emphasis Level Adjustment Control

EXT_TX_EQ_P Controls the value of PHY's protocol0_ext_tx_eq_pre_g1 signal in PCIe mode.
RE_G1
7-0 TX Equalization Post-Emphasis Level Adjustment Control

EXT_TX_EQ_P Controls the value of PHY's protocol0_ext_tx_eq_post_g1 signal in PCIe mode.
OST_G1
Offset
Register Offset
_CTRL_2
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

EXT_TX_EQ_MAIN_G2
W VRD_...
Reset 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0
Fields
Field Function
31-30 Reserved

NXP Semiconductors
Field Function

VRD_G2
27-26 Reserved

AIN_G2

RE_G2

OST_G2
Offset
Register Offset
_CTRL_3
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

EXT_TX_EQ_MAIN_G3
W VRD_...
Reset 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 1 0 0 0 1 0 0 1 0 1 0 1 0 1

NXP Semiconductors
Fields
Field Function
31-30 Reserved

VRD_G3
27-26 Reserved

AIN_G3

RE_G3

OST_G3
2.37 PCIe PHY XPCS_0 Rx Override Control (PCIE_PHY_XPCS0_RX_OVRD_CTRL)
Offset
Register Offset
PCIE_PHY_XPCS0_RX_ C0h
OVRD_CTRL
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R Reserved
XPCS0_RX_VCO_LD_VAL
W
Reset 0 0 0 0 0 1 0 1 0 1 0 0 0 1 1 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserved Reserved XPCS0

XPCS0_RX_REF_LD_VAL
W _R...
Reset 0 0 0 1 1 0 1 1 0 0 0 0 0 0 0 1

NXP Semiconductors
Fields
Field Function
31-29 Reserved
28-16 Override Control for xpcs0_rx0_vco_ld_val

XPCS0_RX_VC Controls the value of PMA's xpcs0_rx0_vco_ld_val signal in working mode 1.
O_LD_VAL
15-14 Reserved
13-8 Override Control For xpcs0_rx0_ref_ld_val

XPCS0_RX_RE Controls the value of PMA's xpcs0_rx0_ref_ld_val signal in working mode 1.
F_LD_VAL
7-1 Reserved
0 XPCS_0 RX Override Control

XPCS0_RX_OV Controls whether XPCS_0 overrides PMA's rx1_ref_ld_val and rx1_vco_ld_val signals in working mode 1.
RD
0b - Does not override
1b - Overrides
2.38 PCIe PHY XPCS_1 Rx Override Control (PCIE_PHY_XPCS1_RX_OVRD_CTRL)
Offset
Register Offset
PCIE_PHY_XPCS1_RX_ D0h
OVRD_CTRL
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R Reserved
XPCS1_RX_VCO_LD_VAL
W
Reset 0 0 0 0 0 1 0 1 0 1 0 0 0 1 1 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserved Reserved XPCS1

XPCS1_RX_REF_LD_VAL
W _R...
Reset 0 0 0 1 1 0 1 1 0 0 0 0 0 0 0 1

NXP Semiconductors
Fields
Field Function
31-29 Reserved
28-16 Override Control for xpcs1_rx0_vco_ld_val

XPCS1_RX_VC Controls the value of PMA's rx1_vco_ld_val signal in working mode 2.
O_LD_VAL
15-14 Reserved
13-8 Override Control For xpcs1_rx0_ref_ld_val

XPCS1_RX_RE Controls the value of the rx1_ref_ld_val signal in working mode 2.
F_LD_VAL
7-1 Reserved
0 XPCS_1 RX Override Control

XPCS1_RX_OV Controls whether XPCS_1 overrides PMA's rx1_ref_ld_val and rx1_vco_ld_val signals in working mode 2.
RD
0b - Does not override
1b - Overrides
2.39 Subsystem Read-Only Register 0 (SS_RO_REG_0)
Offset
Register Offset
SS_RO_REG_0 E0h
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCS1_ PCS1_ PCS1_ PCS0_ PCS0_ PCS0_ CDM_ CDM_ CDM_ PCS1_
R MSTR_ARMISC_INFO_DMA
LI... SG... SG... LI... SG... SG... REG... REG... REG... LI...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCS1_ PCS0_LINK_S MSTR MSTR PHY_ PHY_

R MSI_CTRL_INT_VEC 0
LI... PEED _AR... _AW... RX1... RX0...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0

NXP Semiconductors
Fields
Field Function
31-26 DMA Bits Of The AXI Read Master Transaction

MSTR_ARMISC This field is not part of the standard AXI interface. It is optional for your application.
_INFO_DMA
Bits 5:3 of this field indicate the DMA channel number.
Bits 2:0 of this field indicate the DMA request type as follows:
• 000: Non-DMA request
• 001: DMA write channel MRd request
• 010: Non-DMA completion
• 011: DMA read channel MWr request
• 100: Reserved
• 101: DMA write channel LL element MRd request
• 110: Reserved
• 111: DMA read channel LL element MRd request
25 XPCS_1 Receive Link Status

PCS1_LINK_ST Indicates whether the receive link is up or down.
ATUS
0b - Link down
1b - Link up
24 SGMII Full Duplex Of XPCS_1

PCS1_SGMII_F Indicates whether SGMII supports full duplex or half duplex, as programmed by the DUPLEX_MODE
ULL_DUPLEX field of SR MII MMD Control (SR_MII_CTRL).
0b - Half duplex
1b - Full duplex
23 SGMII Link Status Of XPCS_1

PCS1_SGMII_L Indicates the link status as programmed in the SGMII_LINK_STS field of VR MII MMD AN Control
INK_STS (VR_MII_AN_CTRL).
0b - Link down
1b - Link up
22 XPCS_0 Receive Link Status

PCS0_LINK_ST Indicates whether the receive link is up or down.
ATUS
0b - Link down
1b - Link up
21 SGMII Full Duplex Of XPCS_0

PCS0_SGMII_F Indicates whether SGMII supports full duplex or half duplex, as programmed by the DUPLEX_MODE
ULL_DUPLEX field of SR MII MMD Control (SR_MII_CTRL).

NXP Semiconductors
Field Function
0b - Half duplex
1b - Full duplex
20 SGMII Link Status Of XPCS_0

PCS0_SGMII_L Indicates the link status as programmed in the SGMII_LINK_STS field of VR MII MMD AN Control
INK_STS (VR_MII_AN_CTRL).
0b - Link down
1b - Link up
19 Register Checking Complete

CDM_REG_CH Indicates whether a register-checking sequence has completed.
K_CMPLT
0b - Not completed
1b - Completed
18 CDM Comparison Error

CDM_REG_CH Indicates that the register values read from both CDMs do not match.
K_CMP_ERR
0b - The values are not matched.
1b - The values are matched.
17 Error In Register-Checking Logic

CDM_REG_CH Indicates that there is an error in the register-checking logic.
K_LOGIC_ERR
0b - No error
1b - Error
16-15 SGMII MAC Speed Control

PCS1_LINK_SP Indicates the current operating speed of XPCS_1 in SGMII mode.
EED
00b - 10 Mbps
01b - 100 Mbps
10b - 100 Mbps
11b - Reserved
14-13 SGMII MAC Speed Control

PCS0_LINK_SP Indicates the current operating speed of XPCS_0 in SGMII mode.
EED
00b - 10 Mbps
01b - 100 Mbps
10b - 1000 Mbps
11b - Reserved
12-5 DSP AXI MSI Interrupt Vector

NXP Semiconductors
Field Function
MSI_CTRL_INT Each bit in this field corresponds to a given endpoint number.

_VEC
When a bit is 1, an MSI interrupt is pending.
When a bit is 0, no MSI interrupt is pending.
4 Last TLP Of The PCIe Controller's AXI Master Read Request
MSTR_ARMISC 0b - The TLP in the transaction is not the last TLP of the read request.
_INFO_LAST_D 1b - The TLP in the transaction is the last TLP of the read request.
CMP_TLP
3 Last TLP Of The PCIe controller's AXI Master Write Request
MSTR_AWMIS 0b - The TLP in the transaction is not the last TLP of the write request.
C_INFO_LAST_ 1b - The TLP in the transaction is the last TLP of the write request.
DCMP_TLP
2 Receive Loss Of Signal (LOS) Output 1

PHY_RX1_LOS This field is only valid for low-frequency data on rx1_p/rx1_m.
0b - The receiver has not lost the signal.
1b - The receiver has lost the signal.
1 Receive Loss Of Signal (LOS) Output 0

PHY_RX0_LOS This field is only valid for low-frequency data on rx0_p/rx0_m.
0b - The receiver has not lost the signal.
1b - The receiver has lost the signal.
0 Reserved
Offset
Register Offset
SS_RO_REG_1 E4h

NXP Semiconductors
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLV_B
R 0 SLV_RMISC_INFO
MI...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R SLV_BMISC_INFO MSTR_AWMISC_INFO_DMA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-28 Reserved
27-17 Miscellaneous Read Information

SLV_RMISC_IN Contains miscellaneous information associated with the response from the AXI slave read transaction.
FO
This field is not part of the standard AXI interface. It is optional for your application.
The bits within this field have the following meanings:
• Bit 0: Completion timeout
• Bit 1: TLP's EP
• Bits 4:2: TLP's TC
• Bit 5: TLP's NS
• Bit 6: TLP's RO
• Bits 9:7: TLP's completion status
• Bit 10: Non-posted request
16-6 Miscellaneous Write Information

SLV_BMISC_IN Contains miscellaneous information associated with the response from the AXI slave write transaction.
FO
This field is not part of the standard AXI interface. It is optional for your application.
• Bit 0: Completion timeout
• Bit 1: TLP's EP
• Bit 5: TLP's NS
• Bit 6: TLP's RO

NXP Semiconductors
Field Function
• Bits 9:7: TLP's completion status

• Bit 10: Non-posted request
5-0 DMA Bits Of The AXI Write Master Transaction

MSTR_AWMIS This field is not part of the standard AXI interface. It is optional for your application.
C_INFO_DMA
Bits 5:3 of this field indicate the DMA channel number.
Bits 2:0 of this field indicate the DMA request type as follows:
• 000: Non-DMA request
• 001: DMA write channel MRd request
• 010: Non-DMA completion
• 011: DMA read channel MWr request
• 100: Reserved
• 101: DMA write channel LL element MRd request
• 110: Reserved
• 111: DMA read channel LL element MRd request
Offset
Register Offset
SS_RO_REG_2 E8h
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R REG2
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R REG2
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
Fields
Field Function
31-0 Subsystem Read Only Register 2
REG2
Offset
Register Offset
SS_RO_REG_3 ECh
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R REG3
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R REG3
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0 Subsystem Read Only Register 3
REG3
2.43 Subsystem Read/Write Register 0 (SS_RW_REG_0)
Offset
Register Offset
SS_RW_REG_0 F0h

NXP Semiconductors
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R MSTR PHY_T Reserv PHY_T Reserv SLV_A SLV_A CLKE

MDR SLV_AWMISC_INFO_P_TAG
W _RM... ES... ed ES... ed WM... RM... N
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R SLV_A SLV_ MSTR_RMISC_ MSTR_BMISC_ PHY0_ Reserv APP_X SYS_ SYS_E SYS_C SYS_A
SUBSYS_MODE
W WM... WMI... INFO... INFO... CR... ed FE... INT ML... MD... TT...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31 Miscellaneous Information Related To AXI Master Read-Response Transactions

MSTR_RMISC_ This field offers your application the option of poisoning read requests.
INFO
0b - The controller operates normally.
1b - The controller sets the Poisoned TLP (EP) bit in the TLP header of the current and
subsequent read-data transactions.
30 Memory Data Retention

MDR Controls how the subsystem stores data during Standby mode.
0b - The subsystem retains data stored in memory and disables data inputs.
1b - The subsystem does not retain data stored in memory.
29 TX Reference Clock Output Enable
PHY_TEST_TX 0b - Normal functional operation

_REF_CLK_EN 1b - The reference clock inputs (ref_pad_clk_{p,m} or ref_alt_clk_{p,m}) are directly output to
txN_{p,m}
28 Reserved
27 All Circuits Power-Down Control

PHY_TEST_PO After you write a 1 to PHY_TEST_POWERDOWN, the PHY will stop functioning. If you then write a 0 to
WERDOWN PHY_TEST_POWERDOWN, you must reset the PHY to make it function again.
0b - The PHY circuitry operates normally.
1b - The PHY deactivates all its circuitry for IDDQ testing.
26 Reserved
25 AXI Slave Write Request iATU Bypass

NXP Semiconductors
Field Function
SLV_AWMISC_ 0b - The iATU must process this request.

INFO_ATU_BY
1b - The iATU must not process this request.
PASS
24 AXI Slave Read Request iATU Bypass
SLV_ARMISC_I 0b - The iATU must process this request.

NFO_ATU_BYP 1b - The iATU must not process this request.
ASS
23 PCIe Reference Clock Enable
CLKEN 0b - External clock (phy0_ref_pad_clk_m, phy0_ref_pad_clk_p) is the reference clock for the PCIe
PHY PLL.
1b - Internal clock (PCIE_REF_CLK) is the reference clock for the PCIe PHY PLL.
22-15 AXI Slave Write Request Tag

SLV_AWMISC_ Sets the tag number for output-posted requests. Your application must write a 0 to this field except when
INFO_P_TAG it generates ATS-invalidate requests.
14 Miscellaneous Information Related To AXI Slave Write-Data Transactions

SLV_WMISC_I Offers your application the option of poisoning write requests.
NFO
This field is not a part of the standard AXI interface.
0b - The controller operates normally.
1b - The controller sets the Poisoned TLP (EP) bit in the TLP header of the current and
subsequent write-data transactions.
13-12 AXI Master Read Response Selection Bus

MSTR_RMISC_ Controls the response to be sent on the wire in the case of successful read requests.
INFO_CPL_ST
The controller always sends a completer abort response when it receives:
AT
• A slave error (SLVERR), used when the access has reached the slave successfully, but the slave
wishes to return an error condition to the originating master
• A decode error (DECERR), used to indicate that no slave exists at the transaction address
00b - Successful completion
01b - Completer abort
10b - Unsupported request
11-10 AXI Master Write Response Selection Bus

MSTR_BMISC_ Controls the response to be sent on the wire in the case of successful write requests. The controller
INFO_CPL_ST always sends a completer abort response when it receives SLVERR/DECERR.
AT

NXP Semiconductors
Field Function
01b - Completer abort

10b - Unsupported request
9 Control Register (CR) Parallel Interface Select

PHY0_CR_PAR You can change this field only when the CR parallel clock and JTAG TCK clock inputs are disabled.
A_SEL
0b - Select the JTAG interface.
1b - Select the CR interface.
8 Reserved
7 Application Transfer Pending

APP_XFER_PE This field indicates whether the current application has pending transfers and prevents the core from
NDING entering L1. This field informs the core about the state of external queues and pipeline stages that
contain transactions for the core to transmit. The core uses this information to determine when to enter
or exit L1.
0b - No transactions exist outside the core
1b - Transactions exist outside the core, and the core must transmit these
6 System Interrupt
SYS_INT When SYS_INT goes from low to high, the controller generates an Assert_INTx message. When
SYS_INT goes from high to low, the controller generates a Deassert_INTx message.
5 System Electromechanical Interlock Engaged
SYS_EML_INT 0b - Electromechanical interlock is not engaged

ERLOCK_ENG 1b - Electromechanical interlock is engaged
AGED
4 Command Completed Interrupt

SYS_CMD_CPL Indicates that the hot-plug controller completed a command.
ED_INT
0b - Command not completed
1b - Command completed
3 Attention Button Pressed

SYS_ATTEN_B Indicates that the system attention button was pressed.
UTTON_PRES
SED
2-0 Subsystem Mode Selection

SUBSYS_MOD If you need to enable 2.5G SGMII with PCIe on SerDes lane 0, write 010b to this field and perform the
E procedure in Enabling 2.5G SGMII with PCIe on SerDes lane 0.

NXP Semiconductors
Field Function
000b - PCIe Gen3x2 mode

001b - PCIe Gen3x1 and SGMII 1G bifurcation mode (lane 1 = XPCS_0)
010b - PCIe Gen3x1 and SGMII 1G bifurcation mode (lane 1 = XPCS_1)
011b - Two SGMII 1G/2.5G bifurcation mode, XPCS_0 assigned to PHY control
100b - Two SGMII 1G/2.5G bifurcation mode, XPCS_1 assigned to PHY control
101b - Reserved
110b - Reserved
111b - Reserved
Offset
Register Offset
SS_RW_REG_1 F4h
Function
Controls parity error injection on the AXI slave-read interface.
After you inject parity error, the PCIe controller generates a TLP that the link partner detects as a nullified TLP. As
a result, the link partner does not send any completion confirmation. In this case, the slave AXI read interface gets
a response via the completion-timeout mechanism. Therefore, you must not disable the PCIe controller's completion-
timeout mechanism (via DEVICE_CONTROL2_DEVICE_STATUS2_REG[PCIE_CAP_CPL_TIMEOUT_VALUE] for EP mode
and DEVICE_CONTROL2_DEVICE_STATUS2_REG[PCIE_CAP_CPL_TIMEOUT_VALUE] for RC mode). This mechanism is
enabled by default. If you disable that mechanism, it might cause AXI to hang, which in turn might cause NoC to hang.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R PARIT PARIT PARIT PARIT PARIT PARIT PARIT PARIT

Reserved
W Y_... Y_... Y_... Y_... Y_... Y_... Y_... Y_...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
Fields
Field Function
31-8 Reserved
7 Parity Error Injection In AXI Slave Read Data Bus

PARITY_MODE Allows you to inject a parity error into the specified bus.
_SLV_RD_DAT
The PCIe controller normally uses and expects odd parity. This corresponds to a value of 0 in this field.
A
When you write a 1 to this field, the PCIe controller uses even parity. This injects a parity error.
0b - No error injected
1b - Error injected
6 Parity Error Injection In AXI Master Write Data Bus

_MSTR_WR_D
ATA
1b - Error injected
5 Parity Error Injection In AXI Master Write Address Bus

_MSTR_WR_A
DDR
1b - Error injected
4 Parity Error Injection In AXI Master Read Address Bus

_MSTR_RD_AD
DR
1b - Error injected
3 Parity Error Injection In AXI Slave Write Data Bus

_SLV_WR_DAT
A
1b - Error injected
2 Parity Error Injection In AXI Slave Write Address Bus

NXP Semiconductors
Field Function
_SLV_WR_ADD
R
1b - Error injected
1 Parity Error Injection In AXI Slave Read Address Bus

_SLV_RD_ADD
R
1b - Error injected
0 Parity Error Injection In AXI Master Read Data Bus

_MSTR_RD_DA
TA
1b - Error injected
Offset
Register Offset
SS_RW_REG_2 F8h
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved SLV_ARMISC_INFO
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
SLV_ARMISC_INFO
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
Fields
Field Function
31-22 Reserved
21-0 Miscellaneous Information Associated With The AXI Slave Read Transaction
SLV_ARMISC_I This field is not part of the standard AXI interface. It is optional for your application.
NFO
• Bits 4:0: TLP's type
• Bit 5: Reserved
• Bit 6: TLP's EP
• Bit 7: Reserved
• Bit 8: TLP's NS
• Bit 9: TLP's RO
• Bits 20:13: TLP's MSG code
• Bit 21: AXI transaction is a DBI access (only for shared DBI mode)
Offset
Register Offset
SS_RW_REG_3 FCh
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved SLV_AWMISC_INFO
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
SLV_AWMISC_INFO
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
Fields
Field Function
31-22 Reserved
21-0 Miscellaneous Information Associated With The AXI Slave Write Transaction
SLV_AWMISC_ This field is not part of the standard AXI interface. It is optional for your application.
INFO
• Bits 4:0: TLP's type
• Bit 5: Reserved
• Bit 6: TLP's EP
• Bit 7: Reserved
• Bit 8: TLP's NS
• Bit 9: TLP's RO
• Bits 20:13: TLP's MSG code
• Bit 21: AXI transaction is a DBI access (only for shared DBI mode)
Offset
Register Offset
SS_RW_REG_4 100h
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
SLV_AWMISC_INFO_HDR_3DW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
Fields
Field Function
31-0 AXI Slave Third Header DWs

SLV_AWMISC_ You program this field with the third header DWs that you intend to send on a PCIe Msg/MsgD.
INFO_HDR_3D
The data is in big-endian format. So, for example, bits 7:0 of this field contain byte 15 of the header DW.
W
Offset
Register Offset
SS_RW_REG_5 104h
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0 AXI Slave Fourth Header DWs

SLV_AWMISC_ You program this field with the fourth header DWs that you intend to send on a PCIe Msg/MsgD.
INFO_HDR_4D
The data is in big-endian format. So, for example, bits 7:0 of this field contain byte 15 of the header DW.
W
2.49 PCIe Subsystem Version (PCIE_SUBSYSTEM_VERSION)
Offset
Register Offset
PCIE_SUBSYSTEM_VE 1000h
RSION

NXP Semiconductors
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R VERSION
Reset 0 1 0 1 0 0 0 0 0 0 0 0 1 0 1 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VERSION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0 PCIe Subsystem Version
VERSION
2.50 Link Interrupt Control And Status (LINK_INT_CTRL_STS)
Offset
Register Offset
LINK_INT_CTRL_STS 1040h
Function
Controls the enabling of PCIe link interrupts and monitors the status of the PCIe link interrupt.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LTSS Reserv LINK_ LINK_

R Reserved PHY_L PHY_L LINK_
M_S... ed RE... RE...
IN... IN... RE...
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
Fields
Field Function
31-7 Reserved
6 Recovery Equalization State Status

LTSSM_STATE Indicates whether the PCIe link is in Recovery Equalization state.
_RCVRY_EQ
0b - Not in Recovery Equalization state
1b - In Recovery Equalization state
5 PHY Link Up Interrupt Enable Control

PHY_LINK_UP_ Enables and disables interrupt generation for a PHY link-up event.
INT_EN
0b - Disable
1b - Enable
4 PHY Link Down Interrupt Enable Control

PHY_LINK_DO Enables and disables interrupt generation for a PHY link-down event.
WN_INT_EN
0b - Disable
1b - Enable
3 Reserved
2 Clear Link Request Reset Status

LINK_REQ_RS Causes LINK_REQ_RST_NOT_STS to become 0. After that field becomes 0,
T_NOT_CLR LINK_REQ_RST_NOT_CLR also becomes 0.
0b - Do not change LINK_REQ_RST_NOT_STS
1b - Change LINK_REQ_RST_NOT_STS to 0
1 Link Request Reset Interrupt Enable Control

LINK_REQ_RS Enables and disables the link request reset interrupt. Active high.
T_NOT_INT_EN
0b - Disable
1b - Enable
0 Link Request Reset Status

LINK_REQ_RS Indicates the link request reset status. Active high.
T_NOT_STS
0b - Not set
1b - Set

NXP Semiconductors
2.51 PCIe Controller 0 General Control 1 (PE0_GEN_CTRL_1)
Offset
Register Offset
PE0_GEN_CTRL_1 1050h
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserv Reserv
R TX_LA Reserved RX_LA Reserved
ed ed
NE... NE...
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserv
R Reserved SRIS_ Reserved DEVIC
ed DEVICE_TYPE
MO... E_...
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31 Reserved
30 Manual Lane Reversal For Transmit Lanes In C-PCIe Mode

TX_LANE_FLIP Enables and disables manual lane reversal for transmit lanes.
_EN
For use when automatic lane reversal does not occur because lane 0 is not detected. It must be stable
before PCIe link establishment.
0b - Disabled
1b - Enabled
29-24 Reserved
23 Reserved
22 Manual Lane Reversal For Receive Lanes In C-PCIe Mode

RX_LANE_FLIP Enables and disables manual lane reversal for receive lanes.
_EN

NXP Semiconductors
Field Function
For use when automatic lane reversal does not occur because lane 0 is not detected. It must be stable
before PCIe link establishment.
0b - Disabled
1b - Enabled
21-16 Reserved
15-9 Reserved
8 SRIS Operation Mode

SRIS_MODE See Requirements for Split Reference Independent Spread Spectrum (SRIS).
0b - Non-SRIS
1b - SRIS
7-6 Reserved
5 Reserved
4 Override Device Type

DEVICE_TYPE Allows you to override the device type.
_OVERRIDE
0b - You cannot override the device type.
1b - You can override the device type.
3-0 Device Type

DEVICE_TYPE Controls the PCIe controller device type, PHY type, SRIS mode and manual lane flip enable.
0000b - Endpoint
0100b - Root port of root complex
0110b - Upstream switch port
All other values are reserved.
Offset
Register Offset

NXP Semiconductors
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserved SLV_A MSTR Reserved
W CL... _AC...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-10 Reserved
9 AXI Slave Clock Gating Control

SLV_ACLK_UN Controls the gating of the AXI slave clock when the AXI master is inactive.
GATE
0b - Gate
1b - Do not gate
8 AXI Master Clock Gating Control

MSTR_ACLK_U Controls the gating of the AXI master clock when the AXI master is inactive.
NGATE
0b - Gate
1b - Do not gate
7-0 Reserved
Offset
Register Offset
Function
Controls:
• LTSSM Enable
• Configuration Request Retry Status (CRS) Enable

NXP Semiconductors
• Hot reset
• Holding LTSSM in silicon debug
• Debug signal selection
• LCRC/ECRC error injection in silicon debug
• Timeout threshold for crosslink connection
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R Reserved Reserved Reserved

Reserved Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserved
RAS_ CRS_ LTSS
DIAG_CTRL_BUS Reserved HOT_
W DES... EN M_EN
RES...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-30 Reserved
29-28 Reserved
27-26 Reserved
25-24 Reserved
23-16 Reserved
15-13 Diagnostic Control Bus

DIAG_CTRL_B Bit 2: Select Fast Link mode
US
Bit 1: Insert ECRC error by inverting the LSB of ECRC
Bit 0: Insert LCRC error by inverting the LSB of LCRC
12-8 Reserved

NXP Semiconductors
Field Function
7-4 Reserved
3 Hold And Release LTSSM In Silicon Debug

RAS_DES_SD_ Allows you to keep the PCIe controller LTSSM in the current state.
HOLD_LTSSM
0b - LTSSM not held in current state, and might change on link events
1b - LTSSM held in current state and does not change
2 Hot Reset
HOT_RESET Allows you to trigger a hot reset.
This field always reads zero.
1b - Trigger a hot reset
1 Configuration Request Retry Status (CRS) Enable

CRS_EN Provides a capability to defer incoming configuration requests until initialization is complete.
Active high.
0b - PCIe controller does not complete incoming configuration requests with a Configuration
Request Retry Status.
1b - PCIe controller completes incoming configuration requests with a Configuration Request
Retry Status. Other incoming requests complete with unsupported request status.
0 LTSSM Enable
LTSSM_EN Active high.
0b - Hold LTSSM in the Detect state until your application is ready
1b - Allow LTSSM to continue link establishment and normal operation
Offset
Register Offset
PE0_GEN_CTRL_4 105Ch
Function
Controls:
• Device and function readiness
• MSI table and PBA table debug

NXP Semiconductors
• The LTSSM enable mask

• The CRS enable mask
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R CRS_E LTSS CFG_RAS_DES Reserved

Reserved
W N_... M_E... _TBA...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserv
R Reserved Reserved
ed
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31 CRS_EN Clear Mask

CRS_EN_CLR_ Controls what happens to CRS_EN when the PCIe link goes down.
MASK
0b - CRS_EN does not change
1b - CRS_EN goes to its reset value
30 LTSSM_EN Clear Mask

LTSSM_EN_CL Controls what happens to LTSSM_EN when the PCIe link goes down.
R_MASK
0b - LTSSM_EN does not change
1b - LTSSM_EN goes to its reset value
29-28 Start And End Of Time-Based Analysis

CFG_RAS_DES Controls the start and end of time-based analysis via the PCIE controller's
_TBA_CTRL app_ras_des_tba_ctrl[1:0] signals.
You can read and write to this field. However, it will always read 0.
This field returns to 0 automatically after one clock cycle.
The setting CFG_RAS_DES_TBA_CTRL=10b is only used when the TIME_BASED_DURATION_SELECT
field of Time-based Analysis Control (TIME_BASED_ANALYSIS_CONTROL_REG) (in RC mode) or
Time-based Analysis Control (TIME_BASED_ANALYSIS_CONTROL_REG) (in EP mode) is set to
"Manual control".
00b - No actions
01b - Start
10b - End
11b - Reserved

NXP Semiconductors
Field Function
27-26 Reserved
25-16 Reserved
15-9 Reserved
8 Reserved
7-0 Reserved
2.55 PCIe Controller 0 PM Control (PE0_PM_CTRL)
Offset
Register Offset
PE0_PM_CTRL 1060h
Function
Allows you to control:
• PM_PME requests
• Readiness of PM entry
• PM exit events
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R Reserved
BEAC APP_C APP_C READ EXIT_ ENTE
ON_... LK... LK... Y_E... AS... R_A... PM_P
W
ME_...
Reset 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserv
R Reserved Reserved
ed PME_PF_INDEX
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
Fields
Field Function
31 Beacon Interrupt Enable

BEACON_INT_ Enables and disables SII controller's assertion of rx_beacon_int when the SII controller receives a beacon
EN in L2.
Active high.
0b - Disable
1b - Enable
30-22 Reserved
21 Clock PM Feature Enable

APP_CLK_PM_ Enables and disables the Clock PM feature.
EN
0b - Disable
1b - Enable
20 Wake Up Reference Clock

APP_CLK_REQ Allows your application to request a wakeup of the reference clock.
0b - No request to wake up
1b - Explicit request to wake up
19 Ready To Enter L23

READY_ENTE Tells the PCIe controller that your application is ready to enter the L23 state.
R_L23
This field is intended for applications that must control L23 entry (in case certain tasks must be performed
before entering the L23 state). The PCIe controller delays sending PM_Enter_L23 (in response to
PM_Turn_Off) until this field is 1. Write 1 to this field for applications that do not require this feature.
0b - Not ready
1b - Ready
18 Request To Exit ASPM State L1

EXIT_ASPM_L1 Allows your application to request exit from ASPM State L1.
Only effective when ASPM L1 is enabled.
0b - No request to exit
1b - Explicit request to exit
17 Request To Enter ASPM State L1

ENTER_ASPM_ Allows your application to request entry into ASPM State L1.
L1
Only effective when ASPM L1 is enabled. The PCIe controller ignores the ASPM L1 entry request when it
is busy processing a transaction.

NXP Semiconductors
Field Function
0b - No request to enter
1b - Explicit request to enter
16 PM_PME Message Request

PM_PME_REQ The PF and VF indices are specified by PME_PF_INDEX, PME_VF_ACTIVE and PME_VF_INDEX. To
send a PM_Message, write 1 to this field. The read value of this field is always 0.
15-8 Reserved
7 Reserved
6-5 Reserved
4-0 PF Index Of PM_PME Request And PM Status

PME_PF_INDE Write the PF index before sending a PM_PME message or accessing PCIe Controller 0 PM Status
X (PE0_PM_STS).
2.56 PCIe Controller 0 PM Status (PE0_PM_STS)
Offset
Register Offset
PE0_PM_STS 1064h
Function
Monitors PCIe PM status.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BEAC Reserv Reserv Reserv

R Reserved Reserved
ON_... ed ed ed
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PM_LI PM_LI Reserv PM_LI PM_LI PM_S PM_P

R PM_CURNT_STATE Reserved PM_DSTATE
NK... NK... ed NK... NK... TAT... ME_...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0

NXP Semiconductors
Fields
Field Function
31 Beacon Interrupt Status

BEACON_INT_ Active high. When SII controller receives a beacon in L2 and Beacon Interrupt Enable is set, SII
STS controller will set Beacon Interrupt Status. Write 1 to this register will clear the status.
30-21 Reserved
20 Reserved
19 Reserved
18 Reserved
17-16 Reserved
15 Power Management Is Exiting L2 State

PM_LINKST_L2 Indicates whether power management is in L2 exit state.
_EXIT
Not applicable for downstream port.
0b - Not in L2 exit
1b - In L2 exit
14 Power Management In L2 State

PM_LINKST_IN Indicates whether the PM state is in L2 or not.
_L2
0b - Not in L2
1b - In L2
13 Reserved
12 Power Management In L1 State

PM_LINKST_IN Indicates whether the PM state is in L1 or not.
_L1
0b - Not in L1
1b - In L1
11 Power Management In L0s State

PM_LINKST_IN Indicates whether the PM state is in L0s or not.
_L0S

NXP Semiconductors
Field Function
0b - Not in L0s
1b - In L0s
10-8 PM Controller's Current Power State
PM_CURNT_S 000b - L0 and others

TATE 001b - L0S
010b - L1
011b - L2
100b - L3
7-5 Reserved
4 PME Status Mirror

PM_STATUS Mirrors the value of PMCSR[PME_STATUS] (when the PCIe controller is in EP mode) and
CON_STATUS_REG[PME_STATUS] (when the PCIe controller is in RC mode).
3 PME Enable Mirror

PM_PME_EN Mirrors the value of PMCSR[PME_ENABLE] (when the PCIe controller is in EP mode) and
CON_STATUS_REG[PME_ENABLE] (when the PCIe controller is in RC mode).
2-0 Current Power Management D-State
PM_DSTATE 000b - D0
001b - D1
010b - D2
011b - D3
100b - Uninitialized
2.57 PCIe Controller 0 Transmit Message Header 1 (PE0_TX_MSG_HDR_1)
Offset
Register Offset
PE0_TX_MSG_HDR_1 1070h
Function
Controls the first DWORD of the transmitted message's TLP header.

NXP Semiconductors
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserv Reserv Reserv Reserv Reserv Reserv

R
ed MSG_HDR_FM MSG_HDR_TYPE ed MSG_HDR_TC ed ed ed ed
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R MSG_ MSG_ MSG_HDR_AT Reserved MSG_HDR_LENGTH
W HDR... HDR... TR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31 Reserved
30-29 Format Field

MSG_HDR_FM Controls the Fmt field of the message TLP header.
28-24 Type Field
MSG_HDR_TY
PE
23 Reserved
22-20 Traffic Class
MSG_HDR_TC
19 Reserved
18 Reserved
17 Reserved
16 Reserved
15 TLP Digest (TD)

NXP Semiconductors
Field Function
MSG_HDR_TD Controls the TD field of the message TLP header.
14 Poisoned TLP (EP)

MSG_HDR_EP Controls the EP field of the message TLP header.
13-12 Attribute[1:0], Relaxing Ordering And No Snoop

MSG_HDR_AT Bit 0 of this field controls the "No Snoop" field of the message TLP header.
TR
Bit 1 of this field controls the "Relaxing Ordering" field of the message TLP header.
11-10 Reserved
9-0 Tied to 0.
MSG_HDR_LE
NGTH
Offset
Register Offset
Function
Controls the second DWORD of the transmitted message's TLP header.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MSG_HDR_BYTE4 MSG_HDR_BYTE5
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
Fields
Field Function
31-24 Requeser ID[15:8], Byte 4
MSG_HDR_BY
TE4
23-16 Requester ID[7:0], Byte 5
MSG_HDR_BY
TE5
15-8 Message Tag, Byte 6
MSG_HDR_BY
TE6
7-0 Message Code, Byte 7
MSG_HDR_BY
TE7
Offset
Register Offset
Function
Controls the third DWORD of the transmitted message's TLP header.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
Fields
Field Function
31-24 Byte 8
MSG_HDR_BY
TE8
23-16 Byte 9
MSG_HDR_BY
TE9
15-8 Byte 10
MSG_HDR_BY
TE10
7-0 Byte 11
MSG_HDR_BY
TE11
2.60 PCIe controller 0 transmit message header 4 (PE0_TX_MSG_HDR_4)
Offset
Register Offset
PE0_TX_MSG_HDR_4 107Ch
Function
Controls the fourth DWORD of the transmitted message's TLP header.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
Fields
Field Function
31-24 Byte 12
MSG_HDR_BY
TE12
23-16 Byte 13
MSG_HDR_BY
TE13
15-8 Byte 14
MSG_HDR_BY
TE14
7-0 Byte 15
MSG_HDR_BY
TE15
2.61 PCIe Controller 0 Transmit Message Request (PE0_TX_MSG_REQ)
Offset
Register Offset
PE0_TX_MSG_REQ 1080h
Function
Triggers a message-transmission request through the PCIe SII interface.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserv Reserv Reserv Reserv Reserv

R Reserved
ed ed ed ed VEN_ ed
UNLO PME_ MSG...
W
CK_... TUR...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserv
R Reserved Reserved
ed TX_MSG_PF_NUM
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
Fields
Field Function
31-24 Reserved
23 Reserved
22 Reserved
21 Reserved
20 Unlock message
UNLOCK_REQ Write 1 to this field to send an Unlock message.
The read value of this field is always 0.
This field is valid in RC mode.
19 PME_Turn_Off Message Request

PME_TURN_O Write 1 to this field to send a PME_Turn_Off message.
FF_REQ
The read value of this field is always 0.
This field is valid in RC mode.
18 Reserved
17 Vendor-Defined Message Request

VEN_MSG_RE The subsystem writes 0 to this field when the PCIe controller grants the vendor-defined message.
Q
0b - Normal operation
1b - Trigger a vendor-defined message request
16 Reserved
15-8 Reserved
7 Reserved
6-5 Reserved

NXP Semiconductors
Field Function
4-0 PF Number Of Message Requester
TX_MSG_PF_N
UM
2.62 PCIe Controller 0 Receive Message Header 1 (PE0_RX_MSG_HDR_1)
Offset
Register Offset
PE0_RX_MSG_HDR_1 1090h
Function
Monitors the first DWORD of the received message's TLP header.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R MSG_HDR_BYTE0 MSG_HDR_BYTE1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-24 Byte 0
MSG_HDR_BY
TE0
23-16 Byte 1
MSG_HDR_BY
TE1
15-8 Byte 2

NXP Semiconductors
Field Function
MSG_HDR_BY
TE2
7-0 Byte 3
MSG_HDR_BY
TE3
Offset
Register Offset
Function
Monitors the second DWORD of the received message's TLP header.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-24 Byte 4
MSG_HDR_BY
TE4
23-16 Byte 5
MSG_HDR_BY
TE5

NXP Semiconductors
Field Function
15-8 Byte 6
MSG_HDR_BY
TE6
7-0 Byte 7
MSG_HDR_BY
TE7
Offset
Register Offset
Function
Monitors the third DWORD of the received message's TLP header.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-24 Byte 8
MSG_HDR_BY
TE8
23-16 Byte 9

NXP Semiconductors
Field Function
MSG_HDR_BY
TE9
15-8 Byte 10
MSG_HDR_BY
TE10
7-0 Byte 11
MSG_HDR_BY
TE11
Offset
Register Offset
PE0_RX_MSG_HDR_4 109Ch
Function
Monitors the fourth DWORD of the received message's TLP header.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-24 Byte 12
MSG_HDR_BY
TE12

NXP Semiconductors
Field Function
23-16 Byte 13
MSG_HDR_BY
TE13
15-8 Byte 14
MSG_HDR_BY
TE14
7-0 Byte 15
MSG_HDR_BY
TE15
2.66 PCIe Controller 0 Receive Message Status (PE0_RX_MSG_STS)
Offset
Register Offset
PE0_RX_MSG_STS 10A0h
Function
Identifies the type of a captured message.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSGQ Reserv Reserv Reserv UNLO PME_ VDM_ VDM_ Reserv

R Reserved
_OV... ed ed ed CK_... TUR... TYP... TYP... ed
W W1C W1C W1C W1C W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PM_P PME_T
R Reserved Reserved
ME_... O_...
W W1C W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31 Receive Message Queue Overflow Status

NXP Semiconductors
Field Function
MSGQ_OVERF
LOW
30-24 Reserved
23 Reserved
22 Reserved
21 Reserved
20 Unlock Message Status

UNLOCK_STS Identifies whether an Unlock message is captured.
Write 1 to this field to return its value to 0.
Valid in EP mode.
0b - Not captured
1b - Captured
19 PME_Turn_Off Message Status

PME_TURN_O Identifies whether a PME_Turn_Off message is captured.
FF_STS
Valid in EP mode.
0b - Not captured
1b - Captured
18 Vendor-Defined Type 1 Message Status

VDM_TYPE1_S Identifies whether a vendor-defined Type 1 message is captured.
TS
0b - Not captured
1b - Captured
17 Vendor-Defined Type 0 Message Status

VDM_TYPE0_S Identifies whether a vendor-defined Type 0 message is captured.
TS
0b - Not captured

NXP Semiconductors
Field Function
1b - Captured
16 Reserved
15-13 Reserved
12 PM_PME Message Status

PM_PME_STS Identifies whether a PM_PME message is captured.
Valid in RC mode.
0b - Not captured
1b - Captured
11 PME_TO_Ack message status

PME_TO_ACK_ Identifies whether a PME_TO_Ack message is captured.
STS
Valid in RC mode.
0b - Not captured
1b - Captured
10-0 Reserved
2.67 PCIe Controller 0 Receive Message Capture Control (PE0_RX_MSG_CAP_CTRL)
Offset
Register Offset
PE0_RX_MSG_CAP_CT 10A4h
RL

NXP Semiconductors
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserv Reserv
R Reserved Reserved CAP_ CAP_P CAP_V CAP_V
ed ed
UNL... ME... DM... DM...
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserved CAP_P CAP_P Reserved
W M_... ME...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-24 Reserved
23-22 Reserved
21 Reserved
20 Capture Unlock message in received Message Header register.

CAP_UNLOCK Enables and disables the capture of an Unlock message in the received message header register.
0b - Disable
1b - Enable
19 Capture PME_Turn_Off Message In Received Message Header Register

CAP_PME_TU Enables and disables the capture of a PME_Turn_Off message in the received message header register.
RN_OFF
0b - Disable
1b - Enable
18 Capture Vendor-Defined Type 1 Message In Received Message Header Register

CAP_VDM_TYP Enables and disables the capture of a vendor-defined Type 1 message in the received message
E1 header register.
0b - Disable
1b - Enable
17 Capture Vendor-Defined Type 0 Message In Received Message Header Register

Enables and disables the capture of a vendor-defined Type 0 message in the received message
header register.

NXP Semiconductors
Field Function
CAP_VDM_TYP 0b - Disable
E0
1b - Enable
16 Reserved
15-13 Reserved
12 Capture PM_PME Message In Received Message Header Register

CAP_PM_PME Enables and disables the capture of a PM_PME message in the received message header register.
0b - Disable
1b - Enable
11 Capture PME_TO_Ack Message In Received Message Header Register

CAP_PME_TO_ Enables and disables the capture of a PME_TO_Ack message in the received message header register.
ACK
0b - Disable
1b - Enable
10-0 Reserved
2.68 PCIe Controller 0 Receive Message Interrupt Control (PE0_RX_MSG_INT_CTRL)
Offset
Register Offset
PE0_RX_MSG_INT_CTR 10A8h
L
Function
Control the generation of an interrupt to a local processor when a message is captured.

NXP Semiconductors
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserv Reserv Reserv Reserv

R MSGQ Reserved UNLO PME_ VDM_ VDM_
ed ed ed ed
_OV... CK_... TUR... TYP... TYP...
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserved PM_P PME_T Reserved
W ME_... O_...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31 Interrupt Enable When Message Queue Overflows

MSGQ_OVERF Enables and disables an interrupt when the message queue overflows.
LOW_INT_EN
0b - Disable
1b - Enable
30-24 Reserved
23 Reserved
22 Reserved
21 Reserved
20 Interrupt Enable When Unlock Message In Received Message Header Register

UNLOCK_INT_ Enables and disables an interrupt when an Unlock message is captured.
EN
0b - Disable
1b - Enable
19 Interrupt Enable When PME_Turn_Off Message In Received Message Header Register

PME_TURN_O Enables and disables an interrupt when a PME_Turn_Off message is captured.
FF_INT_EN
0b - Disable
1b - Enable
18 Interrupt Enable When Vendor-Defined Type 1 Message In Received Message Header Register

NXP Semiconductors
Field Function
VDM_TYPE1_I Enables and disables an interrupt when a vendor-defined Type 1 message is captured.
NT_EN
0b - Disable
1b - Enable
17 Interrupt Enable When Vendor-Defined Type 0 Message In Received Message Header Register
VDM_TYPE0_I Enables and disables an interrupt when a vendor-defined Type 0 message is captured.
NT_EN
0b - Disable
1b - Enable
16 Reserved
15-13 Reserved
12 Interrupt Enable When PM_PME Message In Received Message Header Register

PM_PME_INT_ Enables and disables an interrupt when a PM_PME message is captured.
EN
0b - Disable
1b - Enable
11 Interrupt Enable When PME_TO_Ack Message In Received Message Header Register

PME_TO_ACK_ Enables and disables an interrupt when a PME_TO_Ack message is captured.
INT_EN
0b - Disable
1b - Enable
10-0 Reserved
2.69 PCIe Controller 0 Link Debug 1 (PE0_LINK_DBG_1)
Offset
Register Offset
PE0_LINK_DBG_1 10B0h
Function
Indicates lane receiver detection and symbol lock status.

NXP Semiconductors
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYMBOL_LOC
R Reserved
K
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RECEIVER_DE
R Reserved
TECT...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-18 Reserved
17-16 Symbol Lock

SYMBOL_LOC Informs you whether the received symbol in a particular lane is locked.
K
Bits 0 and 1 of this field represent lanes 0 and 1, respectively. For each bit:
• A value of 0 means that the received symbol is not locked in that lane.
• A value of 0 means that the received symbol is locked in that lane.
15-2 Reserved
1-0 Receiver Detected On Lanes

RECEIVER_DE Informs you whether a receiver of a particular lane is detected.
TECTED
Bits 0 and 1 of this field represent lanes 0 and 1, respectively. For each bit:
• A value of 0 means that the receiver of that lane is not detected.
• A value of 1 means that the receiver of that lane is detected.
2.70 PCIe Controller 0 Link Debug 2 (PE0_LINK_DBG_2)
Offset
Register Offset
PE0_LINK_DBG_2 10B4h

NXP Semiconductors
Function
Indicates link state, link rate and traffic status.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CDM_I BRDG BRDG EDMA RADM Reserv Reserv Reserv VC0_Q

R Reserved
N_... _SL... _DB... _XF... _XF... ed ed ed _N...
Reset
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDLH_ SMLH_
R Reserved PHY_POWRDOWN RATE SMLH_LTSSM_STATE
LI... LI...
Reset 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-25 Reserved
24 CDM Register In Reset

CDM_IN_RESE Indicates whether the PCIe controller register block is in reset or to be reset.
T
0b - Not in reset, or will not be reset
1b - In reset, or will be reset
23 AXI Slave Non-DBI Transfer Pending Status

BRDG_SLV_XF Indicates whether an AXI non-DBI slave read or write transfer is pending—that is, AXI slave transfers are
ER_PENDING awaiting a response from the controller.
Use this for debugging purposes.
0b - No pending request
1b - Pending request exists
22 AXI Slave DBI Transfer Pending Status

BRDG_DBI_XF Indicates whether an AXI DBI slave read or write transfer is pending—that is, AXI slave transfers are
ER_PENDING awaiting a response from the controller.

NXP Semiconductors
Field Function
21 eDMA Transfer Pending Status

EDMA_XFER_P Indicates whether an eDMA write- or read-channel transfer is pending—that is, DMA write or read channels
ENDING have not finished transferring data.
20 Receive Request Pending Status

RADM_XFER_ Indicates whether a receive TLP request is pending—that is, requests sent to the RTRGT1 or RTRGT0
PENDING interfaces are awaiting a response from you.
19 Reserved
18 Reserved
17 Reserved
16 VC0 Queue Not Empty

VC0_Q_NOT_E Indicates whether the RADM VC0 queue is empty or not.
MPTY
0b - Empty
1b - Not empty
15-13 Reserved
12-10 PHY Power State
PHY_POWRDO 000b - P0 (L0): Normal

WN 001b - P0s (L0s): Low recovery time, power saving
010b - P1 (L1): Longer recovery time, additional power saving
011b - P2 (L2): Lowest power state
9-8 Link Signaling Rate

RATE Shows the signaling rate to use.

NXP Semiconductors
Field Function
00b - 2.5 GT/s

01b - 5.0 GT/s
10b - 8.0 GT/s
11b - 16.0 GT/s
7 Data Link Layer Up Or Down Indicator

RDLH_LINK_U Indicates that flow control has been initiated and the data link layer is ready to transmit and receive packets.
P This status comes from the flow control initialization state machine. For multi-VC designs, this field indicates
the status only for VC0.
6 PHY Link Up Or Down Indicator
SMLH_LINK_U 0b - Down
P 1b - Up
5-0 LTSSM State

SMLH_LTSSM_ Provides the current LTSSM state.
STATE
00_0000b - S_DETECT_QUIET
00_0001b - S_DETECT_ACT
00_0010b - S_POLL_ACTIVE
00_0011b - S_POLL_COMPLIANCE
00_0100b - S_POLL_CONFIG
00_0101b - S_PRE_DETECT_QUIET
00_0110b - S_DETECT_WAIT
00_0111b - S_CFG_LINKWD_START
00_1000b - S_CFG_LINKWD_ACEPT
00_1001b - S_CFG_LANENUM_WAI
00_1010b - S_CFG_LANENUM_ACEPT
00_1011b - S_CFG_COMPLETE
00_1100b - S_CFG_IDLE
00_1101b - S_RCVRY_LOCK
00_1110b - S_RCVRY_SPEED
00_1111b - S_RCVRY_RCVRCFG
01_0000b - S_RCVRY_IDLE
01_0001b - S_L0
01_0010b - S_L0S
01_0011b - S_L123_SEND_EIDLE

NXP Semiconductors
Field Function
01_0100b - S_L1_IDLE
01_0101b - S_L2_IDLE
01_0110b - S_L2_WAKE
01_0111b - S_DISABLED_ENTRY
01_1000b - S_DISABLED_IDLE
01_1001b - S_DISABLED
01_1010b - S_LPBK_ENTRY
01_1011b - S_LPBK_ACTIVE
01_1100b - S_LPBK_EXIT
01_1101b - S_LPBK_EXIT_TIMEOUT
01_1110b - S_HOT_RESET_ENTRY
01_1111b - S_HOT_RESET
10_0000b - S_RCVRY_EQ0
2.71 PCIe Controller 0 AXI Master Debug 1 (PE0_AXI_MSTR_DBG_1)
Offset
Register Offset
PE0_AXI_MSTR_DBG_1 10C0h
Function
Indidates the status of the AXI master write channel.

NXP Semiconductors
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R MSTR_WR_ERR MSTR_WR_REQ_PEND
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R MSTR_WR_REQ
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-24 AXI Master Write Response Error Counter
MSTR_WR_ER
R
23-16 AXI Master Write Pending Request Counter
MSTR_WR_RE
Q_PEND
15-0 AXI Master Write Request Counter
MSTR_WR_RE
Q
2.72 PCIe Controller 0 AXI Master Debug 2 (PE0_AXI_MSTR_DBG_2)
Offset
Register Offset
PE0_AXI_MSTR_DBG_2 10C4h
Function
Indidates the status of the AXI master read channel.

NXP Semiconductors
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R MSTR_RD_ERR MSTR_RD_REQ_PEND
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R MSTR_RD_REQ
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-24 AXI Master Read Response Error Counter
MSTR_RD_ER
R
23-16 AXI Master Read Pending Request Counter
MSTR_RD_RE
Q_PEND
15-0 AXI Master Read Request Counter
MSTR_RD_RE
Q
2.73 PCIe Controller 0 AXI Slave Debug 1 (PE0_AXI_SLV_DBG_1)
Offset
Register Offset
PE0_AXI_SLV_DBG_1 10D0h
Function
Indidates the status of the AXI slave write channel.

NXP Semiconductors
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R SLV_WR_ERR SLV_WR_REQ_PEND
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R SLV_WR_REQ
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-24 AXI Slave Write Response Error Counter
SLV_WR_ERR
23-16 AXI Slave Write Pending Request Counter
SLV_WR_REQ_
PEND
15-0 AXI Slave Write Request Counter
SLV_WR_REQ
2.74 PCIe Controller 0 AXI Slave Debug 2 (PE0_AXI_SLV_DBG_2)
Offset
Register Offset
PE0_AXI_SLV_DBG_2 10D4h
Function
Indidates the status of the AXI slave read channel.

NXP Semiconductors
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R SLV_RD_ERR SLV_RD_REQ_PEND
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R SLV_RD_REQ
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-24 AXI Slave Read Response Error Counter
SLV_RD_ERR
23-16 AXI Slave Read Pending Request Counter
SLV_RD_REQ_
PEND
15-0 AXI Slave Read Request Counter
SLV_RD_REQ
2.75 PCIe Controller 0 Error Status (PE0_ERR_STS)
Offset
Register Offset
PE0_ERR_STS 10E0h
Function
Indicates error status of:
• Transmit path
• Receive path
• Link down
• APB timeout

NXP Semiconductors
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
APBSL LINK_ RETR RETR Reserv VC_Q

R Reserved Reserved
V_... DO... YSO... YRA... ed OVE...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserv Reserv Reserv P_DAT Reserv Reserv Reserv P_HD RXDA TXDA TXDA
R Reserved
ed ed ed AQ... ed ed ed RQ_... TA_... TA_... TA_...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31 APB Slave Timeout Error

APBSLV_TIME Indicates whether an ABP slave timeout error was detected.
OUT_STS
NOTE
This field behaves differently for read and write operations.
When reading
0b - No timeout error detected
1b - Timeout error detected
When writing
0b - No effect
1b - Return this field's value to 0
30 Link Down Event

LINK_DOWN_S Indicates whether a link down event was detected.
TS
NOTE
When reading
0b - No link down error detected
1b - Link down error detected
When writing
0b - No effect
29-27 Reserved

NXP Semiconductors
Field Function
26 Retry SOT RAM Parity Error

RETRYSOTRA Indicates whether a retry SOT RAM parity error was detected.
M_PARERR_S
TS NOTE
When reading
0b - No parity error detected
1b - Parity error detected
When writing
0b - No effect
25 Retry RAM Parity Error

RETRYRAM_P Indicates whether a retry RAM parity error was detected.
ARERR_STS
NOTE
When reading
When writing
0b - No effect
24 Reserved
23-17 Reserved
16 RADM Queue Overflow Error

VC_QOVERFL Indicates whether an overflow error is detected in the RADM queue.
OW
NOTE
When reading
0b - No overflow error detected

NXP Semiconductors
Field Function
1b - Overflow error detected

When writing
0b - No effect
15 Reserved
14 Reserved
13 Reserved
12 Receive Data Queue 0 Parity Error

P_DATAQ_PAR Indicates whether a parity error is detected in the receive data queue 0.
ERR_STS_0
NOTE
When reading
When writing
0b - No effect
11 Reserved
10 Reserved
9 Reserved
8 Receive Header Queue 0 Parity Error

P_HDRQ_PAR Indicates whether a parity error is detected in the receive header queue 0.
ERR_STS_0
NOTE
When reading

NXP Semiconductors
Field Function

When writing
0b - No effect
7 Parity Error Receive Datapath

RXDATA_PER Indicates whether a parity error is detected in the receive datapath.
R
NOTE
When reading
When writing
0b - No effect
6 Parity Error Back

TXDATA_PERR Indicates whether a parity error is detected at the back end of the transmit datapath.
_BACK
NOTE
When reading
When writing
0b - No effect
5 Parity Error Front

TXDATA_PERR Indicates whether a parity error is detected at the front end of the transmit datapath.
_FRONT
NOTE
When reading

NXP Semiconductors
Field Function

When writing
0b - No effect
4-0 Reserved
2.76 PCIe Controller 0 Error Interrupt Control (PE0_ERR_INT_CTRL)
Offset
Register Offset
PE0_ERR_INT_CTRL 10E4h
Function
Controls the generation of an interrupt to the local processor when the controller encounters an error.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserv
R APBSL LINK_ Reserved RETR RETR Reserved VC_Q
ed
V_... DO... YSO... YRA... OVE...
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserv Reserv Reserv Reserv Reserv Reserv

R P_DAT P_HD RXDA TXDA TXDA Reserved
ed ed ed ed ed ed
AQ... RQ_... TA_... TA_... TA_...
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31 Interrupt Enable For APB Slave Timeout Error

APBSLV_TIME Enables and disables the interrupt arising from a detected APB slave timeout error.
OUT_INT_EN
0b - Disable

NXP Semiconductors
Field Function
1b - Enable
30 Interrupt Enable For Link Down Event

LINK_DOWN_I Enables and disables the interrupt arising from a detected link down event.
NT_EN
0b - Disable
1b - Enable
29-27 Reserved
26 Interrupt Enable For Retry SOT RAM Parity Error

RETRYSOTRA Enables and disables the interrupt arising from a detected retry SOT RAM parity error.
M_PARERR_IN
0b - Disable
T_EN
1b - Enable
25 Interrupt Enable For Retry RAM Parity Error

RETRYRAM_P Enables and disables the interrupt arising from a detected retry RAM parity error.
ARERR_INT_E
0b - Disable
N
1b - Enable
24 Reserved
23-17 Reserved
16 Interrupt Enable For RADM Queue Overflow Error

VC_QOVERFL Enables and disables the interrupt arising from a detected RADM queue overflow error.
OW_INT_EN
0b - Disable
1b - Enable
15 Reserved
14 Reserved
13 Reserved
12 Interrupt Enable For Receive Data Queue 0 Parity Error

NXP Semiconductors
Field Function
P_DATAQ_PAR Enables and disables the interrupt arising from a detected parity error in the receive data queue 0.
ERR_INT_EN_0
0b - Disable
1b - Enable
11 Reserved
10 Reserved
9 Reserved
8 Interrupt Enable For Receive Header Queue 0 Parity Error

P_HDRQ_PAR Enables and disables the interrupt arising from a detected parity error in the receive header queue 0.
ERR_INT_EN_0
0b - Disable
1b - Enable
7 Interrupt Enable For Parity Error In The Receive Datapath

RXDATA_PER Enables and disables the interrupt arising from a detected parity error in the receive datapath.
R_INT_EN
0b - Disable
1b - Enable
6 Interrupt Enable For Parity Error At Back End Of The Transmit Datapath
TXDATA_PERR Enables and disables the interrupt arising from a detected parity error at the back end of the
_BACK_INT_EN transmit datapath.
0b - Disable
1b - Enable
5 Interrupt Enable For Parity Error At Front End Of The Transmit Datapath
TXDATA_PERR Enables and disables the interrupt arising from a detected parity error at the front end of the
_FRONT_INT_E transmit datapath.
N
0b - Disable
1b - Enable
4-0 Reserved

NXP Semiconductors
2.77 PCIe Controller 0 Interrupt Status (PE0_INT_STS)
Offset
Register Offset
PE0_INT_STS 10E8h
Function
Provides the first level interrupt status of interrupt pin pcie0_int_o[4].
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BW_M LINK_ Reserv LINK_ BW_M LINK_ SYS_E HP_IN PME_I AER_ Reserv ERR_I RX_M BEAC
R Reserved
GT_... AU... ed EQ... GT_... AU... RR... T_... NT... RC_... ed NT... SG_... ON_...
W W1C W1C W1C W1C W1C W1C W1C W1C W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-14 Reserved
13 Link Bandwidth Management MSI Status

BW_MGT_MSI_ Becomes 1 when all of the following are true:
STS
• LINK_CONTROL_LINK_STATUS_REG[PCIE_CAP_LINK_AUTO_BW_STATUS] is not updated
• LINK_CONTROL_LINK_STATUS_REG[PCIE_CAP_LINK_AUTO_BW_INT_EN] = 1
• PCIe controller MSI is disabled
0b - The conditions in the field description are not met
1b - The conditions in the field description are met
12 Link Autonomous Bandwidth MSI Status

LINK_AUTO_B Becomes 1 when all of the following are true:
W_MSI_STS

NXP Semiconductors
Field Function

11 Reserved
10 Link Equalization Request Interrupt Status

LINK_EQ_REQ Becomes 1 when both of the following are true:
_INT_STS
• LINK_CONTROL2_LINK_STATUS2_REG[PCIE_CAP_LINK_EQ_REQ] = 1
• LINK_CONTROL3_REG[EQ_REQ_INT_EN] = 1
0b - LINK_CONTROL2_LINK_STATUS2_REG[PCIE_CAP_LINK_EQ_REQ] = 0 or
LINK_CONTROL3_REG[EQ_REQ_INT_EN] = 0
1b - LINK_CONTROL2_LINK_STATUS2_REG[PCIE_CAP_LINK_EQ_REQ] =
LINK_CONTROL3_REG[EQ_REQ_INT_EN] = 1
9 Link Bandwidth Management Interrupt Status

BW_MGT_INT_ Becomes 1 when all of the following are true:
STS
• LINK_CONTROL_LINK_STATUS_REG[PCIE_CAP_LINK_BW_MAN_STATUS] is not updated
• LINK_CONTROL_LINK_STATUS_REG[PCIE_CAP_LINK_BW_MAN_INT_EN] = 1
8 Link Autonomous Bandwidth Interrupt Status

LINK_AUTO_B Becomes 1 when all of the following are true:
W_INT_STS
7 System Error Status

SYS_ERR_RC_ Becomes 1 when any device in the hierarchy reports a system error and the associated error-reporting
STS enable field in Root Control and Capabilities (ROOT_CONTROL_ROOT_CAPABILITIES_REG) is 1.
0b - No device reports any system error, or the error-reporting enable fields in
ROOT_CONTROL_ROOT_CAPABILITIES_REG are 0

NXP Semiconductors
Field Function
1b - A device reports a system error and the associated error-reporting enable field in
ROOT_CONTROL_ROOT_CAPABILITIES_REG = 1
6 Hot-Plug Status
HP_INT_STS Becomes 1 when both of the following are true:
• SLOT_CONTROL_SLOT_STATUS[PCIE_CAP_HOT_PLUG_INT_EN] = 1
• Any other field in Slot Control and Status (SLOT_CONTROL_SLOT_STATUS) is 1
5 PME Interrupt Status

PME_INT_STS Becomes 1 when both ROOT_CONTROL_ROOT_CAPABILITIES_REG[PCIE_CAP_PME_INT_EN] and
ROOT_STATUS_REG[PCIE_CAP_PME_STATUS] are 1.
0b - ROOT_CONTROL_ROOT_CAPABILITIES_REG[PCIE_CAP_PME_INT_EN] = 0 or
ROOT_STATUS_REG[PCIE_CAP_PME_STATUS] = 0
1b - ROOT_CONTROL_ROOT_CAPABILITIES_REG[PCIE_CAP_PME_INT_EN] =
ROOT_STATUS_REG[PCIE_CAP_PME_STATUS] = 1
4 Root Complex Advanced Error Reporting Status

AER_RC_ERR_ Becomes 1 when a reported error condition causes a field in Root Error Status
INT_STS (ROOT_ERR_STATUS_OFF) to become 1 and the associated error message reporting enable field in
Root Error Command (ROOT_ERR_CMD_OFF) is 1.
0b - Fields in ROOT_ERR_STATUS_OFF are 0 or fields in ROOT_ERR_CMD_OFF are 0
1b - A field in ROOT_ERR_STATUS_OFF is 1 and its associated error reporting enable field in
ROOT_ERR_CMD_OFF is 1
3 Reserved
2 Internal Error Interrupt Status

ERR_INT_STS See Error Interrupt Status and Error Interrupt Control register.
1 Receive Message Interrupt Status

RX_MSG_INT_ See Receive Message Status, Receive Message Capture Control and Receive Message Interrupt
STS Control register.
0 Beacon Interrupt Status

BEACON_INT_ Indicates whether beacon signaling is detected or not. See PE0_PM_STS[BEACON_INT_STS].
STS
0b - Not detected
1b - Detected

NXP Semiconductors
2.78 PCIe Controller 0 MSI Generation Control (PE0_MSI_GEN_CTRL)
Offset
Register Offset
PE0_MSI_GEN_CTRL 10ECh
Function
Allows you to trigger an MSI interrupt to a link partner if MSI is enabled.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MSI_INT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MSI_INT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0 MSI Vector

MSI_INT Write 1 to a bit of this field to trigger the corresponding MSI interrupt to a link partner.
2.79 PCIe Controller 0 FSM Track 1 (PE0_FSM_TRACK_1)
Offset
Register Offset
PE0_FSM_TRACK_1 10F0h
Function
Monitors the PCIe link LTSSM.

NXP Semiconductors
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EVEN EVEN EVEN EVEN

R FSM_3 FSM_2
T_B... T_A... T_B... T_A...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EVEN EVEN Reserv

R FSM_1 FSM_
T_B... T_A... ed FSM_TRIG
MON...
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31 TS2 Status In FSM State 3

EVENT_B_3 Indicates whether TS2 is received in FSM state 3.
0b - Not received
1b - Received

EVENT_A_3 Indicates whether TS1 is received in FSM state 3.
0b - Not received
1b - Received
29-24 FSM State 3

FSM_3 Indicates the third state after the trigger state.

0b - Not received
1b - Received

0b - Not received
1b - Received
21-16 FSM State 2

FSM_2 Indicates the second state after the trigger state.

NXP Semiconductors
Field Function

0b - Not received
1b - Received

0b - Not received
1b - Received
13-8 FSM State 1

FSM_1 Indicates the first state after the trigger state.
7 Reserved
6 FSM Track Enable

FSM_MON_EN Enables and disables the FSM tracker.
0b - Disable
1b - Enable
5-0 Trigger State Of FSM Track
FSM_TRIG
2.80 PCIe Controller 0 FSM Track 2 (PE0_FSM_TRACK_2)
Offset
Register Offset
PE0_FSM_TRACK_2 10F4h
Function
Monitors the PCIe link LTSSM.

NXP Semiconductors
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EVEN EVEN EVEN EVEN

R FSM_7 FSM_6
T_B... T_A... T_B... T_A...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EVEN EVEN EVEN EVEN

R FSM_5 FSM_4
T_B... T_A... T_B... T_A...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function

0b - Not received
1b - Received

0b - Not received
1b - Received
29-24 FSM State 7

FSM_7 Indicates the seventh state after the trigger state.

0b - Not received
1b - Received

0b - Not received
1b - Received
21-16 FSM State 6

FSM_6 Indicates the sixth state after the trigger state.

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Field Function

0b - Not received
1b - Received

0b - Not received
1b - Received
13-8 FSM State 5

FSM_5 Indicates the fifth state after the trigger state.

0b - Not received
1b - Received

0b - Not received
1b - Received
5-0 FSM State 4

FSM_4 Indicates the fourth state after the trigger state.
2.81 APB Bridge Timeout Control (APB_BRIDGE_TO_CTRL)
Offset
Register Offset
APB_BRIDGE_TO_CTR 3000h
L
Function
Sets the APB slave timeout threshold.

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Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
APB_TIMER_LIMT
W
Reset 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserved APB_T
APBCLK_FREQ
W IM...
Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0
Fields
Field Function
31-16 APB Watchdog Timeout Threshold (µs)

APB_TIMER_LI When an APB read or write operation is in progress, the APB watchdog timer counts every 1 µs pulse. If
MT the APB watchdog timer exceeds this threshold, APB reports a timeout error through an interrupt to the
local processor.
15-11 Reserved
10 APB Timeout Control Disable

APB_TIMEOUT Enables and disables the APB slave watchdog timeout mechanism.
_DIS
0b - Enable
1b - Disable
9-0 APB Clock Frequency (MHz)

APBCLK_FREQ Generates a one-cycle pulse, at the specified frequency, every 1 µs.
2.82 PHY Register Address (PHY_REG_ADDR)
Offset
Register Offset
PHY_REG_ADDR 3008h
Function
Works together with PHY Register Data (PHY_REG_DATA) to give you access to the PHY registers.

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Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R PHY_R Reserved
W EG...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31 Indirect PHY Register Access Enable

PHY_REG_EN Enables and disables indirect access to PHY registers.
0b - Disable
1b - Enable
30-16 Reserved
15-0 Indirect PHY Register Access Address
ADDR
2.83 PHY Register Data (PHY_REG_DATA)
Offset
Register Offset
PHY_REG_DATA 300Ch
Function
Works together with PHY Register Address (PHY_REG_ADDR) to give you access to the PHY registers.

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Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DATA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-16 Reserved
15-0 Indirect PHY Register Access Data
DATA
2.84 Reset Control (RST_CTRL)
Offset
Register Offset
RST_CTRL 3010h
Function
Allows your software or firmware to trigger a cold (soft) reset or a warm reset.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserved WARM COLD_
W _RST RST
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Fields
Field Function
31-2 Reserved
1 Warm Reset Control

WARM_RST Asserts and deasserts a warm reset.
0b - Deassert
1b - Assert
0 Cold Reset Control

COLD_RST Asserts and deasserts a cold reset.
0b - Deassert
1b - Assert

NXP Semiconductors
Chapter 3
PCIe Controller
3.1 Introduction
This section describes the PCIe controller on this chip and provides a basic description of the PCIe protocol.
3.1.1 Specifications used by this section

The PCIe protocol comprises several specifications. These are maintained and published by the Peripheral Component
Interconnect Special Interest Group (PCI-SIG) (http://pcisig.com). You need a PCI-SIG membership to view them.
This section provides some protocol details, but does not attempt to describe the full intricacies of the protocol. Therefore, this
chapter sometimes directs you to the following specifications for full details:
®
• PCI Express Base Specification, Revision 3.1a, December 7, 2015
• PCI Bus Power Management Interface Specification, Revision 1.2, March 2, 2004
• PCI Local Bus Specification, Revision 3.0, February 3, 2004
3.1.2 Terms and abbreviations
Term Description
x1/x2/x4/x8/x16 1/2/4/8/16 lanes
BAR Base Address Register
CDM Configuration Dependent Module

This is an internal block in the native controller that has the PCIe configuration registers and some
user-accessible registers.
CIC Configuration Intercept Controller

Allows your application logic to detect the occurrence of; and to modify (using the CII) the
behavior of Rx CFG requests (from the remote link partner) that are accessing the controller's
internal registers.
CII Configuration Intercept Interface

See CIC.
CPL Completion
C-PCIe Conventional PCI Express
CRPI Control Register Parallel Interface

The control registers in some Synopsys PHYs (for example, C8/C10/E12/E16) can be accessed
through this interface.
CXPL Common Xpress Port Logic

The internal controller module that implements the majority of the PCI Express protocol layers.

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PCIe Controller
Term Description
DBI Data Bus Interface

You can use this interface to locally access the controller’s internal registers in the CDM, or your
external application registers on the ELBI. You can optionally connect a local CPU or controller to
this port.
DLLP Data Link Layer Packet
DM PCI Express Dual Mode (DM) controller
DRS Device Readiness Status
DWORD Double Word (32 bits)
ELBI External Local Bus Interface

Delivers an inbound register RD/WR received by the controller to external application registers
when the controller is expected to generate the PCIe completion of this register RD/WR.
PRBI PHY Register Bus Interface

This interface facilitates direct access of PHY registers by your application through DBI or
CFG requests.
Note: Only Synopsys PHYs supporting Control Register Parallel Interface (CRPI), for example
Synopsys C8/C10/E12/E16 PHYs can be accessed through this interface.
EP PCI Express Endpoint (EP)
FRS Function Readiness Status
FRSQ FRS Queue
{new}Function {new}In PCIe context, a capability of a PCIe device on a PCIe bus. Always spelled with a capital F.
Each Function has a number. The combination of bus, device, and Function numbers creates a
unique PCIe identifier that is used during PCIe enumeration and communication.
iATU Internal Address Translation Unit
iMSI-RX Integrated MSI-Receive module
iMSIX-TX Integrated MSIX -Transmit module
Inbound traffic PCIe transactions that enter the controller from the wire side of the controller (PCIe wire). These
transactions are delivered to your application side.
LBC Local Bus Controller

This is an internal block that allows the DBI interface (from your application side), or the wire side
interface (through the TRGT0 interface), to access the CDM or your external application registers
on the ELBI.
LTR Latency Tolerance Reporting

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PCIe Controller
Term Description
MTU Maximum Transfer Unit

Specifies the maximum packet payload size supported. This indicates the maximum allowed
transfer size for a write or completion.
NF Number of Functions
The value “1” represents one function.
NW Number of Double Words

The value “1” represents a 32-bit DWORD.
NP Non-posted
Outbound traffic Transactions that enter the controller from your application side of the controller. These transactions
are passed to the native controller, where they are sent out onto the PCIe wire.
P Posted
Page Boundary Specifies the address page boundary size supported by the AXI bridge. No packet can have an
address that crosses the specified address boundary.
PCIe PCI Express
PIPE Standard PIPE interface between the PCI Express PHY and the controller. If you set PHY_TYPE to
be the Synopsys PHY, then the PHY is included inside the controller.
PMC Power Management Controller
PRC PHY Register Controller
PTM Precision Time Measurement feature as defined in PCI Express Base Specification, Revision 4.0,
Version 0.9.
RADM Receive Application-Dependent Module
RAS Reliability, Availability, and Serviceability

A collection of features aimed at error protection, error and event logging, and debug.
RAS-DP / RASDP Data Protection aspect of RAS.
RAS-DES / RASDES Debug, Error injection, and Statistics aspects of RAS.
TRGT0 Receive Target 0 Interface

This is an internal logical receive interface used to access registers in the CDM, or external
application registers on the ELBI.
SII System Information Interface

Exchanges system information between the controller and your application.

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PCIe Controller
Term Description
TLP Transaction Layer Packet
TRGT1 / RBYP When you configure the controller with an AXI bridge, then these interfaces are no longer visible as
they now becomes an internal connection between the native PCIe controller and the AXI bridge.
Your application receives inbound TLPs on AXI bridge, instead of TRGT1 / RBYP.
VC Virtual Channel
VMI Vendor Message Interface

Allows your application to request a transmission of a vendor message.
VSEC Vendor Specific Extended Capability

Most of the Synopsys implementation-specific registers (not defined by the PCI-SIG PCIe
specification) are located in the Port Logic space beginning at 0x700.
Going forward from release 4.40a, all new implementation-specific register groups are implemented
as VSEC’s in the PCIe Extended Capability Structure address space.
XADM Transmit Application-Dependent Module
3.2 Features
3.2.1 Feature summary

Key features of each PCIe controller include:
• Gen2 and Gen3 rate support (the physical layer operates at a data rate of up to 8 Gbaud per lane)
• Maximum of two lanes
• x2 link width support
• Power-on reset configuration options allow RC or EP functionality
• PCIe configuration registers (Type 0 in EP mode, Type 1 in RC mode)
• Both 32-bit and 64-bit addressing
• 256-byte maximum payload size (MAX_PAYLOAD_SIZE)
• Full 64-bit decode with 40-bit wide windows
• Inbound INTx transactions
• Message signaled interrupt (MSI) transactions, including an internal MSI-X generation module
• Supports posting of processor-to-PCIe and PCIe-to-memory writes
• Supports strong and relaxed transaction ordering rules
• Baseline and advanced error reporting support
• PCIe beacon and wake-up mechanism
• PCI power management
• PCIe Active State Power Management (ASPM)
• Supports expansion ROM

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PCIe Controller
• Embedded DMA with hardware control:

— Four channels for reading
— Four channels for writing
• Advanced power and clock management supporting all substates except L1
• Internal address translation unit
• Automatic lane reversal
• [DIP_PCIE_SS_HW_IP_0001]Reliability, availability, and serviceability (RAS):
— Debug, error injection, and statistics (DES)
— Data protection (DP) for datapath and RAMs using ECC or parity[end]
• ECRC generation and checking
• [DIP_PCIE_SS_HW_IP_0004]Automotive support[end]
3.2.2 Feature details

The PCIe controller connects the internal platform to a serial link interface. The PCIe controller implements these PCIe
protocol layers:
• Transaction layer
• Data link layer
• MAC portion of the physical layer
Each of these layers is divided into two sections as shown in Figure 2:
• One layer that processes outbound (to be transmitted) information
• One layer that processes inbound (received) information
The PCIe controller supports all of the non-optional Gen2 5.0 GT/s features defined in the PCI Express Base 3.0 Specification,
revision 1.0. The interface between the controller and the PHY is compliant with the PIPE Specification for PCI Express, Version
4.0. The PCIe controller supports a PCIe link width of x2 (two physical lanes). After coming out of reset, the PCIe interface performs
link width negotiation and exchanges flow control credits with its link partner. After link auto negotiation is successful, the controller
is in operation.
The PCIe controller can operate as a PCIe RC or EP device. You place the controller into EP or RC mode by programming
PE0_GEN_CTRL_1[DEVICE_TYPE] at driver startup.
An RC device connects the host CPU/memory subsystem to I/O devices while an EP device typically denotes a peripheral or I/O
device. RC mode uses a PCIe type-1 configuration header. EP mode uses a PCIe type-0 configuration header.
This figure shows a high-level block diagram of the PCIe controller.

NXP Semiconductors
PCIe Controller
Internal Platform Interface
RX TX
Transaction Layer
Configuration Registers
RX TX
Data Link Layer
RX TX
MAC Layer
SerDes Interface
PCI Express Link
Figure 2. PCIe controller block diagram
As an initiator, the PCIe controller supports memory read and write operations. In addition, configuration and I/O transactions are
supported if the PCIe controller is in RC mode. As a target interface, the PCIe controller accepts read and write operations to local
memory space. When configured as an EP device, the PCIe controller accepts configuration transactions to the internal PCIe
configuration registers. Message generation and acceptance are supported in both RC and EP modes. Locked transactions and
inbound I/O transactions are not supported.
3.2.3 Outbound transactions

Outbound internal platform transactions to PCIe are first mapped to a translation window to determine what PCIe transactions are
to be issued. A transaction from the internal platform can become a PCIe Memory, I/O, Message, or Configuration transaction
depending on the window attributes.
A transaction may be broken up into smaller-sized transactions depending on:
• The original request size
• Transaction type
• Either of the following:
— The PCIe Device Control register [MAX_PAYLOAD_SIZE] field for write requests
— The PCIe Device Control register [MAX_READ_SIZE] field for read requests
The controller performs PCIe ordering rule checking to determine which transaction is to be sent on the PCIe link.

NXP Semiconductors
PCIe Controller
In general, transactions are serviced in the order that they are received from the internal platform. The controller applies PCIe
ordering rules to outstanding transactions only when a stalled condition exists. For posted write transactions, after all data has
been received from the internal platform, the data is forwarded to the PCIe link and the transaction is considered as done. For
non-posted write transactions, the controller waits for the completion packets to return before considering the transaction finished.
For non-posted read transactions, the controller waits for all completion packets to return and then forwards all data back to the
internal platform before terminating the transaction.
After reset or when recovering from a link down condition, external transactions should not be attempted until the link has
successfully trained. Software can poll the link status in PCIe Controller 0 Link Debug 2 (PE0_LINK_DBG_2).
3.2.4 Inbound transactions

Inbound PCIe transactions to internal platform are first mapped to a translation window to determine what internal platform
transactions are to be issued.
A transaction may be broken up into smaller sized transactions when sending to the internal platform depending on the original
request size and starting/ending addresses. The controller performs PCI Express ordering rule checking to determine what
transaction is to be sent next to the internal platform.
In general, transactions are serviced in the order that they are received from the PCIe link. The controller applies PCIe ordering
to outstanding transactions only when a stalled condition occurs. For posted write transactions, after all data has been received
from the PCIe link, the data is forwarded to the internal platform and the transaction is considered as done. For non-posted read
transactions, the controller forwards internal platform data back to the PCIe link.
The controller splits transactions at the crossing of every 256-byte-aligned boundary when sending data back to the PCIe link.
3.3 Modes of operation

PCI Express controller modes of operation are determined at power-on reset (POR). The device is configured for either
RC/EP mode.
3.3.1 Root complex / endpoint modes

The PCIe controller can function as either a root complex (RC) or an endpoint (EP) on the PCIe link. PCIe Controller 0 General
Control 1 (PE0_GEN_CTRL_1) controls the choice of RC or EP mode.
3.3.2 Link width

The controller supports a link width of up to 2×.
3.3.3 Link speed

The controller supports speeds up to 8.0 GT/s.
3.4 External (link interface) signal descriptions

The PCI Express specification defines the connection between two devices as a link. A link consists of a single lane or multiple
lanes. Each lane consists of a differential pair for transmitting (TXn_P and TXn_N) and a differential pair for receiving (RXn_P and
RXn_N) with an embedded data clock, with n starting with 0. This chip's PCIe controller consists of two lanes, and therefore n=1.
Table 6. Detailed signal descriptions
Signal I/O Description
PCI_RXn_P I Receive data, positive. The receive data signals carry PCI Express packet information.

NXP Semiconductors
PCIe Controller
Table 6. Detailed signal descriptions (continued)
Signal I/O Description
State Asserted/Negated — Represents data being received from the PCI Express interface.
Meaning
Timing Assertion/Negation — As described in the PCI Express Base 3.0 Specification, Revision 1.0.
PCI_RXn_N I Receive data, negative. The receive data signals carry PCI Express packet information.
State Asserted/Negated — Represents the inverse of data being received from the PCI
Meaning Express interface.
PCI_TXn_P O Transmit data, positive. The transmit data signals carry PCI Express packet information.
State Asserted/Negated — Represents data being transmitted to the PCI Express interface.
Meaning
PCI_TXn_N O Transmit data, negative. The transmit data signals carry PCI Express packet information.
State Asserted/Negated — Represents the inverse of data being transmitted to the PCI
PCI_CLK_P I Low-swing differential input clock pair with pad.
State Asserted/Negated — Represents data being transmitted to the PCI Express interface.
Meaning
PCI_CLK_N I Low-swing differential input clock pair with pad.
State Asserted/Negated — Represents the inverse of data being transmitted to the PCI
PCI_RESREF - Reference Resistor Connection. Attach a 200-ohm 1% 100-ppm/C precision resistor-to ground on
the board.
3.4.1 Managing signals with unused lanes or PHY

You must configure unused lanes as shown in the following table with the appropriate software settings applied to disable the
SerDes PHY or lane. Dedicated supplies must still remain actively powered.

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PCIe Controller
Table 7. Signal configuration for unused PHY or lane
Signal When you are using only one SerDes lane When you are not using the PHY at all
PCI_TXn_P and Float Float

PCI_TXn_N
PCI_RXn_P and Tie low Float or tie low

PCI_RXn_N
PCI_CLK_P and — Tie low

PCI_CLK_N
PCI_RESREF — Float
3.5 Register configuration space overview†

The controller has 4096 bytes of register space per function. Based on the location of the registers, this space is divided into two
groups, CDM and ELBI.
• Configuration Dependant Module (CDM) Registers
Includes PCI Configuration Header, Standard and Extended Capabilities, and Port Logic registers.
— PCI Configuration Header, Standard Capability, and Extended Capability Registers are PCIe controller configuration
registers specified by the PCI Express Base Specification, Revision 4.0, Version 0.9.
— Port Logic Registers (PL) registers are configuration registers which are not specified by the PCI Express Base
Specification, Revision 4.0, Version 0.9, but which are Synopsys-specific. The port logic registers have specific
pre-defined usages, and can optionally be removed from the controller hardware configuration.
Note: There is one set of iATU and DMA port logic registers that are common for all functions.
• External Local Bus Interface (ELBI) Registers
Your application registers that are external to the controller and connected to the ELBI.

NXP Semiconductors
PCIe Controller
Per Function Space Common for All Functions

CS2 = 0 CS2 = 1
0xFFF
Customer Application Registers CDM/ELBI Select Bit
=1
(ELBI)
CONFIG_LIMIT DMA Registers
(wire view only)
(CDM)
0x8_0000 CDM/ELBI Select Bit
Approx.
=1
0xD00
Port Logic Registers

(excluding iATU / DMA Registers) iATU Registers
(CDM)
(CDM)
0x0000
0x700
Per Function Space
CS2 = 1
PCIe Extended Capability Structures

AER, VC, SN, PB, ARI, SPCIE,
LTR, L1SS, RBAR
CDM/ELBI Select Bit
=0
0x100 CDM/ELBI Select Bit
=0
PCI Standard Capability Structures

PM, MSI, PCIE, MSI-X, VPD
CapPtr
0x03F
PCI Configuration Header Space
(64 bytes / 16 DWORDs)
0x0000
Figure 3. Controller Configuration Space Layout (EP Mode)

NXP Semiconductors
PCIe Controller
Per Function Space Common for All Functions

CS2 = 0 CS2 = 1
0xFFF
DMA Registers
Approx. (CDM)
0xD00 0x8_0000 CDM Select Bit
=1
Port Logic Registers iATU Registers

(excluding iATU / DMA Registers)
(CDM)
(CDM) 0x0000
0x700
Per Function Space
CS2 = 1
PCIe Extended Capability Structures

AER, VC, SN, PB, ARI, SPCIE,
LTR, L1SS, RBAR
CDM Select Bit
=0
0x100 CDM Select Bit
=0
PCI Standard Capability Structures

PM, MSI, PCIE, MSI-X, VPD
CapPtr
0x03F
PCI Configuration Header Space
(64 bytes / 16 DWORDs)
0x0000
Figure 4. Controller Configuration Space Layout (RC Mode)
Capability configuration registers are in structures (groups) identified by a capability ID. The groups are linked together as in PCI.
Register locations within a group are specified, but the starting location of each group must be found by traversing the linked list.
There are two linked lists of register groups:
• PCI compatible capability registers
PCI compatible capability register groups begin at the configuration address stored in the capability pointer register at 0x34.
• PCI Express extended capability registers
PCI Express extended capability register groups begin at address 0x100.
The capability pointer register in the PCI-compatible header register points to the next item in the linked list of capabilities, which
by default is the PCI Power Management capability.
3.5.1 Register types†

There are three types of registers in the controller as shown in the following table.

NXP Semiconductors
PCIe Controller
Table 8. Types of Registers in PCIe Core
Register Description Access/Addressing Method

Type
Simple Single register accessed directly by its address. Direct addressing method. You just supply the address.
Most of the registers (including ATU and DMA)
are of this type.
Shadow Another register exists at the same address Normally can only be accessed through the DBI where you
as a Simple register. For example the BAR select between the two registers using the dbi_cs2 input (or
Mask registers have the same address as the the CS2 address bit if you are using an AXI DBI slave). This
BAR registers. is called DBI2, CS2, dbi_cs2, DBI_CS2, or Dbi2 access; all of
these terms mean the same thing.
Viewport Multiple (n) registers existing at the same Indirect addressing method where you first write to a special
address as a Simple register. For example Gen3 index register to select which of the n registers at the
Coefficient Preset registers. address you want to access. You then proceed to write to
the register address.
3.5.2 Register views and access†

There are three views for most registers in the controller (see Table 9), depending on how you access a register.
Table 9. Types of Views in PCIe Controller
View Type Description Typical Access Attributes (e.g. R/W, read-only)
Wire (USP only) Remote access by link partner over the As per PCI-SIG specification.
PCIe link.
DBI Dbi Local (back-door) access to Simple • Normally as per PCI-SIG specification.
registers by your application logic through
• Some read-only1 registers are permanently R/W.
the DBI interface with dbi_cs =1 and
dbi_cs2(or CS2) =0. • Some read-only1 registers can be made temporarily
R/W when you write 1 to the DBI_RO_WR_EN bit of the
MISC_CONTROL_1_OFF register.
Dbi2 Local (back-door) access to Shadow, iATU, • Normally R/W

and DMA registers by your application logic
• One exception is the BAR mask registers which are
through the DBI interface with dbi_cs =1
W (write-only).
and dbi_cs2(or CS2) =1.
1. As specified by the PCI-SIG specification.
Table 10 describes the possible ways to access the controller registers in USP mode.
Table 10. USP Mode Region Access
Register Location CDM ELBI
Register Type PCI-SIG Synopsys-Specific (Port Logic) User
Normal Shadow Misc IATU DMA User

NXP Semiconductors
PCIe Controller
Table 10. USP Mode Region Access (continued)
DBI CDM/ELBI Selector Bit1 0 0 0 1 1 1

Access Value
Details
CS2 Selector Bit Value 0 1 0 1 1 0
DBI/Wire Access Allowed
DBI Y Y Y Y Y Y
Wire CFG Request Y - Y - - Y
BAR Matched MEM - - Y2 Y Y Y2

Request
1. Selector bit locations are configuration-dependent.

2. IO request also supported.
3.6 BAR details†

In this section, the operation and programming of Base Addres Registers (BARs) is described.
3.6.1 EP mode†
Base Address Registers (Offset: 0x100x24)
The controller provides three pairs of 32-bit BARs for each implemented function. Each pair (BARs 0 and 1, BARs 2 and 3, BARs
4 and 5) can be configured as follows:
• One 64-bit BAR: For example, BARs 0 and 1 are combined to form a single 64-bit BAR.
• Two 32-bit BARs: For example, BARs 0 and 1 are two independent 32-bit BARs.
• One 32-bit BAR: For example, BAR0 is a 32-bit BAR and BAR1 is either disabled or removed from the controller altogether
to reduce gate count.
Using MEM_FUNCN_BARn_TARGET_MAP, you can configure each BAR to have its matched requests routed to:
• 1: TRGT1 (or AXI master interface)
• 0: TRGT0 (to access internal port logic registers or your external application registers on the ELBI)
When a TLP is to be routed by its address, the address range in the BAR decides whether the TLP is rejected or accepted. When
the address is in the range configured in the BAR, the endpoint accepts the TLP and passes it to the application.
For information about routing requests to either TRGT1 or TRGT0 on a BAR-by-BAR basis, see Advanced filtering and routing of
TLPs†. For more information on BAR operation, see Receive routing†.
The following sections describe how to set up the BAR types and sizes by programming values into the base address registers.
3.6.1.1 BAR sizing†

Normally, the BAR masks are used for indicating the amount of address space that each BAR requests from host software. The
BAR masks determine which bits in each BAR are non-writable by host software, which determines the size of the address space
claimed by each BAR. The BAR mask values indicate the range of low-order bits, in each implemented BAR, not to use for address
matching. The BAR mask value also indicates the range of low-order bits in the BAR that cannot be written from the host. The
application can write to all BAR bits to allow setting of memory, I/O, and other standard BAR options.
To set the amount of address space that each BAR requests, you hardwire the mask using the BARn_MASK_N parameter. You
cannot change the mask at runtime.

NXP Semiconductors
PCIe Controller
x28
BAR0 Register
0
0
BAR0_MASK_0[31:4] write data 1 31:4

0x0 1 RW To
BAR
x28
PCie Address
write Matching
Logic in
reset Receive
Filter
dbi_cs
DBI write
0
0
write data 1 3:0
BAR0_ENABLED_0
1 RO(cs)
reset
DBI write to 0x10
*
dbi_cs
* This is gated with the DBI_RO_WR_EN register field.

# The lower 8-bits of write data are overwritten with 0xFF
Figure 5. Fixed and programmable mask example for 32-bit memory BAR0
3.6.1.2 Disabling a BAR†

To disable a BAR (in any of the three schemes), your application can write 0 to the LSB of the BAR mask register. The BAR mask
register is at the same address as the BAR register, and you can access it through the DBI (only) by asserting dbi_cs2 (or the
CS2 address bit when the AXI bridge is used). However, when you want to access the LSB (BAR Enable bit), then you must assert
dbi_cs instead of dbi_cs2.
3.6.1.3 General rules for BAR setup (fixed mask or programmable mask schemes only)†
At runtime, software can overwrite the BAR contents to reconfigure the BARs (unless the affected BAR is removed during
hardware configuration). Software must observe the rules listed below when writing to the BARs. The rules for BAR configuration
are the same for all three pairs. Using BARs 0 and 1 as the example pair, the rules for BAR configuration are:
• Any pair (for example BARs 0 and 1) can be configured as one 64-bit BAR, two 32-bit BARs, or one 32-bit BAR.
• BAR pairs cannot overlap to form a 64-bit BAR. For example, you cannot combine BARs 1 and 2 to form a 64-bit BAR.
• Any 32-bit BAR that is not needed can be removed during controller hardware configuration to reduce gate count.
• An I/O BAR must be a 32-bit BAR and cannot be prefetchable.
• When the device is configured as a PCI Express endpoint (not a Legacy endpoint), then any memory that is configured as
prefetchable must be assigned to a 64-bit memory BAR.
• When BAR0 is configured as a 64-bit BAR:
— BAR1 is the upper 32 bits of the combined 64-bit BAR formed by BAR0 and BAR1. Therefore, BAR1 must be disabled
and cannot be configured independently.
— BAR0 must be a memory BAR and can be either prefetchable or non-prefetchable.

NXP Semiconductors
PCIe Controller
— The contents of the BAR0 mask register determine the number of writable bits in the 64-bit BAR, subject to the
restrictions described in BAR mask registers†. The BAR1 mask register contains the upper 32 bits of the BAR0
mask value.
— BAR0 can be disabled by writing 0 to bit [0] of the BAR0 mask register.
— You can configure BAR1 as an independent 32-bit BAR or remove BAR1 from the controller hardware configuration.
— BAR0 can be configured as a memory BAR or an I/O BAR.
— The contents of the BAR0 mask register determine the number of writable bits in the 32-bit BAR0, subject to the
restrictions described in BAR mask registers†.
• When BAR0 is configured as a 32-bit BAR, BAR1 is available as an independent 32-bit BAR according to the following rules:
— When BAR1 is not required in your design, you can remove BAR1 from the hardware configuration by setting both
BAR1_ENABLED_N and BAR1_MASK_TYPE_N to 0.
The same rules apply for pairs 2/3 and 4/5.
3.6.1.4 Memory BAR sizes†

BAR bits [11:0] are always masked for a memory BAR. The controller requires each memory BAR to claim at least 4 KB. The PCI
Express Base Specification, Revision 4.0, Version 0.9 states that the minimum memory address range requested by a BAR is 128
bytes. In the PCI Local Bus Specification, rev 3.0, it is recommended that devices that need less than 4 KB of address space should
still consume 4 KB of address space in order to minimize the number of bits in the address decoder. A memory BAR size of 256
bytes can be achieved by using a DBI CS2 write to BAR mask.
3.6.1.5 IO BAR sizes†

BAR bits [7:0] are always masked for an I/O BAR. The controller requires each I/O BAR to claim at least 256 bytes. The PCI Local
Bus Specification, rev 3.0 allows I/O BARs to consume between 4 bytes and 256 bytes of address space. The controller only
permits I/O BARs to consume 256 bytes of address space. This restriction is used in order to minimize the number of bits in the
address decoder.
3.6.1.6 BAR mask registers†

Your local CPU can change the mask at runtime using the DBI. The mask register is at the same address as the BAR register.
The mask is a shadow register that is invisible to the PCIe wire but visible to your local CPU through the DBI. Furthermore, it is
only visible for a write and not for a read. You cannot read the mask register but you can write to it. It is accessed by asserting
dbi_cs2 and dbi_cs. If you only assert dbi_cs then you will access the BAR which is the primary register at that location. Use
CS2 instead of dbi_cs2 when you are using the AXI bridge.
3.6.1.7 Example BAR setup†

The following figure shows an example configuration of the six BARs and their corresponding BAR mask registers. The example
configuration includes:
• One 64-bit memory BAR (non-prefetchable)
• One 32-bit memory BAR (non-prefetchable)
• One 32-bit I/O BAR

NXP Semiconductors
PCIe Controller
Base Address Registers

31 0
BAR5 (24h) Disabled
Writable Base Address Masked Base

BAR4 (20h) 01 32-bit I/O BAR
Bits (31:8) Addr. Bits (7:2)
BAR3 (1Ch) Disabled

BAR2 (18h) 0000 32-bit Memory BAR
BAR1 (14h) Upper Address Bits of BAR0 (non-masked)

64-bit Memory BAR
BAR0 (10h) 0100
BAR Mask Registers

31 0
BAR5 Mask (24h) 0x0
BAR4 Mask (20h) 0x000000 FF
BAR3 Mask (1Ch) 0x0
BAR2 Mask (18h) 0x000FFFFF
BAR1 Mask (14h) 0x00000000
Figure 6. Example Base Address Register Configuration
3.6.1.8 Expansion ROM BAR Mask Register†

This register:
• Is at offset 30h
• Is the same as the Expansion ROM BAR
• Requires dbi_cs2 for write access
Your local CPU can change the mask at runtime using the DBI. The mask register is at the same address as the BAR register.
The mask is a shadow register that is invisible to the PCIe wire but visible to your local CPU through the DBI. Furthermore, it is
only visible for a write and not for a read. You cannot read the mask register but you can write to it. It is accessed by asserting
dbi_cs2 and dbi_cs. If you only assert dbi_cs then you will access the BAR which is the primary register at that location. Use
CS2 instead of dbi_cs2 when you are using the AXI bridge.
3.6.2 RC mode†
Base Address Registers (Offset: 0x100x14)
Two BARs are present but are not expected to be used. You should disable them (see Disabling a BAR†) or else they will be
unnecessarily assigned memory during device enumeration. If you do use a BAR, then you should program it to capture TLPs that
are targeted to your local non-application memory space residing on TRGT1[1], and not for the application on TRGT1[2]. The BAR
range must be outside of the three Base/Limit regions. The controller provides one pair of 32-bit BARs (BAR0 and BAR1). The
BARs can be configured as follows:
• One 64-bit BAR: BAR0 and BAR1 are combined to form a single 64-bit BAR.
[1] Or AXI master interface.

[2] Because in a DSP, there is no wire access to TRGT0 (ELBI or CDM) using CFG requests or BAR-matched MEM requests.

NXP Semiconductors
PCIe Controller
• Two 32-bit BARs: BAR0 and BAR1 are two independent 32-bit BARs.
• One 32-bit BAR: BAR0 is a 32-bit BAR and BAR1 is either disabled or removed from controller altogether to reduce gate count.
For information about routing requests to either TRGT1 or TRGT0 on a BAR-by-BAR basis, see Advanced filtering and routing of
TLPs†. For more information on BAR operation, see Receive routing†.
If you have configured (MEM_FUNCN_BARn_TARGET_MAP =0) any BAR to have its incoming requests routed to TRGT0 in ,
then you must disable1 that BAR (through a DBI write) when operating the controller in . See Disabling a BAR†.
3.6.2.1 BAR sizing†

See BAR sizing†.
3.6.2.2 Disabling a BAR†

See Disabling a BAR†; it also applies to RC mode.
3.6.2.3 General rules for BAR setup (fixed mask or programmable mask schemes only)†
At runtime, application software can overwrite the BAR contents to reconfigure the BARs (unless the affected BAR is removed
during hardware configuration). Application software must observe the following rules when writing to the BARs:
• BAR0 and BAR1 can be configured as one 64-bit BAR, two 32-bit BARs, or one 32-bit BAR.
• Any 32-bit BAR that is not needed can be removed during controller hardware configuration to reduce gate count.
— BAR1 is the upper 32 bits of the combined 64-bit BAR formed by BAR0 and BAR1. Therefore, BAR1 must be disabled
— BAR0 must be a memory BAR and can be either prefetchable or non-prefetchable.
— The contents of the BAR0 mask register determine the number of writable bits in the 64-bit BAR, subject to the
restrictions described in BAR mask registers†. The BAR1 mask register contains the upper 32 bits of the BAR0
mask value.
— You can configure BAR1 as an independent 32-bit BAR or remove BAR1 from the controller hardware configuration.
• When BAR0 is configured as a 32-bit BAR, BAR1 is available as an independent 32-bit BAR according to the following rules:
— When BAR1 is not required in your design, you can remove BAR1 from the hardware configuration by setting both
BAR1_ENABLED_0 and BAR1_MASK_TYPE_0 to 0.

NXP Semiconductors
PCIe Controller
3.6.2.4 Memory BAR sizes†

BAR bits [11:0] are always masked for a memory BAR. The PCI Express Base Specification, Revision 4.0, Version 0.9 states that
the minimum memory address range requested by a BAR is 128 bytes. In the PCI Local Bus Specification, it is recommended
that devices that need less than 4 KB of address space should still consume 4 KB of address space in order to minimize the
number of bits in the address decoder. The controller requires each memory BAR to claim at least 4 KB as it does not perform
end address checking.
3.6.2.5 IO BAR sizes†

See IO BAR sizes†; it also applies to RC mode.
3.6.2.6 BAR mask registers†

You can change the mask at runtime through the local DBI. The mask register is at the same address as the BAR register. The
mask is a shadow register that is invisible to the PCIe wire but visible to the local processor over the DBI. Furthermore, it is only
visible for a write not for a read. So you cannot read the mask register but you can write to it. The shadow register is accessed by
asserting dbi_cs2 and dbi_cs. If you assert dbi_cs (only) then you access the BAR which is the primary register at that location.
Use CS2 instead of dbi_cs2 when you are using the AXI bridge.
3.6.2.7 Example BAR setup†

The following figure shows an example configuration of the BARs and their corresponding BAR mask registers. The example
configuration includes one 64-bit memory BAR (non-prefetchable).
Base Address Registers

31 0
BAR1 (14h) Upper Address Bits of BAR0 (non-masked)

64-bit Memory BAR
BAR0 (10h) 0100
BAR Mask Registers

31 0
BAR1 Mask (14h) 0x00000000
Figure 7. Example Base Address Register Configuration
3.6.2.8 Expansion ROM BAR Mask Register†

This register:
• Is at offset 38h
• Is the same as the Expansion ROM BAR
• Requires dbi_cs2/CS2 for write access
Your local CPU can change the mask at runtime using the DBI. The mask register is at the same address as the BAR register. The
mask is a shadow register that is invisible to the PCIe wire but visible to the local processor over the DBI. Furthermore, it is only
visible for a write not for a read. So you cannot read the mask register but you can write to it. The shadow register is accessed by
asserting CS2 and CS. If you assert CS (only) then you access the BAR which is the primary register at that location. Use CS2
instead of dbi_cs2 when you are using the AXI bridge.
3.7 PCIE_EP register descriptions

This section presents the PCIe controller registers when the controller is in endpoint (EP) mode.†

NXP Semiconductors
PCIe Controller
In the field descriptions in this section, "sticky" means that the field is not initialized or modified by a hot reset or a Function-level
reset (FLR). See the PCIe base specification for a full description of FLR.
3.7.1 EP memory map

PCIE_EP relative offset: 0h
(In bits)
0h Device ID And Vendor ID (DEVICE_VENDOR_ID) 32 RO See

description
4h Command And Status (COMMAND) 32 RW 0010_0000h
8h Class Code And Revision ID (CLASS_CODE_REVISION_ID) 32 RO See

description
Ch BIST, Header Type, Latency Timer, And Cache Line Size 32 RW 0000_0000h
(BHTLCLS)
10h Base Address 0 (BAR0) 32 RW 0000_000Ch
14h Base Address 1 (BAR1) 32 RO 0000_0000h
18h Base Address 2 (BAR2) 32 RW 0000_0000h
1Ch Base Address 3 (BAR3) 32 RO 0000_0001h
20h Base Address 4 (BAR4) 32 RW 0000_0000h
24h Base Address 5 (BAR5) 32 RO 0000_0000h
2Ch Subsystem ID And Subsystem Vendor ID (SSID) 32 RO 0000_0000h
30h Expansion ROM Base Address (EROMBAR) 32 RW 0000_0000h
30h Expansion ROM BAR Mask (EROMBARMASK) 32 RW 0001_FFFFh
34h Capabilities Pointer (CAPPR) 32 RO 0000_0040h
3Ch Max_Lat, Min_Gnt, Interrupt Pin, And Interrupt Line (MLMGIPIL) 32 RW 0000_01FFh
40h Power Management Capabilities (PMCAP) 32 RO DBC3_5001h
44h Power Management Control And Status (PMCSR) 32 RW 0000_0008h
50h PCI Express MSI Message Capability ID (MSI_CIDNC) 32 RW 0180_7005h
54h MSI message lower address (MSI_MLADDR) 32 RW 0000_0000h
58h MSI message upper address or data (MSI_MUADDR_DATA) 32 RW 0000_0000h
5Ch MSI data or mask bits (MSI_DATA_MASK) 32 RW 0000_0000h
60h MSI pending or mask bits (MSI_PEND_MASK_BITS) 32 RW 0000_0000h
64h MSI pending bits (MSI_PEND_BITS) 32 RO 0000_0000h
70h Capabilities ID and next pointer (CINCPCR) 32 RO 0002_B010h
74h Device capabilities (DEV_CAPABILITIES) 32 RO 0000_8FC1h
78h Device control and status (DEV_CONTROL_STATUS) 32 RW 0010_2010h

NXP Semiconductors
PCIe Controller
(In bits)
7Ch Link Capabilities (LINK_CAPABILITIES) 32 RO 0046_6823h
80h Link Control And Status (LINK_CONTROL_STATUS) 32 RW 1011_0000h
94h Device capabilities 2 (DEVICE_CAPABILITIES2_REG) 32 RO 0000_001Fh
98h Device control 2 and status 2 32 RW 0000_0000h

(DEVICE_CONTROL2_DEVICE_STATUS2_REG)
9Ch Link capabilities 2 (LINK_CAPABILITIES_2) 32 RO 0000_000Eh
A0h Link Control 2 And Status 2 32 RW 0001_0003h

(LINK_CONTROL2_LINK_STATUS2_REG)
B0h MSI-X Capability ID, Next Pointer, Control 32 RW 003F_0011h

(PCI_MSIX_CAP_ID_NEXT_CTRL_REG)
B4h MSI-X Table Offset And BIR (MSIX_TABLE_OFFSET_REG) 32 RO 0000_0002h
B8h MSI-X PBA Offset And BIR (MSIX_PBA_OFFSET_REG) 32 RO 0000_1002h
100h Advanced Error Reporting Extended Capability Header 32 RO 1482_0001h

(AER_EXT_CAP_HDR_OFF)
104h Uncorrectable error status (UNCORR_ERR_STATUS_OFF) 32 W1C 0000_0000h
108h Uncorrectable error mask (UNCORR_ERR_MASK_OFF) 32 RW 0040_0000h
10Ch Uncorrectable error severity (UNCORR_ERR_SEV_OFF) 32 RW 0046_2030h
110h Correctable error status (CORR_ERR_STATUS_OFF) 32 W1C 0000_0000h
114h Correctable error mask (CORR_ERR_MASK_OFF) 32 RW 0000_E000h
118h Advanced error capabilities and control 32 RW 0000_00A0h

(ADV_ERR_CAP_CTRL_OFF)
11Ch Header Log Register 0. (HDR_LOG_0_OFF) 32 RO 0000_0000h
120h Header Log Register 1. (HDR_LOG_1_OFF) 32 RO 0000_0000h
138h TLP Prefix Log Register 1. (TLP_PREFIX_LOG_1_OFF) 32 RO 0000_0000h
13Ch TLP Prefix Log Register 2. (TLP_PREFIX_LOG_2_OFF) 32 RO 0000_0000h
148h SPCIE Capability Header. (SPCIE_CAP_HEADER_REG) 32 RO 1581_0019h
14Ch Link control 3 (LINK_CONTROL3_REG) 32 RO 0000_0000h
150h Lane error status (LANE_ERR_STATUS_REG) 32 W1C 0000_0000h

NXP Semiconductors
PCIe Controller
(In bits)
154h Lane Equalization Control For Lanes 1 And 0 32 RO 7F00_7F00h

(SPCIE_CAP_OFF_0CH_REG)
158h Vendor-Specific Extended Capability Header. 32 RO 2581_000Bh

(RAS_DES_CAP_HEADER_REG)
15Ch Vendor-Specific Header. (VENDOR_SPECIFIC_HEADER_REG) 32 RO 1004_0002h
160h Event Counter Control (EVENT_COUNTER_CONTROL_REG) 32 RW 0000_0000h
164h Event counter data (EVENT_COUNTER_DATA_REG) 32 RO 0000_0000h
168h Time-based Analysis Control 32 RW 0000_0100h

(TIME_BASED_ANALYSIS_CONTROL_REG)
16Ch Time-Based Analysis Data (TIME_BASED_ANALYSIS_DATA_REG) 32 RO 0000_03E8h
188h Error Injection Enable (EINJ_ENABLE_REG) 32 RW 0000_0000h
18Ch Error Injection Control 0 (CRC Error). (EINJ0_CRC_REG) 32 RW 0000_0000h
190h Error Injection Control 1 (Sequence Number Error) 32 RW 0000_0000h

(EINJ1_SEQNUM_REG)
194h Error Injection Control 2 (DLLP Error). (EINJ2_DLLP_REG) 32 RW 0000_0000h
198h Error Injection Control 3 (Symbol Error) (EINJ3_SYMBOL_REG) 32 RW 0000_0000h
19Ch Error Injection Control 4 (FC Credit Error). (EINJ4_FC_REG) 32 RW 0000_0000h
1A0h Error Injection Control 5 (Specific TLP Error). (EINJ5_SP_TLP_REG) 32 RW 0000_0000h
1A4h Error Injection Control 6 (Compare Point Header DWORD #0). 32 RW 0000_0000h
(EINJ6_COMPARE_POINT_H0_REG)
1A8h Error Injection Control 6 (Compare Point Header DWORD #1). 32 RW 0000_0000h
1ACh Error Injection Control 6 (Compare Point Header DWORD #2). 32 RW 0000_0000h
1B0h Error Injection Control 6 (Compare Point Header DWORD #3). 32 RW 0000_0000h
1B4h Error Injection Control 6 (Compare Value Header DWORD #0). 32 RW 0000_0000h
(EINJ6_COMPARE_VALUE_H0_REG)
1B8h Error Injection Control 6 (Compare Value Header DWORD #1). 32 RW 0000_0000h
1BCh Error Injection Control 6 (Compare Value Header DWORD #2). 32 RW 0000_0000h
1C0h Error Injection Control 6 (Compare Value Header DWORD #3). 32 RW 0000_0000h

NXP Semiconductors
PCIe Controller
(In bits)
1C4h Error Injection Control 6 (Change Point Header DWORD #0). 32 RW 0000_0000h
(EINJ6_CHANGE_POINT_H0_REG)
1C8h Error Injection Control 6 (Change Point Header DWORD #1). 32 RW 0000_0000h
1CCh Error Injection Control 6 (Change Point Header DWORD #2). 32 RW 0000_0000h
1D0h Error Injection Control 6 (Change Point Header DWORD #3). 32 RW 0000_0000h
1D4h Error Injection Control 6 (Change Value Header DWORD #0). 32 RW 0000_0000h
(EINJ6_CHANGE_VALUE_H0_REG)
1D8h Error Injection Control 6 (Change Value Header DWORD #1). 32 RW 0000_0000h
1DCh Error Injection Control 6 (Change Value Header DWORD #2). 32 RW 0000_0000h
1E0h Error Injection Control 6 (Change Value Header DWORD #3). 32 RW 0000_0000h
1E4h Error Injection Control 6 (Packet Error). (EINJ6_TLP_REG) 32 RW 0000_0000h
1F8h Silicon Debug Control 1 (SD_CONTROL1_REG) 32 RW 0000_0000h
1FCh Silicon Debug Control 2 (SD_CONTROL2_REG) 32 RW 0000_0000h
208h Silicon Debug Status (Layer1 Per-lane) 32 RW 0018_0000h

(SD_STATUS_L1LANE_REG)
20Ch Silicon Debug Status (Layer1 LTSSM) 32 W1C 0000_0200h

(SD_STATUS_L1LTSSM_REG)
210h Silicon Debug Status (PM) (SD_STATUS_PM_REG) 32 W1C 0000_0000h
214h Silicon Debug Status (Layer2) (SD_STATUS_L2_REG) 32 RO 00FF_F000h
218h Silicon debug status (layer3 FC) (SD_STATUS_L3FC_REG) 32 RW 0300_0000h
21Ch Silicon Debug Status (Layer3) (SD_STATUS_L3_REG) 32 W1C 0000_0000h
228h Silicon Debug EQ Control 1 (SD_EQ_CONTROL1_REG) 32 RW 0000_0000h
22Ch Silicon Debug EQ Control 2 (SD_EQ_CONTROL2_REG) 32 RW 0000_0000h
238h Silicon Debug EQ Status 1 (SD_EQ_STATUS1_REG) 32 RO 0000_0000h
23Ch Silicon Debug EQ Status 2 (SD_EQ_STATUS2_REG) 32 RO 0000_0000h

NXP Semiconductors
PCIe Controller
(In bits)
258h PCIe Extended Capability ID, Capability Version, And Next Capability 32 RO 0001_000Bh
Offset (RASDP_EXT_CAP_HDR_OFF)
25Ch Vendor Specific Header. (RASDP_VENDOR_SPECIFIC_HDR_OFF) 32 RO 0381_0001h
260h ECC error correction control. (RASDP_ERROR_PROT_CTRL_OFF) 32 RW 0000_0000h
264h Corrected error (1-bit ECC) counter selection and control 32 RW 0000_0010h
(RASDP_CORR_COUNTER_CTRL_OFF)
268h Corrected error (1-bit ECC) counter data. 32 RO 0000_0000h

(RASDP_CORR_COUNT_REPORT_OFF)
26Ch Uncorrected error (2-bit ECC and parity) counter selection and 32 RW 0000_0010h
control. (RASDP_UNCORR_COUNTER_CTRL_OFF)
270h Uncorrected error (2-bit ECC and parity) counter data. 32 RO 0000_0000h
(RASDP_UNCORR_COUNT_REPORT_OFF)
274h Error injection control for the following features: - 1-bit or 2- 32 RW 0000_0000h
bit injection - Continuous or fixed-number (n) injection modes -
Global enable/disable - Selectable location where injection occurs
(RASDP_ERROR_INJ_CTRL_OFF)
278h Corrected errors locations 32 RO 00C0_00C0h

(RASDP_CORR_ERROR_LOCATION_OFF)
27Ch Uncorrected errors locations 32 RO 00C0_00C0h

(RASDP_UNCORR_ERROR_LOCATION_OFF)
280h RASDP error mode enable (RASDP_ERROR_MODE_EN_OFF) 32 RW 0000_0001h
284h Exit RASDP error mode (RASDP_ERROR_MODE_CLEAR_OFF) 32 W1C 0000_0000h
288h RAM Address where a corrected error (1-bit ECC) has been detected 32 RO 0000_0000h
(RASDP_RAM_ADDR_CORR_ERROR_OFF)
28Ch RAM Address where an uncorrected error (2-bit ECC) has been 32 RO 0000_0000h
detected (RASDP_RAM_ADDR_UNCORR_ERROR_OFF)
700h Ack latency timer and replay timer (ACK_LATENCY_TIMER_OFF) 32 RW See

description
704h Vendor-specific DLLP (VENDOR_SPEC_DLLP_OFF) 32 RW FFFF_FFFFh
708h Port force link (PORT_FORCE_OFF) 32 RW 0080_0004h
70Ch Ack Frequency and L0-L1 ASPM Control 32 RW 1BB4_B400h

(ACK_F_ASPM_CTRL_OFF)
710h Port Link Control (PORT_LINK_CTRL_OFF) 32 RW 0003_0120h
714h Lane Skew (LANE_SKEW_OFF) 32 RW 0800_0000h
718h Timer control and max function number 32 RW 4002_4000h

(TIMER_CTRL_MAX_FUNC_NUM_OFF)

NXP Semiconductors
PCIe Controller
(In bits)
71Ch Symbol Timer and Filter Mask 1 (SYMBOL_TIMER_FILTER_1_OFF) 32 RW 0000_0280h
720h Filter Mask 2 (FILTER_MASK_2_OFF) 32 RW 0000_0000h
724h AMBA Multiple Outbound Decomposed NP SubRequests Control 32 RW 0000_0001h

(AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF)
728h Debug Register 0 (PL_DEBUG0_OFF) 32 RO See

description
72Ch Debug Register 1 (PL_DEBUG1_OFF) 32 RO See

description
730h Transmit Posted FC Credit Status 32 RO 0000_0000h

(TX_P_FC_CREDIT_STATUS_OFF)
734h Transmit Non-Posted FC Credit Status 32 RO 0000_0000h

(TX_NP_FC_CREDIT_STATUS_OFF)
738h Transmit Completion FC Credit Status 32 RO 0000_0000h

(TX_CPL_FC_CREDIT_STATUS_OFF)
73Ch Queue Status (QUEUE_STATUS_OFF) 32 RW 0000_0000h
740h VC Transmit Arbitration Register 1 (VC_TX_ARBI_1_OFF) 32 RO 0000_000Fh
744h VC Transmit Arbitration Register 2 (VC_TX_ARBI_2_OFF) 32 RO 0000_0000h
748h Segmented-Buffer VC0 Posted Receive Queue Control. 32 RW 4523_0060h

(VC0_P_RX_Q_CTRL_OFF)
74Ch Segmented-Buffer VC0 Non-Posted Receive Queue Control. 32 RW 0523_000Ch

(VC0_NP_RX_Q_CTRL_OFF)
750h Segmented-Buffer VC0 Completion Receive Queue Control. 32 RW 0580_0000h

(VC0_CPL_RX_Q_CTRL_OFF)
80Ch Link Width And Speed Change Control (GEN2_CTRL_OFF) 32 RW 0003_02B4h
810h PHY status (PHY_STATUS_OFF) 32 RO See

description
814h PHY control (PHY_CONTROL_OFF) 32 RW 0000_0000h
81Ch Programmable target map control (TRGT_MAP_CTRL_OFF) 32 RW 0000_007Bh
820h Integrated MSI Reception Module (iMRM) address 32 RW 0000_0000h

(MSI_CTRL_ADDR_OFF)
824h iMRM Upper Address (MSI_CTRL_UPPER_ADDR_OFF) 32 RW 0000_0000h
828h iMRM Interrupt #0 Enable (MSI_CTRL_INT_0_EN_OFF) 32 RW 0000_0000h
82Ch iMRM Interrupt #0 Mask (MSI_CTRL_INT_0_MASK_OFF) 32 RW 0000_0000h
830h iMRM Interrupt #0 Status (MSI_CTRL_INT_0_STATUS_OFF) 32 W1C 0000_0000h

NXP Semiconductors
PCIe Controller
(In bits)
838h iMRM Interrupt #1 Mask (MSI_CTRL_INT_1_MASK_OFF) 32 RW 0000_0000h
83Ch iMRM Interrupt #1 Status (MSI_CTRL_INT_1_STATUS_OFF) 32 W1C 0000_0000h
84Ch iMRM Interrupt #3 Enable (MSI_CTRL_INT_3_EN_OFF) 32 RW 0000_0000h
85Ch iMRM Interrupt #4 Mask (MSI_CTRL_INT_4_MASK_OFF) 32 RW 0000_0000h
86Ch iMRM Interrupt #5 Status (MSI_CTRL_INT_5_STATUS_OFF) 32 W1C 0000_0000h
87Ch iMRM Interrupt #7 Enable (MSI_CTRL_INT_7_EN_OFF) 32 RW 0000_0000h
888h iMRM general-purpose IO (MSI_GPIO_IO_OFF) 32 RW 0000_0000h
88Ch RADM clock gating enable control (CLOCK_GATING_CTRL_OFF) 32 RW 0000_0001h
890h Gen3 control (GEN3_RELATED_OFF) 32 RW 0000_2001h
8A8h Gen3 EQ Control (GEN3_EQ_CONTROL_OFF) 32 RW 0505_9F71h
8ACh Gen3 EQ Direction Change Feedback Mode Control 32 RW 0000_0040h

(GEN3_EQ_FB_MODE_DIR_CHANGE_OFF)
8B4h Order rule control (ORDER_RULE_CTRL_OFF) 32 RW 0000_0000h
8B8h PIPE loopback control (PIPE_LOOPBACK_CONTROL_OFF) 32 RW 0000_0003h
8BCh DBI Read-Only Write Enable (MISC_CONTROL_1_OFF) 32 RW 0000_0000h
8C0h Up-configure multi-lane control (MULTI_LANE_CONTROL_OFF) 32 RW 0000_0080h

NXP Semiconductors
PCIe Controller
(In bits)
8C4h PHY interoperability control (PHY_INTEROP_CTRL_OFF) 32 RW 0000_0244h
8C8h TRGT_CPL_LUT Delete Entry Control 32 RW 0000_0000h

(TRGT_CPL_LUT_DELETE_ENTRY_OFF)
8CCh Link reset request flush control (LINK_FLUSH_CONTROL_OFF) 32 RW FF00_0001h
8D0h AXI Bridge Slave Error Response 32 RW 0000_9C00h

(AMBA_ERROR_RESPONSE_DEFAULT_OFF)
8D4h Link Down AXI Bridge Slave Timeout (AMBA_LINK_TIMEOUT_OFF) 32 RW 0000_0032h
8D8h AMBA Ordering Control (AMBA_ORDERING_CTRL_OFF) 32 RW 0000_0000h
8E0h ACE Cache Coherency Control Register 1 32 RW 0000_0000h

(COHERENCY_CONTROL_1_OFF)


8F0h Lower 20 bits of the programmable AXI address 32 RW 0000_0000h

where Messages coming from wire are mapped to.
(AXI_MSTR_MSG_ADDR_LOW_OFF)
8F4h Upper 32 bits of the programmable AXI address 32 RW 0000_0000h

where Messages coming from wire are mapped to.
(AXI_MSTR_MSG_ADDR_HIGH_OFF)
8F8h PCIe Controller IIP Release Version Number. 32 RO 3530_302Ah

(PCIE_VERSION_NUMBER_OFF)
8FCh PCIe Controller IIP Release Version Type. 32 RO 6C70_3033h

(PCIE_VERSION_TYPE_OFF)
930h Interface Timer Control (INTERFACE_TIMER_CONTROL_OFF) 32 RW 0000_0000h
934h Interface Timer Target (INTERFACE_TIMER_TARGET_OFF) 32 RW 0000_0032h
938h Interface Timer Status Register. 32 W1C 0000_0000h

(INTERFACE_TIMER_STATUS_OFF)
940h MSI-X Address Match Low (MSIX_ADDRESS_MATCH_LOW_OFF) 32 RW 0000_0000h
944h MSI-X Address Match High (MSIX_ADDRESS_MATCH_HIGH_OFF) 32 RW 0000_0000h
948h MSI-X Doorbell (MSIX_DOORBELL_OFF) 32 WO 0000_0000h
94Ch MSI-X RAM Power Mode And Debug Control 32 RW 0000_0000h

(MSIX_RAM_CTRL_OFF)
960h Masks for functional safety interrupt events. (SAFETY_MASK_OFF) 32 RW 0000_0000h
964h Status for functional safety interrupt events. 32 W1C 0000_0000h

(SAFETY_STATUS_OFF)

NXP Semiconductors
PCIe Controller
(In bits)
B20h CDM Register Checking Control and Status 32 RW 0000_0000h

(PL_CHK_REG_CONTROL_STATUS_OFF)
B24h CDM Register Checking First and Last address to check. 32 RW 0BFF_0000h
(PL_CHK_REG_START_END_OFF)
B28h CDM Register Checking Error Address. 32 RO 0000_0000h

(PL_CHK_REG_ERR_ADDR_OFF)
B2Ch CDM Register Checking error PF and VF Numbers. 32 RO 0000_0000h

(PL_CHK_REG_ERR_PF_VF_OFF)
B40h Auxiliary Clock Frequency Control (AUX_CLK_FREQ_OFF) 32 RW 0000_000Ah
2_0010h BAR0 Mask (BAR0_MASK) 32 WO FFFF_FFFFh
2_001Ch BAR3 Mask (BAR3_MASK) 32 WO FFFF_FFFFh
6_0000h iATU Region Control 1 32 RW 0000_0000h

(IATU_REGION_CTRL_1_OFF_OUTBOUND_0)

6_0008h iATU Lower Base Address 32 RW 0000_0000h

(IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0)
6_000Ch iATU Upper Base Address 32 RW 0000_0000h

(IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0)
6_0010h iATU Limit Address (IATU_LIMIT_ADDR_OFF_OUTBOUND_0) 32 RW 0000_0FFFh
6_0014h iATU Lower Target Address 32 RW 0000_0000h

(IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0)
6_0018h iATU Upper Target Address 32 RW 0000_0000h

(IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0)
6_0020h iATU Upper Limit Address 32 RW 0000_0000h

(IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0)
6_0100h iATU Region Control 1 (IATU_REGION_CTRL_1_OFF_INBOUND_0) 32 RW 0000_0000h

(IATU_LWR_BASE_ADDR_OFF_INBOUND_0)

NXP Semiconductors
PCIe Controller
(In bits)

(IATU_UPPER_BASE_ADDR_OFF_INBOUND_0)
6_0110h iATU Limit Address (IATU_LIMIT_ADDR_OFF_INBOUND_0) 32 RW 0000_0FFFh

(IATU_LWR_TARGET_ADDR_OFF_INBOUND_0)

(IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0)

(IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0)












NXP Semiconductors
PCIe Controller
(In bits)

















NXP Semiconductors
PCIe Controller
(In bits)
















NXP Semiconductors
PCIe Controller
(In bits)

6_0A00h iATU Region Control 1 32 RW 0000_0000h


6_0A08h iATU Lower Base Address 32 RW 0000_0000h

6_0A0Ch iATU Upper Base Address 32 RW 0000_0000h

6_0A10h iATU Limit Address (IATU_LIMIT_ADDR_OFF_OUTBOUND_5) 32 RW 0000_0FFFh
6_0A14h iATU Lower Target Address 32 RW 0000_0000h

6_0A18h iATU Upper Target Address 32 RW 0000_0000h

6_0A20h iATU Upper Limit Address 32 RW 0000_0000h

3.7.2 Device ID And Vendor ID (DEVICE_VENDOR_ID)
Offset
Register Offset
DEVICE_VENDOR_ID 0h
Function
This register is used to identify the device and the manufacturer of the device.
All fields in this register become writable when MISC_CONTROL_1_OFF[DBI_RO_WR_EN] = 1.
NOTE
This register is writeable using internal PCIe_CTRLR_CONFIG_ADDR/ PCIe_CTRLR_CONFIG_DATA accesses,
but is read-only from inbound configuration accesses by an external host.

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R DEVICE_ID
Reset u1 u u u u u u u u u u u u u u u
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VENDOR_ID
Reset 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 1
1. See the chip-specific SerDes information for this value.
Fields
Field Function
31-16 Device ID
DEVICE_ID Identifies the device ID. See the chip-specific SerDes information for this value.
15-0 Vendor ID
VENDOR_ID Identifies the manufacturer as allocated by the PCI-SIG consortium. On this chip, the vendor ID is 1957h.
3.7.3 Command And Status (COMMAND)
Offset
Register Offset
COMMAND 4h
Function
This register controls the generation and response to PCIe cycles and the recording of status information for PCIe-related events.

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DETE SIGNA RCVD RCVD SIGNA MAST INT_S

R 0 0 1 0
CTE... LE... _MA... _TA... LE... ER_... TA...
W W1C W1C W1C W1C W1C W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 INT_ 0 SERR 0 PARIT 0 BUS_ MEM_ IO_SP
W EN EN Y_... MAS... SPA... AC...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31 Detected parity error

DETECTED_PA Set whenever a device receives a poisoned TLP regardless of the state of the PARITY_ERR_RESPONSE
RITY_ERR field. For more details, see the "Error Registers" section of the PCIe Base Specification.
30 Signaled system error

SIGNALED_SY Set whenever a device sends an ERR_FATAL or ERR_NONFATAL message and SERREN=1. For more
S_ERR details, see the "Error Registers" section of the PCIe Base Specification.
29 Received master abort

RCVD_MASTE Set whenever a requestor receives a completion with unsupported request completion status. For more
R_ABORT details, see the "Error Registers" section of the PCIe Base Specification.
28 Received target abort

RCVD_TARGE Set whenever a device receives a completion with completer abort completion status. For more details, see
T_ABORT the "Error Registers" section of the PCIe Base Specification.
27 Signaled target abort

SIGNALED_TA Set whenever a device completes a request using completer abort completion status. For more details, see
RGET_ABORT the "Error Registers" section of the PCIe Base Specification.
26-25 Reserved
24 Master data parity error

MASTER_DPE A Function programs this field to 1 if PARITY_ERR_RESPONSE=1 and either of the following conditions
is true:
• The Function receives a poisoned completion
• The Function transmits a poisoned request
If PARITY_ERR_RESPONSE=0, MASTER_DPE never has the value 1.

NXP Semiconductors
PCIe Controller
Field Function
23-21 Reserved
20 Reserved
19 Emulation interrupt pending

INT_STATUS Indicates whether an INTx emulation interrupt is pending internally in the Function.
Programming INT_EN=1 has no effect on the status of INT_STATUS.
0b - No INTx emulation interrupt is pending.
1b - An INTX emulation interrupt is pending.
18-11 Reserved
10 Interrupt enable/disable
INT_EN Controls the ability of a Function to generate INTx emulation interrupts.
NOTE
Any INTx emulation interrupts already asserted by the Function must be deasserted when
this field is set. INTx interrupts use virtual wires that must, if asserted, be deasserted using
the appropriate Deassert_INTx message(s) when this field is set. Only the INTx virtual wire
interrupt(s) associated with the Function(s) for which this bit is set are affected.
0b - PCIe allows Functions to assert INTx interrupts.

1b - PCIe prevents Functions from asserting INTx interrupts.
9 Reserved
8 SERR# Enable
SERREN Controls the reporting of fatal and non-fatal errors detected by the device to the root complex. For more
details, see the "Error Registers" section of the PCIe Base Specification.
7 Reserved
6 Parity error response

PARITY_ERR_ Controls the logging of poisoned TLPs in the MASTER_DPE field. For more details, see the "Error
RESPONSE Registers" section of the PCIe Base Specification.
5-3 Reserved

NXP Semiconductors
PCIe Controller
Field Function
2 Bus_Master_Enable
BUS_MASTER_ Bus Master Enable
EN
1 Memory_Space_Enable
MEM_SPACE_ Memory Space Enable
EN
0 I_O_Space_Enable
IO_SPACE_EN I/O Space Enable
3.7.4 Class Code And Revision ID (CLASS_CODE_REVISION_ID)
Offset
Register Offset
CLASS_CODE_REVISIO 8h
N_ID
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R BASE_CLASS_CODE SUBCLASS_CODE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R PROGRAM_INTERFACE REVISION_ID
Reset 0 0 0 0 0 0 0 0 u1 u u u u u u u
Fields
Field Function
31-24 Base class code

NXP Semiconductors
PCIe Controller
Field Function
BASE_CLASS_ This field contains a code that broadly classifies the type of operation the Function performs. Encodings
CODE for base class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings
are Reserved.
This field is sticky.
23-16 Sub-class code

SUBCLASS_C This field specifies a base class sub-class, which identifies the operation of the Function more specifically.
ODE Encodings for sub-class are provided in the PCI Code and ID Assignment Specification. All unspecified
encodings are reserved.
15-8 Programming interface

PROGRAM_IN This field identifies a specific register-level programming interface (if any) so that device independent
TERFACE software can interact with the Function. Encodings for interface are provided in the PCI Code and ID
Assignment Specification. All unspecified encodings are reserved.
7-0 Revision ID
REVISION_ID Identifies the revision ID. See the chip-specific SerDes information for this value.
3.7.5 BIST, Header Type, Latency Timer, And Cache Line Size (BHTLCLS)
Offset
Register Offset
BHTLCLS Ch
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MULTI
R BIST HEADER_TYPE
_F...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
CACHE_LINE_SIZE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-24 BIST control and status

BIST The BIST register functions are not supported by the core. All 8 bits of the BIST field are hardwired to 0.
23 Multi-function device
MULTI_FUNC Except where stated otherwise, program this field as follows:
• MULTI_FUNC=1 if you have multiple Functions
• MULTI_FUNC=0 if you have only one Function
0b - Software must not probe for Functions other than Function 0 unless explicitly indicated by
another mechanism, such as an ARI or SR-IOV capability structure.
1b - The device may contain multiple Functions. Software can probe for Functions other than
Function 0.
22-16 Header layout

HEADER_TYP This field identifies the layout of the second part of the predefined header. The controller uses
E 000_0000b encoding.
15-8 Reserved
7-0 Cache line size

CACHE_LINE_ This field exists only for compatibility with earlier PCI software. It has no effect on any PCIe behavior.
SIZE
3.7.6 Base Address 0 (BAR0)
Offset
Register Offset
BAR0 10h
Function
The core provides three pairs of 32-bit BAR for each implemented function. Each pair (BAR 0 and 1, BAR 2 and 3) can be
configured as follows:
• One 64-bit BAR: For example, BAR 0 and 1 are combined to form a single 64-bit BAR.
• Two 32-bit BAR: For example, BAR 0 and 1 are two independent 32-bit BARs.
• One 32-bit BAR: For example, BAR 0 is a 32-bit BAR and BAR 1 is disabled.
In addition, you can configure the BAR to have its incoming Requests routed to RXTGT1.

NXP Semiconductors
PCIe Controller
At runtime, application software can overwrite the BAR contents to reconfigure the BAR. Application software must observe the
rules listed below when writing to the BARs.
The rules for BAR configuration are the same for all three pairs. Using BAR 0 and 1 as the example pair, the rules for BAR
configuration are:
• Any pair (for example, BAR 0 and 1) can be configured as one 64-bit BAR, two 32-bit BARs, or one 32-bit BAR.
• BAR pairs cannot overlap to form a 64-bit BAR. For example, you cannot combine BARs 1 and 2 to form a 64-bit BAR.
• If the device is configured as a PCI Express Endpoint (not a Legacy Endpoint), then any memory that is configured as
prefetchable must be a 64-bit memory BAR.
• If BAR 0 is configured as a 64-bit BAR:
— BAR1 is the upper 32 bits of the combined 64-bit BAR formed by BAR 0 and 1.Therefore, BAR 1 must be disabled
— BAR 1 is the upper 32 bits of the combined 64-bit BAR formed by BAR 0 and 1.
— BAR 0 must be a memory BAR and can be either prefetchable or non-prefetchable.
— The contents of the BAR 0 Mask register determine the number of writable bits in the 64-bit BAR, subject to the
restrictions described in BAR Mask Registers . The BAR 1 Mask register contains the upper 32 bits of the BAR 0
Mask value.
• If BAR 0 is configured as a 32-bit BAR:
— You can configure BAR 1 as an independent 32-bit BAR or remove BAR 1 from the core hardware configuration.
— BAR 0 can be configured as a memory BAR or an I/O BAR.
— The contents of the BAR 0 Mask register determine the number of writable bits in the 32-bit BAR 0, subject to the
restrictions described in BAR Mask Registers.
— BAR 0 can be disabled by writing 0 to bit 0 of the BAR 0 Mask register
• When BAR 0 is configured as a 32-bit BAR, BAR 1 is available as an independent 32-bit BAR according to the following
rules:
— BAR 1 can be configured as a memory BAR or an I/O BAR.
— The contents of the BAR 1 Mask register determine the number of writable bits in the 32-bit BAR 1, subject to the
restrictions described in BAR Mask Registers.
The same rules apply for pairs 2/3.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R ADDRESS
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mem_
R ADDRESS PREF
TYPE I_O
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-4 ADDRESS
ADDRESS BAR 0 base address bits (for a 64-bit BAR, the remaining upper address bits are in BAR 1). The BAR 0 Mask
value determines which address bits are masked.
3 PREF
PREF If BAR 0 is an I/O BAR, bit 3 is the second least significant bit of the base address.
NOTE
Bits [3:0] are writable internally but not externally.
If BAR 0 is a memory BAR, bit 3 indicates if the memory region is prefetchable:

0b - Non-prefetchable
1b - Prefetchable
2-1 TYPE
TYPE If BAR 0 is an I/O BAR, bit 2 the least significant bit of the base address and bit 1 is 0.
NOTE
If BAR 0 is a memory BAR, bits [2:1] determine the BAR type:

00b - = 32-bit BAR
10b - = 64-bit BAR
0 Mem_I_O
Mem_I_O NOTE
0b - = BAR 0 is a memory BAR

1b - = BAR 0 is an I/O BAR
Offset
Register Offset
BAR1 14h

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R ADDRESS
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ADDRESS
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0 ADDRESS
ADDRESS BAR 1 contains the upper 32 bits of the
BAR 0 base address (bits [63:32]).
Offset
Register Offset
BAR2 18h
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R ADDRESS
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM_
R ADDRESS PREF
TYPE I_O
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-4 ADDRESS
3 PREF
PREF If BAR 2 is an I/O BAR, bit 3 is the second least significant bit of the base address.
NOTE

0b - Non-prefetchable
1b - Prefetchable
2-1 TYPE
TYPE If BAR 2 is an I/O BAR, bit 2 the least significant bit of the base address and bit 1 is 0.
NOTE

00b - = 32-bit BAR
10b - = 64-bit BAR
0 MEM_I_O
MEM_I_O NOTE
0b - BAR 2 is a memory BAR

1b - BAR 2 is an I/O BAR
Offset
Register Offset
BAR3 1Ch

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R ADDRESS
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ADDRESS
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Fields
Field Function
31-0 ADDRESS
ADDRESS BAR 3 bit definitions are the same as the BAR 2 bit definitions.
Offset
Register Offset
BAR4 20h
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R ADDRESS
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ADDRESS PREF MEM_

TYPE
W I_O
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-4 ADDRESS

NXP Semiconductors
PCIe Controller
Field Function
3 PREF
PREF PREFETCHABLE4_N for memory BAR
0 for I/O BAR
If BAR 4 is an I/O BAR, bit 3 is the second least significant bit of the base address.
NOTE
Bits [3:0] are writable through the IDBI.

0b - = Non-prefetchable
1b - = Prefetchable
2-1 TYPE
TYPE BAR4_TYPE_N for memory BAR
If BAR 4 is an I/O BAR, bit 2 the least significant bit of the base address and bit 1 is 0.
NOTE

00b - = 32-bit BAR
10b - = 64-bit BAR
0 MEM_I_O
MEM_I_O MEM4_SPACE_DECODER_N
NOTE
0b - = BAR 4 is a memory BAR

1b - = BAR 4 is an I/O BAR
Offset
Register Offset
BAR5 24h

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R ADDRESS
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ADDRESS
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0 ADDRESS
ADDRESS Configuration- dependent
If BAR 4 is a 64-bit BAR, BAR 5 contains the upper 32 bits of the BAR 4 base address (bits 63:32).
If BAR 4 is a 32-bit BAR, BAR 5 can be independently programmed as an additional 32-bit BAR or can be
excluded from the core hardware configuration.
If programmed as an independent 32-bit BAR, the BAR 5 bit definitions are the same as the BAR 4
bit definitions.
3.7.12 Subsystem ID And Subsystem Vendor ID (SSID)
Offset
Register Offset
SSID 2Ch
Function
This register is used to uniquely identify the add-in card or subsystem where the PCIe component resides.

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R SUBSYS_DEV_ID
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R SUBSYS_VENDOR_ID
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-16 Subsystem ID
SUBSYS_DEV_ Subsystem ID
ID
Writable internally but not externally.
15-0 Subsystem vendor ID

SUBSYS_VEN This is a vendor-specific ID that identifies the vendor of the add-in card or subsystem.
DOR_ID
3.7.13 Expansion ROM Base Address (EROMBAR)
Offset
Register Offset
EROMBAR 30h
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
ADDRESS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ENABL
ADDRESS Reserved
W E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-11 ADDRESS
ADDRESS Expansion ROM Address
10-1 Reserved
0 ENABLE
ENABLE Expansion ROM Enable
3.7.14 Expansion ROM BAR Mask (EROMBARMASK)
Offset
Register Offset
EROMBARMASK 30h
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
ROM_MASK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ROM_
R
ROM_MASK BAR...
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Fields
Field Function
31-1 Expansion ROM Mask

ROM_MASK The access attributes of this field are as follows:
• Dbi: No access
• Dbi2: if ROM_BAR_ENABLED then W else R
0 Expansion ROM Bar Mask Register Enabled

NXP Semiconductors
PCIe Controller
Field Function
ROM_BAR_EN The access attributes of this field are as follows:

ABLED
• Dbi: No access
• Dbi2: if ROM_BAR_ENABLED then W else R
3.7.15 Capabilities Pointer (CAPPR)
Offset
Register Offset
CAPPR 34h
Function
Points to a linked list of capabilities implemented by a Function.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 CAP_POINTER
Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
Fields
Field Function
31-8 Reserved
7-0 Capabilities pointer

CAP_POINTER Points to a valid capability structure. Either this structure is the PCIe capability structure, or a subsequent list
item points to the PCIe capability structure. The bottom two bits are reserved, and the controller sets them
to 00b. Software must mask these bits off before using this register as a pointer in Configuration Space to
the first entry of a linked list of new capabilities.
This field becomes writable when MISC_CONTROL_1_OFF[DBI_RO_WR_EN] = 1.

NXP Semiconductors
PCIe Controller
3.7.16 Max_Lat, Min_Gnt, Interrupt Pin, And Interrupt Line (MLMGIPIL)
Offset
Register Offset
MLMGIPIL 3Ch
Function
This register:
• Communicates interrupt line routing information
• Identifies the legacy interrupt messages that the Function uses
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
INT_PIN INT_LINE
W
Reset 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1
Fields
Field Function
31-16 Reserved
15-8 INT_PIN
INT_PIN This field identifies the legacy interrupt messages that the Function uses. The valid values are:
• 00h: The Function doesn't use any legacy interrupt messages.
• 01h: Map to legacy interrupt messages for INTA.
• 02h: Map to legacy interrupt messages for INTB.
• 03h: Map to legacy interrupt messages for INTC.
• 04h: Map to legacy interrupt messages for INTD.
• 05h through FFh: Reserved.
PCIe defines one legacy interrupt message for a single-Function device and up to four legacy interrupt
messages for a multi-Function device. For a single-Function device, only INTA may be used. Any Function
on a multi-Function device can use any of the INTx messages. If a device implements a single legacy

NXP Semiconductors
PCIe Controller
Field Function
interrupt message, it must be INTA. If it implements two legacy interrupt messages, they must be INTA and
INTB; and so forth. For a multi-Function device, all Functions can use the same INTx message, each may
have its own (up to a maximum of four Functions), or any combination thereof. A single Function can never
generate an interrupt request on more than one INTx message.
7-0 Interrupt line

INT_LINE This field communicates interrupt line routing information. Values in this register are programmed by system
software and are specific to the system architecture. The Function itself does not use this value. Instead,
device drivers and operating systems use this value.
3.7.17 Power Management Capabilities (PMCAP)
Offset
Register Offset
PMCAP 40h
Function
Establishes the standard PCIe power management capability structure.
This capability is defined by the PCI Bus Power Management Interface Specification, Revision 1.2, available at https://pcisig.com.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
D2_SU D1_SU
R PME_SUPPORT AUX_CURR DSI 0 PM_SPEC_VER
PP... PP...
Reset 1 1 0 1 1 0 1 1 1 1 0 0 0 0 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R PM_NEXT_POINTER PM_CAP_ID
Reset 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1
Fields
Field Function
31-27 Power Management Event Support

PME_SUPPOR
T

NXP Semiconductors
PCIe Controller
Field Function
This field indicates the power states in which a Function can generate a power-management event (PME).
The individual bits within this field are associated with power states as shown below. A value of 1b for any
bit indicates that the Function is capable of asserting the PME signal in that power state. A value of 0b for
any bit indicates that the Function is not capable of asserting the PME signal in that power state .
• Bit 4 (leftmost in the register diagram): D3cold
• Bit 3: D3hot
• Bit 2: D2
• Bit 1: D1
• Bit 0 (rightmost in the register diagram): D0
26 D2 State Support
D2_SUPPORT Indicates whether the Function supports the D2 power management state.
0b - The Function does not support the D2 power management state.
1b - The Function supports the D2 power management state.
25 D1 State Support
D1_SUPPORT Indicates whether the Function supports the D1 power management state.
0b - The Function does not support the D1 power management state.
1b - The Function supports the D1 power management state.
24-22 Auxiliary Current Requirements

AUX_CURR Reports the 3.3 V auxiliary current requirement for this PCIe Function.
21 Device-Specific Initialization
DSI Indicates whether special initialization of this function is required before the generic class device driver is
able to use it.
0b - The Function does not require a device-specific initialization sequence after a transition to the
D0 uninitialized state.
1b - The Function requires a device-specific initialization sequence after a transition to the D0
uninitialized state.
20-19 Reserved

NXP Semiconductors
PCIe Controller
Field Function
18-16 Power management spec version

PM_SPEC_VE When PM_SPEC_VER=011b, this Function complies with Revision 1.2 of the PCI Bus Power Management
R Interface Specification.
15-8 Next capability pointer

PM_NEXT_POI This field describes the location of the next item in the Function's capability list. The given value
NTER is an offset into the Function's configuration space. If there are no additional items in the capability
list, PM_NEXT_POINTER=0h.
7-0 Power management capability ID

PM_CAP_ID When PM_CAP_ID=1, the data structure currently being pointed to is the PCIe power management
data structure.
3.7.18 Power Management Control And Status (PMCSR)
Offset
Register Offset
PMCSR 44h
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BPCC_ B2_B3
R DATA 0
EN _S...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PME_
R DATA_SCALE 0 PME_ 0 NO_S 0 POWER_STAT
STA...
ENA... OFT... E
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
Fields
Field Function
31-24 Power data information

NXP Semiconductors
PCIe Controller
Field Function
DATA This field reports the state-dependent data requested by the DATA_SELECT field.
The DATA_SCALE field scales the value of the DATA field.
See the PCI Bus Power Management Interface Specification for a full explanation of how DATA,
DATA_SCALE, and DATA_SELECT interact.
23 Bus power/clock control enable

BPCC_EN See the PCI Bus Power Management Interface Specification for a full description of the mechanism that
controls the clock and power source of the PCI bus.
When the bus power/clock control mechanism is disabled, you cannot use the POWER_STATE field to
control the power or clock of the bridge's secondary bus.
0b - The bus power/clock control policies defined in the PCI Bus Power Management Interface
Specification are disabled.
1b - The bus power/clock control policies defined in the PCI Bus Power Management Interface
Specification are enabled.
22 B2/B3 support
B2_B3_SUPPO This field determines the action that occurs as a direct result of placing the Function in D3hot.
RT
This field is meaningful only when BPCC_EN=1.
0b - B3. When you place the bridge Function in D3hot, its secondary bus has its power removed
(B3).
1b - B2. When you place the bridge Function in D3hot, the PCI clock on its secondary bus stops
(B2).
21-16 Reserved
15 PME status
PME_STATUS PME Status
14-13 Data scaling factor

DATA_SCALE This field indicates the scaling factor that you must use when interpreting the value of the DATA field.
The value and meaning of this field varies depending on how you have programmed the
DATA_SELECT field.
See the PCI Bus Power Management Interface Specification for instructions on using and interpreting
this field.
12-9 Reserved
8 PME# enable
PME_ENABLE This field controls whether the Function can or cannot assert PME#.

NXP Semiconductors
PCIe Controller
Field Function
If the function supports PME# from D3cold, then this field is sticky, and the operating system and must
explicitly program it to 0 every time the operating system initially loads.
Functions that do not support PME# generation from any D-state (that is,
PMCSR[PME_SUPPORT}=00000b) can hardwire this field to be read-only always returning a 0 when
read by system software.
0b - The Function cannot assert PME#.
1b - The Function can assert PME#.
7-4 Reserved
3 No Soft Reset
NO_SOFT_RST If PME is supported and enabled, and a system or bus segment causes a transition from from D3hot to D0,
the device returns to the "D0 Uninitialized" state, and preserves only the PME context.
0b - Internal reset. The device performs an internal reset when it transitions from D3hot to D0 via
software control of the POWER_STATE field. Configuration context is lost when the soft reset
occurs. After the device transitions from the D3hot to the D0 state, it needs a full reinitialization
sequence to return to the "D0 initialized" state.
1b - No internal reset. The device does not perform an internal reset when it transitions from D3hot
to D0 via software control of the POWER_STATE field. Configuration Context is preserved. After
the device transitions from the D3hot to the "D0 Initialized" state, the operating system only needs
to program the POWER_STATE field to preserve configuration context.
2 Reserved
1-0 Power state

POWER_STAT This field shows you the current power state of a Function and allows you to set the Function into a new
E power state.
If you try to place the Function into an unsupported power state, the PCIe controller ignores your attempt,
and does not change the power state.
00b - D0
01b - D1
10b - D2
11b - D3hot

NXP Semiconductors
PCIe Controller
3.7.19 PCI Express MSI Message Capability ID (MSI_CIDNC)
Offset
Register Offset
MSI_CIDNC 50h
Function
This register is supported only for EP mode.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXT_D PVM_ ADDR

R 0 EXT_D MULTI_MSG_CAP ENAB
AT... SUP... _CA... MULTI_MSG_EN
AT... LE
W
Reset 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CAP_NEXT_PTR CAP_ID
Reset 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1
Fields
Field Function
31-27 Reserved
26 Extended Message Data Enable

EXT_DATA_EN Controls whether the Function is configured to provide extended-message data.
This field is writable only when you write to EXT_DATA_CAP via DBI.
0b - Not configured
1b - Configured
25 Extended Message Data Capable

EXT_DATA_CA This field becomes writable when MISC_CONTROL_1_OFF[DBI_RO_WR_EN] = 1.
P
0b - The Function is incapable of providing extended-message data.
1b - The Function is capable of providing extended-message data.
24 MSI per-vector masking capable

0b - The Function does not support MSI per-vector masking.

NXP Semiconductors
PCIe Controller
Field Function
PVM_SUPPOR 1b - The Function supports MSI per-vector masking.

T
23 MSI 64-bit address capable

ADDR_CAP_64 This field becomes writable when MISC_CONTROL_1_OFF[DBI_RO_WR_EN] = 1.
0b - The Function is incapable of sending a 64-bit message address.
1b - The Function is capable of sending a 64-bit message address.
22-20 MSI multiple message enable

MULTI_MSG_E Software writes to this field to indicate the number of allocated vectors (equal to or less than the number
N of requested vectors). The number of allocated vectors is aligned to a power of two. If a Function requests
four vectors (indicated by MULTI_MSG_CAP=010b), system software can allocate four, two, or one vector
by writing 010b, 001b or 000b to MULTI_MSG_EN, respectively. When MSI is enabled, a Function will be
allocated at least 1 vector.
000b - 1 vector allocated.
001b - 2 vectors allocated.
110b-111b - Reserved
19-17 MSI multiple message capable

MULTI_MSG_C System software reads this field to determine the number of requested vectors. The number of requested
AP vectors must be aligned to a power of two. For example, if a function requires three vectors, it requests four
by programming MULTI_MSG_CAP=010b.
000b - 1 vector requested.
001b - 2 vectors requested.
110b-111b - Reserved
16 MSI enable
ENABLE See the PCI Local Bus Specification for a full description of this field.

NXP Semiconductors
PCIe Controller
Field Function
15-8 MSI capability next pointer

CAP_NEXT_PT This field is a pointer to the next item in the capabilities list. CAP_NEXT_PTR must be 0h for the final item
R in the list.
7-0 MSI capability ID

CAP_ID This field always has the value 05h. This indicates that the Function is MSI-capable.
3.7.20 MSI message lower address (MSI_MLADDR)
Offset
Register Offset
MSI_MLADDR 54h
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MSG_LOWER_ADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
MSG_LOWER_ADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-2 System-specified message lower address

MSG_LOWER_ If MSI_CIDNC[ENABLE]=1, MSG_LOWER_ADDR specify the DWORD-aligned address (AD[31:2]) for the
ADDR MSI memory write transaction. PCIe drives AD[1:0] to 0 during the address phase.
1-0 Reserved

NXP Semiconductors
PCIe Controller
3.7.21 MSI message upper address or data (MSI_MUADDR_DATA)
Offset
Register Offset
MSI_MUADDR_DATA 58h
Function
This register serves two purposes depending on the size of the MSI message:
• For a 32-bit message, this register contains message data.
• For a 64-bit message, this register contains the upper address of the message.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
EMDATA_UADDRU
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DATA_UADDRL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-16 Extended MSI data or upper 16 bits of the upper address

EMDATA_UAD For a 32-bit message, this field contains the extended MSI data.
DRU
For a 64-bit message, this field contains the upper 16 bits of the upper address.
15-0 Data or lower 16 bits of the upper address

DATA_UADDR For a 32-bit message, this field contains the message data.
L
For a 64-bit message, this field contains the lower 16 bits of the upper address.
3.7.22 MSI data or mask bits (MSI_DATA_MASK)
Offset
Register Offset
MSI_DATA_MASK 5Ch

NXP Semiconductors
PCIe Controller
Function
• For a 32-bit message, and when PVM is enabled, this register contains mask bits.
• For a 64-bit message, this register contains message data.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DATA_UMB
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DATA_LMB
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-16 Data or upper mask bits

DATA_UMB For a 32-bit message, and when PVM is enabled, this field contains the upper mask bits.
For a 64-bit message, this field contains message data.
15-0 Data or lower mask bits

DATA_LMB For a 32-bit MSI message, and when PVM is enabled, this field contains the lower mask bits.
For a 64-bit MSI message, this field contains message data.
3.7.23 MSI pending or mask bits (MSI_PEND_MASK_BITS)
Offset
Register Offset
MSI_PEND_MASK_BITS 60h
Function
• For a 32-bit message, this register contains pending bits.
• For a 64-bit message, this register contains mask bits.

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
PEND_MASK_BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
PEND_MASK_BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0 Pending or mask bits

PEND_MASK_ For a 32-bit message, this field contains pending bits.
BITS
For a 64-bit message, this field contains mask bits.
3.7.24 MSI pending bits (MSI_PEND_BITS)
Offset
Register Offset
MSI_PEND_BITS 64h
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R PEND_BITS
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R PEND_BITS
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-0 Pending bits

PEND_BITS If a bit in this field is 1, the Function has a pending associated message for that bit.
3.7.25 Capabilities ID and next pointer (CINCPCR)
Offset
Register Offset
CINCPCR 70h
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLOT_
R 0 INT_MSG_NUM DEV_PORT_TYPE CAP_VERSION
IMP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CAP_NEXT_PTR CAP_ID
Reset 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0
Fields
Field Function
31-30 Reserved
29-25 PCIe Interrupt Message Number

INT_MSG_NUM See the PCIe base specification for a full description of this field.
24 PCIe Slot Implemented Valid

SLOT_IMP This field becomes writable when MISC_CONTROL_1_OFF[DBI_RO_WR_EN] = 1.
0b - The link associated with this port is either connected to a system-integrated device, or
disabled.
1b - The link associated with this port is connected to a slot.

NXP Semiconductors
PCIe Controller
Field Function
23-20 PCIe device/port type

DEV_PORT_TY This field indicates the specific type of this PCIe Function.
PE
Different Functions in a multi-Function device can generally be of different types.
The valid encodings for EP Functions are shown below. All other encodings are reserved.
0000b - PCIe EP
0001b - Legacy PCIe EP
1001b - RC integrated EP
1010b - RC event collector
19-16 PCIe capability version number

CAP_VERSION This field indicates the version number of the PCIe capability structure, as assigned by PCI-SIG.
On this chip, CAP_VERSION=2h.
15-8 PCIe Next Capability Pointer

CAP_NEXT_PT Contains the offset to the next PCI capability structure, or 00h if the linked list of capabilities has no
R other items.
7-0 PCIe capability ID

CAP_ID This field indicates the capability ID of a PCIe capability structure, 10h.
3.7.26 Device capabilities (DEV_CAPABILITIES)
Offset
Register Offset
DEV_CAPABILITIES 74h

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLR_
R 0 CSPLS CSPLV 0
CAP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ROLE_ EXT_T PHAN_FUNC_S

R 0 EP_L1_ACCPT_LAT EP_L0S_ACCPT_LAT MAX_PL_SIZE_SUP
BA... AG... UP
Reset 1 0 0 0 1 1 1 1 1 1 0 0 0 0 0 1
Fields
Field Function
31-29 Reserved
28 Function-level reset (FLR) capability

FLR_CAP This field indicates whether the Function is capable of supporting FLR.
0b - The Function does not support FLR.
1b - The Function supports FLR.
27-26 Captured slot power limit scale

CSPLS See the PCIe base specification for a full description of this field.
25-18 Captured slot power limit value

CSPLV See the PCIe base specification for a full description of this field.
17-16 Reserved
15 Role-based error reporting

ROLE_BASED_ This is a standard PCIe field that always reads 1.
ERR_REPORT
1b - Role-based error reporting is implemented.
14-12 Reserved

NXP Semiconductors
PCIe Controller
Field Function
11-9 EP L1 acceptable latency

EP_L1_ACCPT This field indicates the acceptable total latency that an EP can withstand due to the transition from L1 state
_LAT to the L0 state. It is essentially an indirect measure of the EP's internal buffering.
Power management software uses the reported L1 acceptable latency number to compare against the L1
exit latencies reported by all components comprising the data path from this EP to the RC root port to
determine whether ASPM L1 entry can be used with no loss of performance.
000b - Maximum of 1 µs.
111b - No limit.
8-6 EP L0s acceptable latency

EP_L0S_ACCP This field indicates the acceptable total latency that an EP can withstand due to the transition from L0s state
T_LAT to the L0 state. It is essentially an indirect measure of the EP's internal buffering.
Power management software uses the reported L0s acceptable latency number to compare against the
L0s exit latencies reported by all components comprising the data path from this EP to the RC root port to
determine whether ASPM L0s entry can be used with no loss of performance.
000b - Maximum of 64 ns.
111b - No limit.
5 Extended Tag Field Supported

EXT_TAG_SUP Indicates the maximum supported size of the Tag field as a requester.
If you need to generate 8-bit Tag fields, you must enable this capability by programming
DEV_CONTROL_STATUS[EXT_TAG_EN] of the Requester function. Until you do this, the Requester
does not generate 8-bit Tag fields.

NXP Semiconductors
PCIe Controller
Field Function

0b - 5-bit Tag field supported.
1b - 8-bit Tag field supported.
4-3 Phantom Functions Supported

PHAN_FUNC_S See the PCIe base specification for a full description of this field.
UP
2-0 Max Payload Size Supported

MAX_PL_SIZE_ Indicates the maximum payload size that the Function can support for TLPs.
SUP
The Functions of a multi-Function device are allowed to report different values for this field.
000b - Max payload size is 128 bytes.
110b - Reserved
111b - Reserved
3.7.27 Device control and status (DEV_CONTROL_STATUS)
Offset
Register Offset
DEV_CONTROL_STATU 78h
S

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TRAN
R 0 APD URD FED NFED CED
S_P...
W W1C W1C W1C W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EN_N
R INITIA PHAN EXT_T EN_R
MAX_READ_REQ_SIZE O_S... APE MAX_PAYLOAD_SIZE URR FER NFER CER
T... TOM... AG... EL_...
W
Reset 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0
Fields
Field Function
31-22 Reserved
21 TP
TRANS_PENDI Transactions pending
NG
0b - All outstanding non-posted requests have completed, or the completion-timeout mechanism
has terminated these requests.
1b - The Function has issued non-posted requests that have not yet completed.
20 Aux power detected status

APD See the PCIe base specification for a full description of this field.
19 Unsupported request detected status

URD See the PCIe base specification for a full description of this field.
18 Fatal error detected status

FED See the PCIe base specification for a full description of this field.
17 Non-fatal error detected status

NFED See the PCIe base specification for a full description of this field.
16 Correctable error detected status

CED See the PCIe base specification for a full description of this field.
15 Initiate FLR
INITIATE_FLR Program INITIATE_FLR=1 to initiate an FLR for the Function.
INITIATE_FLR always reads 0.

NXP Semiconductors
PCIe Controller
Field Function
14-12 Max read request size

MAX_READ_R This field sets the maximum read request size for the Function as a requester.
EQ_SIZE
The Function must not generate read requests with a size exceeding the set value.
000b - Maximum read request size is 128 bytes.
11 Enable no snoop
EN_NO_SNOO See the PCIe base specification for a full description of this field.
P
10 Aux power PM enable

APE See the PCIe base specification for a full description of this field.
9 Phantom Functions enable
PHANTOM_FU 0b - The Function cannot use Phantom functions.

NC_EN 1b - The Function is allowed to use Phantom functions.
8 Extended Tag field enable
EXT_TAG_EN 0b - The Function is restricted to using a 5-bit Tag field.

1b - The Function is allowed to use an 8-bit Tag field.
7-5 Max payload size

MAX_PAYLOA This field sets the maximum TLP payload size for the Function.
D_SIZE
This field accepts values shown in DEV_CAPABILITIES[MAX_PL_SIZE_SUP].
4 Enable relaxed ordering

EN_REL_ORDE See the PCIe base specification for a full description of this field.
R
3 Unsupported request reporting enable

URR See the PCIe base specification for a full description of this field.
2 Fatal error reporting

FER See the PCIe base specification for a full description of this field.
1 Non-fatal error reporting enable

NXP Semiconductors
PCIe Controller
Field Function
NFER See the PCIe base specification for a full description of this field.
0 Correctable error reporting enable

CER See the PCIe base specification for a full description of this field.
3.7.28 Link Capabilities (LINK_CAPABILITIES)
Offset
Register Offset
LINK_CAPABILITIES 7Ch
Function
Identifies PCIe link-specific capabilities.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLOC L1_EXIT_LATE
R PORT_NUM 0 1 0
K_P... NCY
Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
L1_EXI ASPM_SUPPO
R L0S_EXIT_LATENCY MAX_LINK_WIDTH MAX_LINK_SPEED
T... RT
Reset 0 1 1 0 1 0 0 0 0 0 1 0 0 0 1 1
Fields
Field Function
31-24 Port number

PORT_NUM This field indicates the PCIe port number for the given PCIe link.
23 Reserved
22 Reserved

NXP Semiconductors
PCIe Controller
Field Function
21-19 Reserved
18 Clock power management

CLOCK_POWE See the PCIe base specification for a full description of this field.
R_MAN
17-15 L1 exit latency

L1_EXIT_LATE See the PCIe base specification for a full description of this field.
NCY
14-12 L0s exit latency

L0S_EXIT_LAT See the PCIe base specification for a full description of this field.
ENCY
11-10 Active State Power Management (ASPM) support

ASPM_SUPPO This field indicates the level of ASPM supported on the given PCIe link.
RT
00b - No ASPM support
01b - L0s supported
10b - L1 supported
11b - L0s and L1 supported
9-4 Maximum link width

MAX_LINK_WI This field indicates the maximum Link width (xN = corresponding to N lanes) implemented by
DTH the component.
00_0000b - Reserved
00_0001b - x1
00_0010b - x2
00_0100b - x4
00_1000b - x8
00_1100b - x12
01_0000b - x16
10_0000b - x32
3-0 Max link speed

MAX_LINK_SP This field indicates the maximum link speed of the associated port.
EED

NXP Semiconductors
PCIe Controller
Field Function
The encoded value specifies a bit location in the SUPPORTED_LINK_SPEED_VECTOR field in Link
capabilities 2 (LINK_CAPABILITIES_2) that corresponds to the maximum Link speed.
0001b - SUPPORTED_LINK_SPEED_VECTOR field bit 0
3.7.29 Link Control And Status (LINK_CONTROL_STATUS)
Offset
Register Offset
LINK_CONTROL_STAT 80h
US
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DLL_A SLOT_
R 0 0 NEGO_LINK_WIDTH LINK_SPEED
CT... CL...
Reset 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 HW_A EN_CL EXTE COMM 0 0 ASPM_CONTR

RCB
W UTO... K_... NDE... ON_... OL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-30 Reserved

NXP Semiconductors
PCIe Controller
Field Function
29 Data link layer active

DLL_ACTIVE See the PCIe base specification for a full description of this field.
28 Slot Clock Configuration

SLOT_CLK_CO See the PCIe base specification for a full description of this field.
NFIG
27-26 Reserved
25-20 Current link speed

NEGO_LINK_W This field indicates the negotiated width of the given PCIe link.
IDTH
This section shows the permitted field values. All other values are reserved.
The value in this field is undefined when the link is not up.
00_0001b - x1
00_0010b - x2
00_0100b - x4
00_1000b - x8
00_1100b - x12
01_0000b - x16
10_0000b - x32
19-16 Current link speed

LINK_SPEED This field indicates the negotiated link speed of the given PCIe link. The encoded value specifies a bit
location in LINK_CAPABILITIES_2[SUPPORT_LINK_SPEED_VECTOR] that corresponds to the current
link speed.
This section shows the permitted field values. All other values are reserved.
The value in this field is undefined when the link is not up.
0001b - SUPPORT_LINK_SPEED_VECTOR bit 0

NXP Semiconductors
PCIe Controller
Field Function
15-10 Reserved
9 Hardware autonomous width disable

HW_AUTO_WI See the PCIe base specification for a full description of this field.
DTH_DISABLE
8 Enable clock power management

EN_CLK_POW See the PCIe base specification for a full description of this field.
ER_MAN
7 Extended synch
EXTENDED_S See the PCIe base specification for a full description of this field.
YNCH
6 Common clock configuration

COMMON_CLK See the PCIe base specification for a full description of this field.
_CONFIG
5-4 Reserved
3 Read Completion Boundary (RCB)

RCB Indicates the RCB value of the root port upstream from the EP or bridge.
See the PCIe base specification for a full description of this field.
0b - 64 byte
1b - 128 byte
2 Reserved
1-0 Active State Power Management (ASPM) control

ASPM_CONTR See the PCIe base specification for a full description of this field.
OL
00b - Disabled
01b - L0s entry enabled
10b - L1 entry enabled
11b - L0s and L1 entry enabled

NXP Semiconductors
PCIe Controller
3.7.30 Device capabilities 2 (DEVICE_CAPABILITIES2_REG)
Offset
Register Offset
DEVICE_CAPABILITIES 94h
2_REG
Function
For a description of this standard PCIe register, see the PCI Express Specification.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCIE_CAP_OB PCIE_ PCIE_

R 0
FF_S... CA... CA...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCIE_CAP2_L PCIE_ PCIE_ PCIE_ PCIE_ PCIE_ PCIE_ PCIE_ PCIE_ PCIE_ PCIE_ PCIE_CAP_CPL_TIMEOUT_RAN
R
N_SY... CA... CA... CA... CA... CA... CA... CA... CA... CA... CA... GE
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1
Fields
Field Function
31-20 Reserved
19-18 (OBFF) Optimized Buffer Flush/fill Supported. For a description of this standard PCIe register field, see
the PCI Express Specification.
PCIE_CAP_OB
FF_SUPPORT
17 10-Bit Tag Requester Supported. For a description of this standard PCIe register field, see the PCI
Express Base Specification 4.0.
PCIE_CAP2_10
_BIT_TAG_RE
Q_SUPPORT
16 10-Bit Tag Completer Supported. For a description of this standard PCIe register field, see the PCI
PCIE_CAP2_10
_BIT_TAG_CO
MP_SUPPORT

NXP Semiconductors
PCIe Controller
Field Function
15-14 LN System CLS. For a description of this standard PCIe register field, see the PCI Express Specification.
Note: This register field is sticky.
PCIE_CAP2_LN
_SYS_CLS
13 TPH Completer Supported Bit 1. For a description of this standard PCIe register field, see the PCI
Express Specification.
PCIE_CAP_TP
H_CMPLT_SUP
PORT_1
PCIE_CAP_TP
H_CMPLT_SUP
PORT_0
11 LTR Mechanism Supported. For a description of this standard PCIe register field, see the PCI Express
Specification.
PCIE_CAP_LT
R_SUPP
10 No Relaxed Ordering Enabled PR-PR Passing. For a description of this standard PCIe register field, see
PCIE_CAP_NO
_RO_EN_PR2P
R_PAR
9 128 Bit CAS Completer Supported. For a description of this standard PCIe register field, see the PCI
PCIE_CAP_128
_CAS_CPL_SU
PP
8 64 Bit AtomicOp Completer Supported. For a description of this standard PCIe register field, see the PCI
PCIE_CAP_64_
ATOMIC_CPL_
SUPP
PCIE_CAP_32_
ATOMIC_CPL_
SUPP
6 Atomic Operation Routing Supported. For a description of this standard PCIe register field, see the PCI
PCIE_CAP_AT
OMIC_ROUTIN
G_SUPP
5 ARI Forwarding Supported. For a description of this standard PCIe register field, see the PCI Express
Specification.

NXP Semiconductors
PCIe Controller
Field Function
PCIE_CAP_ARI
_FORWARD_S
UPPORT
4 Completion Timeout Disable Supported. For a description of this standard PCIe register field, see the
PCI Express Specification.
PCIE_CAP_CP
L_TIMEOUT_DI
SABLE_SUPPO
RT
3-0 Completion Timeout Ranges Supported. For a description of this standard PCIe register field, see the
PCIE_CAP_CP
L_TIMEOUT_R
ANGE
3.7.31 Device control 2 and status 2 (DEVICE_CONTROL2_DEVICE_STATUS2_REG)
Offset
Register Offset
DEVICE_CONTROL2_D 98h
EVICE_STATUS2_REG
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCIE_
R 0 PCIE_ PCIE_CAP_CPL_TIMEOUT_VAL
CA...
CA... UE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-6 Reserved
5 ARI Forwarding Enable

PCIE_CAP_ARI For a description of this standard PCIe register field, see the PCI Express Specification.
_FORWARD_S
UPPORT_CS
4 Completion Timeout Disable

PCIE_CAP_CP Controls the completion-timeout mechanism.
L_TIMEOUT_DI
0b - Enable completion timeout
SABLE
1b - Disable completion timeout
3-0 Completion Timeout Value

PCIE_CAP_CP For a description of this standard PCIe register field, see the PCI Express Specification.
L_TIMEOUT_V
ALUE NOTE
The access attributes of this field are as follows: Wire: R/W
3.7.32 Link capabilities 2 (LINK_CAPABILITIES_2)
Offset
Register Offset
LINK_CAPABILITIES_2 9Ch
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CROS
R 0 SUPPORT_LINK_SPEED_VECTOR 0
SLI...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-9 Reserved
8 Crosslink supported
CROSSLINK_S See the PCIe base specification for a full description of this field.
UPPORTED
The meaning of CROSSLINK_SUPPORTED=0 depends on the port speed:
• On a port that supports Link speeds of 8.0 GT/s or higher, the value of 0 means the associated Port
does not support crosslinks.
• On a port that only supports Link speeds of 2.5 GT/s or 5.0 GT/s, the value of 0 provides no
information regarding the port's level of crosslink support.
0b - The meaning depends on the port speed as described above.
1b - The associated port supports crosslinks.
7-1 Support_Link_Speed_Vector
SUPPORT_LIN This field indicates the supported link speeds of the associated port. For each bit:
K_SPEED_VEC
• A value of 0 indicates that the corresponding link speed is not supported.
TOR
• A value of 1 indicates that the corresponding link speed is supported.
The bit definitions within this field are:
Bit 0: 2.5 GT/s
Bit 1: 5.0 GT/s
Bit 2: 8.0 GT/s
Bits 3-6: Reserved
0 Reserved
3.7.33 Link Control 2 And Status 2 (LINK_CONTROL2_LINK_STATUS2_REG)
Offset
Register Offset
LINK_CONTROL2_LINK A0h
_STATUS2_REG
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DRS_ DOWNSTREAM_COMP PCIE_ PCIE_ PCIE_ PCIE_ PCIE_ PCIE_

R 0
MES... O_PRESEN... CA... CA... CA... CA... CA... CA...
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCIE_
R PCIE_CAP_COMPLIANCE_PRES PCIE_ PCIE_ PCIE_ PCIE_ PCIE_CAP_TARGET_LINK_SPEE
PCIE_CAP_TX_MARGIN CA...
ET CA... CA... CA... CA... D
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Fields
Field Function
31 DRS Message Received

DRS_MESSAG For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.
E_RECEIVED
30-28 Downstream Component Presence

DOWNSTREA For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.
M_COMPO_PR
ESENCE
27-22 Reserved
21 Link Equalization Request 8.0GT/s

PCIE_CAP_LIN For a description of this standard PCIe register field, see the PCI Express Specification.
K_EQ_REQ
20 Equalization 8.0GT/s Phase 3 Successful

PCIE_CAP_EQ For a description of this standard PCIe register field, see the PCI Express Specification.
_CPL_P3

_CPL_P2

_CPL_P1

NXP Semiconductors
PCIe Controller
Field Function
17 Equalization 8.0GT/s Complete

_CPL
16 Current De-emphasis Level

PCIE_CAP_CU For a description of this standard PCIe register field, see the PCI Express Specification.
RR_DEEMPHA
In C-PCIe mode, its contents are derived by sampling the PIPE.
SIS
15-12 Sets Compliance Preset/De-emphasis for 5 GT/s and 8 GT/s

PCIE_CAP_CO For a description of this standard PCIe register field, see the PCI Express Specification.
MPLIANCE_PR
ESET
NOTE
11 Sets Compliance Skip Ordered Sets transmission.

PCIE_CAP_CO For a description of this standard PCIe register field, see the PCI Express Specification.
MPLIANCE_SO
S
NOTE
10 Enter Modified Compliance

PCIE_CAP_EN For a description of this standard PCIe register field, see the PCI Express Specification.
TER_MODIFIE
D_COMPLIANC
E NOTE
9-7 Controls Transmit Margin for Debug or Compliance

PCIE_CAP_TX_ For a description of this standard PCIe register field, see the PCI Express Specification.
MARGIN
6 Selectable De-emphasis For 5 GT/s

PCIE_CAP_SE For a description of this standard PCIe register field, see the PCI Express Specification.
L_DEEMPHASI
S
5 Hardware Autonomous Speed Disable

For a description of this standard PCIe register field, see the PCI Express Specification.

NXP Semiconductors
PCIe Controller
Field Function
PCIE_CAP_HW This field is sticky.

_AUTO_SPEED
_DISABLE NOTE
4 Enter Compliance Mode

PCIE_CAP_EN For a description of this standard PCIe register field, see the PCI Express Specification.
TER_COMPLIA
NCE
3-0 Target Link Speed

PCIE_CAP_TA For a description of this standard PCIe register field, see the PCI Express Specification.
RGET_LINK_S
PEED
3.7.34 MSI-X Capability ID, Next Pointer, Control (PCI_MSIX_CAP_ID_NEXT_CTRL_REG)
Offset
Register Offset
PCI_MSIX_CAP_ID_NEX B0h
T_CTRL_REG
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R PCI_M PCI_M 0 PCI_MSIX_TABLE_SIZE
W SI... SI...
Reset 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R PCI_MSIX_CAP_NEXT_OFFSET PCI_MSIX_CAP_ID
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1

NXP Semiconductors
PCIe Controller
Fields
Field Function
31 MSI-X Enable
PCI_MSIX_ENA For a description of this standard PCIe register field, see the PCI Express Specification.
BLE
30 Function Mask
PCI_MSIX_FUN For a description of this standard PCIe register field, see the PCI Express Specification. Note: The
CTION_MASK access attributes of this field are as follows: - Wire: R/W
29-27 Reserved
26-16 MSI-X Table Size

PCI_MSIX_TAB For a description of this standard PCIe register field, see the PCI Express Specification.
LE_SIZE
SRIOV Note: All VFs in a single PF have the same value for "MSI-X Table Size" (PCI_MSIX_TABLE_SIZE
field in VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG). To write this common value, you must perform a
DBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing
the PCI_MSIX_TABLE_SIZE field in the PF PCI_MSIX_CAP_ID_NEXT_CTRL_REG register.
The access attributes of this field are as follows:
- Wire: R (sticky)
15-8 MSI-X Next Capability Pointer

PCI_MSIX_CAP For a description of this standard PCIe register field, see the PCI Express Specification.
_NEXT_OFFSE
T
- Wire: R (sticky)
7-0 MSI-X Capability ID

_ID
3.7.35 MSI-X Table Offset And BIR (MSIX_TABLE_OFFSET_REG)
Offset
Register Offset
MSIX_TABLE_OFFSET_ B4h
REG

NXP Semiconductors
PCIe Controller
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R PCI_MSIX_TABLE_OFFSET
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R PCI_MSIX_TABLE_OFFSET PCI_MSIX_BIR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Fields
Field Function
MSI-X Table Offset. For a description of this standard PCIe register field, see the PCI Express
31-3
Specification. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note: This register
PCI_MSIX_TAB field is sticky.
LE_OFFSET
2-0MSI-X Table Bar Indicator Register Field. For a description of this standard PCIe register field, see the
PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note:
PCI_MSIX_BIR This register field is sticky.
3.7.36 MSI-X PBA Offset And BIR (MSIX_PBA_OFFSET_REG)
Offset
Register Offset
MSIX_PBA_OFFSET_R B8h
EG
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R PCI_MSIX_PBA_OFFSET
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R PCI_MSIX_PBA_OFFSET PCI_MSIX_PBA
Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0
Fields
Field Function
MSI-X PBA Offset. For a description of this standard PCIe register field, see the PCI Express
31-3
PCI_MSIX_PBA field is sticky.
_OFFSET
2-0 MSI-X PBA BIR. For a description of this standard PCIe register field, see the PCI Express Specification.
Note: The access attributes of this field are as follows: - Wire: R (sticky) Note: This register field is sticky.
PCI_MSIX_PBA
3.7.37 Advanced Error Reporting Extended Capability Header (AER_EXT_CAP_HDR_OFF)
Offset
Register Offset
AER_EXT_CAP_HDR_O 100h
FF
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R NEXT_OFFSET CAP_VERSION
Reset 0 0 0 1 0 1 0 0 1 0 0 0 0 0 1 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CAP_ID
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Fields
Field Function
Next Capability Offset. For a description of this standard PCIe register field, see the PCI Express
31-20
NEXT_OFFSET field is sticky.
Capability Version. For a description of this standard PCIe register field, see the PCI Express
19-16
CAP_VERSION field is sticky.
15-0 AER Extended Capability ID. For a description of this standard PCIe register field, see the PCI Express
CAP_ID field is sticky.
3.7.38 Uncorrectable error status (UNCORR_ERR_STATUS_OFF)
Offset
Register Offset
UNCORR_ERR_STATU 104h
S_OFF
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TLP_P INTER UNSU ECRC MALF_ REC_ UNEX

R 0 0 0
RF... NA... PPO... _ER... TL... OVE... P_C...
W W1C W1C W1C W1C W1C W1C W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPL CMPL FC_PR POIS_ SURP DL_PR

R 0 0
T_A... T_T... OT... TL... RIS... OT...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-26 Reserved
25 TLP Prefix Blocked Error Status. For a description of this standard PCIe register field, see the PCI
Express Specification. Note: Not supported.
TLP_PRFX_BL
OCKED_ERR_
STATUS
24-23 Reserved
22 Uncorrectable Internal Error Status

INTERNAL_ER For a description of this standard PCIe register field, see the PCI Express Specification. The controller
R_STATUS sets this bit when your application asserts app_err_bus[9]. It does not set this bit when it detects internal
uncorrectable internal errors such as parity and ECC failures. You should use the outputs from these
errors to drive the app_err_bus[9] input.
21 Reserved
20 Unsupported Request Error Status. For a description of this standard PCIe register field, see the PCI
UNSUPPORTE
D_REQ_ERR_S
TATUS
19 ECRC Error Status. For a description of this standard PCIe register field, see the PCI Express
Specification.
ECRC_ERR_ST
ATUS

NXP Semiconductors
PCIe Controller
Field Function
18 Malformed TLP Status. For a description of this standard PCIe register field, see the PCI Express
Specification.
MALF_TLP_ER
R_STATUS
17 Receiver Overflow Status. For a description of this standard PCIe register field, see the PCI Express
Specification.
REC_OVERFL
OW_ERR_STA
TUS
16 Unexpected Completion Status. For a description of this standard PCIe register field, see the PCI
UNEXP_CMPL
T_ERR_STATU
S
15 Completer Abort Status. For a description of this standard PCIe register field, see the PCI Express
Specification.
CMPLT_ABOR
T_ERR_STATU
S
14 Completion Timeout Status. For a description of this standard PCIe register field, see the PCI Express
Specification.
CMPLT_TIMEO
UT_ERR_STAT
US
13 Flow Control Protocol Error Status. For a description of this standard PCIe register field, see the PCI
FC_PROTOCO
L_ERR_STATU
S
12 Poisoned TLP Status. For a description of this standard PCIe register field, see the PCI Express
Specification.
POIS_TLP_ER
R_STATUS
11-6 Reserved
5 Surprise Down Error Status (Optional). For a description of this standard PCIe register field, see the PCI
SURPRISE_DO
WN_ERR_STA
TUS
4 Data Link Protocol Error Status. For a description of this standard PCIe register field, see the PCI

NXP Semiconductors
PCIe Controller
Field Function
DL_PROTOCO
L_ERR_STATU
S
3-0 Reserved
3.7.39 Uncorrectable error mask (UNCORR_ERR_MASK_OFF)
Offset
Register Offset
UNCORR_ERR_MASK_ 108h
OFF
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TLP_P ATOMI
R 0 0 INTER 0 UNSU ECRC MALF_ REC_ UNEX
RF... C_...
NA... PPO... _ER... TL... OVE... P_C...
W
Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SURP
R CMPL CMPL FC_PR POIS_ 0 DL_PR 0
RIS...
T_A... T_T... OT... TL... OT...
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-26 Reserved
25 TLP Prefix Blocked Error Mask. For a description of this standard PCIe register field, see the PCI
Express Specification. Note: Not supported. Note: The access attributes of this field are as follows: -
Wire: R/W (sticky) Note: This register field is sticky.

NXP Semiconductors
PCIe Controller
Field Function
TLP_PRFX_BL
OCKED_ERR_
MASK
24 AtomicOp Egress Block Mask (Optional). For a description of this standard PCIe register field, see the
PCI Express Specification. Note: This register field is sticky.
ATOMIC_EGRE
SS_BLOCKED_
ERR_MASK
23 Reserved
22 Uncorrectable Internal Error Mask (Optional). For a description of this standard PCIe register field, see
the PCI Express Specification. Note: This register field is sticky.
INTERNAL_ER
R_MASK
21 Reserved
20 Unsupported Request Error Mask. For a description of this standard PCIe register field, see the PCI
Express Specification. Note: This register field is sticky.
UNSUPPORTE
D_REQ_ERR_
MASK
19 ECRC Error Mask (Optional). For a description of this standard PCIe register field, see the PCI Express
Specification. Note: The access attributes of this field are as follows: - Wire: R/W (sticky) Note: This
ECRC_ERR_M register field is sticky.
ASK
18 Malformed TLP Mask. For a description of this standard PCIe register field, see the PCI Express
Specification. Note: This register field is sticky.
MALF_TLP_ER
R_MASK
17 Receiver Overflow Mask (Optional). For a description of this standard PCIe register field, see the PCI
REC_OVERFL
OW_ERR_MAS
K
16 Unexpected Completion Mask. For a description of this standard PCIe register field, see the PCI Express
UNEXP_CMPL
T_ERR_MASK
15 Completer Abort Error Mask (Optional). For a description of this standard PCIe register field, see the PCI
CMPLT_ABOR
T_ERR_MASK

NXP Semiconductors
PCIe Controller
Field Function
14 Completion Timeout Error Mask. For a description of this standard PCIe register field, see the PCI
CMPLT_TIMEO
UT_ERR_MAS
K
13 Flow Control Protocol Error Mask. For a description of this standard PCIe register field, see the PCI
FC_PROTOCO
L_ERR_MASK
12 Poisoned TLP Error Mask. For a description of this standard PCIe register field, see the PCI Express
POIS_TLP_ER
R_MASK
11-6 Reserved
5 Surprise Down Error Mask. For a description of this standard PCIe register field, see the PCI Express
SURPRISE_DO
WN_ERR_MAS
K
4 Data Link Protocol Error Mask. For a description of this standard PCIe register field, see the PCI Express
DL_PROTOCO
L_ERR_MASK
3-0 Reserved
3.7.40 Uncorrectable error severity (UNCORR_ERR_SEV_OFF)
Offset
Register Offset
UNCORR_ERR_SEV_O 10Ch
FF
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TLP_P ATOMI
RF... C_...
NA... PPO... _ER... TL... OVE... P_C...
W
Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SURP
RIS...
T_A... T_T... OT... TL... OT...
W
Reset 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0
Fields
Field Function
31-26 Reserved
TLP Prefix Blocked Error Severity (Optional). For a description of this standard PCIe register field, see
25
the PCI Express Specification. Note: Not supported. Note: The access attributes of this field are as
TLP_PRFX_BL follows: - Wire: R/W (sticky) Note: This register field is sticky.
OCKED_ERR_
SEVERITY
AtomicOp Egress Blocked Severity (Optional). For a description of this standard PCIe register field,
24
see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: R/W
ATOMIC_EGRE (sticky) Note: This register field is sticky.
SS_BLOCKED_
ERR_SEVERIT
Y
23 Reserved
22 Uncorrectable Internal Error Severity (Optional). For a description of this standard PCIe register field, see
INTERNAL_ER
R_SEVERITY
21 Reserved
20 Unsupported Request Error Severity. For a description of this standard PCIe register field, see the PCI
UNSUPPORTE
D_REQ_ERR_S
EVERITY

NXP Semiconductors
PCIe Controller
Field Function
19 ECRC Error Severity (Optional). For a description of this standard PCIe register field, see the PCI
Express Specification. Note: The access attributes of this field are as follows: - Wire: R/W (sticky) Note:
ECRC_ERR_S This register field is sticky.
EVERITY
18 Malformed TLP Severity. For a description of this standard PCIe register field, see the PCI Express
MALF_TLP_ER
R_SEVERITY
17 Receiver Overflow Error Severity (Optional). For a description of this standard PCIe register field, see the
REC_OVERFL
OW_ERR_SEV
ERITY
16 Unexpected Completion Error Severity. For a description of this standard PCIe register field, see the PCI
UNEXP_CMPL
T_ERR_SEVER
ITY
15 Completer Abort Error Severity (Optional). For a description of this standard PCIe register field, see the
CMPLT_ABOR
T_ERR_SEVER
ITY
14 Completion Timeout Error Severity. For a description of this standard PCIe register field, see the PCI
CMPLT_TIMEO
UT_ERR_SEVE
RITY
13 Flow Control Protocol Error Severity (Optional). For a description of this standard PCIe register field, see
FC_PROTOCO
L_ERR_SEVER
ITY
12 Poisoned TLP Severity. For a description of this standard PCIe register field, see the PCI Express
POIS_TLP_ER
R_SEVERITY
11-6 Reserved
5 Surprise Down Error Severity (Optional). For a description of this standard PCIe register field, see the
SURPRISE_DO
WN_ERR_SVRI
TY

NXP Semiconductors
PCIe Controller
Field Function
4 Data Link Protocol Error Severity. For a description of this standard PCIe register field, see the PCI
DL_PROTOCO
L_ERR_SEVER
ITY
3-0 Reserved
3.7.41 Correctable error status (CORR_ERR_STATUS_OFF)
Offset
Register Offset
CORR_ERR_STATUS_ 110h
OFF
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HEAD CORR ADVIS RPL_T REPL BAD_ BAD_T RX_E

R 0 0
ER_... ECT... OR... IM... AY_... DLL... LP... RR_...
W W1C W1C W1C W1C W1C W1C W1C W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-16 Reserved
15 Header Log Overflow Error Status (Optional). For a description of this standard PCIe register field, see

NXP Semiconductors
PCIe Controller
Field Function
HEADER_LOG
_OVERFLOW_
STATUS
14 Corrected Internal Error Status (Optional). For a description of this standard PCIe register field, see the
CORRECTED_I
NT_ERR_STAT
US
13 Advisory non-fatal error status

ADVISORY_NO For a description of this standard PCIe register field, see the PCI Express Specification.
N_FATAL_ERR
_STATUS
12 Replay Timer Timeout Status. For a description of this standard PCIe register field, see the PCI Express
Specification.
RPL_TIMER_TI
MEOUT_STAT
US
11-9 Reserved
8 REPLAY_NUM Rollover Status. For a description of this standard PCIe register field, see the PCI
REPLAY_NO_R
OLEOVER_ST
ATUS
7 Bad DLLP Status. For a description of this standard PCIe register field, see the PCI Express
Specification.
BAD_DLLP_ST
ATUS
6 Bad TLP Status. For a description of this standard PCIe register field, see the PCI Express Specification.
BAD_TLP_STA
TUS
5-1 Reserved
0 Receiver Error Status (Optional). For a description of this standard PCIe register field, see the PCI
RX_ERR_STAT
US

NXP Semiconductors
PCIe Controller
3.7.42 Correctable error mask (CORR_ERR_MASK_OFF)
Offset
Register Offset
CORR_ERR_MASK_OF 114h
F
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R HEAD CORR ADVIS RPL_T 0 REPL BAD_ BAD_T 0 RX_E
W ER_... ECT... OR... IM... AY_... DLL... LP... RR_...
Reset 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-16 Reserved
15 Header Log Overflow Error Mask (Optional). For a description of this standard PCIe register field, see
HEADER_LOG
_OVERFLOW_
MASK
14 Corrected Internal Error Mask (Optional). For a description of this standard PCIe register field, see the
CORRECTED_I
NT_ERR_MAS
K
13 Advisory Non-Fatal Error Mask. For a description of this standard PCIe register field, see the PCI
ADVISORY_NO
N_FATAL_ERR
_MASK

NXP Semiconductors
PCIe Controller
Field Function
12 Replay Timer Timeout Mask. For a description of this standard PCIe register field, see the PCI Express
RPL_TIMER_TI
MEOUT_MASK
11-9 Reserved
8 REPLAY_NUM Rollover Mask. For a description of this standard PCIe register field, see the PCI Express
REPLAY_NO_R
OLEOVER_MA
SK
7 Bad DLLP Mask. For a description of this standard PCIe register field, see the PCI Express
BAD_DLLP_MA
SK
6 Bad TLP Mask. For a description of this standard PCIe register field, see the PCI Express Specification.
BAD_TLP_MAS
K
5-1 Reserved
0 Receiver Error Mask (Optional). For a description of this standard PCIe register field, see the PCI
RX_ERR_MAS
K
3.7.43 Advanced error capabilities and control (ADV_ERR_CAP_CTRL_OFF)
Offset
Register Offset
ADV_ERR_CAP_CTRL_ 118h
OFF
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MULTI MULTI ECRC ECRC

R 0 ECRC ECRC FIRST_ERR_POINTER
PL... PL... _CH... _GE...
_CH... _GE...
W
Reset 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0
Fields
Field Function
31-11 Reserved
10 Multiple Header Recording Enable. For a description of this standard PCIe register field, see the PCI
MULTIPLE_HE
ADER_EN
9 Multiple Header Recording Capable. For a description of this standard PCIe register field, see the PCI
MULTIPLE_HE
ADER_CAP
8 ECRC Check Enable. For a description of this standard PCIe register field, see the PCI Express
ECRC_CHECK
_EN
7 ECRC Check Capable. For a description of this standard PCIe register field, see the PCI Express
ECRC_CHECK
_CAP
6 ECRC Generation Enable. For a description of this standard PCIe register field, see the PCI Express
ECRC_GEN_E
N
5 ECRC Generation Capable. For a description of this standard PCIe register field, see the PCI Express
ECRC_GEN_C
AP
4-0 First Error Pointer. For a description of this standard PCIe register field, see the PCI Express
FIRST_ERR_P
OINTER

NXP Semiconductors
PCIe Controller
3.7.44 Header Log Register 0. (HDR_LOG_0_OFF)
Offset
Register Offset
HDR_LOG_0_OFF 11Ch
Function
Header Log Register 0. For a description of this standard PCIe register, see the PCI Express Specification.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R FIRST_DWORD_FOURTH_BYTE FIRST_DWORD_THIRD_BYTE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R FIRST_DWORD_SECOND_BYTE FIRST_DWORD_FIRST_BYTE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-24 Byte 3 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register
field, see the PCI Express Specification. Note: This register field is sticky.
FIRST_DWOR
D_FOURTH_BY
TE
FIRST_DWOR
D_THIRD_BYT
E
FIRST_DWOR
D_SECOND_B
YTE
FIRST_DWOR
D_FIRST_BYTE

NXP Semiconductors
PCIe Controller
Offset
Register Offset
HDR_LOG_1_OFF 120h
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R SECOND_DWORD_FOURTH_BYTE SECOND_DWORD_THIRD_BYTE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R SECOND_DWORD_SECOND_BYTE SECOND_DWORD_FIRST_BYTE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-24 Byte 3 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe
register field, see the PCI Express Specification. Note: This register field is sticky.
SECOND_DWO
RD_FOURTH_
BYTE
SECOND_DWO
RD_THIRD_BY
TE
SECOND_DWO
RD_SECOND_
BYTE
SECOND_DWO
RD_FIRST_BY
TE

NXP Semiconductors
PCIe Controller
Offset
Register Offset
HDR_LOG_2_OFF 124h
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R THIRD_DWORD_FOURTH_BYTE THIRD_DWORD_THIRD_BYTE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R THIRD_DWORD_SECOND_BYTE THIRD_DWORD_FIRST_BYTE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-24 Byte 3 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register
THIRD_DWOR
D_FOURTH_BY
TE
THIRD_DWOR
D_THIRD_BYT
E
THIRD_DWOR
D_SECOND_B
YTE
THIRD_DWOR
D_FIRST_BYTE

NXP Semiconductors
PCIe Controller
Offset
Register Offset
HDR_LOG_3_OFF 128h
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R FOURTH_DWORD_FOURTH_BYTE FOURTH_DWORD_THIRD_BYTE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R FOURTH_DWORD_SECOND_BYTE FOURTH_DWORD_FIRST_BYTE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-24 Byte 3 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register
FOURTH_DWO
RD_FOURTH_
BYTE
FOURTH_DWO
RD_THIRD_BY
TE
FOURTH_DWO
RD_SECOND_
BYTE
FOURTH_DWO
RD_FIRST_BY
TE

NXP Semiconductors
PCIe Controller
3.7.48 TLP Prefix Log Register 1. (TLP_PREFIX_LOG_1_OFF)
Offset
Register Offset
TLP_PREFIX_LOG_1_O 138h
FF
Function
TLP Prefix Log Register 1. For a description of this standard PCIe register, see the PCI Express Specification.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R CFG_TLP_PFX_LOG_1_FOURTH_BYTE CFG_TLP_PFX_LOG_1_THIRD_BYTE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CFG_TLP_PFX_LOG_1_SECOND_BYTE CFG_TLP_PFX_LOG_1_FIRST_BYTE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-24 Byte 3 of Error TLP Prefix Log 1. For a description of this standard PCIe register field, see the PCI
CFG_TLP_PFX
_LOG_1_FOUR
TH_BYTE
CFG_TLP_PFX
_LOG_1_THIRD
_BYTE
CFG_TLP_PFX
_LOG_1_SECO
ND_BYTE
CFG_TLP_PFX
_LOG_1_FIRST
_BYTE

NXP Semiconductors
PCIe Controller
Offset
Register Offset
TLP_PREFIX_LOG_2_O 13Ch
FF
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-24 Byte 3 Error TLP Prefix Log 2. For a description of this standard PCIe register field, see the PCI Express
CFG_TLP_PFX
_LOG_2_FOUR
TH_BYTE
CFG_TLP_PFX
_LOG_2_THIRD
_BYTE
CFG_TLP_PFX
_LOG_2_SECO
ND_BYTE
CFG_TLP_PFX
_LOG_2_FIRST
_BYTE

NXP Semiconductors
PCIe Controller
Offset
Register Offset
FF
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
CFG_TLP_PFX
_LOG_3_FOUR
TH_BYTE
CFG_TLP_PFX
_LOG_3_THIRD
_BYTE
CFG_TLP_PFX
_LOG_3_SECO
ND_BYTE
CFG_TLP_PFX
_LOG_3_FIRST
_BYTE

NXP Semiconductors
PCIe Controller
Offset
Register Offset
FF
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
CFG_TLP_PFX
_LOG_4_FOUR
TH_BYTE
CFG_TLP_PFX
_LOG_4_THIRD
_BYTE
CFG_TLP_PFX
_LOG_4_SECO
ND_BYTE
CFG_TLP_PFX
_LOG_4_FIRST
_BYTE

NXP Semiconductors
PCIe Controller
3.7.52 SPCIE Capability Header. (SPCIE_CAP_HEADER_REG)
Offset
Register Offset
SPCIE_CAP_HEADER_ 148h
REG
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset 0 0 0 1 0 1 0 1 1 0 0 0 0 0 0 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R EXTENDED_CAP_ID
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1
Fields
Field Function
31-20
19-16
15-0 Secondary PCI Express Extended Capability ID. For a description of this standard PCIe register field,
see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: R
EXTENDED_C (sticky) Note: This register field is sticky.
AP_ID
3.7.53 Link control 3 (LINK_CONTROL3_REG)
Offset
Register Offset
LINK_CONTROL3_REG 14Ch

NXP Semiconductors
PCIe Controller
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EQ_R PERF
R 0
EQ_... ORM...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-2 Reserved
1 Link equalization request interrupt enable

EQ_REQ_INT_ For a description of this standard PCIe register field, see the PCI Express Specification.
EN
- Wire: RSVDP
0 Perform equalization
PERFORM_EQ For a description of this standard PCIe register field, see the PCI Express Specification.
- Wire: RSVDP
3.7.54 Lane error status (LANE_ERR_STATUS_REG)
Offset
Register Offset
LANE_ERR_STATUS_R 150h
EG
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LANE_ERR_ST
R 0
ATUS
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-2 Reserved
1-0 Lane Error Status Bits per Lane. For a description of this standard PCIe register field, see the PCI
LANE_ERR_ST
ATUS
3.7.55 Lane Equalization Control For Lanes 1 And 0 (SPCIE_CAP_OFF_0CH_REG)
Offset
Register Offset
SPCIE_CAP_OFF_0CH_ 154h
REG
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
USP_RX_PRESET_HINT DSP_RX_PRESET_HINT
R 0 USP_TX_PRESET1 0 DSP_TX_PRESET1
1 1
Reset 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0
Reset 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
Fields
Field Function
31 Reserved
30-28 Upstream port 8.0 GT/s receiver preset hint 1

USP_RX_PRES The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field
ET_HINT1 of LINK_CAPABILITIES2_REG.
27-24 Upstream port 8.0 GT/s transmitter preset 1

USP_TX_PRES The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field
ET1 of LINK_CAPABILITIES2_REG.
23 Reserved
22-20 Downstream port 8.0 GT/s receiver preset hint 1

DSP_RX_PRES For a description of this standard PCIe register field, see the PCI Express Specification.
ET_HINT1
19-16 Downstream port 8.0 GT/s transmitter preset 1

DSP_TX_PRES For a description of this standard PCIe register field, see the PCI Express Specification.
ET1
15 Reserved

NXP Semiconductors
PCIe Controller
Field Function
14-12 Upstream port 8.0 GT/s receiver preset hint 0

USP_RX_PRES The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field
ET_HINT0 of LINK_CAPABILITIES2_REG.
This register field is sticky.
11-8 Upstream port 8.0 GT/s transmitter preset 0

USP_TX_PRES The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field
ET0 of LINK_CAPABILITIES2_REG.
7 Reserved
6-4 Downstream port 8.0 GT/s receiver preset hint 0

DSP_RX_PRES For a description of this standard PCIe register field, see the PCI Express Specification.
ET_HINT0
3-0 Downstream port 8.0 GT/s transmitter preset 0

DSP_TX_PRES For a description of this standard PCIe register field, see the PCI Express Specification.
ET0
3.7.56 Vendor-Specific Extended Capability Header. (RAS_DES_CAP_HEADER_REG)
Offset
Register Offset
RAS_DES_CAP_HEADE 158h
R_REG
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R EXTENDED_CAP_ID
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1
Fields
Field Function
31-20
19-16
15-0 PCI Express Extended Capability ID. For a description of this standard PCIe register field, see the PCI
Express Specification. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note:
EXTENDED_C This register field is sticky.
AP_ID
3.7.57 Vendor-Specific Header. (VENDOR_SPECIFIC_HEADER_REG)
Offset
Register Offset
VENDOR_SPECIFIC_H 15Ch
EADER_REG
Function
Vendor-Specific Header. For a description of this standard PCIe register, see the PCI Express Specification.

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R VSEC_LENGTH VSEC_REV
Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VSEC_ID
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Fields
Field Function
31-20 VSEC Length. For a description of this standard PCIe register field, see the PCI Express Specification.
VSEC_LENGT
H
19-16 VSEC Rev. For a description of this standard PCIe register field, see the PCI Express Specification.
VSEC_REV
15-0 VSEC ID. For a description of this standard PCIe register field, see the PCI Express Specification.
VSEC_ID
3.7.58 Event Counter Control (EVENT_COUNTER_CONTROL_REG)
Offset
Register Offset
EVENT_COUNTER_CO 160h
NTROL_REG
Function
This is a viewport control register.
• Setting the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register
determine the Event Counter data returned by the EVENT_COUNTER_DATA_REG viewport register.
• Setting the EVENT_COUNTER_ENABLE field in this register enables the Event Counter selected by the
EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register.
• Setting the EVENT_COUNTER_CLEAR field in this register clears the Event Counter selected by the
• Reading the EVENT_COUNTER_STATUS field in this register returns the Enable status of the Event Counter selected by
the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register.

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
EVENT_COUNTER_EVENT_SELECT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EVEN
R 0 0
EVENT_COUNTER_LANE_SELE T_C...
CT EVENT_COUNTER_ENA EVENT_COUN
W
BLE TER_C...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-28 Reserved
27-16 Event Counter Data Select

EVENT_COUN This field in conjunction with the EVENT_COUNTER_LANE_SELECT field indexes the Event Counter data
TER_EVENT_S returned by the EVENT_COUNTER_DATA_REG register.
ELECT
- 27-24: Group number(4-bit: 0..0x7)
- 23-16: Event number(8-bit: 0..0x13) within the Group
For example:
- 0x000: Ebuf Overflow
- 0x001: Ebuf Underrun
- ..
- 0x700: Tx Memory Write
- 0x713: Rx Message TLP
For detailed definitions of Group number and Event number, see RAS Debug, Error Injection, and Statistics
(DES)†.
15-12 Reserved
Event Counter Lane Select. This field in conjunction with EVENT_COUNTER_EVENT_SELECT indexes
11-8
the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 0x0: Lane0 - 0x1:
EVENT_COUN Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note: This register field is sticky.
TER_LANE_SE
LECT

NXP Semiconductors
PCIe Controller
Field Function
Event Counter Status. This register returns the current value of the Event Counter selected by the
7
following fields: - EVENT_COUNTER_EVENT_SELECT - EVENT_COUNTER_LANE_SELECT Note:
EVENT_COUN This register field is sticky.
TER_STATUS
6-5 Reserved
Event Counter Enable. Enables/disables the Event Counter selected by the

4-2
EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. By
EVENT_COUN default, all event counters are disabled. You can enable/disable a specific Event Counter by writing the
TER_ENABLE 'per event off' or 'per event on' codes. You can enable/disable all event counters by writing the 'all on' or
'all off' codes. The read value is always '0'. - 000: no change - 001: per event off - 010: no change - 011:
per event on - 100: no change - 101: all off - 110: no change - 111: all on
Event Counter Clear. Clears the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT
1-0
and EVENT_COUNTER_LANE_SELECT fields in this register. You can clear the value of a specific
EVENT_COUN Event Counter by writing the 'per clear' code and you can clear all event counters at once by writing the
TER_CLEAR 'all clear' code. The read value is always '0'. - 00: no change - 01: per clear - 10: no change - 11: all clear
- Other: reserved
3.7.59 Event counter data (EVENT_COUNTER_DATA_REG)
Offset
Register Offset
EVENT_COUNTER_DA 164h
TA_REG
Function
This viewport register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in
EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG For
more details, see RAS Debug, Error Injection, and Statistics (DES)†.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R EVENT_COUNTER_DATA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
Event Counter Data. This register returns the data selected by the following
31-0
fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG -
EVENT_COUN EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG Note: This register field is
TER_DATA sticky.
3.7.60 Time-based Analysis Control (TIME_BASED_ANALYSIS_CONTROL_REG)
Offset
Register Offset
TIME_BASED_ANALYSI 168h
S_CONTROL_REG
Function
Controls the measurement of RX/TX data throughput and time spent in each low-power LTSSM state. For more details, see RAS
Debug, Error Injection, and Statistics (DES)†.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
TIME_BASED_REPORT_SELECT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 TIMER
TIME_BASED_DURATION_SELECT
W _S...
Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
Fields
Field Function
31-24 Time-based Report Select

TIME_BASED_ Selects what type of data is measured for the selected duration (TIME_BASED_DURATION_SELECT), and
REPORT_SELE returned in TIME_BASED_ANALYSIS_DATA.
CT
Each type of data is measured using one of three types of units:
• Core_clk cycles. Total time in ps is [Value of TIME_BASED_ANALYSIS_DATA returned when
TIME_BASED_REPORT_SELECT=0h] * TIME_BASED_ANALYSIS_DATA.

NXP Semiconductors
PCIe Controller
Field Function
• Aux_clk cycles. Total time in ps is [Period of platform specific clock] *

TIME_BASED_ANALYSIS_DATA.
• Data bytes. Actual amount of bytes is 16 * TIME_BASED_ANALYSIS_DATA.
0000_0000b - Duration of 1 Core_clk cycle
0000_0001b - TxL0s (measured in Core_clk cycles)
0000_0010b - RxL0s (measured in Core_clk cycles)
0000_0011b - L0 (measured in Core_clk cycles)
0000_0100b - L1 (measured in Core_clk cycles; reserved when aux_clk is supplied from the
platform specific clock during L1, L1.1 or L1.2)
0000_0101b - L1.1 (measured in Aux_clk cycles)
0010_0000b - Tx TLP data payload (measured in data bytes)
0010_0001b - Rx TLP data payload (measured in data bytes)
23-16 Reserved
15-8 Time-based Duration Select

TIME_BASED_ Selects the duration of time-based analysis.
DURATION_SE
If you require manual control, you must follow this procedure:
LECT
1. Select TIME_BASED_DURATION_SELECT=0b.
2. Start the analysis by writing 1b to PE0_GEN_CTRL_4[CFG_RAS_DES_TBA_CTRL].
3. Stop the analysis by writing 10b to PE0_GEN_CTRL_4[CFG_RAS_DES_TBA_CTRL].
0000_0000b - Manual control
0000_0001b - 1 ms
0000_0010b - 10 ms
0000_0011b - 100 ms
0000_0100b - 1 s
0000_0101b - 2 s
0000_0110b - 4 s
7-1 Reserved

NXP Semiconductors
PCIe Controller
Field Function
0 Timer Start
TIMER_START This field returns to 0 automatically when the measurement finishes.
The app_ras_des_tba_ctrl input also sets the contents of this field and controls the measurement start/stop.
This field has no effect when TIME_BASED_DURATION_SELECT=0b. Instead, use the procedure
described in TIME_BASED_DURATION_SELECT.
0b - Stop
1b - Start/restart
3.7.61 Time-Based Analysis Data (TIME_BASED_ANALYSIS_DATA_REG)
Offset
Register Offset
TIME_BASED_ANALYSI 16Ch
S_DATA_REG
Function
Contains the measurement results of RX/TX data throughput and time spent in each low-power LTSSM state.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R TIME_BASED_ANALYSIS_DATA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0
Fields
Field Function
31-0 Time-Based Analysis Data

NXP Semiconductors
PCIe Controller
Field Function
TIME_BASED_ Returns the data selected by

ANALYSIS_DA TIME_BASED_ANALYSIS_CONTROL_REG[TIME_BASED_REPORT_SELECT]. For more details, see
TA RAS Debug, Error Injection, and Statistics (DES)†.
This field contains the sum of previous and latest values of TBA event counters. To obtain only the latest
value, you must deduct the previous value from the current value of this field.
3.7.62 Error Injection Enable (EINJ_ENABLE_REG)
Offset
Register Offset
EINJ_ENABLE_REG 188h
Function
Each type of error insertion is enabled by the corresponding bit in this register. The specific injection controls for each type of error
are defined in the following registers:
• 0: CRC Error: EINJ0_CRC_REG
• 1: Sequence Number Error: EINJ1_SEQNUM_REG
• 2: DLLP Error: EINJ2_DLLP_REG
• 3: Symbol DataK Mask Error or Sync Header Error: EINJ3_SYMBOL_REG
• 4: FC Credit Update Error: EINJ4_FC_REG
• 5: TLP Duplicate/Nullify Error: EINJ5_SP_TLP_REG
• 6: Specific TLP Error: EINJ6_COMPARE_*_REG/EINJ6_CHANGE_*_REG/EINJ6_TLP_REG
After the errors have been inserted by controller, it will clear each bit here.
For more details, see RAS Debug, Error Injection, and Statistics (DES)†.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 Reserv ERRO ERRO ERRO ERRO ERRO ERRO
W ed R_I... R_I... R_I... R_I... R_I... R_I...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-7 Reserved
6 Reserved
5 Error Injection5 Enable (TLP Duplicate/Nullify Error). Enables insertion of duplicate/nullified TLPs. For
more details, see the EINJ5_SP_TLP_REG register. Note: This register field is sticky.
ERROR_INJEC
TION5_ENABL
E
4 Error Injection4 Enable (FC Credit Update Error). Enables insertion of errors into UpdateFCs. For more
details, see the EINJ4_FC_REG register. Note: This register field is sticky.
ERROR_INJEC
TION4_ENABL
E
3 Error Injection3 Enable (Symbol DataK Mask Error or Sync Header Error). Enables DataK masking of
special symbols or the breaking of the sync header. For more details, see the EINJ3_SYMBOL_REG
ERROR_INJEC register. Note: This register field is sticky.
TION3_ENABL
E
2 Error Injection2 Enable (DLLP Error). Enables insertion of DLLP errors. For more details, see the
EINJ2_DLLP_REG register. Note: This register field is sticky.
ERROR_INJEC
TION2_ENABL
E
1 Error Injection1 Enable (Sequence Number Error). Enables insertion of errors into sequence numbers.
For more details, see the EINJ1_SEQNUM_REG register. Note: This register field is sticky.
ERROR_INJEC
TION1_ENABL
E
0 Error Injection0 Enable (CRC Error). Enables insertion of errors into various CRC. For more details, see
the EINJ0_CRC_REG register. Note: This register field is sticky.
ERROR_INJEC
TION0_ENABL
E
3.7.63 Error Injection Control 0 (CRC Error). (EINJ0_CRC_REG)
Offset
Register Offset
EINJ0_CRC_REG 18Ch

NXP Semiconductors
PCIe Controller
Function
Error Injection Control 0 (CRC Error). Controls the insertion of errors into the CRC, and parity of ordered sets for the selected
type of the packets as follows: - LCRC. Bad TLP will be detected at the receiver side; receiver responds with NAK DLLP;
Data Link Retry starts. - 16-bit CRC of ACK/NAK DLLPs. Bad DLLP occurs at the receiver side; Replay NUM Rollover occurs.
- 16-bit CRC of UpdateFC DLLPs. Error insertion continues for the specific time; LTSSM transitions to the Recovery state
because of the UpdateFC timeout (if the timeout is implemented at the receiver of the UpdateFCs). - ECRC. If ECRC check
is enabled, ECRC error is detected at the receiver side. - FCRC. Framing error will be detected, TLP is discarded, and
the LTSSM transitions to Recovery state. - Parity of TSOS. Error insertion continues for the specific time; LTSSM Recovery/
Configuration timeout will occur. - Parity of SKPOS. Lane error will be detected at the receiver side.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
EINJ0_CRC_TYPE EINJ0_COUNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-12 Reserved
Error injection type. Selects the type of CRC error to be inserted. Tx Path - 0000b: New TLP's LCRC
11-8
error injection - 0001b: 16bCRC error injection of ACK/NAK DLLP - 0010b: 16bCRC error injection of
EINJ0_CRC_TY Update-FC DLLP - 0011b: New TLP's ECRC error injection - 0100b: TLP's FCRC error injection (128b/
PE 130b) - 0101b: Parity error of TSOS (128b/130b) - 0110b: Parity error of SKPOS (128b/130b) Rx Path -
1000b: LCRC error injection - 1011b: ECRC error injection - Others: Reserved Note: This register field is
sticky.
Error injection count. Indicates the number of errors. This register is decremented when the errors have
7-0
been inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION0_ENABLE in
EINJ0_COUNT EINJ_ENABLE_REG returns 0b. - If the counter value is 0x00 and ERROR_INJECTION0_ENABLE=1,
the errors are inserted until ERROR_INJECTION0_ENABLE is set to '0'. Note: This register field is sticky.
3.7.64 Error Injection Control 1 (Sequence Number Error) (EINJ1_SEQNUM_REG)
Offset
Register Offset
EINJ1_SEQNUM_REG 190h

NXP Semiconductors
PCIe Controller
Function
Controls the sequence number of the specific TLPs and ACK/NAK DLLPs. Data Link Protocol Error will be detected at the Rx
side of ACK/NAL DLLPs when one of these conditions is true: - ((NEXT_TRANSMIT_SEQ -1) - AckNak_Seq_Num) mod 4096
> 2048 - (AckNak_Seq_Num - ACKD_SEQ) mod 4096 >= 2048 TLP is treated as Duplicate TLP at the Rx side when all these
conditions are true: - Sequence Number != NEXT_RCV_SEQ - (NEXT_RCV_SEQ - Sequence Number) mod 4096 <= 2048
TLP is treated as Bad TLP at the Rx side when all these conditions are true: - Sequence Number != NEXT_RCV_SEQ and -
(NEXT_RCV_SEQ - Sequence Number) mod 4096 > 2048
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
EINJ1_BAD_SEQNUM
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 EINJ1_
EINJ1_COUNT
W S...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-29 Reserved
28-16Bad sequence number. Indicates the value to add/subtract from the naturally-assigned sequence
numbers. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1
EINJ1_BAD_SE - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 - .. - 0x1001: -4095 For example: - Set Type, SEQ# and Count --
QNUM EINJ1_SEQNUM_TYPE =0 (Insert errors into new TLPs) -- EINJ1_BAD_SEQNUM =0x1FFD (represents
-3) -- EINJ1_COUNT =1 - Enable Error Injection -- ERROR_INJECTION1_ENABLE =1 - Send a TLP
From the Core's Application Interface -- Assume SEQ#5 is given to the TLP. - The SEQ# is Changed to
#2 by the Error Injection Function in Layer2. -- 5 + (-3) = 2 - The TLP with SEQ#2 is Transmitted to PCIe
Link. Note: This register field is sticky.
15-9 Reserved
8 Sequence number type. Selects the type of sequence number. - 0b: Insertion of New TLP's SEQ# error -
1b: Insertion of ACK/NAK DLLP's SEQ# Error Note: This register field is sticky.
EINJ1_SEQNU
M_TYPE
Error injection count. Indicates the number of errors. This register is decremented as the errors are
7-0
being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION1_ENABLE in
EINJ1_COUNT EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION1_ENABLE=1,

NXP Semiconductors
PCIe Controller
3.7.65 Error Injection Control 2 (DLLP Error). (EINJ2_DLLP_REG)
Offset
Register Offset
EINJ2_DLLP_REG 194h
Function
Error Injection Control 2 (DLLP Error). Controls the transmission of DLLPs and inserts the following errors: - If "ACK/NAK
DLLP's transmission block" is selected, replay timeout error will occur at the transmitter of the TLPs and then Data Link Retry
will occur. - If "Update FC DLLP's transmission block" is selected, LTSSM will transition to the Recovery state because of the
UpdateFC timeout (if the timeout is implemented at the receiver of the UpdateFCs). - If "Always Transmission for NAK DLLP"
is selected, Data Link Retry will occur at the transmitter of the TLPs. Furthermore, Replay NUM Rollover will occur when the
transmitter has been requested four times to send the TLP with the same sequence number.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 EINJ2_DLLP_T
EINJ2_COUNT
W YPE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-10 Reserved
9-8DLLP Type. Selects the type of DLLP errors to be inserted. - 00b: ACK/NAK DLLP's transmission block
- 01b: Update FC DLLP's transmission block - 10b: Always Transmission for NAK DLLP - 11b: Reserved
EINJ2_DLLP_T Note: This register field is sticky.
YPE
7-0
being inserted. - If the counter value is 0x01 and the error is inserted, ERROR_INJECTION2_ENABLE
EINJ2_COUNT in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION2_ENABLE =1,
the errors are inserted until ERROR_INJECTION2_ENABLE is set to '0'. This register is affected only
when EINJ2_DLLP_TYPE =2'10b. Note: This register field is sticky.

NXP Semiconductors
PCIe Controller
3.7.66 Error Injection Control 3 (Symbol Error) (EINJ3_SYMBOL_REG)
Offset
Register Offset
EINJ3_SYMBOL_REG 198h
Function
When 8b/10b encoding is used, this register controls error insertion into the special (K code) symbols.
• If TS1/TS2/FTS/E-Idle/SKP is selected, it affects whole of the ordered set. It might cause timeout of the LTSSM.
• If END/EDB/STP/SDP is selected, TLP/DLLP will be discarded at the receiver side.
When 128b/130b encoding is used, this register controls error insertion into the sync-header.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
EINJ3_SYMBOL_TYPE EINJ3_COUNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-11 Reserved
10-8 Error Type

EINJ3_SYMBO • 8b/10b encoding - Mask K symbol.
L_TYPE
— 000b: Reserved
— 001b: COM/PAD(TS1 Order set)
— 011b: COM/FTS(FTS Order set)
— 100b: COM/IDL(E-Idle Order set)
— 101b: END/EDB Symbol

NXP Semiconductors
PCIe Controller
Field Function
— 110b: STP/SDP Symbol

— 111b: COM/SKP(SKP Order set)
• 128b/130b encoding - Change sync header.
— 000b: Invert sync header
— Others: Reserved
7-0 Error Injection Count

EINJ3_COUNT Indicates the number of errors.
This register is decremented as the errors are being inserted.
• If the counter value is 0x01 and error is inserted, ERROR_INJECTION3_ENABLE in
EINJ_ENABLE_REG returns '0'.
• If the counter value is 0x00 and ERROR_INJECTION3_ENABLE =1, the errors are inserted until
ERROR_INJECTION3_ENABLE is set to '0'.
3.7.67 Error Injection Control 4 (FC Credit Error). (EINJ4_FC_REG)
Offset
Register Offset
EINJ4_FC_REG 19Ch
Function
Error Injection Control 4 (FC Credit Error). Controls error insertion into the credit value in the UpdateFCs. It is possible to insert
errors for any of the following types: - Posted TLP Header credit - Non-Posted TLP Header credit - Completion TLP Header
credit - Posted TLP Data credit - Non-Posted TLP Data credit - Completion TLP Data credit These errors are not correctable
while error insertion is enabled. Receiver buffer overflow error might occur.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
EINJ4_BAD_UPDFC_VALUE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0
EINJ4_VC_NUMBER EINJ4_UPDFC_TYPE EINJ4_COUNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-29 Reserved
28-16Bad update-FC credit value. Indicates the value to add/subtract from the UpdateFC credit. This value is
represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF:
EINJ4_BAD_UP -1 - 0x1FFE: -2 - .. - 0x1001: -4095 Note: This register field is sticky.
DFC_VALUE
15 Reserved
14-12 VC Number. Indicates target VC Number. Note: This register field is sticky.
EINJ4_VC_NU
MBER
11 Reserved
10-8 Update-FC type. Selects the credit type. - 000b: Posted TLP Header Credit value control - 001b:
Non-Posted TLP Header Credit value control - 010b: Completion TLP Header Credit value control -
EINJ4_UPDFC_ 011b: Reserved - 100b: Posted TLP Data Credit value control - 101b: Non-Posted TLP Data Credit value
TYPE control - 110b: Completion TLP Data Credit value control - 111b: Reserved Note: This register field is
sticky.
7-0Error injection count. Indicates the number of errors. This register is decremented as the errors are
EINJ4_COUNT EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION4_ENABLE =1,
3.7.68 Error Injection Control 5 (Specific TLP Error). (EINJ5_SP_TLP_REG)
Offset
Register Offset
EINJ5_SP_TLP_REG 1A0h
Function
Error Injection Control 5 (Specific TLP Error). Controls the generation of specified TLPs. Correctable errors will occur which
will be fixed by the PCIe protocol. - For Duplicate TLP, the controller initiates Data Link Retry by handling ACK DLLP as NAK
DLLP. These TLPs will be duplicate TLPs at the receiver side. - For Nullified TLP, the TLPs that the controller transmits are
changed into nullified TLPs and the original TLPs are stored in the retry buffer. The receiver of these TLPs will detect the lack
of seq# and send NAK DLLP at the next TLP. Then the original TLPs are sent from retry buffer and the data controls are
recovered. For 128 bit controller or more than 128 bit, the controller inserts errors the number of times of EINJ5_COUNT but
doesn't ensure that the errors are continuously inserted into TLPs.

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 EINJ5_
EINJ5_COUNT
W S...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-9 Reserved
8 Specified TLP. Selects the specified TLP to be inserted. - 0: Generates duplicate TLPs by handling ACK
DLLP as NAK DLLP. - 1: Generates Nullified TLP (Original TLP will be stored in retry buffer). Note: This
EINJ5_SPECIFI register field is sticky.
ED_TLP
7-0
3.7.69 Error Injection Control 6 (Compare Point Header DWORD #0).

Offset
Register Offset
EINJ6_COMPARE_POIN 1A4h
T_H0_REG
Function
Error Injection Control 6 (Compare Point Header DWORD #0). Program this register for the 1st DWORD of TLP header/
prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW0[7:0],
TLP_DW0[15:8], TLP_DW0[23:16], TLP_DW0[31:24] The Packet Compare Point registers (EINJ6_COMPARE_POINT*)
specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers
(EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the
controller inserts errors into the TLP. The type and number of errors are specified by the EINJ6_TLP_REG register.

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
EINJ6_COMPARE_POINT_H0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
Packet Compare Point: 1st DWORD. Specifies which Tx TLP header DWORD#0 bits to compare with
31-0
the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all
EINJ6_COMPA specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors
RE_POINT_H0 into the TLP. Note: This register field is sticky.

Offset
Register Offset
T_H1_REG
Function
Error Injection Control 6 (Compare Point Header DWORD #1). Program this register for the 2nd DWORD of TLP header/

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
Packet Compare Point: 2nd DWORD. Specifies which Tx TLP header DWORD#1 bits to compare with
31-0

Offset
Register Offset
EINJ6_COMPARE_POIN 1ACh
T_H2_REG
Function
Error Injection Control 6 (Compare Point Header DWORD #2). Program this register for the 3rd DWORD of TLP header/

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
Packet Compare Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to compare with
31-0

Offset
Register Offset
EINJ6_COMPARE_POIN 1B0h
T_H3_REG
Function
Error Injection Control 6 (Compare Point Header DWORD #3). Program this register for the 4th DWORD of TLP header/

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
Packet Compare Point: 4th DWORD. Specifies which Tx TLP header DWORD#3 bits to compare with
31-0
3.7.73 Error Injection Control 6 (Compare Value Header DWORD #0).

Offset
Register Offset
EINJ6_COMPARE_VAL 1B4h
UE_H0_REG
Function
Error Injection Control 6 (Compare Value Header DWORD #0). Program this register for the 1st DWORD of TLP header/

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
EINJ6_COMPARE_VALUE_H0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
Packet Compare Value: 1st DWORD. Specifies the value to compare against Tx the TLP header
31-0
DWORD#0 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note:
EINJ6_COMPA This register field is sticky.
RE_VALUE_H0

Offset
Register Offset
UE_H1_REG
Function
Error Injection Control 6 (Compare Value Header DWORD #1). Program this register for the 2nd DWORD of TLP header/

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
Packet Compare Value: 2nd DWORD. Specifies the value to compare against Tx the TLP header
31-0
RE_VALUE_H1

Offset
Register Offset
EINJ6_COMPARE_VAL 1BCh
UE_H2_REG
Function
Error Injection Control 6 (Compare Value Header DWORD #2). Program this register for the 3rd DWORD of TLP header/

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
Packet Compare Value: 3rd DWORD. Specifies the value to compare against Tx the TLP header
31-0
RE_VALUE_H2

Offset
Register Offset
EINJ6_COMPARE_VAL 1C0h
UE_H3_REG
Function
Error Injection Control 6 (Compare Value Header DWORD #3). Program this register for the 4th DWORD of TLP header/

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
Packet Compare Value: 4th DWORD. Specifies the value to compare against Tx the TLP header
31-0
RE_VALUE_H3
3.7.77 Error Injection Control 6 (Change Point Header DWORD #0).

Offset
Register Offset
EINJ6_CHANGE_POINT 1C4h
_H0_REG
Function
Error Injection Control 6 (Change Point Header DWORD #0). Program this register for the 1st DWORD of TLP header/
TLP_DW0[15:8], TLP_DW0[23:16], TLP_DW0[31:24] The Packet Change Point registers (EINJ6_CHANGE_POINT*)
specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers
(EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register. Only applies
when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
EINJ6_CHANGE_POINT_H0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
Packet Change Point: 1st DWORD. Specifies which Tx TLP header DWORD#0 bits to replace with the
31-0
corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register
EINJ6_CHANG field is sticky.
E_POINT_H0

Offset
Register Offset
_H1_REG
Function
Error Injection Control 6 (Change Point Header DWORD #1). Program this register for the 2nd DWORD of TLP header/

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
Packet Change Point: 2nd DWORD. Specifies which Tx TLP header DWORD#1 bits to replace with the
31-0
E_POINT_H1

Offset
Register Offset
EINJ6_CHANGE_POINT 1CCh
_H2_REG
Function
Error Injection Control 6 (Change Point Header DWORD #2). Program this register for the 3rd DWORD of TLP header/

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
Packet Change Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to replace with the
31-0
E_POINT_H2

Offset
Register Offset
EINJ6_CHANGE_POINT 1D0h
_H3_REG
Function
Error Injection Control 6 (Change Point Header DWORD #3). Program this register for the 4th DWORD of TLP header/

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
Packet Change Point: 4th DWORD. Specifies which Tx TLP header DWORD#3 bits to replace with the
31-0
E_POINT_H3
3.7.81 Error Injection Control 6 (Change Value Header DWORD #0).

Offset
Register Offset
EINJ6_CHANGE_VALU 1D4h
E_H0_REG
Function
Error Injection Control 6 (Change Value Header DWORD #0). Program this register for the 1st DWORD of TLP header/

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
EINJ6_CHANGE_VALUE_H0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
Packet Change Value: 1st DWORD. Specifies replacement values for the Tx TLP header DWORD#0
31-0
bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the
EINJ6_CHANG EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG is '0'. Note: This register field is sticky.
E_VALUE_H0

Offset
Register Offset
E_H1_REG
Function
Error Injection Control 6 (Change Value Header DWORD #1). Program this register for the 2nd DWORD of TLP header/

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
Packet Change Value: 2nd DWORD. Specifies replacement values for the Tx TLP header DWORD#1
31-0
E_VALUE_H1

Offset
Register Offset
EINJ6_CHANGE_VALU 1DCh
E_H2_REG
Function
Error Injection Control 6 (Change Value Header DWORD #2). Program this register for the 3rd DWORD of TLP header/

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
Packet Change Value: 3rd DWORD. Specifies replacement values for the Tx TLP header DWORD#2
31-0
E_VALUE_H2

Offset
Register Offset
EINJ6_CHANGE_VALU 1E0h
E_H3_REG
Function
Error Injection Control 6 (Change Value Header DWORD #3). Program this register for the 4th DWORD of TLP header/

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
Packet Change Value: 4th DWORD. Specifies replacement values for the Tx TLP header DWORD#3
31-0
E_VALUE_H3
3.7.85 Error Injection Control 6 (Packet Error). (EINJ6_TLP_REG)
Offset
Register Offset
EINJ6_TLP_REG 1E4h
Function
Error Injection Control 6 (Packet Error). The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx
TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).
When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors
into the TLP. The type and number of errors are specified by the this register. The Packet Change Point registers
(EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change
Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the this register. Only applies
when EINJ6_INVERTED_CONTROL in this register =0. The TLP into that errors are injected will not arrive at the transaction
layer of the remote device when all of the following conditions are true. - Using 128b/130b encoding - Injecting errors into TLP
Length field / TLP digest bit

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 EINJ6_
EINJ6_PACKET_TYPE EINJ6_COUNT
W I...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-12 Reserved
11-9 Packet type. Selects the TLP packets to inject errors into. - 0: TLP Header - 1: TLP Prefix 1st
4-DWORDs - 2: TLP Prefix 2nd -DWORDs - Else: Reserved Note: This register field is sticky.
EINJ6_PACKET
_TYPE
8 Inverted Error Injection Control. - 0: EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace bits specified

by EINJ6_CHANGE_POINT_H[0/1/2/3]. - 1: EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and inverts
EINJ6_INVERT bits specified by EINJ6_CHANGE_POINT_H[0/1/2/3]. Note: This register field is sticky.
ED_CONTROL
Error Injection Count. Indicates the number of errors to insert. This counter is decremented while errors
7-0
are been inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION6_ENABLE
EINJ6_COUNT in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION6_ENABLE=1,
errors are inserted until ERROR_INJECTION6_ENABLE is set to '0'. Note: This register field is sticky.
3.7.86 Silicon Debug Control 1 (SD_CONTROL1_REG)
Offset
Register Offset
SD_CONTROL1_REG 1F8h
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 LOW_POWER_ 0 FORC
TX_EIOS_NUM
W INTER... E_D...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
FORCE_DETECT_LANE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-24 Reserved
Low Power Entry Interval Time. Interval Time that the controller starts monitoring RXELECIDLE signal
23-22
after L0s/L1/L2 entry. You should set the value according to the latency from receiving EIOS to,
LOW_POWER_ RXELECIDLE assertion at the PHY. - 0x0: 40ns - 0x1: 160ns - 0x2: 320ns - 0x3: 640ns Note: This
INTERVAL register field is sticky.
Number of Tx EIOS. This register sets the number of transmit EIOS for L0s/L1 entry and Disable/
21-20
Loopback/Hot-reset exit. The controller selects the greater value between this register and the value
TX_EIOS_NUM defined by the PCI-SIG specification. 2.5GT/s, 8.0GT/s or higher: - 0x0: 1 - 0x1: 4 - 0x2: 8 - 0x3: 16
5.0GT/s: - 0x0: 2 - 0x1: 8 - 0x2: 16 - 0x3: 32 Note: This register field is sticky.
19-17 Reserved
16 Force Detect Lane Enable. When this bit is set, the controller ignores receiver detection from PHY during
LTSSM Detect state and uses FORCE_DETECT_LANE. Note: This register field is sticky.
FORCE_DETE
CT_LANE_EN
15-0 Force Detect Lane. When the FORCE_DETECT_LANE_EN field is set, the controller ignores receiver
detection from PHY during LTSSM Detect state and uses this value instead. - 0: Lane0 - 1: Lane1 - 2:
FORCE_DETE Lane2 - .. - 15: Lane15 Note: This register field is sticky.
CT_LANE
Offset
Register Offset
SD_CONTROL2_REG 1FCh

NXP Semiconductors
PCIe Controller
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 FRAMI
W NG...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0
DIREC DIREC DIREC NOAC HOLD
T_... T_... T_... K_F... RECO _LT...
W
VER...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-17 Reserved
16 Framing Error Recovery Disable. This bit disables a transition to Recovery state when a Framing Error is
occurred. Note: This register field is sticky.
FRAMING_ERR
_RECOVERY_
DISABLE
15-11 Reserved
10 Direct Loopback Slave To Exit. When this bit is set and the LTSSM is in Loopback Slave Active State,
the LTSSM transitions to Loopback Slave Exit state. Note: This register field is sticky.
DIRECT_LPBK
SLV_TO_EXIT
9 Direct Polling.Compliance to Detect. When this bit is set and the LTSSM is in Polling Compliance State,
the LTSSM transitions to Detect state. Note: This register field is sticky.
DIRECT_POLC
OMP_TO_DET
ECT
8 Direct Recovery.Idle to Configuration. When this bit is set and the LTSSM is in Recovery Idle State, the
LTSSM transitions to Configuration state. Note: This register field is sticky.
DIRECT_RECI
DLE_TO_CONF
IG
7-3 Reserved

NXP Semiconductors
PCIe Controller
Field Function
2 Force LinkDown. When this bit is set and the controller detects REPLY_NUM rolling over 4 times, the
LTSSM transitions to Detect State. Note: This register field is sticky.
NOACK_FORC
E_LINKDOWN
1 Recovery Request. When this bit is set to '1' in L0 or L0s, the LTSSM starts transitioning to Recovery
State. This request does not cause a speed change or re-equalization.
RECOVERY_R
EQUEST
0 Hold and Release LTSSM. For as long as this register is '1', the controller stays in the current LTSSM.
HOLD_LTSSM
3.7.88 Silicon Debug Status (Layer1 Per-lane) (SD_STATUS_L1LANE_REG)
Offset
Register Offset
SD_STATUS_L1LANE_ 208h
REG
Function
This viewport register returns the data selected by the following field: - LANE_SELECT in SD_STATUS_L1LANE_REG For
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PIPE_ PIPE_ PIPE_ PIPE_ PIPE_

R DESKEW_POINTER 0
TX... RX... RX... DE... RX...
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
LANE_SELECT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-24 Deskew Pointer. Indicates Deskew pointer of internal Deskew buffer of selected lane
number(LANE_SELECT). Note: This register field is sticky.
DESKEW_POI
NTER
23-21 Reserved
20 PIPE:TxElecIdle. Indicates PIPE TXELECIDLE signal of selected lane number(LANE_SELECT). Note:

PIPE_TXELECI
DLE
19 PIPE:RxElecIdle. Indicates PIPE RXELECIDLE signal of selected lane number(LANE_SELECT). Note:

PIPE_RXELECI
DLE
18 PIPE:RxValid. Indicates PIPE RXVALID signal of selected lane number(LANE_SELECT). Note: This
register field is sticky.
PIPE_RXVALID
17 PIPE:Detect Lane. Indicates whether PHY indicates receiver detection or not on selected lane
PIPE_DETECT
_LANE
16 PIPE:RxPolarity. Indicates PIPE RXPOLARITY signal of selected lane number(LANE_SELECT). Note:

PIPE_RXPOLA
RITY
15-4 Reserved
3-0 Lane Select. Lane Select register for Silicon Debug Status Register of Layer1-PerLane. - 0x0: Lane0 -
0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note: This register field is sticky.
LANE_SELECT
3.7.89 Silicon Debug Status (Layer1 LTSSM) (SD_STATUS_L1LTSSM_REG)
Offset
Register Offset
SD_STATUS_L1LTSSM 20Ch
_REG
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R LTSSM_VARIABLE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LANE_ FRAMI
R 0 PIPE_POWER_DOWN FRAMING_ERR_PTR
RE... NG...
W W1C
Reset 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
Fields
Field Function
LTSSM Variable. Indicates internal LTSSM variables defined in the PCI Express Base
31-16
Specification. C-PCIe Mode: - 0: directed_speed_change - 1: changed_speed_recovery
LTSSM_VARIA - 2: successful_speed_negotiation - 3: upconfigure_capable; Set to '1' if both
BLE ports advertised the UpConfigure capability in the last Config.Complete. - 4:
select_deemphasis - 5: start_equalization_w_preset - 6: equalization_done_8GT_data_rate - 7:
equalization_done_16GT_data_rate - 15:8: idle_to_rlock_transitioned Note: This register field is sticky.
15 Lane Reversal Operation. Receiver detected lane reversal. This field is only valid in the L0 LTSSM state.
LANE_REVERS
AL
14-11 Reserved
10-8 PIPE:PowerDown. Indicates PIPE PowerDown signal. Note: This register field is sticky.
PIPE_POWER_
DOWN
7 Framing Error. Indicates Framing Error detection status.
FRAMING_ERR
6-0 First Framing Error Pointer

FRAMING_ERR Identifies the first Framing Error using the following encoding. The field contents are only valid value when
_PTR FRAMING_ERR =1.
• Received Unexpected Framing Token
— 01h: When non- STP/SDP/IDL Token was received and it was not in TLP/DLLP reception
— 02h: When current token was not a valid EDB token and previous token was an EDB. (128/256
bit controller only)

NXP Semiconductors
PCIe Controller
Field Function
— 03h: When SDP token was received but not expected. (128 bit & (x8 | x16) controller only)
— 04h: When STP token was received but not expected. (128 bit & (x8 | x16) controller only)
— 05h: When EDS token was expected but not received or whenever an EDS token was received
but not expected.
— 06h: When a framing error was detected in the deskew block while a packet has been in
progress in token_finder.
• Received Unexpected STP Token
— 11h: When Framing CRC in STP token did not match
— 12h: When Framing Parity in STP token did not match.
— 13h: When Framing TLP Length in STP token was smaller than 5 DWORDs.
• Received Unexpected Block
— 21h: When Receiving an OS Block following SDS in Datastream state
— 22h: When Data Block followed by OS Block different from SKP, EI, EIE in Datastream state
— 23h: When Block with an undefined Block Type in Datastream state
— 24h: When Data Stream without data over three cycles in Datastream state
— 25h: When OS Block during Data Stream in Datastream state
— 26h: When RxStatus Error was detected in Datastream state
— 27h: When Not all active lanes receiving SKP OS starting at same cycle time in SKPOS state
— 28h: When a 2-Block timeout occurs for SKP OS in SKPOS state
— 29h: When Receiving consecutive OS Blocks within a Data Stream in SKPOS state
— 2Ah: When Phy status error was detected in SKPOS state
— 2Bh: When Not all active lanes receiving EIOS starting at same cycle time in EIOS state
— 2Ch: When At least one Symbol from the first 4 Symbols is not EIOS Symbol in EIOS state
— 2Dh: When Not all active lanes receiving EIEOS starting at same cycle time in EIEOS state
— 2Eh: When Not full 16 eieos symbols are received in EIEOS state
All other values not listed above are reserved.
3.7.90 Silicon Debug Status (PM) (SD_STATUS_PM_REG)
Offset
Register Offset
SD_STATUS_PM_REG 210h
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 LATCHED_NFTS
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PME_
R 0 INTERNAL_PM_SSTATE 0 INTERNAL_PM_MSTATE
RES...
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-24 Reserved
23-16 Latched N_FTS. Indicates the value of N_FTS in the received TS Ordered Sets from the Link Partner
LATCHED_NFT
S
15-13 Reserved
PME Re-send flag. When the DUT sends a PM_PME message TLP, the DUT sets PME_Status bit.
12
If host software does not clear PME_Status bit for 100ms(+50%/-5%), the DUT resends the PM_PME
PME_RESEND Message. This bit indicates that a PM_PME was resent.
_FLAG
Internal PM State(Slave). Indicates internal state machine of Power Management Slave controller.
11-8
- 0h: S_IDLE - 1h: S_RESPOND_NAK - 2h: S_BLOCK_TLP - 3h: S_WAIT_LAST_TLP_ACK -
INTERNAL_PM 4h: S_WAIT_EIDLE - 5h: S_LINK_ENTR_L1 - 6h: S_L1 - 7h: S_L1_EXIT - 8h: S_L23RDY
_SSTATE - 9h: S_LINK_ENTR_L23 - Ah: S_L23RDY_WAIT4ALIVE - Bh: S_ACK_WAIT4IDLE - Ch:
S_WAIT_LAST_PMDLLP Note: This register field is sticky.
7-5 Reserved
Internal PM State(Master). Indicates internal state machine of Power Management Master controller. -
4-0
00h: IDLE - 01h: L0 - 02h: L0S - 03h: ENTER_L0S - 04h: L0S_EXIT - 05h: WAIT_PMCSR_CPL_SENT
INTERNAL_PM - 08h: L1 - 09h: L1_BLOCK_TLP - 0Ah: L1_WAIT_LAST_TLP_ACK - 0Bh: L1_WAIT_PMDLLP_ACK
_MSTATE - 0Ch: L1_LINK_ENTR_L1 - 0Dh: L1_EXIT - 0Fh: PREP_4L1 - 10h: L23_BLOCK_TLP - 11h:
L23_WAIT_LAST_TLP_ACK - 12h: L23_WAIT_PMDLLP_ACK - 13h: L23_ENTR_L23 - 14h: L23RDY -
15h: PREP_4L23 - 16h: L23RDY_WAIT4ALIVE - 17h: L0S_BLOCK_TLP - 18h: WAIT_LAST_PMDLLP -
19h: WAIT_DSTATE_UPDATE Note: This register field is sticky.

NXP Semiconductors
PCIe Controller
3.7.91 Silicon Debug Status (Layer2) (SD_STATUS_L2_REG)
Offset
Register Offset
SD_STATUS_L2_REG 214h
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FC_INI FC_INI
R 0 DLCMSM RX_ACK_SEQ_NO
T2 T1
Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RX_ACK_SEQ_NO TX_TLP_SEQ_NO
Reset 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-28 Reserved
27 FC_INIT2. Indicates the controller is in FC_INIT2(VC0) state. Note: This register field is sticky.
FC_INIT2
FC_INIT1
25-24 DLCMSM. Indicates the current DLCMSM. - 00b: DL_INACTIVE - 01b: DL_FC_INIT - 11b: DL_ACTIVE
DLCMSM
23-12 Tx Ack Sequence Number. Indicates ACKD_SEQ which is updated by receiving ACK/NAK DLLP. Note:
RX_ACK_SEQ_
NO
11-0 Tx Tlp Sequence Number. Indicates next transmit sequence number for transmit TLP. Note: This register
field is sticky.
TX_TLP_SEQ_
NO

NXP Semiconductors
PCIe Controller
3.7.92 Silicon debug status (layer3 FC) (SD_STATUS_L3FC_REG)
Offset
Register Offset
SD_STATUS_L3FC_RE 218h
G
Function
The CREDIT_DATA[0/1] fields in this viewport register return the data for the VC and TLP Type selected by the following fields:
• CREDIT_SEL_VC
• CREDIT_SEL_CREDIT_TYPE
• CREDIT_SEL_TLP_TYPE
• CREDIT_SEL_HD
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R CREDIT_DATA1 CREDIT_DATA0
Reset 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CREDIT_DATA0 0 CREDI CREDIT_SEL_T CREDI

CREDIT_SEL_VC
W T_... LP_... T_...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-20 Credit data1

CREDIT_DATA Current FC credit data selected by the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE,
1 CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields.
• Rx: Credit allocated value
• Tx: Credit limit value. This value is valid when DLCMSM=0x3 (DL_ACTIVE).
19-8 Credit data0

CREDIT_DATA Current FC credit data selected by the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE,
0 CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields.

NXP Semiconductors
PCIe Controller
Field Function
• Rx: Credit received value

• Tx: Credit consumed value
7 Reserved
6 Credit select(header data)

CREDIT_SEL_ This field in conjunction with the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, and
HD CREDIT_SEL_TLP_TYPE viewport-select fields determines that data that is returned by the
CREDIT_DATA0 and CREDIT_DATA1 data fields.
0b - Header credit
1b - Data credit
5-4 Credit select (TLP type)

CREDIT_SEL_T This field in conjunction with the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, and CREDIT_SEL_HD
LP_TYPE viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1
data fields.
00b - Posted
01b - Non-posted
10b - Completion
3 Credit select (credit type)

CREDIT_SEL_ This field in conjunction with the CREDIT_SEL_VC, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD
CREDIT_TYPE viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1
data fields.
0b - Rx
1b - Tx
2-0 Credit select (VC)

CREDIT_SEL_ This field in conjunction with the CREDIT_SEL_CREDIT_TYPE, CREDIT_SEL_TLP_TYPE, and
VC CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0
and CREDIT_DATA1 data fields.
0x0: VC0
0x1: VC1
0x2: VC2

NXP Semiconductors
PCIe Controller
Field Function
...
0x7: VC7
Offset
Register Offset
SD_STATUS_L3_REG 21Ch
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MFTLP
R 0 MFTLP_POINTER
_S...
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-8 Reserved
7 Malformed TLP Status. Indicates malformed TLP has occurred.
MFTLP_STATU
S
6-0 First Malformed TLP Error Pointer. Indicates the element of the received first malformed TLP. This
pointer is validated by MFTLP_STATUS. - 01h: AtomicOp address alignment - 02h: AtomicOp operand
- 03h: AtomicOp byte enable - 04h: TLP length miss match - 05h: Max payload size - 06h: Message

NXP Semiconductors
PCIe Controller
Field Function
MFTLP_POINT TLP without TC0 - 07h: Invalid TC - 08h: Unexpected route bit in Message TLP - 09h: Unexpected CRS
ER status in Completion TLP - 0Ah: Byte enable - 0Bh: Memory Address 4KB boundary - 0Ch: TLP prefix
rules - 0Dh: Translation request rules - 0Eh: Invalid TLP type - 0Fh: Completion rules - 7Fh: Application -
Else: Reserved Note: This register field is sticky.
3.7.94 Silicon Debug EQ Control 1 (SD_EQ_CONTROL1_REG)
Offset
Register Offset
SD_EQ_CONTROL1_RE 228h
G
Function
This is a viewport control register. Setting the EQ_RATE_SEL and EQ_LANE_SEL fields in this register determine the per-lane
Silicon Debug EQ Status data returned by the SD_EQ_STATUS[1/2/3] viewport registers. For more details, see RAS Debug,
Error Injection, and Statistics (DES)†.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R FOM_ 0 EVAL_INTERV
FOM_TARGET
W TAR... AL_T...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 EXT_EQ_TIME 0 EQ_R
EQ_LANE_SEL
W OUT ATE...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
FOM Target. Indicates figure of merit target criteria value of EQ Master(DSP in EQ Phase3/USP in
31-24
EQ Phase2). This field is only valid when GEN3_EQ_FB_MODE is 0001b(Figure Of Merit). Note: This
FOM_TARGET register field is sticky.
23 FOM Target Enable. Enables the FOM_TARGET fields. Note: This register field is sticky.
FOM_TARGET
_ENABLE
22-18 Reserved

NXP Semiconductors
PCIe Controller
Field Function
Eval Interval Time. Indicates interval time of RxEqEval assertion. - 00: 500ns - 01: 1us - 10: 2us - 11:
17-16
4us This field is used for EQ Master(DSP in EQ Phase3/USP in EQ Phase2). Note: This register field is
EVAL_INTERV sticky.
AL_TIME
15-10 Reserved
9-8Extends EQ Phase2/3 Timeout. This field is used when the Ltssm is in Recovery.EQ2/3. When this field
is set, the value of EQ2/3 timeout is extended. EQ Master(DSP in EQ Phase3/USP in EQ Phase2). - 00:
EXT_EQ_TIME 24ms (default) - 01: 48ms (x2) - 10: 240ms (x10) - 11: No timeout EQ Slave(DSP in EQ Phase2/USP
OUT in EQ Phase3). - 00: 32ms (default) - 01: 56ms (32ms+24ms) - 10: 248ms (32ms +9*24ms) - 11: No
timeout Note: This register field is sticky.
7-5 Reserved
4 EQ Status Rate Select. Setting this field in conjunction with the EQ_LANE_SEL field determines the per-
lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3]
EQ_RATE_SEL viewport registers. - 0x0: 8.0GT/s Speed - 0x1: 16.0GT/s Speed Note: This register field is sticky.
3-0EQ Status Lane Select. Setting this field in conjunction with the EQ_RATE_SEL field determines the per-
EQ_LANE_SEL viewport registers. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note: This register field is
sticky.
Offset
Register Offset
SD_EQ_CONTROL2_RE 22Ch
G
Function
This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the
SD_EQ_CONTROL1_REG register. For more details, see RAS Debug, Error Injection, and Statistics (DES)†.

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 FORC FORC FORC 0 FORCE_LOCAL_RX_HI FORCE_LOCA

FORCE_LOCAL_TX_PRESET
W E_L... E_L... E_L... NT L_TX_...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R FORCE_LOCAL_TX_POST_CUR
FORCE_LOCAL_TX_CURSOR FORCE_LOCAL_TX_PRE_CURSOR
W SOR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31 Reserved
30 Force Local Transmitter Preset Enable. Enables the FORCE_LOCAL_TX_PRESET field. Note: This
FORCE_LOCA
L_TX_PRESET
_ENABLE
29 Force Local Receiver Preset Hint Enable. Enables the FORCE_LOCAL_RX_HINT field. Note: This
FORCE_LOCA
L_RX_HINT_EN
ABLE
Force Local Transmitter Coefficient Enable. Enables the following

28
fields: - FORCE_LOCAL_TX_PRE_CURSOR - FORCE_LOCAL_TX_CURSOR -
FORCE_LOCA FORCE_LOCAL_TX_POST_CURSOR Note: This register field is sticky.
L_TX_COEF_E
NABLE
27-24 Force Local Transmitter Preset. Indicates initial preset value of USP in EQ Slave(EQ Phase2) instead of
receiving EQ TS2. Note: This register field is sticky.
FORCE_LOCA
L_TX_PRESET
23-21 Reserved
20-18 Force Local Receiver Preset Hint. Indicates the RxPresetHint value of EQ Slave(DSP in EQ
Phase2/USP in EQ Phase3), instead of received or set value. Note: This register field is sticky.
FORCE_LOCA
L_RX_HINT

NXP Semiconductors
PCIe Controller
Field Function
Force Local Transmitter Post-Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ

17-12
Phase2/USP in EQ Phase3), instead of the value instructed from link partner. Note: This register field is
FORCE_LOCA sticky.
L_TX_POST_C
URSOR
11-6 Force Local Transmitter Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in
EQ Phase3), instead of the value instructed from link partner. Note: This register field is sticky.
FORCE_LOCA
L_TX_CURSOR
5-0 Force Local Transmitter Pre-cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP
in EQ Phase3), instead of the value instructed from link partner. Note: This register field is sticky.
FORCE_LOCA
L_TX_PRE_CU
RSOR
Offset
Register Offset
G
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 FORC 0 FORCE_REMO
W E_R... TE_TX...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R FORCE_REMOTE_TX_POST_CU
FORCE_REMOTE_TX_CURSOR FORCE_REMOTE_TX_PRE_CURSOR
W RSOR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-29 Reserved
28 Force Remote Transmitter Coefficient Enable. Enables the following

fields: - FORCE_REMOTE_TX_PRE_CURSOR - FORCE_REMOTE_TX_CURSOR -
FORCE_REMO FORCE_REMOTE_TX_POST_CURSOR Note: This register field is sticky.
TE_TX_COEF_
ENABLE
27-18 Reserved
Force Remote Transmitter Post-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ

17-12
FORCE_REMO sticky.
TE_TX_POST_
CURSOR
11-6 Force Remote Transmitter Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP
FORCE_REMO
TE_TX_CURSO
R
5-0Force Remote Transmitter Pre-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ

FORCE_REMO sticky.
TE_TX_PRE_C
URSOR
3.7.97 Silicon Debug EQ Status 1 (SD_EQ_STATUS1_REG)
Offset
Register Offset
SD_EQ_STATUS1_REG 238h
Function
This viewport register returns the first of three words of Silicon Debug EQ Status data for the rate and lane selected by the
EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register.
The following fields are available when Equalization finished unsuccessfully(EQ_CONVERGENCE_INFO=2).
• EQ_RULEA_VIOLATION
• EQ_RULEB_VIOLATION
• EQ_RULEC_VIOLATION
• EQ_REJECT_EVENT

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EQ_R EQ_R EQ_R EQ_R EQ_CONVERG EQ_S

R 0 0
EJE... ULE... ULE... ULE... ENCE_... EQU...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-8 Reserved
7EQ Reject Event. Indicates that the controller receives two consecutive TS1 OS w/Reject=1b during
EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). This bit is automatically cleared when the
EQ_REJECT_E controller starts EQ Master phase again. Note: This register field is sticky.
VENT
6EQ Rule C Violation. Indicates that coefficients rule C violation is detected in the values provided by PHY
using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The
EQ_RULEC_VI coefficients rule C correspond to the rules c) from section "Rules for Transmitter Coefficents" in the PCI
OLATION Express Base Specification. This bit is automatically cleared when the controller starts EQ Master phase
again. Note: This register field is sticky.
5EQ Rule B Violation. Indicates that coefficients rule B violation is detected in the values provided by PHY
EQ_RULEB_VI coefficients rules B correspond to the rules b) from section "Rules for Transmitter Coefficents" in the PCI
4EQ Rule A Violation. Indicates that coefficients rule A violation is detected in the values provided by PHY
EQ_RULEA_VI coefficients rules A correspond to the rules a) from section "Rules for Transmitter Coefficents" in the PCI
3 Reserved
EQ Convergence Info. Indicates equalization convergence information. - 0x0: Equalization is not

2-1
attempted - 0x1: Equalization finished successfully - 0x2: Equalization finished unsuccessfully - 0x3:
EQ_CONVERG Reserved This bit is automatically cleared when the controller starts EQ Master phase again. Note: This
ENCE_INFO register field is sticky.

NXP Semiconductors
PCIe Controller
Field Function
0 EQ Sequence. Indicates that the controller is starting the equalization sequence. Note: This register field
is sticky.
EQ_SEQUENC
E
Offset
Register Offset
SD_EQ_STATUS2_REG 23Ch
Function
This viewport register returns the second of three words of Silicon Debug EQ Status data for the rate and lane selected by the
EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. Each field is available when Equalization
finished successfully(EQ_CONVERGENCE_INFO=1). For more details, see RAS Debug, Error Injection, and Statistics (DES)
†.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EQ_LOCAL_PO
R EQ_LOCAL_FOM_VALUE 0 EQ_LOCAL_RX_HINT
ST_C...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R EQ_LOCAL_POST_CURSOR EQ_LOCAL_CURSOR EQ_LOCAL_PRE_CURSOR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-24 EQ Local Figure of Merit. Indicates Local maximum Figure of Merit value. Note: This register field is
sticky.
EQ_LOCAL_FO
M_VALUE
23-21 Reserved

NXP Semiconductors
PCIe Controller
Field Function
20-18 EQ Local Receiver Preset Hint. Indicates Local Receiver Preset Hint value. Note: This register field is
sticky.
EQ_LOCAL_RX
_HINT
17-12 EQ Local Post-Cursor. Indicates Local post cursor coefficient value. Note: This register field is sticky.
EQ_LOCAL_PO
ST_CURSOR
11-6 EQ Local Cursor. Indicates Local cursor coefficient value. Note: This register field is sticky.
EQ_LOCAL_CU
RSOR
5-0 EQ Local Pre-Cursor. Indicates Local pre cursor coefficient value. Note: This register field is sticky.
EQ_LOCAL_PR
E_CURSOR
Offset
Register Offset
Function
This viewport register returns the third of three words of Silicon Debug EQ Status data for the rate and lane selected by the
†.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EQ_REMOTE_
R 0 EQ_REMOTE_FS EQ_REMOTE_LF
POST_...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R EQ_REMOTE_POST_CURSOR EQ_REMOTE_CURSOR EQ_REMOTE_PRE_CURSOR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-30 Reserved
29-24 EQ Remote FS. Indicates Remote FS value. Note: This register field is sticky.
EQ_REMOTE_
FS
23-18 EQ Remote LF. Indicates Remote LF value. Note: This register field is sticky.
EQ_REMOTE_
LF
17-12 EQ Remote Post-Cursor. Indicates Remote post cursor coefficient value. Note: This register field is
sticky.
EQ_REMOTE_
POST_CURSO
R
11-6 EQ Remote Cursor. Indicates Remote cursor coefficient value. Note: This register field is sticky.
EQ_REMOTE_
CURSOR
5-0 EQ Remote Pre-Cursor. Indicates Remote pre cursor coefficient value. Note: This register field is sticky.
EQ_REMOTE_
PRE_CURSOR
3.7.100 PCIe Extended Capability ID, Capability Version, And Next Capability Offset
(RASDP_EXT_CAP_HDR_OFF)
Offset
Register Offset
RASDP_EXT_CAP_HDR 258h
_OFF
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R NEXT_OFFSET CAP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ID
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1
Fields
Field Function
Next Capability Offset. For a description of this standard PCIe register, see the PCI Express
31-20
19-16 Capability Version. For a description of this standard PCIe register, see the PCI Express Specification.
Note: The access attributes of this field are as follows: - Wire: R (sticky) Note: This register field is sticky.
CAP
15-0 PCI Express Extended Capability ID. For a description of this standard PCIe register, see the PCI
Express Specification. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note:
ID This register field is sticky.
3.7.101 Vendor Specific Header. (RASDP_VENDOR_SPECIFIC_HDR_OFF)
Offset
Register Offset
RASDP_VENDOR_SPE 25Ch
CIFIC_HDR_OFF
Function
Vendor Specific Header. For a description of this standard PCIe register, see the PCI Express Specification.

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VSEC_ID
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Fields
Field Function
31-20 VSEC Length. For a description of this standard PCIe register, see the PCI Express Specification. Note:
VSEC_LENGT
H
19-16 VSEC Rev. For a description of this standard PCIe register, see the PCI Express Specification. Note:
VSEC_REV
15-0 VSEC ID. For a description of this standard PCIe register, see the PCI Express Specification. Note: This
VSEC_ID
3.7.102 ECC error correction control. (RASDP_ERROR_PROT_CTRL_OFF)
Offset
Register Offset
RASDP_ERROR_PROT 260h
_CTRL_OFF
Function
ECC error correction control. Allows you to disable ECC error correction for RAMs and datapath. When the AXI Bridge Module
is implemented and the master / slave clocks are asynchronous to the PCIe native controller clock (core_clk), you must not
write this register while operations are in progress in the AXI master / slave interface.

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 ERRO ERRO ERRO ERRO ERRO ERRO ERRO
W R_P... R_P... R_P... R_P... R_P... R_P... R_P...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-23 Reserved
22 Error correction disable for ADM Rx path. Note: This register field is sticky.
ERROR_PROT
_DISABLE_AD
M_RX
21 Error correction disable for layer 3 Rx path. Note: This register field is sticky.
ERROR_PROT
_DISABLE_LAY
ER3_RX
ERROR_PROT
_DISABLE_LAY
ER2_RX
19 Error correction disable for DMA read engine. Note: This register field is sticky.
ERROR_PROT
_DISABLE_DM
A_READ
18 Error correction disable for AXI bridge inbound request path. Note: This register field is sticky.
ERROR_PROT
_DISABLE_AXI
_BRIDGE_INB
OUND_REQUE
ST
17 Error correction disable for AXI bridge inbound completion composer. Does not disable the error
detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky.

NXP Semiconductors
PCIe Controller
Field Function
ERROR_PROT
_DISABLE_AXI
_BRIDGE_INB
OUND_COMPL
ETION
16 Global error correction disable for all Rx layers. Note: This register field is sticky.
ERROR_PROT
_DISABLE_RX
15-7 Reserved
6 Error correction disable for Adm Tx path. Note: This register field is sticky.
ERROR_PROT
_DISABLE_AD
M_TX
5 Error correction disable for layer 3 Tx path. Note: This register field is sticky.
ERROR_PROT
_DISABLE_LAY
ER3_TX
ERROR_PROT
_DISABLE_LAY
ER2_TX
3 Error correction disable for DMA write engine. Note: This register field is sticky.
ERROR_PROT
_DISABLE_DM
A_WRITE
2 Error correction disable for AXI bridge outbound request path. Note: This register field is sticky.
ERROR_PROT
_DISABLE_AXI
_BRIDGE_OUT
BOUND
1 Error correction disable for AXI bridge master completion buffer. Note: This register field is sticky.
ERROR_PROT
_DISABLE_AXI
_BRIDGE_MAS
TER

NXP Semiconductors
PCIe Controller
Field Function
0 Global error correction disable for all Tx layers. Does not disable the error detection reporting for 1-bit
and 2-bit ECC errors. Note: This register field is sticky.
ERROR_PROT
_DISABLE_TX
3.7.103 Corrected error (1-bit ECC) counter selection and control

Offset
Register Offset
RASDP_CORR_COUNT 264h
ER_CTRL_OFF
Function
This is a viewport control register. Setting the CORR_COUNTER_SELECTION_REGION and
CORR_COUNTER_SELECTION fields in this register determine the counter data returned by the
RASDP_CORR_COUNT_REPORT_OFF viewport data register.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R CORR_COUNTER_SELECTION_ 0
CORR_COUNTER_SELECTION
W REGION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CORR
R 0 CORR 0
_CL...
_EN...
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Fields
Field Function
Counter selection. This field selects the counter ID (within the region defined
31-24
by CORR_COUNTER_SELECTION_REGION) whose contents can be read from the
CORR_COUNT RASDP_CORR_COUNT_REPORT_OFF register. You can cycle this field value from 0 to 255 to access
ER_SELECTIO all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/
N DWC_pcie/latest/doc/RASDP_CheckPoints.pdf
23-20 Select correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3
Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region

NXP Semiconductors
PCIe Controller
Field Function
CORR_COUNT select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion
ER_SELECTIO composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8:
N_REGION Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for
AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer
path - 0xc: Reserved - 0xf: Reserved
19-5 Reserved
4 Enable correctable errors counters. - 1: counters increment when the controller detects a correctable
error - 0: counters are frozen The counters are enabled by default.
CORR_EN_CO
UNTERS
3-1 Reserved
0 Clear all correctable error counters.
CORR_CLEAR
_COUNTERS
3.7.104 Corrected error (1-bit ECC) counter data. (RASDP_CORR_COUNT_REPORT_OFF)
Offset
Register Offset
_REPORT_OFF
Function
Corrected error (1-bit ECC) counter data. This viewport register returns the counter data
selected by the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in the
RASDP_CORR_COUNTER_CTRL_OFF register.

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CORR_COUNTER_SELECTED_R
R CORR_COUNTER_SELECTED 0
EGION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 CORR_COUNTER
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-24 Counter selection. Returns the value set in the CORR_COUNTER_SELECTION field of the
CORR_COUNT
ER_SELECTED
Selected correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for
23-20
layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path
CORR_COUNT - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound
ER_SELECTED completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path
_REGION - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select
for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion
buffer path - 0xc: Reserved - 0xf: Reserved
19-8 Reserved
7-0 Current corrected error count for the selected counter.
CORR_COUNT
ER
3.7.105 Uncorrected error (2-bit ECC and parity) counter selection and control.
(RASDP_UNCORR_COUNTER_CTRL_OFF)
Offset
Register Offset
RASDP_UNCORR_COU 26Ch
NTER_CTRL_OFF

NXP Semiconductors
PCIe Controller
Function
Uncorrected error (2-bit ECC and parity) counter selection and control. This is a viewport control register. Setting the
UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in this register determine the
counter data returned by the RASDP_UNCORR_COUNT_REPORT_OFF viewport data register.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R UNCORR_COUNTER_SELECTIO 0
UNCORR_COUNTER_SELECTION
W N_REGION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UNCO
R 0 UNCO 0
RR_...
RR_...
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Fields
Field Function
31-24
by UNCORR_COUNTER_SELECTION_REGION) whose contents can be read from the
UNCORR_COU RASDP_UNCORR_COUNT_REPORT_OFF register. You can cycle this field value from 0 to 255 to
NTER_SELECT access all counters according to the detailed report of check points at http://www.synopsys.com/dw/
ION doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf
Select uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for
23-20
UNCORR_COU - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound
NTER_SELECT completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path
ION_REGION - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select
19-5 Reserved
4 Enable uncorrectable errors counters. - 1: enables the counters to increment on detected correctable
errors - 0: counters are frozen The counters are enabled by default.
UNCORR_EN_
COUNTERS
3-1 Reserved
0 Clear uncorrectable errors counters. When asserted causes all counters tracking the uncorrectable
errors to be cleared.
UNCORR_CLE
AR_COUNTER
S

NXP Semiconductors
PCIe Controller
3.7.106 Uncorrected error (2-bit ECC and parity) counter data.

Offset
Register Offset
RASDP_UNCORR_COU 270h
NT_REPORT_OFF
Function
Uncorrected error (2-bit ECC and parity) counter data. This viewport register returns the counter data
selected by the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in the
RASDP_UNCORR_COUNTER_CTRL_OFF register.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UNCORR_COUNTER_SELECTE
R UNCORR_COUNTER_SELECTED 0
D_REGION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 UNCORR_COUNTER
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-24 Counter selection. Returns the value set in the UNCORR_COUNTER_SELECTION field of the
UNCORR_COU
NTER_SELECT
ED
Selected uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for
23-20
ED_REGION - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select
19-8 Reserved

NXP Semiconductors
PCIe Controller
Field Function
7-0 Current uncorrected error count for the selected counter
UNCORR_COU
NTER
3.7.107 Error injection control for the following features: - 1-bit or 2-bit injection - Continuous or
fixed-number (n) injection modes - Global enable/disable - Selectable location where injection
occurs (RASDP_ERROR_INJ_CTRL_OFF)
Offset
Register Offset
RASDP_ERROR_INJ_C 274h
TRL_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
ERROR_INJ_LOC
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 ERROR_INJ_T 0 ERRO
ERROR_INJ_COUNT
W YPE R_I...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-24 Reserved
23-16 Error injection location. Selects where error injection takes place. You can cycle this field value
from 0 to 255 to access all locations according to the detailed report of check points at http://
ERROR_INJ_L www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf
OC
15-8 Error injection count. - 0: errors are inserted in every TLP until you clear ERROR_INJ_EN. - 1: one errors
injected - 2: two errors injected - n: amount of errors injected
ERROR_INJ_C
OUNT

NXP Semiconductors
PCIe Controller
Field Function
7-6 Reserved
5-4 Error injection type: - 0: none - 1: 1-bit - 2: 2-bit
ERROR_INJ_T
YPE
3-1 Reserved
0 Error injection global enable. When set enables the error insertion logic.
ERROR_INJ_E
N
3.7.108 Corrected errors locations (RASDP_CORR_ERROR_LOCATION_OFF)
Offset
Register Offset
RASDP_CORR_ERROR 278h
_LOCATION_OFF
Function
For more details, see RAS data protection (DP)†.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R LOC_LAST_CORR_ERROR REG_LAST_CORR_ERROR 0
Reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R LOC_FIRST_CORR_ERROR REG_FIRST_CORR_ERROR 0
Reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
Location/ID of the last corrected error within the region defined by REG_LAST_CORR_ERROR. You can
31-24
cycle this field value from 0 to 255 to access all counters according to the detailed report of check points
LOC_LAST_CO at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf
RR_ERROR
Region of the last corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3
23-20
REG_LAST_CO select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion
RR_ERROR composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8:
Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for
19-16 Reserved
15-8 Location/ID of the first corrected error within the region defined by REG_FIRST_CORR_ERROR. You
can cycle this field value from 0 to 255 to access all counters according to the detailed report of check
LOC_FIRST_C points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf
ORR_ERROR
7-4Region of the first corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3
REG_FIRST_C select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion
ORR_ERROR composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8:
3-0 Reserved
3.7.109 Uncorrected errors locations (RASDP_UNCORR_ERROR_LOCATION_OFF)
Offset
Register Offset
RASDP_UNCORR_ERR 27Ch
OR_LOCATION_OFF
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R LOC_LAST_UNCORR_ERROR REG_LAST_UNCORR_ERROR 0
Reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R LOC_FIRST_UNCORR_ERROR REG_FIRST_UNCORR_ERROR 0
Reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0
Fields
Field Function
Location/ID of the last uncorrected error within the region defined by REG_LAST_UNCORR_ERROR.
31-24
You can cycle this field value from 0 to 255 to access all counters according to the detailed report of
LOC_LAST_UN check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf
CORR_ERROR
Region of the last uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for
23-20
REG_LAST_UN - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound
CORR_ERROR completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path
- 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select
19-16 Reserved
15-8 Location/ID of the first uncorrected error within the region defined by REG_FIRST_UNCORR_ERROR.
LOC_FIRST_U check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf
NCORR_ERRO
R
Region of the first uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for
7-4
REG_FIRST_U - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound
NCORR_ERRO completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path
R - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select
3-0 Reserved

NXP Semiconductors
PCIe Controller
3.7.110 RASDP error mode enable (RASDP_ERROR_MODE_EN_OFF)
Offset
Register Offset
RASDP_ERROR_MODE 280h
_EN_OFF
Function
The controller enters RASDP error mode (if ERROR_MODE_EN =1) upon detection of the first uncorrectable error. During this
mode, Rx TLPs that are forwarded to your application are not guaranteed to be correct; you must discard them. For more
details, see RAS data protection (DP)†.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 AUTO_ ERRO
W LI... R_M...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Fields
Field Function
31-2 Reserved
1 Write '1' to enable the controller to bring the link down when the controller enters RASDP error mode.
AUTO_LINK_D
OWN_EN
0 Write '1' to enable the controller enter RASDP error mode when it detects an uncorrectable error. Note:
ERROR_MODE
_EN

NXP Semiconductors
PCIe Controller
3.7.111 Exit RASDP error mode (RASDP_ERROR_MODE_CLEAR_OFF)
Offset
Register Offset
_CLEAR_OFF
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRO
R 0
R_M...
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-1 Reserved
0 Write '1' to take the controller out of RASDP error mode. The controller will then report uncorrectable
errors (through AER internal error reporting) and also stop nullifying/discarding TLPs.
ERROR_MODE
_CLEAR
3.7.112 RAM Address where a corrected error (1-bit ECC) has been detected
Offset
Register Offset
RASDP_RAM_ADDR_C 288h
ORR_ERROR_OFF

NXP Semiconductors
PCIe Controller
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RAM_INDEX_CORR_ERROR 0 RAM_ADDR_CORR_ERROR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RAM_ADDR_CORR_ERROR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-28 RAM index where a corrected error (1-bit ECC) has been detected.
RAM_INDEX_C
ORR_ERROR
27 Reserved
26-0 RAM Address where a corrected error (1-bit ECC) has been detected.
RAM_ADDR_C
ORR_ERROR
3.7.113 RAM Address where an uncorrected error (2-bit ECC) has been detected
(RASDP_RAM_ADDR_UNCORR_ERROR_OFF)
Offset
Register Offset
RASDP_RAM_ADDR_U 28Ch
NCORR_ERROR_OFF
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RAM_INDEX_UNCORR_ERROR 0 RAM_ADDR_UNCORR_ERROR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RAM_ADDR_UNCORR_ERROR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-28 RAM index where an uncorrected error (2-bit ECC) has been detected.
RAM_INDEX_U
NCORR_ERRO
R
27 Reserved
26-0 RAM Address where an uncorrected error (2-bit ECC) has been detected.
RAM_ADDR_U
NCORR_ERRO
R
3.7.114 Ack latency timer and replay timer (ACK_LATENCY_TIMER_OFF)
Offset
Register Offset
ACK_LATENCY_TIMER 700h
_OFF

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
REPLAY_TIME_LIMIT
W
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ROUND_TRIP_LATENCY_TIME_LIMIT
W
1. When the chip resets, this field resets to 1846h. However, the field is not accessible until later, when the PCIe reset
finishes. At that moment, this field's value becomes C0h. Therefore, you can treat C0h as this register's usable reset value.
2. When the chip resets, this field resets to 817h. However, the field is not accessible until later, when the PCIe reset finishes.
At that moment, this field's value becomes 40h. Therefore, you can treat 40h as this register's usable reset value.
Fields
Field Function
Replay Timer Limit. The replay timer expires when it reaches this limit. The controller initiates a
31-16
replay upon reception of a NAK or when the replay timer expires. For more details, see "Transmit
REPLAY_TIME Replay". You can modify the effective timer limit with the TIMER_MOD_REPLAY_TIMER field of the
_LIMIT TIMER_CTRL_MAX_FUNC_NUM_OFF register. After reset, the controller updates the default according
to the Negotiated Link Width, Max_Payload_Size, and speed. The value is determined from Tables 3-4,
3-5, and 3-6 of the PCIe 3.0 specification. If there is a change in the payload size or link speed, the
controller will override any value that you have written to this register field, and reset the field back to the
specification-defined value. It will not change the value in the TIMER_MOD_REPLAY_TIMER field of the
TIMER_CTRL_MAX_FUNC_NUM_OFF register.
Ack Latency Timer Limit. The Ack latency timer expires when it reaches this limit. For more details, see
15-0
"Ack Scheduling". You can modify the effective timer limit with the TIMER_MOD_ACK_NAK field of the
ROUND_TRIP_ TIMER_CTRL_MAX_FUNC_NUM_OFF register. After reset, the controller updates the default according
LATENCY_TIM to the Negotiated Link Width, Max_Payload_Size, and speed. The value is determined from Tables 3-7,
E_LIMIT 3-8, and 3-9 of the PCIe 3.0 specification. The limit must reflect the round trip latency from requester to
completer. If there is a change in the payload size or link width, the controller will override any value that
you have written to this register field, and reset the field back to the specification-defined value. It will
not change the value in the TIMER_MOD_ACK_NAK field of the TIMER_CTRL_MAX_FUNC_NUM_OFF
register.
3.7.115 Vendor-specific DLLP (VENDOR_SPEC_DLLP_OFF)
Offset
Register Offset
VENDOR_SPEC_DLLP_ 704h
OFF

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
VENDOR_SPEC_DLLP
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
VENDOR_SPEC_DLLP
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Fields
Field Function
Used to send a specific PCI Express DLLP. Your application writes the 8-bit DLLP Type and
31-0
24-bits of Payload data into this register, then sets the field VENDOR_SPECIFIC_DLLP_REQ of
VENDOR_SPE PORT_LINK_CTRL_OFF to send the DLLP. - [7:0] = Type - [31:8] = Payload (24 bits) The dllp type
C_DLLP is in bits [7:0] while the remainder is the vendor defined payload. Note: This register field is sticky.
3.7.116 Port force link (PORT_FORCE_OFF)
Offset
Register Offset
PORT_FORCE_OFF 708h
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 Reserv 0
LINK_STATE
W ed
Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FORC
R 0
E_EN FORCED_LTSSM LINK_NUM
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-24 Reserved
23 Reserved
22 Reserved
21-16 Forced LTSSM State. The LTSSM state that the controller is forced to when you set the FORCE_EN
bit (Force Link). LTSSM state encoding is defined by the lts_state variable in workspace/src/Layer1/
LINK_STATE smlh_ltssm.v. Note: This register field is sticky.
15 Force Link. The controller supports a testing and debug capability to allow your software to force
the LTSSM state machine into a specific state, and to force the controller to transmit a specific Link
FORCE_EN Command. Asserting this bit triggers the following actions: - Forces the LTSSM to the state specified by
the Forced LTSSM State field. - Forces the controller to transmit the command specified by the Forced
Link Command field. This is a self-clearing register field. Reading from this register field always returns a
"0".
14-12 Reserved
Forced Link Command. The link command that the controller is forced to transmit when you set
11-8
FORCE_EN bit (Force Link). Link command encoding is defined by the ltssm_cmd variable in
FORCED_LTSS workspace/src/Layer1/smlh_ltssm.v. Note: This register field is sticky.
M
7-0 Link Number. Not used for endpoint. Note: This register field is sticky.
LINK_NUM
3.7.117 Ack Frequency and L0-L1 ASPM Control (ACK_F_ASPM_CTRL_OFF)
Offset
Register Offset
ACK_F_ASPM_CTRL_O 70Ch
FF

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 ENTE L1_ENTRANCE_LATEN L0S_ENTRANCE_LATE COMMON_CLK_N_FTS
W R_A... CY NCY
Reset 0 0 0 1 1 0 1 1 1 0 1 1 0 1 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ACK_N_FTS ACK_FREQ
W
Reset 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31 Reserved
ASPM L1 Entry Control. - 1: Core enters ASPM L1 after a period in which it has been idle. - 0: Core
30
enters ASPM L1 only after idle period during which both receive and transmit are in L0s. Note: This
ENTER_ASPM register field is sticky.
L1 Entrance Latency. Value range is: - 000: 1 us - 001: 2 us - 010: 4 us - 011: 8 us - 100: 16 us - 101: 32
29-27
us - 110 or 111: 64 us Note: Programming this timer with a value greater that 32us has no effect unless
L1_ENTRANCE extended sync is used, or all of the credits are infinite. Note: This register field is sticky.
_LATENCY
26-24 L0s Entrance Latency. Values correspond to: - 000: 1 us - 001: 2 us - 010: 3 us - 011: 4 us - 100: 5 us -
101: 6 us - 110 or 111: 7 us Note: This register field is sticky.
L0S_ENTRANC
E_LATENCY
23-16 Common Clock N_FTS

COMMON_CLK This is the N_FTS when common clock is used.
_N_FTS
The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0.
The maximum number of FTS ordered-sets that a component can request is 255.
The controller does not support a value of zero; a value of zero can cause the LTSSM to go into the recovery
state when exiting from L0s.
- Wire: R
15-8 N_FTS. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from
L0s to L0. The maximum number of FTS ordered-sets that a component can request is 255. The
ACK_N_FTS controller does not support a value of zero; a value of zero can cause the LTSSM to go into the recovery
state when exiting from L0s. Note: This register field is sticky.
7-0 Ack Frequency. The controller accumulates the number of pending ACKs specified here (up to 255)
before sending an ACK DLLP. - 0: Indicates that this Ack frequency control feature is turned off. The
ACK_FREQ controller schedules a low-priority ACK DLLP for every TLP that it receives. - 1-255: Indicates that the

NXP Semiconductors
PCIe Controller
Field Function
controller will schedule a high-priority ACK after receiving this number of TLPs. It might schedule the
ACK before receiving this number of TLPs, but never later. For a typical system, you do not have to
modify the default setting. For more details, see "ACK/NAK Scheduling". Note: This register field is
sticky.
3.7.118 Port Link Control (PORT_LINK_CTRL_OFF)
Offset
Register Offset
PORT_LINK_CTRL_OFF 710h
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 TRAN EXTE CORR BEAC 0

LINK_CAPABLE
W SMI... NDE... UPT... ON_...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VEND
R 0 FAST_ LINK_ DLL_LI 0 RESE LOOP SCRA
LINK_RATE OR_...
LI... DI... N... T_A... BAC... MBL...
W W1C
Reset 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0
Fields
Field Function
31-28 Reserved
27 TRANSMIT_LANE_REVERSALE_ENABLE is an internally reserved field. Do not use. Note: This register

field is sticky.
TRANSMIT_LA
NE_REVERSAL
E_ENABLE
26 EXTENDED_SYNCH is an internally reserved field. Do not use. Note: This register field is sticky.
EXTENDED_S
YNCH
25 CORRUPT_LCRC_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky.

NXP Semiconductors
PCIe Controller
Field Function
CORRUPT_LC
RC_ENABLE
24 BEACON_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky.
BEACON_ENA
BLE
23-22 Reserved
21-16 Link mode enable

LINK_CAPABL Sets the number of lanes in the link that you want to connect to the link partner. When you have unused
E lanes in your system, then you must change the value in this register to reflect the number of lanes. You must
also change the value in the "Predetermined Number of Lanes" field of the "Link Width and Speed Change
Control Register". For more information, see "How to Tie Off Unused Lanes". For information on upsizing
and downsizing the link width, see "Link Establishment".
• 000001: x1
• 000011: x2
• 000111: x4
• 001111: x8
• 011111: x16
• 111111: x32 (not supported)
15-12 Reserved
11-8 LINK_RATE is an internally reserved field. Do not use. Note: This register field is sticky.
LINK_RATE
7 Fast Link Mode. Sets all internal LTSSM millisecond timers to Fast Mode for speeding up simulation.
Forces the LTSSM training (link initialization) to use shorter time-outs and to link up faster. The
FAST_LINK_M default scaling factor can be changed using the DEFAULT_FAST_LINK_SCALING_FACTOR parameter
ODE or through the FAST_LINK_SCALING_FACTOR field in the TIMER_CTRL_MAX_FUNC_NUM_OFF
register. Fast Link Mode can also be activated by setting the diag_ctrl_bus[2] pin to '1'. For more details,
see the "Fast Link Simulation Mode" section in the "Integrating the Core with the PHY or Application RTL
or Verification IP" chapter of the User Guide. If this bit is set to '1', tRRAPInitiatorResponse is set to 1.88
ms(60 ms/32). Note: This register field is sticky.
6 LINK_DISABLE is an internally reserved field. Do not use. Note: This register field is sticky.
LINK_DISABLE
5 DLL Link Enable. Enables link initialization. When DLL Link Enable =0, the controller does not transmit
InitFC DLLPs and does not establish a link. Note: This register field is sticky.

NXP Semiconductors
PCIe Controller
Field Function
DLL_LINK_EN
4 Reserved
3 Reset Assert. Triggers a recovery and forces the LTSSM to the hot reset state (downstream port only).
RESET_ASSER
T
2 Loopback Enable. Turns on loopback. For more details, see "Loopback". Note: This register field is
sticky.
LOOPBACK_E
NABLE
1 Scramble Disable. Turns off data scrambling. Note: This register field is sticky.
SCRAMBLE_DI
SABLE
0 Vendor Specific DLLP Request. When software writes a '1' to this bit, the controller transmits the
DLLP contained in the VENDOR_SPEC_DLLP field of VENDOR_SPEC_DLLP_OFF. Reading from this
VENDOR_SPE self-clearing register field always returns a '0'.
CIFIC_DLLP_R
EQ
3.7.119 Lane Skew (LANE_SKEW_OFF)
Offset
Register Offset
LANE_SKEW_OFF 714h
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R DISAB GEN3 ACK_ FLOW

IMPLEMENT_NUM_LANES INSERT_LANE_SKEW
W LE... 4_E... NAK... _CT...
Reset 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
INSERT_LANE_SKEW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31 Disable Lane-to-Lane Deskew. Causes the controller to disable the internal Lane-to-Lane deskew logic.
DISABLE_LAN
E_TO_LANE_D
ESKEW
Implementation-specific Number of Lanes. Set the implementation-specific number of lanes. Allowed

30-27
values are: - 4'b0000: 1 lane - 4'b0001: 2 lanes - 4'b0011: 4 lanes - 4'b0111: 8 lanes - 4'b1111: 16 lanes
IMPLEMENT_N The number of lanes to be used when in Loopback Master. The number of lanes programmed must be
UM_LANES equal to or less than the valid number of lanes set in LINK_CAPABLE field. You must configure this field
before initiating Loopback by writing in the LOOPBACK_ENABLE field. The controller will transition from
Loopback.Entry to Loopback.Active after receiving two consecutive TS1 Ordered Sets with the Loopback
bit asserted on the implementation specific number of lanes configured in this field. Note: This register
field is sticky.
26 Selects Elasticity Buffer operating mode in Gen3 or Gen4 rate: 0: Nominal Half Full Buffer mode 1:
Nominal Empty Buffer Mode This register bit only affects Gen3 or Gen4 operating rate. For Gen1 or
GEN34_ELASTI Gen2 operating rate the Elasticity Buffer operating mode is always the Nominal Half Full Buffer mode.
C_BUFFER_M Note: This register field is sticky.
ODE
25 Ack/Nak Disable. Prevents the controller from sending ACK and NAK DLLPs. Note: This register field is
sticky.
ACK_NAK_DIS
ABLE
24 Flow Control Disable. Prevents the controller from sending FC DLLPs. Note: This register field is sticky.
FLOW_CTRL_D
ISABLE
23-0 INSERT_LANE_SKEW is an internally reserved field. Do not use. Note: This register field is sticky.
INSERT_LANE
_SKEW
3.7.120 Timer control and max function number (TIMER_CTRL_MAX_FUNC_NUM_OFF)
Offset
Register Offset
TIMER_CTRL_MAX_FU 718h
NC_NUM_OFF

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 FAST_LINK_SC TIMER_MOD_REPLAY_
UPDATE_FREQ_TIMER TIMER_MOD_ACK_NAK
W ALI... TIMER
Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R TIMER_MOD_R 0
MAX_FUNC_NUM
W EPLA...
Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31 Reserved
Fast Link Timer Scaling Factor. Sets the scaling factor of LTSSM timer when FAST_LINK_MODE field in
30-29
PORT_LINK_CTRL_OFF is set to '1'. - 0: Scaling Factor is 1024 (1ms is 1us) - 1: Scaling Factor is 256
FAST_LINK_SC (1ms is 4us) - 2: Scaling Factor is 64 (1ms is 16us) - 3: Scaling Factor is 16 (1ms is 64us) Default is set
ALING_FACTO by the hidden configuration parameter DEFAULT_FAST_LINK_SCALING_FACTOR which defaults to '0'.
R Note: This register field is sticky.
28-24 UPDATE_FREQ_TIMER is an internally reserved field. Do not use.
UPDATE_FRE
Q_TIMER
23-19 Ack latency timer modifier

TIMER_MOD_A Increases the timer value for the Ack latency timer in increments of 64 clock cycles. A value of "0" represents
CK_NAK no modification to the timer value. For more details, see the ROUND_TRIP_LATENCY_TIME_LIMIT field of
the ACK_LATENCY_TIMER_OFF register.
18-14 Replay timer limit modifier

TIMER_MOD_R Increases the time-out value for the replay timer in increments of 64 clock cycles at Gen1 or Gen2 speed,
EPLAY_TIMER and in increments of 256 clock cycles at Gen3 speed. A value of "0" represents no modification to the timer
limit. For more details, see the REPLAY_TIME_LIMIT field of the ACK_LATENCY_TIMER_OFF register.
At Gen3 speed, the controller automatically changes the value of this field
to DEFAULT_GEN3_REPLAY_ADJ.
13-8 Reserved
7-0 Maximum function number that can be used in a request

NXP Semiconductors
PCIe Controller
Field Function
MAX_FUNC_N Configuration requests targeted at function numbers above this value are returned with UR
UM (unsupported request).
3.7.121 Symbol Timer and Filter Mask 1 (SYMBOL_TIMER_FILTER_1_OFF)
Offset
Register Offset
SYMBOL_TIMER_FILTE 71Ch
R_1_OFF
Function
Modifies the RADM filtering and error handling rules. For more details, see the following table and Receive filtering†. In each case,
'0' applies the associated filtering rule and '1' masks the associated filtering rule.
Table 11. MASK_RADM_1 field details
Bit position in Rule field name Values and description

MASK_RAD
M_1
15 CX_FLT_MASK_RC_CFG_DISCARD 0: For RADM RC filter to not allow CFG transaction

being received
1: For RADM RC filter to allow CFG transaction being received
14 CX_FLT_MASK_RC_IO_DISCARD 0: For RADM RC filter to not allow IO transaction being received

1: For RADM RC filter to allow IO transaction being received
13 CX_FLT_MASK_MSG_DROP 0: Drop MSG TLP (except for Vendor MSG). Send decoded
message on the SII.
1: Do not Drop MSG (except for Vendor MSG). Send message
TLPs to your application on TRGT1 and send decoded
message on the SII.
The default for this bit is the inverse of FLT_DROP_MSG. That
is, if FLT_DROP_MSG =1, then the default of this bit is "0"
(drop message TLPs). This bit only controls message TLPs
other than Vendor MSGs. Vendor MSGs are controlled by Filter
Mask Register 2, bits [1:0].
The controller never passes ATS Invalidate messages to the
SII interface regardless of this filter rule setting. The controller
passes all ATS Invalidate messages to TRGT1 (or AXI bridge
master), as they are too big for the SII.

NXP Semiconductors
PCIe Controller
Table 11. MASK_RADM_1 field details (continued)

MASK_RAD
M_1
12 CX_FLT_MASK_CPL_ECRC_DISCARD Only used when completion queue is advertised with infinite

credits and is in store-and-forward mode.
0: Discard completions with ECRC errors
1: Allow completions with ECRC errors to be passed up
Reserved field for SW.
11 CX_FLT_MASK_ECRC_DISCARD 0: Discard TLPs with ECRC errors

1: Allow TLPs with ECRC errors to be passed up
10 CX_FLT_MASK_CPL_LEN_MATCH 0: Enforce length match for completions; a violation results in

cpl_abort, and possibly AER of unexp_cpl_err
1: MASK length match for completions
9 CX_FLT_MASK_CPL_ATTR_MATCH 0: Enforce attribute match for completions; a violation results

in a malformed TLP error, and possibly AER of unexp_cpl_err,
cpl_rcvd_ur, cpl_rcvd_ca
1: Mask attribute match for completions
8 CX_FLT_MASK_CPL_TC_MATCH 0: Enforce Traffic Class match for completions; a violation

results in a malformed TLP error, and possibly AER of
unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca
1: Mask Traffic Class match for completions
7 CX_FLT_MASK_CPL_FUNC_MATCH 0: Enforce function match for completions; a violation

results in cpl_abort, and possibly AER of unexp_cpl_err,
1: Mask function match for completions
6 CX_FLT_MASK_CPL_REQID_MATCH 0: Enforce Req. Id match for completions; a violation

result in cpl_abort, and possibly AER of unexp_cpl_err,
1: Mask Req. Id match for completions
5 CX_FLT_MASK_CPL_TAGERR_MATCH 0: Enforce Tag Error Rules for completions; a violation

result in cpl_abort, and possibly AER of unexp_cpl_err,
1: Mask Tag Error Rules for completions
4 CX_FLT_MASK_LOCKED_RD_AS_UR 0: Treat locked Read TLPs as UR for EP; Supported for RC

1: Treat locked Read TLPs as Supported for EP; UR for RC
3 CX_FLT_MASK_CFG_TYPE1_REQ_AS_UR 0: Treat CFG type1 TLPs as UR for EP; Supported for RC

1: Treat CFG type1 TLPs as Supported for EP; UR for RC

NXP Semiconductors
PCIe Controller

MASK_RAD
M_1
When CX_SRIOV_ENABLE is set then this bit is set to allow

the filter to process Type 1 Config requests if the EP consumes
more than one bus number.
2 CX_FLT_MASK_UR_OUTSIDE_BAR 0: Treat out-of-bar TLPs as UR

1: Do not treat out-of-bar TLPs as UR
1 CX_FLT_MASK_UR_POIS 0: Treat poisoned request TLPs as UR

1: Do not treat poisoned request TLPs as UR
The native controller always passes poisoned completions
to your application except when you are using the DMA
read channel.
0 CX_FLT_MASK_UR_FUNC_MISMATCH 0: Treat Function MisMatched TLPs as UR

1: Do not treat Function MisMatched TLPs as UR
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MASK_RADM_1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DISAB
EIDLE_TIMER SKP_INT_VAL
W LE...
Reset 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0
Fields
Field Function
31-16 Filter Mask 1

MASK_RADM_ The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details, see Table
1 11 and Receive filtering†. In each case, '0' applies the associated filtering rule and '1' masks the associated
filtering rule.
15 Disable FC Watchdog Timer. Note: This register field is sticky.
DISABLE_FC_
WD_TIMER

NXP Semiconductors
PCIe Controller
Field Function
14-11 EIDLE_TIMER is an internally reserved field. Do not use. Note: This register field is sticky.
EIDLE_TIMER
10-0 SKP Interval Value. The number of symbol times to wait between transmitting SKP ordered sets. Note
that the controller actually waits the number of symbol times in this register plus 1 between transmitting
SKP_INT_VAL SKP ordered sets. Your application must program this register accordingly. For example, if 1536 were
programmed into this register (in a 250 MHz controller), then the controller actually transmits SKP
ordered sets once every 1537 symbol times. The value programmed to this register is actually clock
ticks and not symbol times. In a 125 MHz controller, programming the value programmed to this register
should be scaled down by a factor of 2 (because one clock tick = two symbol times in this case). Note:
This value is not used at Gen3 speed; the skip interval is hardcoded to 370 blocks. Note: This register
field is sticky.
3.7.122 Filter Mask 2 (FILTER_MASK_2_OFF)
Offset
Register Offset
FILTER_MASK_2_OFF 720h
Function
Modifies the RADM filtering and error handling rules. For more details, see the following table and Receive filtering†. In each case,
'0' applies the associated filtering rule and '1' masks the associated filtering rule.
Table 12. MASK_RADM_2 field details

MASK_RAD
M_2
31–8 — Reserved
7 CX_FLT_MASK_PRS_DROP 0: Allow PRS message to pass through

1: Drop PRS Messages silently
This bit is ignored when the CX_FLT_MASK_MSG_DROP
bit in the MASK_RADM_1 field of the
SYMBOL_TIMER_FILTER_1_OFF register is set to '1'.
6 CX_FLT_UNMASK_TD 0: Disable unmask TD bit if CX_STRIP_ECRC_ENABLE

1: Enable unmask TD bit if CX_STRIP_ECRC_ENABLE
5 CX_FLT_UNMASK_UR_POIS_TRGT0 0: Disable unmask CX_FLT_MASK_UR_POIS with

TRGT0 destination
1: Enable unmask CX_FLT_MASK_UR_POIS with
TRGT0 destination

NXP Semiconductors
PCIe Controller

MASK_RAD
M_2
4 CX_FLT_MASK_LN_VENMSG1_DROP 0: Allow LN message to pass through

1: Drop LN Messages silently
3 CX_FLT_MASK_HANDLE_FLUSH 0: Disable controller Filter to handle flush request

1: Enable controller Filter to handle flush request
2 CX_FLT_MASK_DABORT_4UCPL 0: Enable DLLP abort for unexpected completion

1: Do not enable DLLP abort for unexpected completion
1 CX_FLT_MASK_DABORT_4UCPL 0: Vendor MSG Type 1 dropped silently

1: Vendor MSG Type 1 not dropped
0 CX_FLT_MASK_VENMSG0_DROP 0: Vendor MSG Type 0 dropped with UR error reporting

1: Vendor MSG Type 0 not dropped
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MASK_RADM_2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MASK_RADM_2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0 Filter Mask 2

MASK_RADM_ Modifies the RADM filtering and error handling rules. For more details, see Table 12 and Receive filtering†.
2 In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule.

NXP Semiconductors
PCIe Controller
3.7.123 AMBA Multiple Outbound Decomposed NP SubRequests Control

Offset
Register Offset
AMBA_MUL_OB_DECO 724h
MP_NP_SUB_REQ_CTR
L_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 OB_R
W D_S...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Fields
Field Function
31-1 Reserved
0Enable AMBA Multiple Outbound Decomposed NP SubRequests. This bit when set to "0" disables the
possibility of having multiple outstanding non-posted requests that were derived from decomposition
OB_RD_SPLIT_ of an outbound AMBA request. You should not clear this register unless your application master is
BURST_EN requesting an amount of read data greater than Max_Read_Request_Size, and the remote device (or
switch) is reordering completions that have different tags. Note: The access attributes of this field are as
follows: - Wire: R/W (sticky) Note: This register field is sticky.
3.7.124 Debug Register 0 (PL_DEBUG0_OFF)
Offset
Register Offset
PL_DEBUG0_OFF 728h

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R DEB_REG_0
Reset u u u u u u u u u u u u u u u u
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DEB_REG_0
Fields
Field Function
31-0 Debug Field 0

DEB_REG_0 The bits in this field have the following meaning:
Bits 31:26: Reserved
Bit 25: Receiver is receiving logical idle
Bit 24: 2n symbol is also idle (16bit PHY interface only)
Bits 23:8: PIPE transmit data
Bits 7:6: PIPE transmit K indication
Bits 5:0: LTSSM current state
Offset
Register Offset
PL_DEBUG1_OFF 72Ch
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R DEB_REG_1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DEB_REG_1

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-0 Debug Field 1

DEB_REG_1 The bits in this field have the following meaning:
Bit 31: Scrambling disabled for the link
Bit 30: TSSM in DISABLE state; link inoperable
Bit 29: LTSSM performing link training
Bit 28: LTSSM is in Polling.Configuration state
Bit 27: LTSSM-negotiated link reset
Bit 22: Reserved
Bit 21: PIPE transmit electrical idle request
Bit 20: PIPE transmit compliance request
Bit 19: Application request to initiate training reset
Bits 18:6: Reserved
Bit 5: A skip ordered set has been transmitted
Bit 4: LTSSM reports PHY link up or LTSSM is in Loopback.Active for Loopback Master
Bits 3:0: Reserved
3.7.126 Transmit Posted FC Credit Status (TX_P_FC_CREDIT_STATUS_OFF)
Offset
Register Offset
TX_P_FC_CREDIT_STA 730h
TUS_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 TX_P_HEADER_FC_CREDIT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R TX_P_HEADER_FC_CREDIT TX_P_DATA_FC_CREDIT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-20 Reserved
Transmit Posted Header FC Credits. The posted Header credits advertised by the receiver at the
19-12
other end of the link, updated with each UpdateFC DLLP. Default value depends on the number
TX_P_HEADER of advertised credits for header and data [12'b0, xtlh_xadm_ph_cdts, xtlh_xadm_pd_cdts]; When the
_FC_CREDIT number of advertised completion credits (both header and data) are infinite, then the default would be
[12'b0, 8'hFF, 12'hFFF].
Transmit Posted Data FC Credits. The posted Data credits advertised by the receiver at the other end of
11-0
the link, updated with each UpdateFC DLLP. Default value depends on the number of advertised credits
TX_P_DATA_F for header and data [12'b0, xtlh_xadm_ph_cdts, xtlh_xadm_pd_cdts]; When the number of advertised
C_CREDIT completion credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].
3.7.127 Transmit Non-Posted FC Credit Status (TX_NP_FC_CREDIT_STATUS_OFF)
Offset
Register Offset
TX_NP_FC_CREDIT_ST 734h
ATUS_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 TX_NP_HEADER_FC_CREDIT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R TX_NP_HEADER_FC_CREDIT TX_NP_DATA_FC_CREDIT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-20 Reserved
19-12 Transmit Non-Posted Header FC Credits. The non-posted Header credits advertised by the receiver at
the other end of the link, updated with each UpdateFC DLLP. Default value depends on the number

NXP Semiconductors
PCIe Controller
Field Function
TX_NP_HEADE of advertised credits for header and data [12'b0, xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts]; When the
R_FC_CREDIT number of advertised completion credits (both header and data) are infinite, then the default would be
[12'b0, 8'hFF, 12'hFFF].
Transmit Non-Posted Data FC Credits. The non-posted Data credits advertised by the receiver at the
11-0
other end of the link, updated with each UpdateFC DLLP. Default value depends on the number of
TX_NP_DATA_ advertised credits for header and data [12'b0, xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts]; When the
FC_CREDIT number of advertised completion credits (both header and data) are infinite, then the default would be
[12'b0, 8'hFF, 12'hFFF].
3.7.128 Transmit Completion FC Credit Status (TX_CPL_FC_CREDIT_STATUS_OFF)
Offset
Register Offset
TX_CPL_FC_CREDIT_S 738h
TATUS_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 TX_CPL_HEADER_FC_CREDIT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R TX_CPL_HEADER_FC_CREDIT TX_CPL_DATA_FC_CREDIT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-20 Reserved
Transmit Completion Header FC Credits. The Completion Header credits advertised by the receiver at
19-12
TX_CPL_HEAD of advertised credits for header and data [12'b0, xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts]; When the
ER_FC_CREDI number of advertised completion credits (both header and data) are infinite, then the default would be
T [12'b0, 8'hFF, 12'hFFF].

NXP Semiconductors
PCIe Controller
Field Function
Transmit Completion Data FC Credits. The Completion Data credits advertised by the receiver at the
11-0
TX_CPL_DATA advertised credits for header and data [12'b0, xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts]; When the
[12'b0, 8'hFF, 12'hFFF].
3.7.129 Queue Status (QUEUE_STATUS_OFF)
Offset
Register Offset
QUEUE_STATUS_OFF 73Ch
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R TIMER 0
TIMER_MOD_FLOW_CONTROL
W _M...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX_SE RX_SE RX_SE RX_Q RX_Q TX_RE RX_TL

R 0
RI... RI... RI... UEU... UEU... TR... P_...
W W1C W1C W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
FC Latency Timer Override Enable. When this bit is set, the value from the "FC Latency Timer Override
31
Value" field in this register will override the FC latency timer value that the controller calculates according
TIMER_MOD_F to the PCIe specification. Note: This register field is sticky.
LOW_CONTRO
L_EN
30-29 Reserved
FC Latency Timer Override Value. When you set the "FC Latency Timer Override Enable" in this register,
28-16
the value in this field will override the FC latency timer value that the controller calculates according to
TIMER_MOD_F the PCIe specification. For more details, see "Flow Control". Note: This register field is sticky.
LOW_CONTRO
L

NXP Semiconductors
PCIe Controller
Field Function
15 Receive Serialization Read Error. Indicates the serialization queue has attempted to read an incorrectly
formatted TLP.
RX_SERIALIZA
TION_Q_READ
_ERR
14 Receive Serialization Queue Write Error. Indicates insufficient buffer space available to write to the
serialization queue.
RX_SERIALIZA
TION_Q_WRIT
E_ERR
13 Receive Serialization Queue Not Empty. Indicates there is data in the serialization queue.
RX_SERIALIZA
TION_Q_NON_
EMPTY
12-4 Reserved
3 Receive Credit Queue Overflow. Indicates insufficient buffer space available to write to the P/NP/CPL
credit queue.
RX_QUEUE_O
VERFLOW
2 Receive Credit Queue Not Empty. Indicates there is data in one or more of the receive buffers.
RX_QUEUE_N
ON_EMPTY
1 Transmit Retry Buffer Not Empty. Indicates that there is data in the transmit retry buffer.
TX_RETRY_BU
FFER_NE
0 Received TLP FC Credits Not Returned. Indicates that the controller has received a TLP but has not yet
sent an UpdateFC DLLP indicating that the credits for that TLP have been restored by the receiver at the
RX_TLP_FC_C other end of the link.
REDIT_NON_R
ETURN
3.7.130 VC Transmit Arbitration Register 1 (VC_TX_ARBI_1_OFF)
Offset
Register Offset
VC_TX_ARBI_1_OFF 740h

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R WRR_WEIGHT_VC_3 WRR_WEIGHT_VC_2
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
Fields
Field Function
31-24 WRR Weight for VC3. Note: The access attributes of this field are as follows: - Wire: R
WRR_WEIGHT
_VC_3
WRR_WEIGHT
_VC_2
WRR_WEIGHT
_VC_1
WRR_WEIGHT
_VC_0
Offset
Register Offset

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
WRR_WEIGHT
_VC_7
WRR_WEIGHT
_VC_6
WRR_WEIGHT
_VC_5
WRR_WEIGHT
_VC_4
3.7.132 Segmented-Buffer VC0 Posted Receive Queue Control. (VC0_P_RX_Q_CTRL_OFF)
Offset
Register Offset
VC0_P_RX_Q_CTRL_O 748h
FF

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R VC_O TLP_T VC0_P_DATA_ VC0_P_HDR_S RESE VC0_P_HEADER_CREDIT

RESERVED5 VC0_P_TLP_Q_MODE
W RDE... YP... SCALE CALE RVE...
Reset 0 1 0 0 0 1 0 1 0 0 1 0 0 0 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VC0_P_HEADER_CREDIT VC0_P_DATA_CREDIT
Reset 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0
Fields
Field Function
31 VC Ordering for Receive Queues. Determines the VC ordering rule for the receive queues, used only in
the segmented-buffer configuration: - 1: Strict ordering, higher numbered VCs have higher priority - 0:
VC_ORDERIN Round robin Note: This register field is sticky.
G_RX_Q
TLP Type Ordering for VC0. Determines the TLP type ordering rule for VC0 receive queues, used only in
30
the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted,
TLP_TYPE_OR completion, then non-posted Note: This register field is sticky.
DERING_VC0
29-28 Reserved Note: This register field is sticky.
RESERVED5
27-26 VC0 Scale Posted Data Credites. Note: This register field is sticky.
VC0_P_DATA_
SCALE
25-24 VC0 Scale Posted Header Credites. Note: This register field is sticky.
VC0_P_HDR_S
CALE
VC0_P_TLP_Q_
MODE
20 Reserved Note: This register field is sticky.
RESERVED4
VC0 Posted Header Credits. The number of initial posted header credits for VC0, used only in the
19-12
segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: R (sticky)
VC0_P_HEADE Note: This register field is sticky.
R_CREDIT

NXP Semiconductors
PCIe Controller
Field Function
VC0 Posted Data Credits. The number of initial posted data credits for VC0, used only in the segmented-
11-0
buffer configuration. Note: The access attributes of this field are as follows: - Wire: R (sticky) Note: This
VC0_P_DATA_ register field is sticky.
CREDIT
3.7.133 Segmented-Buffer VC0 Non-Posted Receive Queue Control. (VC0_NP_RX_Q_CTRL_OFF)
Offset
Register Offset
VC0_NP_RX_Q_CTRL_ 74Ch
OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R VC0_NP_DATA VC0_NP_HDR_ RESE VC0_NP_HEADER_CREDIT

RESERVED7 VC0_NP_TLP_Q_MODE
W _SCA... SCALE RVE...
Reset 0 0 0 0 0 1 0 1 0 0 1 0 0 0 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VC0_NP_HEADER_CREDIT VC0_NP_DATA_CREDIT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0
Fields
Field Function
RESERVED7
27-26 VC0 Scale Non-Posted Data Credites. Note: This register field is sticky.
VC0_NP_DATA
_SCALE
25-24 VC0 Scale Non-Posted Header Credites. Note: This register field is sticky.
VC0_NP_HDR_
SCALE

NXP Semiconductors
PCIe Controller
Field Function
VC0_NP_TLP_
Q_MODE
RESERVED6
VC0 Non-Posted Header Credits. The number of initial non-posted header credits for VC0, used only
19-12
in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: R
VC0_NP_HEAD (sticky) Note: This register field is sticky.
ER_CREDIT
VC0 Non-Posted Data Credits. The number of initial non-posted data credits for VC0, used only in the
11-0
VC0_NP_DATA Note: This register field is sticky.
_CREDIT
3.7.134 Segmented-Buffer VC0 Completion Receive Queue Control. (VC0_CPL_RX_Q_CTRL_OFF)
Offset
Register Offset
VC0_CPL_RX_Q_CTRL_ 750h
OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R VC0_CPL_DAT VC0_CPL_HDR VC0_CPL_TLP_Q_MOD RESE VC0_CPL_HEADER_CREDIT

RESERVED9
W A_SC... _SCA... E RVE...
Reset 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VC0_CPL_HEADER_CREDIT VC0_CPL_DATA_CREDIT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
RESERVED9

NXP Semiconductors
PCIe Controller
Field Function
27-26 VC0 Scale CPL Data Credites. Note: This register field is sticky.
VC0_CPL_DAT
A_SCALE
25-24 VC0 Scale CPL Header Credites. Note: This register field is sticky.
VC0_CPL_HDR
_SCALE
VC0_CPL_TLP_
Q_MODE
RESERVED8
VC0 Completion Header Credits. The number of initial Completion header credits for VC0, used only
19-12
in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: R
VC0_CPL_HEA (sticky) Note: This register field is sticky.
DER_CREDIT
VC0 Completion Data Credits. The number of initial Completion data credits for VC0, used only in the
11-0
VC0_CPL_DAT Note: This register field is sticky.
A_CREDIT
3.7.135 Link Width And Speed Change Control (GEN2_CTRL_OFF)
Offset
Register Offset
GEN2_CTRL_OFF 80Ch
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 GEN1_ SEL_D CONFI CONFI DIREC AUTO
W EI... EE... G_... G_... T_... _LA...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
PRE_DET_LANE NUM_OF_LANES FAST_TRAINING_SEQ
W
Reset 0 0 0 0 0 0 1 0 1 0 1 1 0 1 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-22 Reserved
21 Electrical Idle Inference Mode at Gen1 Rate. Programmable mode to determine inferred electrical idle
(EI) in Recovery.Speed or Loopback.Active (as slave) state at Gen1 speed by looking for a "1" value
GEN1_EI_INFE on RxElecIdle instead of looking for a "0" on RxValid. If the PHY fails to deassert the RxValid signal
RENCE in Recovery.Speed or Loopback.Active (because of corrupted EIOS for example), then EI cannot be
inferred successfully in the controller by just detecting the condition RxValid=0. - 0: Use RxElecIdle
signal to infer Electrical Idle - 1: Use RxValid signal to infer Electrical Idle Note: This register field is
sticky.
20 Used to set the de-emphasis level for upstream ports. This bit selects the level of de-emphasis the link
operates at. - 0: -6 dB - 1: -3.5 dB Note: The access attributes of this field are as follows: - Wire: R/W
SEL_DEEMPH (sticky) Note: This register field is sticky.
ASIS
19 Config Tx Compliance Receive Bit. When set to 1, signals LTSSM to transmit TS ordered sets with the
compliance receive bit assert (equal to "1"). Note: The access attributes of this field are as follows: -
CONFIG_TX_C Wire: R/W (sticky) Note: This register field is sticky.
OMP_RX
18 Config PHY Tx Swing. Controls the PHY transmitter voltage swing level. The controller drives the
mac_phy_txswing output from this register bit field. - 0: Full Swing - 1: Low Swing Note: The access
CONFIG_PHY_ attributes of this field are as follows: - Wire: R/W (sticky) Note: This register field is sticky.
TX_CHANGE
17 Directed Speed Change. Writing "1" to this field instructs the LTSSM to initiate a speed change
to Gen2 or Gen3 after the link is initialized at Gen1 speed. When the speed change occurs, the
DIRECT_SPEE controller will clear the contents of this field; and a read to this field by your software will return
D_CHANGE a "0". To manually initiate the speed change: - Write to LINK_CONTROL2_LINK_STATUS2_REG .
PCIE_CAP_TARGET_LINK_SPEED in the local device - Deassert this field - Assert this field If you set
the default of this field using the DEFAULT_GEN2_SPEED_CHANGE configuration parameter to "1",
then the speed change is initiated automatically after link up, and the controller clears the contents
of this field. If you want to prevent this automatic speed change, then write a lower speed value to
the Target Link Speed field of the Link Control 2 register (LINK_CONTROL2_LINK_STATUS2_OFF .
PCIE_CAP_TARGET_LINK_SPEED) through the DBI before link up. Note: The access attributes of this
field are as follows: - Wire: R/W
16 Enable Auto Flipping Of The Lanes

AUTO_LANE_F For more details, see Lane reversal and flipping†.
LIP_CTRL_EN
Note: The access attributes of this field are as follows:
- Wire: R/W (sticky)
15-13 Predetermined Lane For Auto Flip

PRE_DET_LAN This field defines which physical lane is connected to logical Lane0 by the flip operation performed in Detect.
E Allowed values are shown below.

NXP Semiconductors
PCIe Controller
Field Function
This field is used to restrict the receiver detect procedure to a particular lane when the default detect and
polling procedure performed on all lanes cannot be successful. A notable example of when it is useful to
program this field to a value different from the default, is when a lane is asymmetrically broken, that is, it is
detected in Detect LTSSM state but it cannot exit Electrical Idle in Polling LTSSM state.
000b - Connect logical Lane0 to physical lane 0 or 1, depending on which lane is detected
001b - Connect logical Lane0 to physical lane 1
12-8 Predetermined Number of Lanes. Defines the number of lanes which are connected and not bad. Used
to limit the effective link width to ignore 'broken" or "unused" lanes that detect a receiver. Indicates the
NUM_OF_LAN number of lanes to check for exit from Electrical Idle in Polling.Active and L2.Idle. It is possible that the
ES LTSSM might detect a receiver on a bad or broken lane during the Detect Substate. However, it is also
possible that such a lane might also fail to exit Electrical Idle and therefore prevent a valid link from being
configured. This value is referred to as the "Predetermined Number of Lanes" in section 4.2.6.2.1 of the
PCI Express Base 3.0 Specification, revision 1.0. Encoding is as follows: - 0x01: 1 lane - 0x02: 2 lanes
- 0x03: 3 lanes - .. When you have unused lanes in your system, then you must change the value in
this register to reflect the number of lanes. You must also change the value in the "Link Mode Enable"
field of PORT_LINK_CTRL_OFF. The value in this register is normally the same as the encoded value in
PORT_LINK_CTRL_OFF. If you find that one of your used lanes is bad then you must reduce the value
in this register. For more information, see "How to Tie Off Unused Lanes." For information on upsizing
and downsizing the link width, see "Link Establishment." Note: The access attributes of this field are as
follows: - Wire: R/W (sticky) Note: This register field is sticky.
7-0 Sets the Number of Fast Training Sequences (N_FTS) that the controller advertises as its N_FTS during
Gen2 or Gen3 link training. This value is used to inform the link partner about the PHY's ability to recover
FAST_TRAININ synchronization after a low power state. The number should be provided by the PHY vendor. Do not
G_SEQ set N_FTS to zero; doing so can cause the LTSSM to go into the recovery state when exiting from L0s.
Note: The access attributes of this field are as follows: - Wire: R/W (sticky) Note: This register field is
sticky.
3.7.136 PHY status (PHY_STATUS_OFF)
Offset
Register Offset
PHY_STATUS_OFF 810h
Function
This is a memory-mapped register from the phy_cfg_status GPIO input pins.

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R PHY_STATUS
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R PHY_STATUS
Fields
Field Function
31-0 PHY status

PHY_STATUS Data received directly from the phy_cfg_status bus.
This is a GPIO register reflecting the values on the static phy_cfg_status input signals. The usage is left
completely to the user and does not in any way influence controller functionality. You can use it for any static
sideband status signalling requirements that you have for your PHY.
3.7.137 PHY control (PHY_CONTROL_OFF)
Offset
Register Offset
PHY_CONTROL_OFF 814h
Function
This is a memory-mapped register for the cfg_phy_control GPIO output pins.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
PHY_CONTROL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
PHY_CONTROL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
PHY Control. Data sent directly to the cfg_phy_control bus. These is a GPIO register driving the values
31-0
on the static cfg_phy_control output signals. The usage is left completely to the user and does not
PHY_CONTRO in any way influence controller functionality. You can use it for any static sideband control signalling
L requirements that you have for your PHY. Note: This register field is sticky.
3.7.138 Programmable target map control (TRGT_MAP_CTRL_OFF)
Offset
Register Offset
TRGT_MAP_CTRL_OFF 81Ch
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R TARGET_MAP_RESERVED_21_31
TARGET_MAP_INDEX
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TARGET_MAP_RESER
R 0 TARG
VED_13_... TARGET_MAP_PF
ET_...
W
Reset 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 1
Fields
Field Function
31-21 Reserved Note: The access attributes of this field are as follows: - Wire: RSVDP
TARGET_MAP_
RESERVED_21
_31
20-16 The number of the PF Function on which the Target Values are set. This register does not respect the
Byte Enable setting. any write will affect all register bits.
TARGET_MAP_
INDEX
15-13 Reserved Note: The access attributes of this field are as follows: - Wire: RSVDP
TARGET_MAP_
RESERVED_13
_15

NXP Semiconductors
PCIe Controller
Field Function
12-7 Reserved
6 Target Value for the ROM page of the PF Function selected by the index number. This register does not
respect the Byte Enable setting. any write will affect all register bits.
TARGET_MAP_
ROM
5-0 Target Values for each BAR on the PF Function selected by the index number. This register does not
TARGET_MAP_
PF
3.7.139 Integrated MSI Reception Module (iMRM) address (MSI_CTRL_ADDR_OFF)
Offset
Register Offset
MSI_CTRL_ADDR_OFF 820h
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MSI_CTRL_ADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MSI_CTRL_ADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
iMRM address. System specified address for MSI memory write transaction termination. Within the AXI
31-0
Bridge, every received Memory Write request is examined to see if it targets the MSI Address that has
MSI_CTRL_AD been specified in this register; and also to see if it satisfies the definition of an MSI interrupt request.
DR When these conditions are satisfied the Memory Write request is marked as an MSI request. Note: This

NXP Semiconductors
PCIe Controller
3.7.140 iMRM Upper Address (MSI_CTRL_UPPER_ADDR_OFF)
Offset
Register Offset
MSI_CTRL_UPPER_AD 824h
DR_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MSI_CTRL_UPPER_ADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MSI_CTRL_UPPER_ADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0 iMRM upper address. System specified upper address for MSI memory write transaction termination.
Allows functions to support a 64-bit MSI address. Note: This register field is sticky.
MSI_CTRL_UP
PER_ADDR
3.7.141 iMRM Interrupt #0 Enable (MSI_CTRL_INT_0_EN_OFF)
Offset
Register Offset
MSI_CTRL_INT_0_EN_O 828h
FF

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MSI_CTRL_INT_0_EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MSI_CTRL_INT_0_EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
MSI Interrupt #0 Enable. Specifies which interrupts are enabled. When an MSI is received from a
31-0
disabled interrupt, no status bit gets set in MSI controller interrupt status register. Each bit corresponds
MSI_CTRL_INT to a single MSI Interrupt Vector. Note: This register field is sticky.
_0_EN
3.7.142 iMRM Interrupt #0 Mask (MSI_CTRL_INT_0_MASK_OFF)
Offset
Register Offset
MSI_CTRL_INT_0_MAS 82Ch
K_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MSI_CTRL_INT_0_MASK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MSI_CTRL_INT_0_MASK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
MSI Interrupt #0 Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked
31-0
interrupt, the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is
MSI_CTRL_INT not set HIGH. Each bit corresponds to a single MSI Interrupt Vector. Note: This register field is sticky.
_0_MASK
3.7.143 iMRM Interrupt #0 Status (MSI_CTRL_INT_0_STATUS_OFF)
Offset
Register Offset
MSI_CTRL_INT_0_STAT 830h
US_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R MSI_CTRL_INT_0_STATUS
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
MSI Interrupt #0 Status. When an MSI is detected for EP#i, one bit in this register is set. The decoding
31-0
of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is
MSI_CTRL_INT cleared by writing a 1 to the bit. Each bit corresponds to a single MSI Interrupt Vector.
_0_STATUS
Offset
Register Offset
FF

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MSI_CTRL_INT_1_EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MSI_CTRL_INT_1_EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0
_1_EN
Offset
Register Offset
MSI_CTRL_INT_1_MAS 838h
K_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MSI_CTRL_INT_1_MASK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MSI_CTRL_INT_1_MASK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-0
_1_MASK
Offset
Register Offset
MSI_CTRL_INT_1_STAT 83Ch
US_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0
_1_STATUS
Offset
Register Offset
FF

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MSI_CTRL_INT_2_EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MSI_CTRL_INT_2_EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0
_2_EN
Offset
Register Offset
K_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MSI_CTRL_INT_2_MASK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MSI_CTRL_INT_2_MASK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-0
_2_MASK
Offset
Register Offset
US_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0
_2_STATUS
Offset
Register Offset
MSI_CTRL_INT_3_EN_O 84Ch
FF

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MSI_CTRL_INT_3_EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MSI_CTRL_INT_3_EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0
_3_EN
Offset
Register Offset
K_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MSI_CTRL_INT_3_MASK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MSI_CTRL_INT_3_MASK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-0
_3_MASK
Offset
Register Offset
US_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0
_3_STATUS
Offset
Register Offset
FF

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MSI_CTRL_INT_4_EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MSI_CTRL_INT_4_EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0
_4_EN
Offset
Register Offset
K_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MSI_CTRL_INT_4_MASK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MSI_CTRL_INT_4_MASK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-0
_4_MASK
Offset
Register Offset
US_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0
_4_STATUS
Offset
Register Offset
FF

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MSI_CTRL_INT_5_EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MSI_CTRL_INT_5_EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0
_5_EN
Offset
Register Offset
K_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MSI_CTRL_INT_5_MASK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MSI_CTRL_INT_5_MASK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-0
_5_MASK
Offset
Register Offset
US_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0
_5_STATUS
Offset
Register Offset
FF

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MSI_CTRL_INT_6_EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MSI_CTRL_INT_6_EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0
_6_EN
Offset
Register Offset
K_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MSI_CTRL_INT_6_MASK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MSI_CTRL_INT_6_MASK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-0
_6_MASK
Offset
Register Offset
US_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0
_6_STATUS
Offset
Register Offset
FF

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MSI_CTRL_INT_7_EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MSI_CTRL_INT_7_EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0
_7_EN
Offset
Register Offset
K_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MSI_CTRL_INT_7_MASK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MSI_CTRL_INT_7_MASK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-0
_7_MASK
Offset
Register Offset
US_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0
_7_STATUS
3.7.165 iMRM general-purpose IO (MSI_GPIO_IO_OFF)
Offset
Register Offset
MSI_GPIO_IO_OFF 888h

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MSI_GPIO_REG
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MSI_GPIO_REG
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0 MSI GPIO Register. The contents of this register drives the top-level GPIO msi_ctrl_io[31:0] Note: This
MSI_GPIO_RE
G
3.7.166 RADM clock gating enable control (CLOCK_GATING_CTRL_OFF)
Offset
Register Offset
CLOCK_GATING_CTRL 88Ch
_OFF
Function
Using this register you can disable the RADM clock gating feature. The DWC_pcie_clk_rst.v modules uses the en_radm_clk_g
output to gate core_clk and create the radm_clk_g clock input. The controller de-asserts the en_radm_clk_g output when there
is no Rx traffic, Rx queues and pre/post-queue pipelines are empty, RADM completion LUT is empty, and there are no FLR
actions pending. You must set the RADM_CLK_GATING_EN field to enable this functionality; otherwise the en_radm_clk_g
output will always be set to '1'.

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 RADM
W _CL...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Fields
Field Function
31-1 Reserved
0 Enable Radm clock gating feature. - 0: Disable - 1: Enable(default)
RADM_CLK_G
ATING_EN
3.7.167 Gen3 control (GEN3_RELATED_OFF)
Offset
Register Offset
GEN3_RELATED_OFF 890h
Function
There is no Gen3-specific N_FTS field. The N_FTS field in the "Link Width and Speed Change Control Register" is used for
both Gen2 and Gen3 speed modes. There is no Gen3-specific "Directed Speed Change" field. The "Directed Speed Change"
field in the "Link Width and Speed Change Control Register" is used to change to Gen2 or Gen3 speed. A speed change to
Gen3 occurs if (1) the "Directed Speed Change" field is set to "1" and (2) the "Target Link Speed" field in the Link Control 2
Register is set to Gen3. Gen3 support is advertised by both sides of the link during link training.

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 GEN3_ 0 GEN3_ GEN3_ GEN3_
W EQ... DC... DL... EQ...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 RXEQ RXEQ EQ_ EQ_EI EQ_P DISAB 0 GEN3_
W _RG... _PH... REDO EO... HAS... LE... ZR...
Reset 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1
Fields
Field Function
31-24 Reserved
23 Eq InvalidRequest and RxEqEval Different Time Assertion Disable.

GEN3_EQ_INV Disable the assertion of Eq InvalidRequest and RxEqEval at different time.
REQ_EVAL_DI
FF_DISABLE
22-19 Reserved
18 DC Balance Disable
GEN3_DC_BAL Disable DC Balance feature.
ANCE_DISABL
E
17 DLLP Transmission Delay Disable

GEN3_DLLP_X Disable delay transmission of DLLPs before equalization.
MT_DELAY_DI
SABLE
16 Equalization Disable
GEN3_EQUALI Disable equalization feature.
ZATION_DISAB
LE
15-14 Reserved
13 Assert RxEqEval

NXP Semiconductors
PCIe Controller
Field Function
RXEQ_RGRDL When set to '1', the controller as Gen3 EQ master asserts RxEqEval to instruct the PHY to do Rx adaptation
ESS_RXTS and evaluation after a 500ns timeout from a new preset request.
- Wire: see description
0b - mac_phy_rxeqeval asserts after 1us and 2 TS1 received from remote partner.
1b - mac_phy_rxeqeval asserts after 500ns regardless of TS's received or not.
12 Rx Equalization Phase 0/Phase 1 Hold Enable

RXEQ_PH01_E When this bit is set the upstream port holds phase 0 (the downstream port holds phase 1) for 10ms. Holding
N phase 0 or phase 1 can be used to allow sufficient time for Rx Equalization to be performed by the PHY. This
bit is used during Virtex-7 Gen3 equalization. The programmable bits [RXEQ_PH01_EN, EQ_PHASE_2_3]
can be used to obtain the following variations of the equalization procedure:
• 00: Tx equalization only in phase 2/3
• 01: No Tx equalization, no Rx equalization
• 10: Tx equalization in phase 2/3, Rx equalization in phase 0/1
• 11: No Tx equalization, Rx equalization in phase 0/1
11 Equalization Redo Disable

EQ_REDO Disable autonomous mechanism for requesting to redo the equalization process.
10 Equalization EIEOS Count Reset Disable

EQ_EIEOS_CN Disable requesting reset of EIEOS count during equalization.
T
9 Equalization Phase 2 And Phase 3 Disable

EQ_PHASE_2_ This applies to downstream ports only.
3
8 Disable Scrambler For Gen3 and Gen4 Data Rate

DISABLE_SCR The Gen3 and Gen4 scrambler/descrambler within the controller needs to be disabled when the scrambling
AMBLER_GEN function is implemented outside of the controller (for example within the PHY).
_3

NXP Semiconductors
PCIe Controller
Field Function
7-1 Reserved
0 Gen3 Receiver Impedance ZRX-DC Not Compliant

GEN3_ZRXDC_ Receivers that operate at 8.0 GT/s with an impedance other than the range defined by the ZRX-DC
NONCOMPL parameter for 2.5 GT/s (40-60 Ohms) must meet additional behavior requirements in the following
LTSSM states:
• Polling
• Rx_L0s
• L1
• L2
• Disabled
0b - The receiver complies with the ZRX-DC parameter for 2.5 GT/s when operating at 8 GT/s or
higher.
1b - The receiver does not comply with the ZRX-DC parameter for 2.5 GT/s when operating at 8
GT/s or higher.
3.7.168 Gen3 EQ Control (GEN3_EQ_CONTROL_OFF)
Offset
Register Offset
GEN3_EQ_CONTROL_ 8A8h
OFF
Function
Controls equalization for Phase2 in an upstream port (USP), or Phase3 in a downstream port (DSP).

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 GEN3_ GEN3_ GEN3_

GEN3_EQ_PSET_REQ_VEC
W RE... EQ... EQ...
Reset 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

GEN3_EQ_PSET_REQ_VEC GEN3_EQ_FB_MODE
W LO... EQ... EQ...
Reset 1 0 0 1 1 1 1 1 0 1 1 1 0 0 0 1
Fields
Field Function
31-27 Reserved
Request controller to send back-to-back EIEOS in Recovery.RcvrLock state until presets to coefficients
26
mapping is complete. - 0: Do not request - 1: request Note: Gen3 and Gen4 share the same register bit
GEN3_REQ_SE and have the same feature. Note: This register field is sticky.
ND_CONSEC_
EIEOS_FOR_P
SET_MAP
25 GEN3_EQ_PSET_REQ_AS_COEF is an internally reserved field. Do not use. Note: This register field is
sticky.
GEN3_EQ_PSE
T_REQ_AS_CO
EF
24 Include Initial FOM

GEN3_EQ_FO Include or not the FOM feedback from the initial preset evaluation performed in the EQ Master, when finding
M_INC_INITIAL the highest FOM among all preset evaluations.
_EVAL
0b - Do not include
1b - Include
Preset Request Vector. Requesting of Presets during the initial part of the EQ Master Phase. Encoding
23-8
scheme is as follows: Bit [15:0] =0x0: No preset is requested and evaluated in EQ Master Phase. Bit
GEN3_EQ_PSE [i] =1: "Preset=i" is requested and evaluated in EQ Master Phase. - 0000000000000000: No preset be
T_REQ_VEC requested and evaluated in EQ Master Phase - 000000xxxxxxxxx1: Preset 0 is requested and evaluated
in EQ Master Phase - 000000xxxxxxxx1x: Preset 1 is requested and evaluated in EQ Master Phase
- 000000xxxxxxx1xx: Preset 2 is requested and evaluated in EQ Master Phase - 000000xxxxxx1xxx:
Preset 3 is requested and evaluated in EQ Master Phase - 000000xxxxx1xxxx: Preset 4 is requested
and evaluated in EQ Master Phase - 000000xxxx1xxxxx: Preset 5 is requested and evaluated in
EQ Master Phase - 000000xxx1xxxxxx: Preset 6 is requested and evaluated in EQ Master Phase -
000000xx1xxxxxxx: Preset 7 is requested and evaluated in EQ Master Phase - 000000x1xxxxxxxx:

NXP Semiconductors
PCIe Controller
Field Function
Preset 8 is requested and evaluated in EQ Master Phase - 00000x1xxxxxxxxx: Preset 9 is requested

and evaluated in EQ Master Phase - 000001xxxxxxxxxx: Preset 10 is requested and evaluated in EQ
Master Phase - All other encodings: Reserved Note: You must contact your PHY vendor to ensure 24 ms
timeout does not occur in presets requests in EQ master phase, i.e., you must set a proper value to the
GEN3_EQ_PSET_REQ_VEC register so that the EQ tunning for Figure of Merit in the EQ master phase
completes before 24 ms timeout. Note: This register field is sticky.
7 Reserved
6 Support EQ redo and lower rate change: - 0: not support - 1: support Note: Gen3 and Gen4 share the
same register bit and have the same feature. Note: This register field is sticky.
GEN3_LOWER
_RATE_EQ_RE
DO_ENABLE
5 Phase2_3 2 ms Timeout Disable

GEN3_EQ_EVA Determine behavior in Phase2 for USP (Phase3 if DSP) when the PHY does not respond within 2ms to the
L_2MS_DISABL assertion of RxEqEval.
E
0b - Abort the current evaluation, stop any attempt to modify the remote transmitter settings,
Phase2 is terminated by the 24ms timeout
1b - ignore the 2ms timeout and continue as normal. This is used to support PHYs that require
more than 2ms to respond to the assertion of RxEqEval.
4 Behavior After 24 ms Timeout (When Optimal Settings Are Not Found)

GEN3_EQ_PHA For a USP: Determine next LTSSM state from Phase2 after 24ms Timeout
SE23_EXIT_M
• 0: Recovery.Speed
ODE
• 1: Recovery.Equalization.Phase3
When optimal settings are not found then:
• Equalization Phase 2 Successful status bit is not set in the "Link Status Register 2" when
GEN3_EQ_PHASE23_EXIT_MODE = 0
• Equalization Phase 2 Successful status bit is set in the "Link Status Register 2" when
• Equalization Phase 2 Complete status bit is set in the "Link Status Register 2"
For a DSP: Determine next LTSSM state from Phase3 after 24ms Timeout
• 1: Recovery.Equalization.RcvrLock

NXP Semiconductors
PCIe Controller
Field Function
GEN3_EQ_PHASE23_EXIT_MODE = 1 affects Direction Change feed back mode. EQ requests for Figure
Of Merit mode complete before 24 ms timeout. Please see GEN3_EQ_PSET_REQ_VEC Register for more.
3-0 Feedback Mode

GEN3_EQ_FB_ This field is sticky.
MODE
0000b - Direction change
0001b - Figure of merit
3.7.169 Gen3 EQ Direction Change Feedback Mode Control

Offset
Register Offset
GEN3_EQ_FB_MODE_D 8ACh
IR_CHANGE_OFF
Function
Equalization controls to be used in Phase2 (USP) or Phase 3 (DSP), when you set the Feedback Mode in "Gen3 EQ Control
Register" to "Direction Change." These fields allow control over the initial starting point for the search of optimal coefficient
settings, and allow control over the criteria used to determine when the optimal settings have been achieved. The values are
applied to all the lanes.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 GEN3_EQ_FM
W DC_MA...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R GEN3_EQ_FM GEN3_EQ_FMDC_MAX_PRE_CU
GEN3_EQ_FMDC_N_EVALS GEN3_EQ_FMDC_T_MIN_PHASE23
W DC_MA... SROR_DEL...
Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-18 Reserved
17-14 Convergence Window Aperture For C+1

GEN3_EQ_FM Post-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0,1,2,..15.
DC_MAX_POS
T_CUSROR_D
ELTA
13-10 Convergence Window Aperture For C-1

GEN3_EQ_FM Pre-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0,1,2,..15.
DC_MAX_PRE_
CUSROR_DEL
TA
9-5 Convergence Window Depth

GEN3_EQ_FM Number of consecutive evaluations considered in Phase 2/3 when determining if optimal coefficients have
DC_N_EVALS been found. Allowed range: 0,1,2,.. up to a maximum of 8.
When set to 0, EQ Master is performed without sending any requests to the remote partner in Phase 2 for
USP and Phase 3 for DSP. Therefore, the remote partner will not change its transmitter coefficients and will
move to the next state.
4-0 Minimum Time (in ms) To Remain in EQ Master Phase

GEN3_EQ_FM The LTSSM stays in EQ Master phase for at least this amount of time, before starting to check for
DC_T_MIN_PH convergence of the coefficients. Allowed values 0,1,...,24.
ASE23
3.7.170 Order rule control (ORDER_RULE_CTRL_OFF)
Offset
Register Offset
ORDER_RULE_CTRL_O 8B4h
FF

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CPL_PASS_P NP_PASS_P
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-16 Reserved
15-8 Completion Passing Posted Ordering Rule Control. Determines if CPL can pass halted P queue. - 0:
CPL can not pass P (recommended) - 1: CPL can pass P
CPL_PASS_P
7-0 Non-Posted Passing Posted Ordering Rule Control. Determines if NP can pass halted P queue. - 0 : NP
can not pass P (recommended). - 1 : NP can pass P
NP_PASS_P
3.7.171 PIPE loopback control (PIPE_LOOPBACK_CONTROL_OFF)
Offset
Register Offset
PIPE_LOOPBACK_CON 8B8h
TROL_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R PIPE_ 0
RXSTATUS_LANE
W LO...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
LPBK_RXVALID
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

NXP Semiconductors
PCIe Controller
Fields
Field Function
31 PIPE Loopback Enable. Note: This register field is sticky.
PIPE_LOOPBA
CK
30-22 Reserved
21-16 RXSTATUS_LANE is an internally reserved field. Do not use. Note: This register field is sticky.
RXSTATUS_LA
NE
15-0 LPBK_RXVALID is an internally reserved field. Do not use. Note: This register field is sticky.
LPBK_RXVALI
D
3.7.172 DBI Read-Only Write Enable (MISC_CONTROL_1_OFF)
Offset
Register Offset
MISC_CONTROL_1_OF 8BCh
F
Function
Table 13. Other registers and fields affected when MISC_CONTROL_1_OFF[DBI_RO_WR_EN] = 1
Register Fields
Device ID And Vendor ID (DEVICE_VENDOR_ID) All
Class Code And Revision ID (CLASS_CODE_REVISION_ID) All
Capabilities Pointer (CAPPR) CAP_POINTER
SPCIE Capability Header. (SPCIE_CAP_HEADER_REG) All
Lane Equalization Control For Lanes 1 And 0 All

Vendor-Specific Extended Capability Header. All

PCIe Extended Capability ID, Capability Version, And Next Capability All
Power Management Capabilities (PMCAP) • PM_NEXT_POINTER

NXP Semiconductors
PCIe Controller
Table 13. Other registers and fields affected when MISC_CONTROL_1_OFF[DBI_RO_WR_EN] = 1 (continued)
Register Fields
• PM_SPEC_VER
• DSI
• AUX_CURR
• D1_SUPPORT
• D2_SUPPORT
• PME_SUPPORT
Power Management Control And Status (PMCSR) NO_SOFT_RST
Capabilities ID and next pointer (CINCPCR) • CAP_NEXT_PTR

• SLOT_IMP
• INT_MSG_NUM
Device capabilities (DEV_CAPABILITIES) • MAX_PL_SIZE_SUP

• PHAN_FUNC_SUP
• EXT_TAG_SUP
• ROLE_BASED_ERR_REPORT
Link Capabilities (LINK_CAPABILITIES) All
Link Control And Status (LINK_CONTROL_STATUS) • RCB

• SLOT_CLK_CONFIG
Link Control 2 And Status 2 (LINK_CONTROL2_LINK_STATUS2_REG) PCIE_CAP_SEL_DEEMPHASIS
Advanced Error Reporting Extended Capability Header All

PCI Express MSI Message Capability ID (MSI_CIDNC) • CAP_NEXT_PTR

• MULTI_MSG_CAP
• ADDR_CAP_64
• EXT_DATA_CAP
MSI-X Capability ID, Next Pointer, Control • PCI_MSIX_CAP_NEXT_OFFSET

• PCI_MSIX_TABLE_SIZE
MSI-X Table Offset And BIR (MSIX_TABLE_OFFSET_REG) All
MSI-X PBA Offset And BIR (MSIX_PBA_OFFSET_REG) All

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 ARI_D 0 SIMPL UR_C DEFA DBI_R
W EV... IF... A_M... ULT... O_...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-6 Reserved
5 When ARI is enabled, this field enables use of the device ID. Note: This register field is sticky.
ARI_DEVICE_N
UMBER
4 Reserved
3 Enables Simplified Replay Timer (Gen4)

SIMPLIFIED_R Simplified Replay Timer Values are: - A value from 24,000 to 31,000 Symbol Times when Extended
EPLAY_TIMER Synch is 0b. - A value from 80,000 to 100,000 Symbol Times when Extended Synch is 1b. Must not be
changed while link is in use. Note: This register field is sticky.
2 Suppress
UR_CA_MASK_ This field only applies to request TLPs (with UR filtering status) that you have chosen to forward to the
4_TRGT1 application (when you set DEFAULT_TARGET in this register). - When you set this field to '1', the core
suppresses error logging, Error Message generation, and CPL generation (for non-posted requests). You
should set this if you have set the Default Target port logic register to '1'. Note: This register field is
sticky.
1Default target a received IO or MEM request with UR/CA/CRS is sent to by the controller. - 0: The
controller drops all incoming I/O or MEM requests (after corresponding error reporting). A completion
DEFAULT_TAR with UR status will be generated for non-posted requests. - 1: The controller forwards all incoming
GET I/O or MEM requests with UR/CA/CRS status to your application Default value is DEFAULT_TARGET
configuration parameter. Note: This register field is sticky.
0 Write To Read-Only Fields Using DBI

DBI_RO_WR_E When this field is 1, the read-only fields specified in Table 13 become writable from the local application
N through the DBI.

NXP Semiconductors
PCIe Controller
3.7.173 Up-configure multi-lane control (MULTI_LANE_CONTROL_OFF)
Offset
Register Offset
MULTI_LANE_CONTRO 8C0h
L_OFF
Function
Used when upsizing or downsizing the link width through Configuration state without bringing the link down. For more details,
see Link establishment†.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 UPCO DIREC
TARGET_LINK_WIDTH
W NFI... T_...
Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
Fields
Field Function
31-8 Reserved
7 Upconfigure Support. The controller sends this value as the Link Upconfigure Capability in TS2 Ordered
Sets in Configuration.Complete state. Note: This register field is sticky.
UPCONFIGUR
E_SUPPORT
6 Directed Link Width Change. The controller always moves to Configuration state through
Recovery state when this bit is set to '1'. - If the upconfigure_capable variable is '1' and
DIRECT_LINK_ the PCIE_CAP_HW_AUTO_WIDTH_DISABLE bit in LINK_CONTROL_LINK_STATUS_REG is '0', the
WIDTH_CHAN controller starts upconfigure or autonomous width downsizing (to the TARGET_LINK_WIDTH value) in
GE the Configuration state. - If TARGET_LINK_WIDTH value is 0x0, the controller does not start upconfigure
or autonomous width downsizing in the Configuration state. The controller self-clears this field when the
controller accepts this request.
Target Link Width. Values correspond to: - 6'b000000: Core does not start upconfigure or autonomous
5-0
width downsizing in the Configuration state. - 6'b000001: x1 - 6'b000010: x2 - 6'b000100: x4 -
TARGET_LINK 6'b001000: x8 - 6'b010000: x16 - 6'b100000: x32
_WIDTH

NXP Semiconductors
PCIe Controller
3.7.174 PHY interoperability control (PHY_INTEROP_CTRL_OFF)
Offset
Register Offset
PHY_INTEROP_CTRL_ 8C4h
OFF
Function
This register is reserved for internal use. You should not write to this register and change the default unless specifically
instructed by Synopsys support.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
L1_NO
R 0 L1_CL 0
WA... RXSTANDBY_CONTROL
K_...
W
Reset 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0
Fields
Field Function
31-11 Reserved
10 L1 Clock control bit. - 1: Controller does not request aux_clk switch and core_clk gating in L1. - 0:
Controller requests aux_clk switch and core_clk gating in L1. Note: This register field is sticky.
L1_CLK_SEL
9L1 entry control bit. - 1: Core does not wait for PHY to acknowledge transition to P1 before entering
L1. - 0: Core waits for the PHY to acknowledge transition to P1 before entering L1. Note: The access
L1_NOWAIT_P attributes of this field are as follows: - Wire: R/W (sticky) Note: This register field is sticky.
1
8-7 Reserved
6-0 Rxstandby Control. Bits 0..5 determine if the controller asserts the RxStandby signal
(mac_phy_rxstandby) in the indicated condition. Bit 6 enables the controller to perform the RxStandby/
RXSTANDBY_ RxStandbyStatus handshake. - [0]: Rx EIOS and subsequent T TX-IDLE-MIN - [1]: Rate Change - [2]:
CONTROL Inactive lane for upconfigure/downconfigure - [3]: PowerDown=P1orP2 - [4]: RxL0s.Idle - [5]: EI Infer in
L0 - [6]: Execute RxStandby/RxStandbyStatus Handshake Note: This register field is sticky.

NXP Semiconductors
PCIe Controller
3.7.175 TRGT_CPL_LUT Delete Entry Control (TRGT_CPL_LUT_DELETE_ENTRY_OFF)
Offset
Register Offset
TRGT_CPL_LUT_DELE 8C8h
TE_ENTRY_OFF
Function
Using this register you can delete one entry in the target completion LUT. You should only use this register when you know that
your application will never send the completion because of an FLR or any other reason.
The target completion LUT (and associated target completion timeout event) is watching for completions (from your application
on AXI master read channel) corresponding to previously received non-posted requests from the PCIe wire.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DELET
R
E_... LOOK_UP_ID
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
LOOK_UP_ID
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31 This is a one-shot bit. A '1' write to this bit triggers the deletion of the target completion LUT entry that
is specified in the LOOK_UP_ID field. This is a self-clearing register field. Reading from this register field
DELETE_EN always returns a '0'.
30-0 This number selects one entry to delete of the TRGT_CPL_LUT.
LOOK_UP_ID
3.7.176 Link reset request flush control (LINK_FLUSH_CONTROL_OFF)
Offset
Register Offset
LINK_FLUSH_CONTRO 8CCh
L_OFF

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
RSVD_I_8
W
Reset 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 AUTO_
W FL...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Fields
Field Function
31-24 This is an internally reserved field. Do not use. Note: This register field is sticky.
RSVD_I_8
23-1 Reserved
0Enables automatic flushing of pending requests before sending the reset request to the application logic
to reset the PCIe controller and the AXI Bridge. The flushing process is initiated if any of the following
AUTO_FLUSH_ events occur: - Hot reset request. A downstream port (DSP) can "hot reset" an upstream port (USP) by
EN sending two consecutive TS1 ordered sets with the hot reset bit asserted. - Warm (Soft) reset request.
Generated when exiting from D3 to D0 and cfg_pm_no_soft_rst=0. - Link down reset request. A high to
low transition on smlh_req_rst_not indicates the link has gone down and the controller is requesting a
reset. If you disable automatic flushing, your application is responsible for resetting the PCIe controller
and the AXI Bridge. Note: This register field is sticky.
3.7.177 AXI Bridge Slave Error Response (AMBA_ERROR_RESPONSE_DEFAULT_OFF)
Offset
Register Offset
AMBA_ERROR_RESPO 8D0h
NSE_DEFAULT_OFF

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 AMBA_ERROR AMBA 0 AMBA

AMBA_ERROR_RESPONSE_MAP
W _RESP... _ER... _ER...
Reset 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-16 Reserved
AXI Slave Response Error Map. Allows you to selectively map the errors received from the PCIe
15-10
completion (for non-posted requests) to the AXI slave responses, slv_rresp or slv_bresp. The
AMBA_ERROR recommended setting is SLVERR. CRS is always mapped to OKAY. - [0] -- 0: UR (unsupported request)
_RESPONSE_ -> DECERR -- 1: UR (unsupported request) -> SLVERR - [1] -- 0: CRS (configuration retry status) ->
MAP DECERR -- 1: CRS (configuration retry status) -> SLVERR - [2] -- 0: CA (completer abort) -> DECERR
-- 1: CA (completer abort) -> SLVERR - [3]: Reserved - [4]: Reserved - [5]: -- 0: Completion Timeout
-> DECERR -- 1: Completion Timeout -> SLVERR The AXI bridge internally drops (processes internally
but not passed to your application) a completion that has been marked by the Rx filter as UC or MLF,
and does not pass its status directly down to the slave interface. It waits for a timeout and then signals
"Completion Timeout" to the slave interface. The controller sets the AXI slave read databus to 0xFFFF
for all error responses. Note: This register field is sticky.
9-5 Reserved
4-3 CRS Slave Error Response Mapping

AMBA_ERROR Determines the AXI slave response for CRS completions.
_RESPONSE_
CRS
00b - OKAY
01b - OKAY with all FFFF_FFFF data for all CRS completions
10b - OKAY with FFFF_0001 data for CRS completions to vendor ID read requests, OKAY with
FFFF_FFFF data for all other CRS completions
11b - SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP field determines the PCIe-to-AXI
Slave error response mapping)
2 Vendor ID Non-existent Slave Error Response Mapping

Determines the AXI slave response for errors on reads to non-existent Vendor ID register.

NXP Semiconductors
PCIe Controller
Field Function
AMBA_ERROR This field is sticky.

_RESPONSE_V
0b - OKAY (with FFFF data)
ENDORID
1 Reserved
0 Global Slave Error Response Mapping

AMBA_ERROR Determines the AXI slave response for all error scenarios on non-posted requests.
_RESPONSE_
The error response mapping is not applicable to Non-existent Vendor ID register reads.
GLOBAL
0b - OKAY (with FFFF data for non-posted requests)
3.7.178 Link Down AXI Bridge Slave Timeout (AMBA_LINK_TIMEOUT_OFF)
Offset
Register Offset
AMBA_LINK_TIMEOUT_ 8D4h
OFF
Function
If your application AXI master issues outbound requests to the AXI bridge slave interface before the PCIe link is operational,
the controller starts a "flush" timer. The timeout value of the timer is set by this register. The timer will timeout and then
flush the bridge TX request queues after this amount of time. The timer counts when there are pending outbound AXI slave
interface (or DMA) requests and the PCIe TX link is not transmitting any of these requests.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 LINK_
LINK_TIMEOUT_PERIOD_DEFAULT
W TI...
Reset 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-9 Reserved
8 Disable Flush. You can disable the flush feature by setting this field to "1". Note: This register field is
sticky.
LINK_TIMEOUT
_ENABLE_DEF
AULT
Timeout Value (ms). The timer will timeout and then flush the bridge TX request queues after this
7-0
amount of time. The timer counts when there are pending outbound AXI slave interface requests and
LINK_TIMEOUT the PCIe TX link is not transmitting any of these requests. The timer is clocked by core_clk. Note: This
_PERIOD_DEF register field is sticky.
AULT
3.7.179 AMBA Ordering Control (AMBA_ORDERING_CTRL_OFF)
Offset
Register Offset
AMBA_ORDERING_CT 8D8h
RL_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 AX_M 0 AX_MSTR_OR 0 AX_SN 0
W STR... DR_P_... P_...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-8 Reserved
7 AXI Master Zero Length Read Forward To The Application

NXP Semiconductors
PCIe Controller
Field Function
AX_MSTR_ZER The PCIe controller's AXI bridge is able to terminate in order with the Posted transactions the zero length
OLREAD_FW read, implementing the PCIe express flush semantics of the Posted transactions.
0b - The zero-length read terminates at the PCIe AXI bridge master
1b - The zero-length read is forwarded to the application
6-5 Reserved
4-3 AXI Master Posted Ordering Event Selector

AX_MSTR_OR Selects how the master interface determines when a P write is completed when enforcing the PCIe ordering
DR_P_EVENT_ rule, "NP must not pass P" at the AXI Master Interface.
SEL
The AXI protocol does not support ordering between channels. Therefore, NP reads can pass P on your AXI
bus fabric. This can result in an ordering violation when the read overtakes a P that is going to the same
address. Therefore, the bridge master does not issue any NP requests until all outstanding P writes reach
their destination. It does this by waiting for the all of the write responses on the B channel. This can affect
the performance of the master read channel.
For scenarios where the interconnect serializes the AXI master "AW", "W" and "AR" channels, you can
increase the performance by reducing the need to wait until the complete Posted transaction has effectively
reached the application slave.
This setting does not affect:
• MSI interrupt catcher and P data ordering; this is always driven by the B'last event
• DMA read engine TLP ordering; this is always driven by the B'last event
• NP write transactions which are always serialized with P write transactions
00b - B'last event: wait for the all of the write responses on the B channel, thereby ensuring that
the complete Posted transaction has effectively reached the application slave
01b - AW'last event: wait until the complete Posted transaction has left the AXI address channel
at the bridge master
2 Reserved
1 AXI Serialize Non-Posted Requests Enable

AX_SNP_EN This field enables the AXI Bridge to serialize same ID Non-Posted Read/Write Requests on the wire.
Serialization implies one outstanding same ID NP Read or Write on the wire and used to avoid AXI RAR and
WAW hazards at the remote link partner.
0 Reserved

NXP Semiconductors
PCIe Controller
3.7.180 ACE Cache Coherency Control Register 1 (COHERENCY_CONTROL_1_OFF)
Offset
Register Offset
COHERENCY_CONTRO 8E0h
L_1_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
CFG_MEMTYPE_BOUNDARY_LOW_ADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 CFG_
W MEM...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
Boundary Lower Address For Memory Type. Bits [31:0] of dword-aligned address of the boundary for
31-2
Memory type. The two lower address LSBs are "00". Addresses up to but not including this value are
CFG_MEMTYP in the lower address space region; addresses equal or greater than this value are in the upper address
E_BOUNDARY space region. Note: This register field is sticky.
_LOW_ADDR
1 Reserved
0 Sets the memory type for the lower and upper parts of the address space: - 0: lower = Peripheral; upper
= Memory - 1: lower = Memory type; upper = Peripheral Note: This register field is sticky.
CFG_MEMTYP
E_VALUE
Offset
Register Offset
L_2_OFF

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
CFG_MEMTYPE_BOUNDARY_HIGH_ADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0 Boundary Upper Address For Memory Type. Bits [63:32] of the 64-bit dword-aligned address of the
boundary for Memory type. Note: This register field is sticky.
CFG_MEMTYP
E_BOUNDARY
_HIGH_ADDR
Offset
Register Offset
L_3_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 0 CFG_MSTR_A 0 0 CFG_MSTR_A
CFG_MSTR_AWCACHE_VALUE CFG_MSTR_ARCACHE_VALUE
W WDOMA... RDOMA...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFG_MSTR_AWCACHE_MODE CFG_MSTR_ARCACHE_MODE
W WDOMA... RDOMA...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31 Reserved
30-27 Master Write CACHE Signal Value. Value of the individual bits in mstr_awcache when
CFG_MSTR_AWCACHE_MODE is '1'. Note: not applicable to message requests; for message requests
CFG_MSTR_A the value of mstr_awcache is always "0000" Note: This register field is sticky.
WCACHE_VAL
UE
26 Reserved
25-24 Master Write DOMAIN Signal Value. Value of the individual bits in mstr_awdomain when
CFG_MSTR_AWDOMAIN_MODE is '1'. Note: not applicable to message requests; for message requests
CFG_MSTR_A the value of mstr_awdomain is always "11" Note: This register field is sticky.
WDOMAIN_VA
LUE
23 Reserved
22-19 Master Read CACHE Signal Value. Value of the individual bits in mstr_arcache when
CFG_MSTR_ARCACHE_MODE is '1'. Note: This register field is sticky.
CFG_MSTR_A
RCACHE_VAL
UE
18 Reserved
17-16 Master Read DOMAIN Signal Value. Value of the individual bits in mstr_ardomain when
CFG_MSTR_ARDOMAIN_MODE is '1' Note: This register field is sticky.
CFG_MSTR_A
RDOMAIN_VAL
UE
15 Reserved
14-11 Master Write CACHE Signal Behavior. Defines how the individual bits in mstr_awcache are controlled:
- 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the
CFG_MSTR_A CFG_MSTR_AWCACHE_VALUE field Note: for message requests the value of mstr_awcache is always
WCACHE_MO "0000" regardless of the value of this bit Note: This register field is sticky.
DE
10 Reserved

NXP Semiconductors
PCIe Controller
Field Function
9-8Master Write DOMAIN Signal Behavior. Defines how the individual bits in mstr_awdomain[1:0] are
controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of
CFG_MSTR_A the CFG_MSTR_AWDOMAIN_VALUE field Note:: for message requests the value of mstr_awdomain is
WDOMAIN_MO always "11" regardless of the value of this bit Note: This register field is sticky.
DE
7 Reserved
6-3 Master Read CACHE Signal Behavior. Defines how the individual bits in mstr_arcache are controlled:
CFG_MSTR_A CFG_MSTR_ARCACHE_VALUE field Note: This register field is sticky.
RCACHE_MOD
E
2 Reserved
1-0 Master Read DOMAIN Signal Behavior. Defines how the individual bits in mstr_ardomain[1:0] are
controlled: - 0: set automatically by the AXI master - 1: set the value of the corresponding bit of the
CFG_MSTR_A CFG_MSTR_ARDOMAIN_VALUE field Note: This register field is sticky.
RDOMAIN_MO
DE
3.7.183 Lower 20 bits of the programmable AXI address where Messages coming from wire are
mapped to. (AXI_MSTR_MSG_ADDR_LOW_OFF)
Offset
Register Offset
AXI_MSTR_MSG_ADDR 8F0h
_LOW_OFF
Function
Lower 20 bits of the programmable AXI address where Messages coming from wire are mapped to. Bits [11:0] of the
register are tied to zero for the address to be 4k-aligned. In previous releases, the third and fourth DWORDs of a message
(Msg/MsgD) TLP header were delivered though the AXI master address bus (mstr_awaddr). These DWORDS are now
supplied through the mstr_awmisc_info_hdr_34dw[63:0] output; and the value on mstr_awaddr is driven to the value you have
programmed into the AXI_MSTR_MSG_ADDR_LOW_OFF and AXI_MSTR_MSG_ADDR_HIGH_OFF registers.

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
CFG_AXIMSTR_MSG_ADDR_LOW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CFG_AXIMSTR_MSG_ADDR_LO CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED
W W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-12 Lower 20 bits of the programmable AXI address for Messages. Note: This register field is sticky.
CFG_AXIMSTR
_MSG_ADDR_L
OW
11-0 Reserved for future use. Note: This register field is sticky.
CFG_AXIMSTR
_MSG_ADDR_L
OW_RESERVE
D
3.7.184 Upper 32 bits of the programmable AXI address where Messages coming from wire are
mapped to. (AXI_MSTR_MSG_ADDR_HIGH_OFF)
Offset
Register Offset
_HIGH_OFF

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
CFG_AXIMSTR_MSG_ADDR_HIGH
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0 Upper 32 bits of the programmable AXI address for Messages. Note: This register field is sticky.
CFG_AXIMSTR
_MSG_ADDR_
HIGH
3.7.185 PCIe Controller IIP Release Version Number. (PCIE_VERSION_NUMBER_OFF)
Offset
Register Offset
PCIE_VERSION_NUMB 8F8h
ER_OFF
Function
PCIe Controller IIP Release Version Number. The version number is given in hex format. You should convert each pair of
hex characters to ASCII to interpret. Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which translates
to 470* - VERSION_TYPE = 0x67612a2a which translates to ga** Using 4.70a-ea01 as an example: - VERSION_NUMBER
= 0x3437302a which translates to 470* - VERSION_TYPE = 0x65613031 which translates to ea01 GA is a general release
available on www.designware.com EA is an early release available on a per-customer basis.

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R VERSION_NUMBER
Reset 0 0 1 1 0 1 0 1 0 0 1 1 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VERSION_NUMBER
Reset 0 0 1 1 0 0 0 0 0 0 1 0 1 0 1 0
Fields
Field Function
31-0 Version Number.
VERSION_NU
MBER
3.7.186 PCIe Controller IIP Release Version Type. (PCIE_VERSION_TYPE_OFF)
Offset
Register Offset
PCIE_VERSION_TYPE_ 8FCh
OFF
Function
PCIe Controller IIP Release Version Type. The type is given in hex format. You should convert each pair of hex characters
to ASCII to interpret. Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which translates to 470*
- VERSION_TYPE = 0x67612a2a which translates to ga** Using 4.70a-ea01 as an example: - VERSION_NUMBER =
0x3437302a which translates to 470* - VERSION_TYPE = 0x65613031 which translates to ea01 GA is a general release
available on www.designware.com EA is an early release available on a per-customer basis.

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R VERSION_TYPE
Reset 0 1 1 0 1 1 0 0 0 1 1 1 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VERSION_TYPE
Reset 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 1
Fields
Field Function
31-0 Version Type.
VERSION_TYP
E
3.7.187 Interface Timer Control (INTERFACE_TIMER_CONTROL_OFF)
Offset
Register Offset
INTERFACE_TIMER_C 930h
ONTROL_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 FORC INTERFACE_TI INTER INTER
W E_P... MER... FA... FA...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-5 Reserved
4 Writing to this bit forces the value of the pending flags. Note: This register field is sticky.
FORCE_PENDI
NG
3-2Interface timer scaling. This field can be used to reduce the timer duration for verification purpose. This
field should only be programmed when the INTERFACE_TIMER_EN bit is set to 1'b0. Note: This register
INTERFACE_TI field is sticky.
MER_SCALING
1 Interface timer AER generation enable. Note: This register field is sticky.
INTERFACE_TI
MER_AER_EN
0 Interface timer enable. Note: This register field is sticky.
INTERFACE_TI
MER_EN
3.7.188 Interface Timer Target (INTERFACE_TIMER_TARGET_OFF)
Offset
Register Offset
INTERFACE_TIMER_TA 934h
RGET_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
INTERFACE_TIMER_TARGET
W
Reset 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-16 Reserved
15-0 Interface timer target value. This field should only be programmed when the INTERFACE_TIMER_EN bit
is set to 1'b0. Note: This register field is sticky.
INTERFACE_TI
MER_TARGET
3.7.189 Interface Timer Status Register. (INTERFACE_TIMER_STATUS_OFF)
Offset
Register Offset
INTERFACE_TIMER_ST 938h
ATUS_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SLAVE SLAVE SLAVE MAST MAST CLIEN CLIEN CPL_I MESS

R 0 0 0
_R... _W... _W... ER_... ER_... T2... T1... NT... AGE...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-12 Reserved
11 Slave read address channel timeout.
SLAVE_RD_AD
D_TIMEOUT
10 Slave write data channel timeout.

NXP Semiconductors
PCIe Controller
Field Function
SLAVE_WR_D
ATA_TIMEOUT
9 Slave write address channel timeout.
SLAVE_WR_A
DD_TIMEOUT
8-7 Reserved
6 Master read data channel timeout.
MASTER_RD_
DATA_TIMEOU
T
5 Master write response channel timeout.
MASTER_WR_
RES_TIMEOUT
4 Client2 interface timeout.
CLIENT2_INTE
RFACE_TIMEO
UT
CLIENT1_INTE
RFACE_TIMEO
UT
2 Reserved
1 CPL interface timeout.
CPL_INTERFA
CE_TIMEOUT
0 Message interface timeout.
MESSAGE_INT
ERFACE_TIME
OUT

NXP Semiconductors
PCIe Controller
3.7.190 MSI-X Address Match Low (MSIX_ADDRESS_MATCH_LOW_OFF)
Offset
Register Offset
MSIX_ADDRESS_MATC 940h
H_LOW_OFF
Function
When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1), the controller implements the logic and RAM required
to generate MSI-X requests. For more details, see Interrupts†. This register is only used in AXI configurations. When your local
AXI application writes (MWr) to the address defined in this register (and MSIX_ADDRESS_MATCH_HIGH_OFF), the controller
will load the MSIX_DOORBELL_OFF register with the contents of the MWr and subsequently create and send MSI-X TLPs
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MSIX_ADDRESS_MATCH_LOW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSIX_
R MSIX_
MSIX_ADDRESS_MATCH_LOW AD...
AD...
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-2 MSI-X Address Match Low Address. Note: This register field is sticky.
MSIX_ADDRES
S_MATCH_LO
W
MSIX_ADDRES
S_MATCH_RE
SERVED_1
0 MSI-X Match Enable. Enable the MSI-X Address Match feature when the AXI bridge is present. Note:
MSIX_ADDRES
S_MATCH_EN

NXP Semiconductors
PCIe Controller
3.7.191 MSI-X Address Match High (MSIX_ADDRESS_MATCH_HIGH_OFF)
Offset
Register Offset
H_HIGH_OFF
Function
AXI application writes (MWr) to the address defined in this register (and MSIX_ADDRESS_MATCH_LOW_OFF), the controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MSIX_ADDRESS_MATCH_HIGH
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0 MSI-X Address Match High Address. Note: This register field is sticky.
MSIX_ADDRES
S_MATCH_HIG
H
3.7.192 MSI-X Doorbell (MSIX_DOORBELL_OFF)
Offset
Register Offset
MSIX_DOORBELL_OFF 948h
Function
When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1), the controller implements the logic and RAM required to
generate MSI-X requests. For more details, see Interrupts†.

NXP Semiconductors
PCIe Controller
For AXI configurations: when your local application writes (MWr) to the address defined in MSIX_ADDRESS_MATCH_LOW_OFF,
the controller will load this register with the contents of the MWr and subsequently create and send MSI-X TLPs.
For non-AMBA configurations: when your local application writes to this register, the controller will create and send MSI-X TLPs.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSIX_DOORBELL_RES
W MSIX_DOORBELL_PF MSIX_DOORBELL_VF
ERVED_...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSIX_ MSIX_
W MSIX_DOORBELL_TC MSIX_DOORBELL_VECTOR
DO... DO...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-29 Reserved
MSIX_DOORB
ELL_RESERVE
D_29_31
28-24 MSIX Doorbell Physical Function. This register determines the Physical Function for the MSI-X
transaction.
MSIX_DOORB
ELL_PF
23-16 MSIX Doorbell Virtual Function. This register determines the Virtual Function for the MSI-X transaction.
MSIX_DOORB
ELL_VF
15 MSIX Doorbell Virtual Function Active. This register determines whether a Virtual Function is used to
generate the MSI-X transaction.
MSIX_DOORB
ELL_VF_ACTIV
E
14-12 MSIX Doorbell Traffic Class. This register determines which traffic class to generate the MSI-X
transaction with.
MSIX_DOORB
ELL_TC
11 Reserved

NXP Semiconductors
PCIe Controller
Field Function
MSIX_DOORB
ELL_RESERVE
D_11
10-0 MSI-X Doorbell Vector. This register determines which vector to generate the MSI-X transaction for.
MSIX_DOORB
ELL_VECTOR
3.7.193 MSI-X RAM Power Mode And Debug Control (MSIX_RAM_CTRL_OFF)
Offset
Register Offset
MSIX_RAM_CTRL_OFF 94Ch
Function
to generate MSI-X requests. For more details, see Interrupts†.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R MSIX_RAM_CTRL_RESERVED_26_31 MSIX_ MSIX_ MSIX_RAM_CTRL_RESERVED_17_23 MSIX_
W RA... RA... RA...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R MSIX_RAM_CTRL_RESERVED_10_15 MSIX_ MSIX_ MSIX_RAM_CTRL_RESERVED_2_7 MSIX_ MSIX_
W RA... RA... RA... RA...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
MSIX_RAM_CT
RL_RESERVE
D_26_31

NXP Semiconductors
PCIe Controller
Field Function
25 MSIX PBA RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access
to the PBA. Use can also use the dbg_pba input to activate debug mode. Debug mode turns off the
MSIX_RAM_CT PF/VF/Offset-based addressing into the RAM and maps the entire table linearly from the base address of
RL_DBG_PBA the BAR (indicated by the BIR) in function 0. Note: This register field is sticky.
24 MSIX Table RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write
access to the Table. Use can also use the dbg_table input to activate debug mode. Debug mode turns
MSIX_RAM_CT off the PF/VF/Offset-based addressing into the RAM and maps the entire table linearly from the base
RL_DBG_TABL address of the BAR (indicated by the BIR) in function 0. Note: This register field is sticky.
E
MSIX_RAM_CT
RL_RESERVE
D_17_23
16 MSIX RAM Control Bypass. The bypass field, when set, disables the internal generation of low power
signals for both RAMs. It is up to the application to ensure the RAMs are in the proper power state before
MSIX_RAM_CT trying to access them. Moreover, the application needs to observe all timing requirements of the RAM
RL_BYPASS low power signals before trying to use the MSIX functionality. Note: This register field is sticky.
MSIX_RAM_CT
RL_RESERVE
D_10_15
9 MSIX PBA RAM Shut Down. Set this bit to drive the cfg_msix_pba_sd output to signal your external logic
to place the MSIX PBA RAM in Shut Down low-power mode. Note: This register field is sticky.
MSIX_RAM_CT
RL_PBA_SD
8 MSIX PBA RAM Deep Sleep. Set this bit to drive the cfg_msix_pba_ds output to signal your external
logic to place the MSIX PBA RAM in Deep Sleep low-power mode. Note: This register field is sticky.
MSIX_RAM_CT
RL_PBA_DS
MSIX_RAM_CT
RL_RESERVE
D_2_7
1 MSIX Table RAM Shut Down. Set this bit to drive the cfg_msix_table_sd output to signal your external
logic to place the MSIX Table RAM in Shut Down low-power mode. Note: This register field is sticky.
MSIX_RAM_CT
RL_TABLE_SD
0 MSIX Table RAM Deep Sleep. Set this bit to drive the cfg_msix_table_ds output to signal your external
logic to place the MSIX Table RAM in Deep Sleep low-power mode. Note: This register field is sticky.
MSIX_RAM_CT
RL_TABLE_DS

NXP Semiconductors
PCIe Controller
3.7.194 Masks for functional safety interrupt events. (SAFETY_MASK_OFF)
Offset
Register Offset
SAFETY_MASK_OFF 960h
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 SAFET SAFET SAFET SAFET SAFET SAFET
W Y_... Y_... Y_... Y_... Y_... Y_...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-6 Reserved
5 Mask for functional safety interrupt event 5 (RASDP correctable). Note: This register field is sticky.
SAFETY_INT_
MASK_5
4 Mask for functional safety interrupt event 4 (PCIe correctable). Note: This register field is sticky.
SAFETY_INT_
MASK_4
3 Mask for functional safety interrupt event 3 (PCIe uncorrectable). Note: This register field is sticky.
SAFETY_INT_
MASK_3
2 Mask for functional safety interrupt event 2 (Interface timers). Note: This register field is sticky.
SAFETY_INT_
MASK_2
1 Mask for functional safety interrupt event 1 (CDM register checker). Note: This register field is sticky.
SAFETY_INT_
MASK_1

NXP Semiconductors
PCIe Controller
Field Function
0 Mask for functional safety interrupt event 0 (RASDP). Note: This register field is sticky.
SAFETY_INT_
MASK_0
3.7.195 Status for functional safety interrupt events. (SAFETY_STATUS_OFF)
Offset
Register Offset
SAFETY_STATUS_OFF 964h
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAFET SAFET SAFET SAFET SAFET SAFET

R 0
Y_... Y_... Y_... Y_... Y_... Y_...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-6 Reserved
5 Status for functional safety interrupt event 5 (RASDP correctable).
SAFETY_INT_S
TATUS_5
4 Status for functional safety interrupt event 4 (PCIe correctable).
SAFETY_INT_S
TATUS_4
3 Status for functional safety interrupt event 3 (PCIe uncorrectable).

NXP Semiconductors
PCIe Controller
Field Function
SAFETY_INT_S
TATUS_3
2 Status for functional safety interrupt event 2 (Interface timers).
SAFETY_INT_S
TATUS_2
1 Status for functional safety interrupt event 1 (CDM register checker).
SAFETY_INT_S
TATUS_1
0 Status for functional safety interrupt event 0 (RASDP).
SAFETY_INT_S
TATUS_0
3.7.196 CDM Register Checking Control and Status (PL_CHK_REG_CONTROL_STATUS_OFF)
Offset
Register Offset
PL_CHK_REG_CONTR B20h
OL_STATUS_OFF
Function
CDM Register Checking Control and Status Register. Controls register checking and displays status of register checking.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHK_ CHK_ CHK_

R 0
REG... REG... REG...
W W1C W1C W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 CHK_ CHK_
W REG... REG...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-19 Reserved
18 The system has completed a checking cycle.
CHK_REG_CO
MPLETE
17 The system has detected an error in its own checking logic.
CHK_REG_LO
GIC_ERROR
16 The system has detected that there is a bit error in the CDM Register Data.
CHK_REG_CO
MPARISON_ER
ROR
15-2 Reserved
1 Set Continuous Checking Sequence. Note: This register field is sticky.
CHK_REG_CO
NTINUOUS
0 Begins a checking sequence. Note: This register field is sticky.
CHK_REG_STA
RT
3.7.197 CDM Register Checking First and Last address to check. (PL_CHK_REG_START_END_OFF)
Offset
Register Offset
PL_CHK_REG_START_ B24h
END_OFF

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
CHK_REG_END_ADDR
W
Reset 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CHK_REG_START_ADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-16 The last address that is checked by the system. Note: This register field is sticky.
CHK_REG_EN
D_ADDR
15-0 The first address that is checked by the system. Note: This register field is sticky.
CHK_REG_STA
RT_ADDR
3.7.198 CDM Register Checking Error Address. (PL_CHK_REG_ERR_ADDR_OFF)
Offset
Register Offset
PL_CHK_REG_ERR_AD B28h
DR_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R CHK_REG_ERR_ADDR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CHK_REG_ERR_ADDR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-0 The address at which an error has been detected. Valid only when the CDM Register Checker
Comparison Error bit is set in the status register. Note: This register field is sticky.
CHK_REG_ER
R_ADDR
3.7.199 CDM Register Checking error PF and VF Numbers. (PL_CHK_REG_ERR_PF_VF_OFF)
Offset
Register Offset
PL_CHK_REG_ERR_PF B2Ch
_VF_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 CHK_REG_VF_ERR_NUMBER
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 CHK_REG_PF_ERR_NUMBER
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-28 Reserved
27-16 The VF number at which the error was detected. Valid only when the CDM Register Checker
CHK_REG_VF_
ERR_NUMBER
15-5 Reserved
4-0 The PF number at which the error was detected. Valid only when the CDM Register Checker
CHK_REG_PF_
ERR_NUMBER

NXP Semiconductors
PCIe Controller
3.7.200 Auxiliary Clock Frequency Control (AUX_CLK_FREQ_OFF)
Offset
Register Offset
AUX_CLK_FREQ_OFF B40h
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
AUX_CLK_FREQ
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0
Fields
Field Function
31-10 Reserved
The aux_clk frequency in MHz. This value is used to provide a 1 us reference for counting time during
9-0
low-power states with aux_clk when the PHY has removed the pipe_clk. Frequencies lower than 1 MHz
AUX_CLK_FRE are possible but with a loss of accuracy in the time counted. If the actual frequency (f) of aux_clk does
Q not exactly match the programmed frequency (f_prog), then there is an error in the time counted by the
controller that can be expressed in percentage as: err% = (f_prog/f-1)*100. For example if f=2.5 MHz
and f_prog=3 MHz, then err% =(3/2.5-1)*100 =20%, meaning that the time counted by the controller
on aux_clk will be 20% greater than the time in us programmed in the corresponding time register (for
example T_POWER_ON). Note: This register field is sticky.
3.7.201 BAR0 Mask (BAR0_MASK)
Offset
Register Offset
BAR0_MASK 2_0010h
Function
Serves as the mask for BAR0.

NXP Semiconductors
PCIe Controller
Your local CPU can change the mask at runtime using the DBI. The mask register is invisible to the PCIe wire but visible to your
local CPU through the DBI. You cannot read the mask register but you can write to it. It is accessed by asserting dbi_cs2 and
dbi_cs. If you only assert dbi_cs then you will access the BAR which is the primary register at that location. Use CS2 instead of
dbi_cs2 when you are using the AXI bridge.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
W PCI_TYPE0_BAR0_MASK
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCI_T
YP...
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Fields
Field Function
31-1 BAR0 Mask

PCI_TYPE0_BA This field is sticky and untestable.
R0_MASK
0 BAR0 Mask Enabled

R0_ENABLED
0b - Disabled
1b - Enabled
Offset
Register Offset
BAR1_MASK 2_0014h
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCI_T
YP...
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Fields
Field Function
31-1 BAR1 Mask

R1_MASK
0 BAR1 Mask Enabled

R1_ENABLED
0b - Disabled
1b - Enabled
Offset
Register Offset
BAR2_MASK 2_0018h
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCI_T
YP...
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Fields
Field Function
31-1 BAR2 Mask

R2_MASK
0 BAR2 Mask Enabled

R2_ENABLED
0b - Disabled
1b - Enabled
Offset
Register Offset
BAR3_MASK 2_001Ch
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCI_T
YP...
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Fields
Field Function
31-1 BAR3 Mask

R3_MASK
0 BAR3 Mask Enabled

R3_ENABLED
0b - Disabled
1b - Enabled
Offset
Register Offset
BAR4_MASK 2_0020h
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCI_T
YP...
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Fields
Field Function
31-1 BAR4 Mask

R4_MASK
0 BAR4 Mask Enabled

R4_ENABLED
0b - Disabled
1b - Enabled
Offset
Register Offset
BAR5_MASK 2_0024h
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCI_T
YP...
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Fields
Field Function
31-1 BAR5 Mask

R5_MASK
0 BAR5 Mask Enabled

R5_ENABLED
0b - Disabled
1b - Enabled
3.7.207 iATU Region Control 1 (IATU_REGION_CTRL_1_OFF_OUTBOUND_0 -

IATU_REGION_CTRL_1_OFF_OUTBOUND_5)
Offset
Register Offset
IATU_REGION_CTRL_1 6_0000h
_OFF_OUTBOUND_0

NXP Semiconductors
PCIe Controller
Register Offset
_OFF_OUTBOUND_1
_OFF_OUTBOUND_2
_OFF_OUTBOUND_3
_OFF_OUTBOUND_4
IATU_REGION_CTRL_1 6_0A00h
_OFF_OUTBOUND_5
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 0
CTRL_1_FUNC_NUM
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 INCRE 0
ATTR TD TC TYPE
W AS...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-23 Reserved
22-20 Function Number

CTRL_1_FUNC When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU
_NUM Control 2 Register" is '0', then the function number used in generating the function part of the requester ID
(RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0h.
When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the
correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.
19-14 Reserved

NXP Semiconductors
PCIe Controller
Field Function
13 Increase Maximum ATU Region Size

INCREASE_RE This field is sticky.
GION_SIZE
0b - Maximum ATU region size is 4 GB
1b - Maximum ATU region size is 1 TB
12-11 Reserved
10-9 When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is
changed to the value in this register. Note: This register field is sticky.
ATTR
8 When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed
to the value in this register. Note: This register field is sticky.
TD
7-5 When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed
TC
4-0 When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is
TYPE

Offset
Register Offset
_OFF_OUTBOUND_0
_OFF_OUTBOUND_1
_OFF_OUTBOUND_2
_OFF_OUTBOUND_3
_OFF_OUTBOUND_4
_OFF_OUTBOUND_5

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R REGIO 0 INVER CFG_ DMA_ 0 HEAD INHIBI 0 FUNC 0 TAG_S

SNP
W N_... T_... SHI... BYP... ER_... T... _BY... UB...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
TAG Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31 Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is
sticky.
REGION_EN
30 Reserved
Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs
29
when the untranslated address is in the region outside the defined range (Base Address to Limit
INVERT_MODE Address). Note: This register field is sticky.
28 CFG Shift Mode

CFG_SHIFT_M The iATU uses bits [27:12] of the untranslated address (on the AXI slave interface address) to form the BDF
ODE number of the outgoing CFG TLP. This supports the Enhanced Configuration Address Mapping (ECAM)
mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing
I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB
region of the PCIe configuration space.
DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the
27
iATU untranslated. Note: This field is reserved for the SW product. You must set it to '0'. Note: This
DMA_BYPASS register field is sticky.
26-24 Reserved
Header Substitute Enable. When enabled and region address is matched, the iATU fully substitutes
23
bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header
HEADER_SUB with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i.
STITUTE_EN - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill
bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP
header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms
the new address of the translated region. Note: This register field is sticky.

NXP Semiconductors
PCIe Controller
Field Function
22 Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When
enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing
INHIBIT_PAYL the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so
OAD that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1
so that TLPs with or without data can be sent. Note: This register field is sticky.
21 Reserved
20 Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-
Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted
SNP Requests outstanding. Note: This register field is sticky.
19 Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken
from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control
FUNC_BYPAS 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register." Note: This register field is sticky.
S
18-17 Reserved
16 TAG Substitute Enable

TAG_SUBSTIT When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP
UTE_EN header with the contents of the TAG field in this register. The expected usage scenario is translation from
AXI MWr to Vendor Defined Msg/MsgD.
15-8 TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.
TAG
7-0 Reserved
3.7.209 iATU Lower Base Address (IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 -

IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5)
Offset
Register Offset
IATU_LWR_BASE_ADD 6_0008h
R_OFF_OUTBOUND_0
R_OFF_OUTBOUND_1

NXP Semiconductors
PCIe Controller
Register Offset
R_OFF_OUTBOUND_2
R_OFF_OUTBOUND_3
R_OFF_OUTBOUND_4
IATU_LWR_BASE_ADD 6_0A08h
R_OFF_OUTBOUND_5
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
LWR_BASE_RW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R LWR_BASE_HW
LWR_BASE_RW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-12 Forms bits 31:12 of the start address of the address region to be translated.
LWR_BASE_R This field is sticky.
W
LWR_BASE_H The PCIe controller ignores any writes to this location.
W

NXP Semiconductors
PCIe Controller
3.7.210 iATU Upper Base Address (IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 -

IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5)
Offset
Register Offset
IATU_UPPER_BASE_A 6_000Ch
DDR_OFF_OUTBOUND
_0
DDR_OFF_OUTBOUND
_1
DDR_OFF_OUTBOUND
_2
DDR_OFF_OUTBOUND
_3
DDR_OFF_OUTBOUND
_4
IATU_UPPER_BASE_A 6_0A0Ch
DDR_OFF_OUTBOUND
_5
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
UPPER_BASE_RW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
UPPER_BASE_RW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with
31-0
a 32-bit address space, this register is not used and therefore writing to this register has no effect. Note:
UPPER_BASE_ This register field is sticky.
RW

NXP Semiconductors
PCIe Controller
3.7.211 iATU Limit Address (IATU_LIMIT_ADDR_OFF_OUTBOUND_0 -

IATU_LIMIT_ADDR_OFF_OUTBOUND_5)
Offset
Register Offset
IATU_LIMIT_ADDR_OFF 6_0010h
_OUTBOUND_0
_OUTBOUND_1
_OUTBOUND_2
_OUTBOUND_3
_OUTBOUND_4
IATU_LIMIT_ADDR_OFF 6_0A10h
_OUTBOUND_5
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
LIMIT_ADDR_RW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R LIMIT_ADDR_HW
LIMIT_ADDR_RW
W
Reset 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
Fields
Field Function
31-12 Forms upper bits of the end address of the address region to be translated.
LIMIT_ADDR_R The end address must be aligned to a 4 KB boundary, so these bits are always 0.
W
The PCIe controller ignores writes to this location.
11-0 Forms lower bits of the end address of the address region to be translated.
LIMIT_ADDR_H The end address must be aligned to a 4 KB boundary, so these bits are always 0.
W

NXP Semiconductors
PCIe Controller
3.7.212 iATU Lower Target Address (IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0 -

IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5)
Offset
Register Offset
IATU_LWR_TARGET_A 6_0014h
DDR_OFF_OUTBOUND
_0
DDR_OFF_OUTBOUND
_1
DDR_OFF_OUTBOUND
_2
DDR_OFF_OUTBOUND
_3
DDR_OFF_OUTBOUND
_4
IATU_LWR_TARGET_A 6_0A14h
DDR_OFF_OUTBOUND
_5
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
LWR_TARGET_RW_OUTBOUND
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0 Lower Target Outbound

When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0'
(normal operation):

NXP Semiconductors
PCIe Controller
Field Function
LWR_TARGET • LWR_TARGET_RW[31:12] forms MSB's of the Lower Target part of the new address of the
_RW_OUTBOU translated region
ND
• LWR_TARGET_RW[11:0] are not used. (The start address must be aligned to a 4 KB boundary, so
the lower bits of the start address of the new address of the translated region [bits 11:0] are always
'0').
When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1',
LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header)
of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where
the controller determines the content of bytes 12 to 15 of the TLP header.
3.7.213 iATU Upper Target Address (IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 -

IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5)
Offset
Register Offset
IATU_UPPER_TARGET 6_0018h
_ADDR_OFF_OUTBOU
ND_0
_ADDR_OFF_OUTBOU
ND_1
_ADDR_OFF_OUTBOU
ND_2
_ADDR_OFF_OUTBOU
ND_3
_ADDR_OFF_OUTBOU
ND_4
IATU_UPPER_TARGET 6_0A18h
_ADDR_OFF_OUTBOU
ND_5

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
UPPER_TARGET_RW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
UPPER_TARGET_RW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0 Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.
UPPER_TARG
ET_RW
3.7.214 iATU Upper Limit Address (IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0 -

IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5)
Offset
Register Offset
IATU_UPPR_LIMIT_ADD 6_0020h
R_OFF_OUTBOUND_0
R_OFF_OUTBOUND_1
R_OFF_OUTBOUND_2
R_OFF_OUTBOUND_3
R_OFF_OUTBOUND_4
IATU_UPPR_LIMIT_ADD 6_0A20h
R_OFF_OUTBOUND_5
Function
The maximum size of an address translation region is 1 TB. This register is only used when the INCREASE_REGION_SIZE
field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R UPPR_LIMIT_ADDR_HW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UPPR_LIMIT_ADDR_RW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
Forms MSB's of the Upper Limit part of the region "end address" to be translated. Only applies to 64-bit
31-8
systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i
UPPR_LIMIT_A is '1'. These bits are always '0'.
DDR_HW
7-0Forms the LSB's of the Upper Limit part of the region "end address" to be
translated. Only applies to 64-bit systems and when the INCREASE_REGION_SIZE field in
UPPR_LIMIT_A IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1' Note: This register field is sticky.
DDR_RW
3.7.215 iATU Region Control 1 (IATU_REGION_CTRL_1_OFF_INBOUND_0 -

IATU_REGION_CTRL_1_OFF_INBOUND_3)
Offset
Register Offset
_OFF_INBOUND_0
_OFF_INBOUND_1
_OFF_INBOUND_2
_OFF_INBOUND_3

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 0
CTRL_1_FUNC_NUM
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 INCRE 0
ATTR TD TC TYPE
W AS...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-23 Reserved
Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a
22-20
MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation
CTRL_1_FUNC proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control
_NUM 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of
the TLP header matches the function, then address translation proceeds. This check is only performed if
the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. Note: This register field
is sticky.
19-14 Reserved

GION_SIZE
0b - Maximum ATU Region size is 4 GB
1b - Maximum ATU Region size is 1 TB
12-11 Reserved
10-9 When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds
(when all other enabled field-matches are successful). This check is only performed if the "ATTR Match
ATTR Enable" bit of the "iATU Control 2 Register" is set. Note: This register field is sticky.
8 When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when
all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit
TD of the "iATU Control 2 Register" is set. Note: This register field is sticky.
7-5 When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when
all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit
TC of the "iATU Control 2 Register" is set. Note: This register field is sticky.

NXP Semiconductors
PCIe Controller
Field Function
4-0 When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds
(when all other enabled field-matches are successful). Note: This register field is sticky.
TYPE

Offset
Register Offset
_OFF_INBOUND_0
_OFF_INBOUND_1
_OFF_INBOUND_2
_OFF_INBOUND_3
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R REGI MATC INVER CFG_ FUZZ 0 RESPONSE_C SINGL 0 Reserv 0 FUNC 0 ATTR_
W ON_... H_M... T_... SHI... Y_T... ODE E_... ed _NU... MA...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R TD_M TC_M MSG_ 0

BAR_NUM Reserved
W ATC... ATC... TYP...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
sticky.
REGION_EN
Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that
30
is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode.
MATCH_MODE The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers

NXP Semiconductors
PCIe Controller
Field Function
must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not
used for RC. For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU
interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16
bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit
of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions
as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0
TLPs should be processed regardless of the Bus number. For MSG/MSGD TLPs, this field is interpreted
as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound
MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. -
1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU
ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header,
but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of
the Region Upper Base register should be programmed with the required Vendor ID. The lower Base
and Limit Register should be programmed to translate TLPs based on vendor specific information in
the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND
MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored. Note: This register field is sticky.
29 Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs
28 CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits
[27:12] of the address to the bus/device and function number. This allows a CFG configuration space
CFG_SHIFT_M to be located in any 256MB window of your application memory space using a 28-bit effective address.
ODE Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address. Note: This
27 Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against
the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0
FUZZY_TYPE_ and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs
MATCH_CODE is ignored - FetchAdd, Swap and CAS are seen as identical. For example, CFG0 in the TYPE field in the
"iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP. Note:
26 Reserved
25-24 Response Code. Defines the type of response to give for accesses matching this region. This overrides
the normal RADM filter response. Note that this feature is not available for any region where Single
RESPONSE_C Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported
ODE request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved. Note: This register field
is sticky.
23 Single Address Location Translate Enable. When enabled, Rx TLPs can be translated to a single
address location as determined by the target address register of the iATU region. The main usage
SINGLE_ADDR scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the
_LOC_TRANS_ AXI bridge is enabled. Note: This register field is sticky.
EN
22 Reserved

NXP Semiconductors
PCIe Controller
Field Function
21 Reserved
20 Reserved
19 Function Number Match Enable. Ensures that a successful Function Number TLP field comparison
match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1
FUNC_NUM_M transactions) for address translation to proceed. Note: This register field is sticky.
ATCH_EN
18-17 Reserved
16 ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field
of the "iATU Control 1 Register") occurs for address translation to proceed. Note: This register field is
ATTR_MATCH_ sticky.
EN
15 TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU
Control 1 Register") occurs for address translation to proceed. Note: This register field is sticky.
TD_MATCH_E
N
14 TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU
TC_MATCH_E
N
13 Message Type Match Mode. When enabled, and if single address location translate enable is set, then
inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound
MSG_TYPE_M register (=>TYPE[4:3]=2'b10) will be translated. Message type match mode overrides any value of
ATCH_MODE MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages
when AXI bridge is configured on client interface. Note: This register field is sticky.
12-11 Reserved
10-8 BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal
internal BAR address matching mechanism " is the same as this field, address translation proceeds
BAR_NUM (when all other enabled field-matches are successful). This check is only performed if the "Match Mode"
bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3
- 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either
00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that
BAR configured as an IO BAR. Note: This register field is sticky.
7-0 Reserved

NXP Semiconductors
PCIe Controller
3.7.217 iATU Lower Base Address (IATU_LWR_BASE_ADDR_OFF_INBOUND_0 -

IATU_LWR_BASE_ADDR_OFF_INBOUND_3)
Offset
Register Offset
R_OFF_INBOUND_0
R_OFF_INBOUND_1
R_OFF_INBOUND_2
R_OFF_INBOUND_3
Function
The minimum size of an address translation region is 4 KB. The lower 12 bits are zero.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
LWR_BASE_RW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R LWR_BASE_HW
LWR_BASE_RW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-12 Start Address High

LWR_BASE_R Forms bits 31:12 of the start address of the address region to be translated.
W
11-0 Start Address Low

LWR_BASE_H Forms bits 11:0 of the start address of the address region to be translated.
W
The PCIe controller ignores any writes to this location.

NXP Semiconductors
PCIe Controller
3.7.218 iATU Upper Base Address (IATU_UPPER_BASE_ADDR_OFF_INBOUND_0 -

IATU_UPPER_BASE_ADDR_OFF_INBOUND_3)
Offset
Register Offset
DDR_OFF_INBOUND_0
DDR_OFF_INBOUND_1
DDR_OFF_INBOUND_2
DDR_OFF_INBOUND_3
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
UPPER_BASE_RW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
UPPER_BASE_RW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0 Forms bits [63:32] of the start (and end) address of the address region to be translated. Note: This
UPPER_BASE_
RW
3.7.219 iATU Limit Address (IATU_LIMIT_ADDR_OFF_INBOUND_0 -

IATU_LIMIT_ADDR_OFF_INBOUND_3)
Offset
Register Offset
_INBOUND_0

NXP Semiconductors
PCIe Controller
Register Offset
_INBOUND_1
_INBOUND_2
_INBOUND_3
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
LIMIT_ADDR_RW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R LIMIT_ADDR_HW
LIMIT_ADDR_RW
W
Reset 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
Fields
Field Function
W
W

NXP Semiconductors
PCIe Controller
3.7.220 iATU Lower Target Address (IATU_LWR_TARGET_ADDR_OFF_INBOUND_0 -

IATU_LWR_TARGET_ADDR_OFF_INBOUND_3)
Offset
Register Offset
DDR_OFF_INBOUND_0
DDR_OFF_INBOUND_1
DDR_OFF_INBOUND_2
DDR_OFF_INBOUND_3
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
LWR_TARGET_RW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R LWR_TARGET_HW
LWR_TARGET_RW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-12 Forms MSB's of the Lower Target part of the new address of the translated region.
LWR_TARGET These bits are always '0'.
_RW
11-0 Forms the LSB's of the Lower Target part of the new address of the translated region.
LWR_TARGET The start address must be aligned to a 4 KB boundary (in address match mode); and to the Bar size
_HW boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region
size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.

NXP Semiconductors
PCIe Controller
3.7.221 iATU Upper Target Address (IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0 -

IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3)
Offset
Register Offset
_ADDR_OFF_INBOUND
_0
_ADDR_OFF_INBOUND
_1
_ADDR_OFF_INBOUND
_2
_ADDR_OFF_INBOUND
_3
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
UPPER_TARGET_RW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
UPPER_TARGET_RW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In
31-0
systems with a 32-bit address space, this register is not used and therefore writing to this register has no
UPPER_TARG effect. Note: This register field is sticky.
ET_RW

NXP Semiconductors
PCIe Controller
3.7.222 iATU Upper Limit Address (IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0 -

IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3)
Offset
Register Offset
R_OFF_INBOUND_0
R_OFF_INBOUND_1
R_OFF_INBOUND_2
R_OFF_INBOUND_3
Function
The maximum size of an address translation region is 1 TB. This register is only used when the INCREASE_REGION_SIZE field
in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UPPR_LIMIT_ADDR_RW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-8
systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is
UPPR_LIMIT_A '1'. These bits are always '0'.
DDR_HW
UPPR_LIMIT_A IATU_REGION_CTRL_1_OFF_INBOUND_i is '1' Note: This register field is sticky.
DDR_RW
3.8 PCIE_RC register descriptions

This section presents the PCIe controller registers when the controller is in root complex (RC) mode.†

NXP Semiconductors
PCIe Controller
3.8.1 RC memory map

PCIE_RC relative offset: 0h
(In bits)
0h Device ID And Vendor ID (TYPE1_DEV_ID_VEND_ID_REG) 32 RO See

description
4h Status and Command (TYPE1_STATUS_COMMAND_REG) 32 RW 0010_0000h
8h Class Code And Revision ID (TYPE1_CLASS_CODE_REV_ID_REG) 32 RO See

description
Ch BIST, Header Type, Latency Timer, and Cache Line Size 32 RW 0001_0000h
(TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG)
18h Secondary Latency Timer, Subordinate Bus Number, 32 RW 0000_0000h

Secondary Bus Number, and Primary Bus Number
(SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG)
1Ch Secondary Status, I/O Limit, And Base 32 RW 0000_0000h

(SEC_STAT_IO_LIMIT_IO_BASE_REG)
20h Memory Limit and Base (MEM_LIMIT_MEM_BASE_REG) 32 RW 0000_0000h
24h Prefetchable Memory Limit And Base 32 RW 0000_0000h

(PREF_MEM_LIMIT_PREF_MEM_BASE_REG)
28h Prefetchable Base Upper 32 Bits (PREF_BASE_UPPER_REG) 32 RO 0000_0000h
2Ch Prefetchable Limit Upper 32 Bits (PREF_LIMIT_UPPER_REG) 32 RO 0000_0000h
30h I/O Limit And Base Upper 16 Bits 32 RO 0000_0000h

(IO_LIMIT_UPPER_IO_BASE_UPPER_REG)
34h Capabilities Pointer (TYPE1_CAP_PTR_REG) 32 RO 0000_0040h
38h Expansion ROM Base Address (TYPE1_EXP_ROM_BASE_REG) 32 RW 0000_0000h
3Ch Bridge Control, Interrupt Pin, And Interrupt Line 32 RW 0000_01FFh

(BRIDGE_CTRL_INT_PIN_INT_LINE_REG)
40h Power Management Capabilities (CAP_ID_NXT_PTR_REG) 32 RO DBC3_5001h
44h Power Management Control And Status (CON_STATUS_REG) 32 RW 0000_0008h
50h MSI Capability ID, Next Pointer, Capability And Control 32 RW 0180_7005h
(PCI_MSI_CAP_ID_NEXT_CTRL_REG)
54h MSI message lower address (MSI_CAP_OFF_04H_REG) 32 RW 0000_0000h
58h Data or upper address (MSI_CAP_OFF_08H_REG) 32 RW 0000_0000h
5Ch Data or mask bits (MSI_CAP_OFF_0CH_REG) 32 RW 0000_0000h
60h Pending or Mask Bits (MSI_CAP_OFF_10H_REG) 32 RW 0000_0000h
64h Pending Bits (MSI_CAP_OFF_14H_REG) 32 RO 0000_0000h

NXP Semiconductors
PCIe Controller
(In bits)
70h PCI Express Capabilities, ID, Next Pointer 32 RO 0042_B010h

(PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG)
74h Device Capabilities (DEVICE_CAPABILITIES_REG) 32 RO 0000_8001h
78h Device Control and Status (DEVICE_CONTROL_DEVICE_STATUS) 32 RW 0010_2010h
7Ch Link Capabilities (LINK_CAPABILITIES_REG) 32 RO 007A_6823h
80h Link Control and Status (LINK_CONTROL_LINK_STATUS_REG) 32 RW 1011_0000h
84h Slot Capabilities (SLOT_CAPABILITIES_REG) 32 RO 0000_0000h
88h Slot Control and Status (SLOT_CONTROL_SLOT_STATUS) 32 RW 0040_03C0h
8Ch Root Control and Capabilities 32 RW 0001_0000h

(ROOT_CONTROL_ROOT_CAPABILITIES_REG)
90h Root Status (ROOT_STATUS_REG) 32 W1C 0000_0000h
94h Device Capabilities 2 (DEVICE_CAPABILITIES2_REG) 32 RO 0000_041Fh
98h Device Control 2 and Status 2 32 RW 0000_0000h

(DEVICE_CONTROL2_DEVICE_STATUS2_REG)
9Ch Link Capabilities 2 (LINK_CAPABILITIES2_REG) 32 RO 0000_000Eh
A0h Link Control 2 and Status 2 32 RW 0001_0003h

(LINK_CONTROL2_LINK_STATUS2_REG)
B0h MSI-X Capability ID, Next Pointer, Control 32 RW 003F_0011h

B4h MSI-X Table Offset and BIR (MSIX_TABLE_OFFSET_REG) 32 RO 0000_0002h
B8h MSI-X PBA Offset and BIR (MSIX_PBA_OFFSET_REG) 32 RO 0000_1002h
100h Advanced Error Reporting Extended Capability Header 32 RO 1482_0001h

104h Uncorrectable Error Status (UNCORR_ERR_STATUS_OFF) 32 W1C 0000_0000h
108h Uncorrectable Error Mask (UNCORR_ERR_MASK_OFF) 32 RW 0040_0000h
10Ch Uncorrectable Error Severity (UNCORR_ERR_SEV_OFF) 32 RW 0046_2030h
110h Correctable Error Status (CORR_ERR_STATUS_OFF) 32 W1C 0000_0000h
114h Correctable Error Mask (CORR_ERR_MASK_OFF) 32 RW 0000_E000h
118h Advanced Error Capabilities and Control 32 RW 0000_00A0h

(ADV_ERR_CAP_CTRL_OFF)
11Ch Header Log Register 0 (HDR_LOG_0_OFF) 32 RO 0000_0000h
120h Header Log Register 1 (HDR_LOG_1_OFF) 32 RO 0000_0000h

NXP Semiconductors
PCIe Controller
(In bits)
12Ch Root Error Command (ROOT_ERR_CMD_OFF) 32 RW 0000_0000h
130h Root Error Status (ROOT_ERR_STATUS_OFF) 32 W1C 0000_0000h
134h Error Source Identification (ERR_SRC_ID_OFF) 32 RO 0000_0000h
138h TLP Prefix Log Register 1 (TLP_PREFIX_LOG_1_OFF) 32 RO 0000_0000h
13Ch TLP Prefix Log Register 2 (TLP_PREFIX_LOG_2_OFF) 32 RO 0000_0000h
148h SPCIE Capability Header (SPCIE_CAP_HEADER_REG) 32 RO 1581_0019h
14Ch Link control 3 (LINK_CONTROL3_REG) 32 RW 0000_0000h
150h Lane Error Status (LANE_ERR_STATUS_REG) 32 W1C 0000_0000h
154h Lane Equalization Control Register For Lanes 1 And 0 32 RO 7F7F_7F7Fh

158h Vendor-Specific Extended Capability Header 32 RO 2581_000Bh

15Ch Vendor-Specific Header (VENDOR_SPECIFIC_HEADER_REG) 32 RO 1004_0002h
160h Event Counter Control (EVENT_COUNTER_CONTROL_REG) 32 RW 0000_0000h
164h Event Counter Data (EVENT_COUNTER_DATA_REG) 32 RO 0000_0000h
168h Time-based Analysis Control 32 RW 0000_0100h

(TIME_BASED_ANALYSIS_CONTROL_REG)
16Ch Time-Based Analysis Data (TIME_BASED_ANALYSIS_DATA_REG) 32 RO 0000_03E8h
188h Error Injection Enable (EINJ_ENABLE_REG) 32 RW 0000_0000h
18Ch Error Injection Control 0 (CRC Error) (EINJ0_CRC_REG) 32 RW 0000_0000h
190h Error Injection Control 1 (Sequence Number Error) 32 RW 0000_0000h

(EINJ1_SEQNUM_REG)
194h Error Injection Control 2 (DLLP Error) (EINJ2_DLLP_REG) 32 RW 0000_0000h
198h Error Injection Control 3 (Symbol Error) (EINJ3_SYMBOL_REG) 32 RW 0000_0000h
19Ch Error Injection Control 4 (FC Credit Error) (EINJ4_FC_REG) 32 RW 0000_0000h
1A0h Error Injection Control 5 (Specific TLP Error) (EINJ5_SP_TLP_REG) 32 RW 0000_0000h
1A4h Error Injection Control 6 (Compare Point Header DWORD #0) 32 RW 0000_0000h
1A8h Error Injection Control 6 (Compare Point Header DWORD #1) 32 RW 0000_0000h

NXP Semiconductors
PCIe Controller
(In bits)
1ACh Error Injection Control 6 (Compare Point Header DWORD #2) 32 RW 0000_0000h
1B0h Error Injection Control 6 (Compare Point Header DWORD #3) 32 RW 0000_0000h
1B4h Error Injection Control 6 (Compare Value Header DWORD #0) 32 RW 0000_0000h
1B8h Error Injection Control 6 (Compare Value Header DWORD #1) 32 RW 0000_0000h
1BCh Error Injection Control 6 (Compare Value Header DWORD #2) 32 RW 0000_0000h
1C0h Error Injection Control 6 (Compare Value Header DWORD #3) 32 RW 0000_0000h
1C4h Error Injection Control 6 (Change Point Header DWORD #0) 32 RW 0000_0000h
1C8h Error Injection Control 6 (Change Point Header DWORD #1) 32 RW 0000_0000h
1CCh Error Injection Control 6 (Change Point Header DWORD #2) 32 RW 0000_0000h
1D0h Error Injection Control 6 (Change Point Header DWORD #3) 32 RW 0000_0000h
1D4h Error Injection Control 6 (Change Value Header DWORD #0) 32 RW 0000_0000h
1D8h Error Injection Control 6 (Change Value Header DWORD #1) 32 RW 0000_0000h
1DCh Error Injection Control 6 (Change Value Header DWORD #2) 32 RW 0000_0000h
1E0h Error Injection Control 6 (Change Value Header DWORD #3) 32 RW 0000_0000h
1E4h Error Injection Control 6 (Packet Error) (EINJ6_TLP_REG) 32 RW 0000_0000h
1F8h Silicon Debug Control 1 (SD_CONTROL1_REG) 32 RW 0000_0000h
1FCh Silicon Debug Control 2 (SD_CONTROL2_REG) 32 RW 0000_0000h
208h Silicon Debug Status (Layer1 Per-lane) 32 RW 0018_0000h

(SD_STATUS_L1LANE_REG)
20Ch Silicon Debug Status (Layer1 LTSSM) 32 W1C 0000_0200h

(SD_STATUS_L1LTSSM_REG)
210h Silicon Debug Status (PM) (SD_STATUS_PM_REG) 32 W1C 0000_0000h

NXP Semiconductors
PCIe Controller
(In bits)
214h Silicon Debug Status (Layer2) (SD_STATUS_L2_REG) 32 RO 00FF_F000h
218h Silicon Debug Status (Layer3 FC) (SD_STATUS_L3FC_REG) 32 RW 0300_0000h
21Ch Silicon Debug Status (Layer3) (SD_STATUS_L3_REG) 32 W1C 0000_0000h
22Ch Silicon Debug EQ Control 2 (SD_EQ_CONTROL2_REG) 32 RW 0000_0000h
23Ch Silicon Debug EQ Status 2 (SD_EQ_STATUS2_REG) 32 RO 0000_0000h
258h PCIe Extended Capability ID, Capability Version And Next Capability 32 RO 0001_000Bh
25Ch Vendor Specific Header (RASDP_VENDOR_SPECIFIC_HDR_OFF) 32 RO 0381_0001h
260h ECC error correction control (RASDP_ERROR_PROT_CTRL_OFF) 32 RW 0000_0000h
264h Corrected error (1-bit ECC) counter selection and control 32 RW 0000_0010h
268h Corrected error (1-bit ECC) counter data 32 RO 0000_0000h

(RASDP_CORR_COUNT_REPORT_OFF)
26Ch Uncorrected error (2-bit ECC and parity) counter selection and 32 RW 0000_0010h
control (RASDP_UNCORR_COUNTER_CTRL_OFF)
270h Uncorrected error (2-bit ECC and parity) counter data 32 RO 0000_0000h
274h Error injection control (RASDP_ERROR_INJ_CTRL_OFF) 32 RW 0000_0000h
278h Corrected errors locations 32 RO 00C0_00C0h

(RASDP_CORR_ERROR_LOCATION_OFF)
27Ch Uncorrected errors locations 32 RO 00C0_00C0h

(RASDP_UNCORR_ERROR_LOCATION_OFF)
280h RASDP error mode enable (RASDP_ERROR_MODE_EN_OFF) 32 RW 0000_0001h
284h Exit RASDP error mode (RASDP_ERROR_MODE_CLEAR_OFF) 32 W1C 0000_0000h
288h RAM Address where a corrected error (1-bit ECC) has been detected 32 RO 0000_0000h
28Ch RAM Address where an uncorrected error (2-bit ECC) has been 32 RO 0000_0000h
detected (RASDP_RAM_ADDR_UNCORR_ERROR_OFF)
700h Ack Latency Timer and Replay Timer 32 RW See

(ACK_LATENCY_TIMER_OFF) description

NXP Semiconductors
PCIe Controller
(In bits)
704h Vendor Specific DLLP (VENDOR_SPEC_DLLP_OFF) 32 RW FFFF_FFFFh
708h Port Force Link (PORT_FORCE_OFF) 32 RW 0080_0004h
70Ch Ack Frequency and L0-L1 ASPM Control 32 RW 1BB4_B400h

(ACK_F_ASPM_CTRL_OFF)
710h Port Link Control (PORT_LINK_CTRL_OFF) 32 RW 0003_0120h
714h Lane Skew (LANE_SKEW_OFF) 32 RW 0800_0000h
718h Timer Control and Max Function Number 32 RW 4002_4000h

(TIMER_CTRL_MAX_FUNC_NUM_OFF)
71Ch Symbol Timer and Filter Mask 1 (SYMBOL_TIMER_FILTER_1_OFF) 32 RW 0000_0280h
720h Filter Mask 2 (FILTER_MASK_2_OFF) 32 RW 0000_0000h
724h AMBA Multiple Outbound Decomposed NP SubRequests Control 32 RW 0000_0001h

728h Debug Register 0 (PL_DEBUG0_OFF) 32 RO 00B4_AF00h
72Ch Debug Register 1 (PL_DEBUG1_OFF) 32 RO 0820_0000h
730h Transmit Posted FC Credit Status 32 RO 0000_0000h

(TX_P_FC_CREDIT_STATUS_OFF)
734h Transmit Non-Posted FC Credit Status 32 RO 0000_0000h

(TX_NP_FC_CREDIT_STATUS_OFF)
738h Transmit Completion FC Credit Status 32 RO 0000_0000h

(TX_CPL_FC_CREDIT_STATUS_OFF)
73Ch Queue Status (QUEUE_STATUS_OFF) 32 RW 0000_0000h
740h VC Transmit Arbitration Register 1 (VC_TX_ARBI_1_OFF) 32 RO 0000_000Fh
744h VC Transmit Arbitration Register 2 (VC_TX_ARBI_2_OFF) 32 RO 0000_0000h
748h Segmented-Buffer VC0 Posted Receive Queue Control 32 RW 4523_0060h

(VC0_P_RX_Q_CTRL_OFF)
74Ch Segmented-Buffer VC0 Non-Posted Receive Queue Control 32 RW 0523_000Ch

(VC0_NP_RX_Q_CTRL_OFF)
750h Segmented-Buffer VC0 Completion Receive Queue Control 32 RW 0580_0000h

(VC0_CPL_RX_Q_CTRL_OFF)
80Ch Link Width And Speed Change Control (GEN2_CTRL_OFF) 32 RW 0003_02B4h
810h PHY Status (PHY_STATUS_OFF) 32 RO See

description
814h PHY Control (PHY_CONTROL_OFF) 32 RW 0000_0000h
81Ch Programmable Target Map Control (TRGT_MAP_CTRL_OFF) 32 RW 0000_007Bh

NXP Semiconductors
PCIe Controller
(In bits)
820h Integrated MSI Reception Module (iMRM) Address 32 RW 0000_0000h

(MSI_CTRL_ADDR_OFF)
824h Integrated MSI Reception Module Upper Address 32 RW 0000_0000h

(MSI_CTRL_UPPER_ADDR_OFF)
828h Integrated MSI Reception Module Interrupt #0 Enable 32 RW 0000_0000h

(MSI_CTRL_INT_0_EN_OFF)
82Ch Integrated MSI Reception Module Interrupt #0 Mask 32 RW 0000_0000h

(MSI_CTRL_INT_0_MASK_OFF)
830h Integrated MSI Reception Module Interrupt #0 Status 32 W1C 0000_0000h

(MSI_CTRL_INT_0_STATUS_OFF)

838h Integrated MSI Reception Module Interrupt #1 Mask 32 RW 0000_0000h

83Ch Integrated MSI Reception Module Interrupt #1 Status 32 W1C 0000_0000h




84Ch Integrated MSI Reception Module Interrupt #3 Enable 32 RW 0000_0000h




85Ch Integrated MSI Reception Module Interrupt #4 Mask 32 RW 0000_0000h




NXP Semiconductors
PCIe Controller
(In bits)

86Ch Integrated MSI Reception Module Interrupt #5 Status 32 W1C 0000_0000h




87Ch Integrated MSI Reception Module Interrupt #7 Enable 32 RW 0000_0000h



888h Integrated MSI Reception Module General Purpose IO 32 RW 0000_0000h

(MSI_GPIO_IO_OFF)
88Ch RADM clock gating enable control (CLOCK_GATING_CTRL_OFF) 32 RW 0000_0001h
890h Gen3 Control (GEN3_RELATED_OFF) 32 RW 0000_2001h
8A8h Gen3 EQ Control (GEN3_EQ_CONTROL_OFF) 32 RW 0505_9F71h
8ACh Gen3 EQ Direction Change Feedback Mode Control 32 RW 0000_0040h

8B4h Order Rule Control (ORDER_RULE_CTRL_OFF) 32 RW 0000_0000h
8B8h PIPE Loopback Control (PIPE_LOOPBACK_CONTROL_OFF) 32 RW 0000_0003h
8BCh DBI Read-Only Write Enable (MISC_CONTROL_1_OFF) 32 RW 0000_0000h
8C0h UpConfigure Multi-lane Control (MULTI_LANE_CONTROL_OFF) 32 RW 0000_0080h
8C4h PHY Interoperability Control (PHY_INTEROP_CTRL_OFF) 32 RW 0000_0244h
8C8h TRGT_CPL_LUT Delete Entry Control 32 RW 0000_0000h

(TRGT_CPL_LUT_DELETE_ENTRY_OFF)
8CCh Link Reset Request Flush Control (LINK_FLUSH_CONTROL_OFF) 32 RW FF00_0001h
8D0h AXI Bridge Slave Error Response 32 RW 0000_9C00h

(AMBA_ERROR_RESPONSE_DEFAULT_OFF)
8D4h Link Down AXI Bridge Slave Timeout (AMBA_LINK_TIMEOUT_OFF) 32 RW 0000_0032h
8D8h AMBA Ordering Control (AMBA_ORDERING_CTRL_OFF) 32 RW 0000_0000h

NXP Semiconductors
PCIe Controller
(In bits)



8F0h Lower 20 bits of the programmable AXI address 32 RW 0000_0000h

where Messages coming from wire are mapped to
(AXI_MSTR_MSG_ADDR_LOW_OFF)
8F4h Upper 32 bits of the programmable AXI address 32 RW 0000_0000h

where Messages coming from wire are mapped to
(AXI_MSTR_MSG_ADDR_HIGH_OFF)
8F8h PCIe Controller IIP Release Version Number 32 RO 3530_302Ah

(PCIE_VERSION_NUMBER_OFF)
8FCh PCIe Controller IIP Release Version Type 32 RO 6C70_3033h

(PCIE_VERSION_TYPE_OFF)
930h Interface Timer Control (INTERFACE_TIMER_CONTROL_OFF) 32 RW 0000_0000h
934h Interface Timer Target (INTERFACE_TIMER_TARGET_OFF) 32 RW 0000_0032h
938h Interface Timer Status (INTERFACE_TIMER_STATUS_OFF) 32 W1C 0000_0000h
940h MSI-X Address Match Low (MSIX_ADDRESS_MATCH_LOW_OFF) 32 RW 0000_0000h
944h MSI-X Address Match High (MSIX_ADDRESS_MATCH_HIGH_OFF) 32 RW 0000_0000h
948h MSI-X Doorbell (MSIX_DOORBELL_OFF) 32 WO 0000_0000h
94Ch MSI-X RAM Power Mode And Debug Control 32 RW 0000_0000h

(MSIX_RAM_CTRL_OFF)
960h Masks for functional safety interrupt events (SAFETY_MASK_OFF) 32 RW 0000_0000h
964h Status for functional safety interrupt events. 32 W1C 0000_0000h

(SAFETY_STATUS_OFF)
B20h CDM Register Checking Control and Status 32 RW 0000_0000h

(PL_CHK_REG_CONTROL_STATUS_OFF)
B24h CDM Register Checking First and Last address to check 32 RW 0BFF_0000h
(PL_CHK_REG_START_END_OFF)
B28h CDM Register Checking Error Address. 32 RO 0000_0000h

(PL_CHK_REG_ERR_ADDR_OFF)
B2Ch CDM Register Checking error PF and VF Numbers 32 RO 0000_0000h

(PL_CHK_REG_ERR_PF_VF_OFF)
B40h Auxiliary Clock Frequency Control (AUX_CLK_FREQ_OFF) 32 RW 0000_000Ah

NXP Semiconductors
PCIe Controller
(In bits)
2_001Ch BAR3 Mask (BAR3_MASK) 32 WO FFFF_FFFFh













NXP Semiconductors
PCIe Controller
(In bits)

















NXP Semiconductors
PCIe Controller
(In bits)
















NXP Semiconductors
PCIe Controller
(In bits)














6_0A08h iATU Lower Base Address 32 RW 0000_0000h

6_0A0Ch iATU Upper Base Address 32 RW 0000_0000h

6_0A10h iATU Limit Address (IATU_LIMIT_ADDR_OFF_OUTBOUND_5) 32 RW 0000_0FFFh

NXP Semiconductors
PCIe Controller
(In bits)
6_0A14h iATU Lower Target Address 32 RW 0000_0000h

6_0A18h iATU Upper Target Address 32 RW 0000_0000h

6_0A20h iATU Upper Limit Address 32 RW 0000_0000h

3.8.2 Device ID And Vendor ID (TYPE1_DEV_ID_VEND_ID_REG)
Offset
Register Offset
TYPE1_DEV_ID_VEND_ 0h
ID_REG
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R DEVICE_ID
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VENDOR_ID
Reset 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 1
Fields
Field Function
31-16 Device ID
DEVICE_ID Identifies the device ID. See the chip-specific SerDes information for this value.

NXP Semiconductors
PCIe Controller
Field Function
15-0 Vendor ID
VENDOR_ID Identifies the manufacturer of the Function. Valid vendor identifiers are allocated by the PCI-SIG to ensure
uniqueness. It is not permitted to populate this register with a value of FFFFh, which is an invalid value for
Vendor ID.
- Wire: No access.
3.8.3 Status and Command (TYPE1_STATUS_COMMAND_REG)
Offset
Register Offset
TYPE1_STATUS_COM 4h
MAND_REG
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DETE SIGNA RCVD RCVD SIGNA DEV_SEL_TIMI MAST FAST_ FAST_ CAP_ INT_S
R 0 0
CTE... LE... _MA... _TA... LE... NG ER_... B2... 66... LIST TA...
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VGAP MWI_
R RESERV INT_ 0 SERR IDSEL PERR SCO
S EN BME MSE IO_EN
EN EN EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
Detected Parity Error. This bit is set by a Function whenever it receives a Poisoned TLP, regardless of
31
the state the Parity Error Response bit in the Command register. The bit is set when the Poisoned TLP is
DETECTED_PA received by a Function's primary side.
RITY_ERROR
30 Signaled System Error. This bit is set when a Function sends an ERR_FATAL or ERR_NONFATAL
Message, and the SERR# Enable bit in the Command register is 1b.

NXP Semiconductors
PCIe Controller
Field Function
SIGNALED_SY
S_ERROR
29 Received Master Abort. This bit is set when a Requester receives a Completion with Unsupported
Request Completion status. The bit is set when the Unsupported Request is received by a Function's
RCVD_MASTE primary side.
R_ABORT
28 Received Target Abort. This bit is set when a Requester receives a Completion with Completer Abort
Completion status. The bit is set when the Completer Abort is received by a Function's primary side.
RCVD_TARGE
T_ABORT
27 Signaled Target Abort. This bit is set when a Function completes a Posted or Non-Posted Request as
a Completer Abort error. This applies to a Function when the Completer Abort was generated by its
SIGNALED_TA primary side.
RGET_ABORT
26-25 DEVSEL Timing. This field was originally described in the PCI Local Bus Specification. Its functionality
does not apply to PCI Express. The controller hardwires it to 00b.
DEV_SEL_TIMI
NG
24 Master Data Parity Error. This bit is set by a Function if the Parity Error Response bit in the Command
register is 1b and either of the following two conditions occurs: - Port receives a Poisoned Completion
MASTER_DPE going downstream - Port transmits a Poisoned Request upstream If the Parity Error Response bit is 0b,
this bit is never set.
23 Fast Back-to-Back Transactions Capable. This bit was originally described in the PCI Local Bus
Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b.
FAST_B2B_CA
P
22 Reserved
21 66 MHz Capable. This bit was originally described in the PCI Local Bus Specification. Its functionality
does not apply to PCI Express. The controller hardwires this bit to 0b.
FAST_66MHZ_
CAP
20 Capabilities List. Indicates the presence of an Extended Capability list item. Since all PCI Express device
Functions are required to implement the PCI Express Capability structure, the controller hardwires this
CAP_LIST bit to 1b.
19 Interrupt Status. When set, indicates that an INTx emulation interrupt is pending internally in the
Function. INTx emulation interrupts forwarded by Functions from the secondary side are not reflected
INT_STATUS in this bit. Setting the Interrupt Disable bit has no effect on the state of this bit. For Functions that do not
generate INTx interrupts, the controller hardwires this bit to 0b.
18-16 Reserved

NXP Semiconductors
PCIe Controller
Field Function
15-11 Reserved
RESERV
10 Interrupt Disable. Controls the ability of a Function to generate INTx emulation interrupts. When set,
Functions are prevented from asserting INTx interrupts. Note: - Any INTx emulation interrupts already
INT_EN asserted by the Function must be deasserted when this bit is set. INTx interrupts use virtual wires
that must, if asserted, be deasserted using the appropriate Deassert_INTx message(s) when this bit is
set. - Only the INTx virtual wire interrupt(s) associated with the Function(s) for which this bit is set are
affected. - For Functions that generate INTx interrupts on their own behalf, this bit is required. This bit
has no effect on interrupts forwarded from the secondary side. For Functions that do not generate INTx
interrupts on their own behalf this bit is optional. If this bit is not implemented, the controller hardwires it
to 0b.
9 Reserved
8 SERR# Enable. When set, this bit enables reporting upstream of Non-fatal and Fatal errors detected
by the Function. Note: The errors are reported if enabled either through this bit or through the PCI
SERREN Express specific bits in the Device Control register. For more details see the "Error Registers" section
of the PCI Express Specification. In addition, this bit controls transmission by the primary interface of
ERR_NONFATAL and ERR_FATAL error Messages forwarded from the secondary interface. This bit
does not affect the transmission of forwarded ERR_COR messages.
7 IDSEL Stepping/Wait Cycle Control. This bit was originally described in the PCI Local Bus Specification.
Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b.
IDSEL
6 Parity Error Response. This bit controls the logging of poisoned TLPs in the Master Data Parity
Error bit in the Status register. For more details see the "Error Registers" section of the PCI Express
PERREN Specification.
5 VGA Palette Snoop. This bit was originally described in the PCI Local Bus Specification and the PCI-to-
PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller
VGAPS hardwires this bit to 0b.
4 Memory Write and Invalidate. This bit was originally described in the PCI Local Bus Specification and
the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The
MWI_EN controller hardwires this bit to 0b. For PCI Express to PCI/PCI-X Bridges, refer to the PCI Express to
PCI/PCI-X Bridge Specification for requirements for this register.
3 Special Cycle Enable. This bit was originally described in the PCI Local Bus Specification. Its
functionality does not apply to PCI Express. The controller hardwires this bit to 0b.
SCO
2 Bus Master Enable. This bit controls forwarding of Memory or I/O requests by a port in the Upstream
direction. When this bit is 0b, Memory and I/O Requests received at a Root Port must be handled as
BME Unsupported Requests (UR) For Non-Posted Requests a Completion with UR completion status must
be returned. This bit does not affect forwarding of Completions in either the Upstream or Downstream
direction. The forwarding of Requests other than Memory or I/O Requests is not controlled by this bit.
1 Memory Space Enable. This bit controls a Function's response to Memory Space accesses received
on its primary side. - When set, the Function is enabled to decode the address and further process

NXP Semiconductors
PCIe Controller
Field Function
MSE Memory Space accesses. - When clear, all received Memory Space accesses are caused to be handled
as Unsupported Requests. You cannot write to this register if your configuration has no MEM bars; that
is, the internal signal has_mem_bar =0. Note: The access attributes of this field are as follows: - Wire: No
access.
0 IO Space Enable. This bit controls a Function's response to I/O Space accesses received on its
primary side. - When set, the Function is enabled to decode the address and further process I/O
IO_EN Space accesses. - When clear, all received I/O accesses are caused to be handled as Unsupported
Requests. You cannot write to this register if your configuration has no IO bars; that is, the internal signal
has_io_bar =0. Note: The access attributes of this field are as follows: - Wire: No access.
3.8.4 Class Code And Revision ID (TYPE1_CLASS_CODE_REV_ID_REG)
Offset
Register Offset
TYPE1_CLASS_CODE_ 8h
REV_ID_REG
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R BASE_CLASS_CODE SUBCLASS_CODE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R PROGRAM_INTERFACE REVISION_ID
Reset 0 0 0 0 0 0 0 0 u1 u u u u u u u
Fields
Field Function
31-24 Base Class Code. A code that broadly classifies the type of operation the Function performs. Encodings
for base class, are provided in the PCI Code and ID Assignment Specification. All unspecified encodings

NXP Semiconductors
PCIe Controller
Field Function
BASE_CLASS_ are reserved. Note: The access attributes of this field are as follows: - Wire: No access. Note: This
CODE register field is sticky.
23-16 Sub-Class Code. Specifies a base class sub-class, which identifies more specifically the operation of the
Function. Encodings for sub-class are provided in the PCI Code and ID Assignment Specification. All
SUBCLASS_C unspecified encodings are reserved. Note: The access attributes of this field are as follows: - Wire: No
ODE access. Note: This register field is sticky.
15-8 Programming Interface. This field identifies a specific register level programming interface (if any) so that
device independent software can interact with the Function. Encodings for interface are provided in the
PROGRAM_IN PCI Code and ID Assignment Specification. All unspecified encodings are reserved. Note: The access
TERFACE attributes of this field are as follows: - Wire: No access. Note: This register field is sticky.
7-0 Revision ID
REVISION_ID Identifies the revision ID. See the chip-specific SerDes information for this value.
3.8.5 BIST, Header Type, Latency Timer, and Cache Line Size
(TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG)
Offset
Register Offset
TYPE1_BIST_HDR_TYP Ch
E_LAT_CACHE_LINE_SI
ZE_REG
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MULTI
R BIST HEADER_TYPE
_F...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R LATENCY_MASTER_TIMER
CACHE_LINE_SIZE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-24 BIST. This register is used for control and status of BIST. Functions that do not support BIST must
hardwire the register to 00h. A Function whose BIST is invoked must not prevent normal operation of the
BIST PCI Express Link. Bit descriptions: - [31]: BIST Capable. When set, this bit indicates that the Function
supports BIST. When Clear, the Function does not support BIST. - [30]: Start BIST. If BIST Capable is
set, set this bit to invoke BIST. The Function resets the bit when BIST is complete. Software is permitted
to fail the device if this bit is not Clear (BIST is not complete) 2 seconds after it had been set. Writing this
bit to 0b has no effect. The controller hardwires this bit to 0b if BIST Capable is clear. - [29:28]: Reserved
- [27:24]: Completion Code. This field encodes the status of the most recent test. A value of 0000b
means that the Function has passed its test. Non-zero values mean the Function failed. Function-specific
failure codes can be encoded in the non-zero values. This field's value is only meaningful when BIST
Capable is set and Start BIST is Clear. This field must be hardwired to 0000b if BIST Capable is clear.
23 Multi-Function Device. - When set, indicates that the device may contain multiple Functions, but not
necessarily. Software is permitted to probe for Functions other than Function 0. - When clear, software
MULTI_FUNC must not probe for Functions other than Function 0 unless explicitly indicated by another mechanism,
such as an ARI or SR-IOV Capability structure. Except where stated otherwise, it is recommended that
this bit be set if there are multiple Functions, and clear if there is only one Function. Note: This register
field is sticky.
22-16 Header Layout

HEADER_TYP This field identifies the layout of the second part of the predefined header. The controller uses 000 0001b
E encoding. The encoding 000 0010b is reserved. This encoding was originally described in the PC Card
Standard Electrical Specification and is used in previous versions of the programming model. Careful
consideration should be given to any attempt to repurpose it.
15-8 Latency Timer. This register is also referred to as Primary Latency Timer. The Latency Timer
was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture
LATENCY_MA Specification. Its functionality does not apply to PCI Express. The controller hardwires this register to
STER_TIMER 00h.
7-0Cache Line Size. The Cache Line Size register is programmed by the system firmware or the operating
system to system cache line size. However, legacy conventional PCI software may not always be able
CACHE_LINE_ to program this register correctly especially in the case of Hot-Plug devices. This read-write register is
SIZE implemented for legacy compatibility purposes but has no effect on any PCI Express device behavior.
3.8.6 Secondary Latency Timer, Subordinate Bus Number, Secondary Bus Number, and Primary Bus
Number (SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG)
Offset
Register Offset
SEC_LAT_TIMER_SUB_ 18h
BUS_SEC_BUS_PRI_BU
S_REG

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R SEC_LAT_TIMER
SUB_BUS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
SEC_BUS PRIM_BUS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-24 Secondary Latency Timer. This register does not apply to PCI Express. The controller hardwires it to
00h.
SEC_LAT_TIM
ER
23-16 Subordinate Bus Number. The Subordinate Bus Number register is used to record the bus number of
the highest numbered PCI bus segment which is behind (or subordinate to) the bridge. Configuration
SUB_BUS software programs the value in this register. The bridge uses this register in conjunction with the
Secondary Bus Number register to determine when to respond to and pass on a Type 1 configuration
transaction on the primary interface to the secondary interface.
15-8 Secondary Bus Number. The Secondary Bus Number register is used to record the bus number of the
PCI bus segment to which the secondary interface of the bridge is connected. Configuration software
SEC_BUS programs the value in this register. The bridge uses this register to determine when to respond to and
convert a Type 1 configuration transaction on the primary interface into a Type 0 transaction on the
secondary interface.
7-0 Primary Bus Number. This register is not used by PCI Express Functions. It is implemented for
compatibility with legacy software.
PRIM_BUS
3.8.7 Secondary Status, I/O Limit, And Base (SEC_STAT_IO_LIMIT_IO_BASE_REG)
Offset
Register Offset
SEC_STAT_IO_LIMIT_I 1Ch
O_BASE_REG
Function
The I/O Limit and I/O Base registers are optional and define an address range that is used by the bridge to determine when to
forward I/O transactions from one interface to the other. If a bridge does not implement an I/O address range, then both the I/O
Limit and I/O Base registers must be implemented as read-only registers that return zero when read. If a bridge supports an I/O
address range, then these registers must be initialized by configuration software so default states are not specified.

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SEC_S SEC_S SEC_S SEC_S SEC_S SEC_S

R 0 0 SEC_STAT_RESERV
TA... TA... TA... TA... TA... TA...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IO_DE IO_DE
R IO_RESERV1 IO_RESERV
IO_LIMIT CO... IO_BASE CO...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31 Detected Parity Error. This bit is set by a Function when a Poisoned TLP is received by its secondary
side, regardless of the state the Parity Error Response Enable bit in the Bridge Control register.
SEC_STAT_DP
E
30 Received System Error. This bit is set when the secondary side of a Function receives an ERR_FATAL
or ERR_NONFATAL message.
SEC_STAT_RC
VD_SYS_ERR
29 Received Master Abort. This bit is set when the secondary side of a Function (for requests initiated by
the Type 1 header Function itself) receives a Completion with Unsupported Request Completion status.
SEC_STAT_RC
VD_MSTR_AB
RT
28 Received Target Abort. This bit is set when the secondary side of a Function (for requests initiated by the
Type 1 header Function itself) receives a Completion with Completer Abort Completion status.
SEC_STAT_RC
VD_TRGT_ABR
T
27 Signaled Target Abort. This bit is set when the secondary side of the Function (for Requests completed
by the Type 1 header Function itself) completes a Posted or Non-Posted request as a Completer Abort
SEC_STAT_SI error.
G_TRGT_ABRT
26-25 Reserved
Master Data Parity Error. This bit is set by a Function if the Parity Error Response Enable bit in
24
the Bridge Control register is set, and either of the following two conditions occurs: - Port receives a
SEC_STAT_MD Poisoned Completion coming Upstream - Port transmits a Poisoned Request Downstream If the Parity
PE Error Response Enable bit is clear, this bit is never set.
23 Reserved

NXP Semiconductors
PCIe Controller
Field Function
22-16 Reserved
SEC_STAT_RE
SERV
15-12 I/O Limit Address. These bits correspond to the address[15:12] of IO address range. For the purpose
of address decoding, the bridge assumes that the lower 12 address bits, address[11:0], of the I/O limit
IO_LIMIT address (not implemented in the I/O Limit register) are FFFh. The I/O Limit register can be programmed
to a smaller value than the I/O Base register, if there are no I/O addresses on the secondary side of
the bridge. In this case, the bridge will not forward any I/O transactions from the primary bus to the
secondary and will forward all I/O transactions from the secondary bus to the primary bus.
11-9 Reserved
IO_RESERV1
8 I/O Addressing Encode (I/O Limit Address)

IO_DECODE_B Encodes the I/O addressing capability of the bridge.
IT8
- Wire: No access.
0b - The bridge supports only 16-bit I/O addressing (for ISA compatibility). For the purpose of
address decoding, the bridge assumes that the upper 16 address bits, Address[31:16], of the I/O
limit address (not implemented in I/O Limit register) are zero. The bridge must still perform a full
32-bit decode of the I/O address (that is, check that Address[31:16] are 0000h). In this case, the
I/O address range supported by the bridge is restricted to the first 64 KB of I/O space (0h to
FFFFh).
1b - The bridge supports 32-bit I/O address decoding. The I/O limit upper 16 bits hold the
upper 16 bits, corresponding to Address[31:16], of the 32-bit Limit address. In this case, system
configuration software is permitted to locate the I/O address range supported by the bridge
anywhere in the 4 GB I/O space. The 4 KB alignment and granularity restrictions still apply when
the bridge supports 32-bit I/O addressing.
7-4 I/O Base Address. These bits correspond to the address[15:12] of IO address range. For the purpose
of address decoding, the bridge assumes that the lower 12 address bits, address[11:0], of the I/O base
IO_BASE address (not implemented in the I/O Base register) are zero.
3-1 Reserved
IO_RESERV
0 I/O addressing encode (I/O base address)

IO_DECODE This field encodes the IO addressing capability of the bridge.
- Wire: No access.

NXP Semiconductors
PCIe Controller
Field Function
0b - The bridge supports only 16-bit I/O addressing (for ISA compatibility). For the purpose of
address decoding, the bridge assumes that the upper 16 address bits, Address[31:16], of the I/O
base address (not implemented in I/O base register) are zero. The bridge must still perform a
full 32-bit decode of the I/O address (that is, check that Address[31:16] are 0000h). In this case,
the I/O address range supported by the bridge will be restricted to the first 64 KB of I/O space
(0000_0000h to 0000_FFFFh).
1b - The bridge supports 32-bit I/O address decoding, and the I/O base upper 16 bits hold the
upper 16 bits, corresponding to Address[31:16], of the 32-bit base address. In this case, system
configuration software is permitted to locate the I/O address range supported by the bridge
anywhere in the 4 GB I/O space. The 4 KB alignment and granularity restrictions still apply when
the bridge supports 32-bit I/O addressing.
3.8.8 Memory Limit and Base (MEM_LIMIT_MEM_BASE_REG)
Offset
Register Offset
MEM_LIMIT_MEM_BAS 20h
E_REG
Function
Memory Limit and Base Register. The Memory Limit and Memory Base registers define a memory mapped address range
which is used by the bridge to determine when to forward memory transactions from one interface to the other. If there is no
prefetchable memory space, and there is no memory-mapped space on the secondary side of the bridge, then the bridge will
not forward any memory transactions from the primary bus to the secondary bus and will forward all memory transactions from
the secondary bus to the primary bus.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R MEM_LIMIT_RESERV
MEM_LIMIT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R MEM_BASE_RESERV
MEM_BASE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-20 Memory Limit Address. These bits correspond to the upper 12 address bits, Address[31:20], of 32-bit
addresses. For the purpose of address decoding, the bridge assumes that the lower 20 address bits,
MEM_LIMIT Address[19:0], of the memory limit address (not implemented in the Memory Limit register) are F FFFFh.
The Memory Limit register must be programmed to a smaller value than the Memory Base register if
there is no memory-mapped address space on the secondary side of the bridge.
19-16 Reserved
MEM_LIMIT_R
ESERV
15-4 Memory Base Address. These bits correspond to the upper 12 address bits, Address[31:20], of 32-bit
addresses. For the purpose of address decoding, the bridge assumes that the lower 20 address bits,
MEM_BASE Address[19:0], of the memory base address (not implemented in the Memory Base register) are zero.
3-0 Reserved
MEM_BASE_R
ESERV
3.8.9 Prefetchable Memory Limit And Base (PREF_MEM_LIMIT_PREF_MEM_BASE_REG)
Offset
Register Offset
PREF_MEM_LIMIT_PRE 24h
F_MEM_BASE_REG
Function
The Prefetchable Memory Limit and Prefetchable Memory Base registers must indicate that 64-bit addresses are supported,
as defined in PCI-to-PCI Bridge Architecture Specification. The Prefetchable Memory Limit and Prefetchable Memory Base
registers are optional. They define a prefetchable memory address range which is used by the bridge to determine when
to forward memory transactions from one interface to the other (see the PCI-to-PCI Bridge Architecture Specification for
additional details).

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PREF_
R PREF_RESERV1
PREF_MEM_LIMIT ME...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PREF_
R PREF_RESERV
PREF_MEM_BASE ME...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
Prefetchable Memory Limit Address. If the Prefetchable Memory Limit register indicates support for
31-20
32-bit addressing, then the Prefetchable Limit Upper 32 Bits register is implemented as a read-only
PREF_MEM_LI register that returns zero when read. If the Prefetchable Memory Limit registers indicate support for 64-
MIT bit addressing, then the Prefetchable Limit Upper 32 Bits register is implemented as a read/write register
which must be initialized by configuration software. If a 64-bit prefetchable memory address range is
supported, the Prefetchable Limit Upper 32 Bits register specifies the upper 32 bits, corresponding to
Address[63:32], of the 64-bit limit addresses which specify the prefetchable memory address range.
19-17 Reserved
PREF_RESER
V1
Prefetchable Memory Limit Decode. This bit encodes whether or not the bridge supports 64-bit
16
addresses. The value of PREF_MEM_LIMIT_DECODE indicates the following: - 0b: Indicates that
PREF_MEM_LI the bridge supports only 32 bit addresses - 1b: Indicates that the bridge supports 64 bit addresses.
MIT_DECODE Prefetchable Limit Upper 32 Bits registers holds the rest of the 64-bit prefetchable limit address.
15-4 Prefetchable Memory Base Address. If the Prefetchable Memory Base register indicates support for
32-bit addressing, then the Prefetchable Base Upper 32 Bits register is implemented as a read-only
PREF_MEM_B register that returns zero when read. If the Prefetchable Memory Base register indicates support for 64-
ASE bit addressing, then the Prefetchable Limit Upper 32 Bits register is implemented as a read/write register
which must be initialized by configuration software. If a 64-bit prefetchable memory address range is
supported, the Prefetchable Base Upper 32 Bits register specifies the upper 32 bits, corresponding to
Address[63:32], of the 64-bit base addresses which specify the prefetchable memory address range.
3-1 Reserved
PREF_RESER
V
0 Prefetchable Memory Base Decode

PREF_MEM_D Encodes whether or not the bridge supports 64-bit addresses.
ECODE

NXP Semiconductors
PCIe Controller
Field Function
- Wire: No access.
0b - The bridge supports only 32-bit addresses.
1b - The bridge supports 64 bit addresses; Prefetchable Base Upper 32 Bits registers holds the
rest of the 64-bit prefetchable base address
3.8.10 Prefetchable Base Upper 32 Bits (PREF_BASE_UPPER_REG)
Offset
Register Offset
PREF_BASE_UPPER_R 28h
EG
Function
Optional extension to the Prefetchable Memory Base register.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R PREF_MEM_BASE_UPPER
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R PREF_MEM_BASE_UPPER
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0 Prefetchable Base Upper 32 Bit

PREF_MEM_B If the Prefetchable Memory Base register indicates support for 32-bit addressing, then this register is
ASE_UPPER implemented as read-only register that returns zero when read.
If the Prefetchable Memory Base register indicate support for 64-bit addressing, then this register is
implemented as read/write register which must be initialized by configuration software.

NXP Semiconductors
PCIe Controller
Field Function
This register specifies the upper 32 bits, corresponding to Address[63:32], of the 64-bit base addresses
which specify the prefetchable memory address range.
- Wire: No access.
3.8.11 Prefetchable Limit Upper 32 Bits (PREF_LIMIT_UPPER_REG)
Offset
Register Offset
PREF_LIMIT_UPPER_R 2Ch
EG
Function
Optional extension to the Prefetchable Memory Limit register.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R PREF_MEM_LIMIT_UPPER
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R PREF_MEM_LIMIT_UPPER
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0 Prefetchable Limit Upper 32 Bit

PREF_MEM_LI If the Prefetchable Memory Limit register indicate support for 64-bit addressing, then this register is
MIT_UPPER implemented as read/write register which must be initialized by configuration software.
This register specifies the upper 32 bits, corresponding to Address[63:32], of the 64-bit base addresses
which specify the prefetchable memory address range.
- Wire: No access.

NXP Semiconductors
PCIe Controller
3.8.12 I/O Limit And Base Upper 16 Bits (IO_LIMIT_UPPER_IO_BASE_UPPER_REG)
Offset
Register Offset
IO_LIMIT_UPPER_IO_B 30h
ASE_UPPER_REG
Function
Optional extensions to the I/O Limit and I/O Base registers.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R IO_LIMIT_UPPER
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R IO_BASE_UPPER
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-16 I/O Limit Upper 16 Bits. If the I/O Limit register indicates support for 16-bit I/O address decoding, then
this register is implemented as a read-only register which return zero when read. If the I/O Limit register
IO_LIMIT_UPP indicates support for 32-bit I/O addressing, then this register must be initialized by configuration software.
ER If 32-bit I/O address decoding is supported, this register specifies the upper 16 bits, corresponding to
Address[31:16], of the 32-bit limit address, that specify the I/O address range. See the PCI-to-PCI Bridge
Architecture Specification for additional details). Note: The access attributes of this field are as follows: -
Wire: No access.
I/O Base Upper 16 Bits. If the I/O Base register indicates support for 16-bit I/O address decoding, then
15-0
this register is implemented as a read-only register which return zero when read. If the I/O base register
IO_BASE_UPP indicates support for 32-bit I/O addressing, then this register must be initialized by configuration software.
ER If 32-bit I/O address decoding is supported, this register specifies the upper 16 bits, corresponding to
Address[31:16], of the 32-bit base address, that specify the I/O address range. See the PCI-to-PCI
Bridge Architecture Specification for additional details. Note: The access attributes of this field are as
follows: - Wire: No access.

NXP Semiconductors
PCIe Controller
3.8.13 Capabilities Pointer (TYPE1_CAP_PTR_REG)
Offset
Register Offset
TYPE1_CAP_PTR_REG 34h
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 CAP_POINTER
Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
Fields
Field Function
31-8 Reserved
7-0 Capabilities Pointer

CAP_POINTER Used to point to a linked list of capabilities implemented by this Function. Since all PCI Express Functions
are required to implement the PCI Express Capability structure, this register must point to a valid capability
structure and either this structure is the PCI Express Capability structure, or a subsequent list item points to
the PCI Express Capability structure. The bottom two bits are Reserved and must be set to 00b. Software
must mask these bits off before using this register as a pointer in Configuration Space to the first entry of a
linked list of new capabilities.
- Wire: No access.

NXP Semiconductors
PCIe Controller
3.8.14 Expansion ROM Base Address (TYPE1_EXP_ROM_BASE_REG)
Offset
Register Offset
TYPE1_EXP_ROM_BAS 38h
E_REG
Function
This register is defined to handle the base address and size information for this expansion ROM. The mask for this ROM BAR
exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2
address bit for the AXI bridge) is required to write to the second register at this address.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
EXP_ROM_BASE_ADDRESS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 ROM_
EXP_ROM_BASE_ADDRESS
W BAR...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-11 Expansion ROM Base Address. Upper 21 bits of the Expansion ROM base address. The number of bits
(out of these 21) that a Function actually implements depends on how much address space the Function
EXP_ROM_BA requires. The mask for this ROM BAR exists (if implemented) as a shadow register at this address. The
SE_ADDRESS assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required
to write to the second register at this address. Note: The access attributes of this field are as follows: -
Wire: No access.
10-1 Reserved
Expansion ROM Enable. This bit controls whether or not the Function accepts accesses to its expansion
0
ROM. When this bit is 0b, the Function's expansion ROM address space is disabled. When the bit is
ROM_BAR_EN 1b, address decoding is enabled using the parameters in the other part of the Expansion ROM Base
ABLE Address register. The Memory Space Enable bit in the Command register has precedence over the
Expansion ROM Enable bit. A Function must claim accesses to its expansion ROM only if both the
Memory Space Enable bit and the Expansion ROM Enable bit are set. Note: The access attributes of this
field are as follows: - Wire: No access.

NXP Semiconductors
PCIe Controller
3.8.15 Bridge Control, Interrupt Pin, And Interrupt Line (BRIDGE_CTRL_INT_PIN_INT_LINE_REG)
Offset
Register Offset
BRIDGE_CTRL_INT_PIN 3Ch
_INT_LINE_REG
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSTR VGA_1 VGA_

R BRIDGE_CTRL_RESERV ISA_ SERR
SBR _AB... 6B... EN PERE
EN _EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R INT_PIN
INT_LINE
W
Reset 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1
Fields
Field Function
31-23 Reserved
BRIDGE_CTRL
_RESERV
22 Secondary Bus Reset. Setting this bit triggers a hot reset on the corresponding PCI Express Port.
Software must ensure a minimum reset duration (Trst) as defined in the PCI Local Bus Specification.
SBR Software and systems must honor first-access-following-reset timing requirements, unless the Readiness
Notifications mechanism is used or if the Immediate Readiness bit in the relevant Function's Status
Register register is set. Port configuration registers must not be changed, except as required to update
Port status.
Master Abort Mode. This bit was originally described in the PCI-to-PCI Bridge Architecture Specification.
21
Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b. Note: The access
MSTR_ABORT attributes of this field are as follows: - Wire: No access.
_MODE
VGA 16 bit decode. This bit only has meaning if VGA Enable bit is set. This bit enables system
20
configuration software to select between 10-bit and 16-bit I/O address decoding for all VGA I/O register
VGA_16B_DEC accesses that are forwarded from primary to secondary. The following actions are taken based on the
value of the VGA_16B_DEC bit: - 0b: Execute 10-bit address decodes on VGA I/O accesses - 1b:
Execute 16-bit address decodes on VGA I/O accesses For Functions that do not support VGA, the
controller hardwires this bit to 0b. Note: The access attributes of this field are as follows: - Wire: No
access.

NXP Semiconductors
PCIe Controller
Field Function
19 VGA Enable. Modifies the response by the bridge to VGA compatible addresses. If the VGA Enable bit
is set, the bridge will positively decode and forward the following accesses on the primary interface to
VGA_EN the secondary interface (and, conversely, block the forwarding of these addresses from the secondary
to primary interface): - Memory accesses in the range 000A 0000h to 000B FFFFh - I/O addresses
in the first 64 KB of the I/O address space (Address[31:16] are 0000h) where Address[9:0] are in the
ranges 3B0h to 3BBh and 3C0h to 3DFh (inclusive of ISA address aliases determined by the setting
of VGA 16-bit Decode ) If the VGA Enable bit is set, forwarding of these accesses is independent of
the I/O address range and memory address ranges defined by the I/O Base and Limit registers, the
Memory Base and Limit registers, and the Prefetchable Memory Base and Limit registers of the bridge.
(Forwarding of these accesses is also independent of the setting of the ISA Enable bit (in the Bridge
Control register) when the VGA Enable bit is set. Forwarding of these accesses is qualified by the I/O
Space Enable and Memory Space Enable bits in the Command register.) The following actions are taken
based on the value of the VGA_EN bit: - 0b: Do not forward VGA compatible memory and I/O addresses
from the primary to the secondary interface (addresses defined above) unless they are enabled for
forwarding by the defined I/O and memory address ranges - 1b: Forward VGA compatible memory and
I/O addresses (addresses defined above) from the primary interface to the secondary interface (if the
I/O Space Enable and Memory Space Enable bits are set) independent of the I/O and memory address
ranges and independent of the ISA Enable bit For Functions that do not support VGA, the controller
hardwires this bit to 0b. Note: The access attributes of this field are as follows: - Wire: No access.
18 ISA Enable. Modifies the response by the bridge to ISA I/O addresses. This applies only to I/O
addresses that are enabled by the I/O Base and I/O Limit registers and are in the first 64 KB of I/O
ISA_EN address space (0000 0000h to 0000 FFFFh). If this bit is set, the bridge will block any forwarding
from primary to secondary of I/O transactions addressing the last 768 bytes in each 1-KB block. In the
opposite direction (secondary to primary), I/O transactions will be forwarded if they address the last
768 bytes in each 1-KB block. The following actions are taken based on the value of the ISA_EN bit: -
0b: Forward downstream all I/O addresses in the address range defined by the I/O Base and I/O Limit
registers - 1b: Forward upstream ISA I/O addresses in the address range defined by the I/O Base and
I/O Limit registers that are in the first 64 KB of PCI I/O address space (top 768 bytes of each 1-KB block.
17 SERR# Enable. This bit controls forwarding of ERR_COR, ERR_NONFATAL and ERR_FATAL from
secondary to primary.
SERR_EN
16 Parity Error Response Enable. This bit controls the logging of poisoned TLPs in the Master Data Parity
Error bit in the Secondary Status register.
PERE
15-8 Interrupt PIN

INT_PIN Identifies the legacy interrupt Message(s) the Function uses. Valid values are:
• 00h: The Function uses no legacy interrupt Message(s)
• 01h, 02h, 03h, and 04h: Map to legacy interrupt Messages for INTA, INTB, INTC, and INTD
respectively
• 05h through FFh: Reserved
PCI Express defines one legacy interrupt Message for a single Function device and up to four legacy
interrupt Messages for a multi-Function device. For a single Function device, only INTA may be used.

NXP Semiconductors
PCIe Controller
Field Function
Any Function on a multi-Function device can use any of the INTx Messages. If a device implements a single
legacy interrupt Message, it must be INTA; if it implements two legacy interrupt Messages, they must be
INTA and INTB; and so forth.
For a multi-Function device, all Functions may use the same INTx Message or each may have its own (up to
a maximum of four Functions) or any combination thereof. A single Function can never generate an interrupt
request on more than one INTx Message.
- Wire: No access.
7-0 Interrupt Line. The Interrupt Line register communicates interrupt line routing information. The register
must be implemented by any Function that uses an interrupt pin. Values in this register are programmed
INT_LINE by system software and are system architecture specific. The Function itself does not use this value;
rather the value in this register is used by device drivers and operating systems.
3.8.16 Power Management Capabilities (CAP_ID_NXT_PTR_REG)
Offset
Register Offset
CAP_ID_NXT_PTR_REG 40h
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
D2_SU D1_SU PME_

R PME_SUPPORT AUX_CURR DSI 0 PM_SPEC_VER
PP... PP... CLK
Reset 1 1 0 1 1 0 1 1 1 1 0 0 0 0 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R PM_NEXT_POINTER PM_CAP_ID
Reset 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-27 Power Management Event Support

PME_SUPPOR This field indicates the power states in which a Function can generate a power-management event (PME).
T The individual bits within this field are associated with power states as shown below. A value of 1b for any
bit indicates that the Function is capable of asserting the PME signal in that power state. A value of 0b for
any bit indicates that the Function is not capable of asserting the PME signal in that power state .
• Bit 4 (leftmost in the register diagram): D3cold
• Bit 3: D3hot
• Bit 2: D2
• Bit 1: D1
• Bit 0 (rightmost in the register diagram): D0
26 D2 State Support
D2_SUPPORT For a description of this standard PCIe register field, see the PCI Express Specification.
- Wire: No access.
25 D1 State Support
D1_SUPPORT For a description of this standard PCIe register field, see the PCI Express Specification.
- Wire: No access.
24-22 Auxiliary Current Requirements

AUX_CURR For a description of this standard PCIe register field, see the PCI Express Specification.
- Wire: No access.
21 Device Specific Initialization

DSI For a description of this standard PCIe register field, see the PCI Express Specification.

NXP Semiconductors
PCIe Controller
Field Function
- Wire: No access.
20 Reserved
19 PCI Clock Requirement

PME_CLK For a description of this standard PCIe register field, see the PCI Express Specification.
18-16 Power Management Spec Version

PM_SPEC_VE For a description of this standard PCIe register field, see the PCI Express Specification.
R
- Wire: No access.
15-8 Next Capability Pointer

PM_NEXT_POI For a description of this standard PCIe register field, see the PCI Express Specification.
NTER
- Wire: No access.
7-0 Power Management Capability ID. For a description of this standard PCIe register field, see the PCI
PM_CAP_ID
3.8.17 Power Management Control And Status (CON_STATUS_REG)
Offset
Register Offset
CON_STATUS_REG 44h
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUS_P B2_B3
R DATA_REG_ADD_INFO 0
WR... _S...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PME_ NO_S
R DATA_SCALE DATA_SELECT PME_ 0 0 POWER_STAT
STA... OFT...
ENA... E
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
Fields
Field Function
31-24 Power data information

DATA_REG_AD For a description of this standard PCIe register field, see the PCI Express Specification.
D_INFO
23 Bus power/clock control enable

BUS_PWR_CL For a description of this standard PCIe register field, see the PCI Express Specification.
K_CON_EN
22 B2B3 support for D3hot

B2_B3_SUPPO For a description of this standard PCIe register field, see the PCI Express Specification.
RT
21-16 Reserved
15 PME status
PME_STATUS For a description of this standard PCIe register field, see the PCI Express Specification.
14-13 Data scaling factor

DATA_SCALE For a description of this standard PCIe register field, see the PCI Express Specification.
12-9 Data select

DATA_SELECT For a description of this standard PCIe register field, see the PCI Express Specification.
8 PME enable
PME_ENABLE For a description of this standard PCIe register field, see the PCI Express Specification.
The PMC registers this value under aux power. Sometimes it might remember the old value, even if you try
to clear it by writing a 0 to it.

NXP Semiconductors
PCIe Controller
Field Function
7-4 Reserved
3 No Soft Reset
NO_SOFT_RST For a description of this standard PCIe register field, see the PCI Express Specification.
- Wire: No access.
2 Reserved
1-0 Power State

POWER_STAT For a description of this standard PCIe register field, see the PCI Express Specification.
E
You can write to this register. However, the read-back value is the actual power state, not the write value.
- Wire: No access.
3.8.18 MSI Capability ID, Next Pointer, Capability And Control (PCI_MSI_CAP_ID_NEXT_CTRL_REG)
Offset
Register Offset
PCI_MSI_CAP_ID_NEXT 50h
_CTRL_REG
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCI_M PCI_M PCI_P PCI_M PCI_MSI_MULTIPLE_M

R 0 PCI_MSI_MULTIPLE_M PCI_M
SI... SI... VM... SI... SG_CAP
SG_EN SI...
W
Reset 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R PCI_MSI_CAP_NEXT_OFFSET PCI_MSI_CAP_ID
Reset 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1
Fields
Field Function
31-27 Reserved
26 Extended message data enable

PCI_MSI_EXT_ For a description of this standard PCIe register, see the PCI-SIG ECN for Extended MSI Data, Feb 24, 2016,
DATA_EN affecting PCI Express Specification.
- Wire: No access.
25 Extended Message Data Capable

PCI_MSI_EXT_ For a description of this standard PCIe register, see the PCI-SIG ECN for Extended MSI Data, Feb 24, 2016,
DATA_CAP affecting PCI Express Specification.
- Wire: No access.
24 MSI Per Vector Masking Capable

PCI_PVM_SUP For a description of this standard PCIe register field, see the PCI Express Specification.
PORT
23 MSI 64-bit Address Capable

PCI_MSI_64_BI For a description of this standard PCIe register field, see the PCI Express Specification.
T_ADDR_CAP
- Wire: No access.

NXP Semiconductors
PCIe Controller
Field Function
22-20 MSI Multiple Message Enable. For a description of this standard PCIe register field, see the PCI Express
Specification.
PCI_MSI_MULT
IPLE_MSG_EN
19-17 MSI Multiple Message Capable

PCI_MSI_MULT For a description of this standard PCIe register field, see the PCI Express Specification.
IPLE_MSG_CA
P
- Wire: No access.
16 MSI Enable. For a description of this standard PCIe register field, see the PCI Express Specification.
PCI_MSI_ENAB
LE
15-8 MSI Capability Next Pointer

PCI_MSI_CAP_ For a description of this standard PCIe register field, see the PCI Express Specification.
NEXT_OFFSET
- Wire: No access.
7-0 MSI Capability ID. For a description of this standard PCIe register field, see the PCI Express
Specification.
PCI_MSI_CAP_
ID
3.8.19 MSI message lower address (MSI_CAP_OFF_04H_REG)
Offset
Register Offset
MSI_CAP_OFF_04H_RE 54h
G
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
PCI_MSI_CAP_OFF_04H
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
PCI_MSI_CAP_OFF_04H
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-2 MSI Message Lower Address Field. For a description of this standard PCIe register field, see the PCI
Express Specification. Note: The access attributes of this field are as follows: - Wire: No access.
PCI_MSI_CAP_
OFF_04H
1-0 Reserved
3.8.20 Data or upper address (MSI_CAP_OFF_08H_REG)
Offset
Register Offset
G
Function
For a 32 bit MSI Message, this register contains Data. For 64 bit it contains the Upper Address. For a description of this
standard PCIe register, see the PCI Express Specification.

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
PCI_MSI_CAP_OFF_0AH
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
PCI_MSI_CAP_OFF_08H
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-16For a 32 bit MSI Message, this field contains Ext MSI Data. For 64-bit it contains upper 16 bits of the
Upper Address. For a description of this standard PCIe register field, see the PCI Express Specification
PCI_MSI_CAP_ Note: The access attributes of this field are as follows: - Wire: No access.
OFF_0AH
For a 32-bit MSI Message, this field contains Data. For 64-bit it contains lower 16 bits of the Upper
15-0
Address. For a description of this standard PCIe register field, see the PCI Express Specification. Note:
PCI_MSI_CAP_ The access attributes of this field are as follows: - Wire: No access.
OFF_08H
3.8.21 Data or mask bits (MSI_CAP_OFF_0CH_REG)
Offset
Register Offset
MSI_CAP_OFF_0CH_RE 5Ch
G
Function
For a 64-bit MSI message, this register contains data. For 32 bit, it contains mask bits if PVM enabled. For a description of this
standard PCIe register, see the PCI Express Specification.

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R PCI_MSI_CAP_OFF_0EH
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
PCI_MSI_CAP_OFF_0CH
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-16For a 64-bit MSI Message, this field contains Data. For 32-bit, it contains the upper Mask Bits if PVM is
enabled. For a description of this standard PCIe register field, see the PCI Express Specification Note:
OFF_0EH
For a 64-bit MSI Message, this field contains Data. For 32-bit, it contains the lower Mask Bits if PVM is
15-0
enabled. For a description of this standard PCIe register field, see the PCI Express Specification Note:
OFF_0CH
3.8.22 Pending or Mask Bits (MSI_CAP_OFF_10H_REG)
Offset
Register Offset
G
Function
Used for MSI when Vector Masking Capable. For 32 bit contains Pending Bits. For 64 bit, contains Mask Bits. For a
description of this standard PCIe register, see the PCI Express Specification.

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
PCI_MSI_CAP_OFF_10H
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
PCI_MSI_CAP_OFF_10H
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
Used for MSI when Vector Masking Capable. For 32-bit contains Pending Bits. For 64-bit, contains Mask
31-0
Bits. For a description of this standard PCIe register field, see the PCI Express Specification. Note: The
PCI_MSI_CAP_ access attributes of this field are as follows: - Wire: No access.
OFF_10H
3.8.23 Pending Bits (MSI_CAP_OFF_14H_REG)
Offset
Register Offset
G
Function
Used for MSI 64 bit messaging when Vector Masking Capable. Contains Pending Bits. For a description of this standard PCIe
register, see the PCI Express Specification.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R PCI_MSI_CAP_OFF_14H
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R PCI_MSI_CAP_OFF_14H
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-0 Used for MSI 64-bit messaging when Vector Masking Capable. Contains Pending Bits. For a description
of this standard PCIe register field, see the PCI Express Specification.
PCI_MSI_CAP_
OFF_14H
3.8.24 PCI Express Capabilities, ID, Next Pointer

Offset
Register Offset
PCIE_CAP_ID_PCIE_NE 70h
XT_CAP_PTR_PCIE_CA
P_REG
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCIE_
R 0 RSVD PCIE_INT_MSG_NUM PCIE_DEV_PORT_TYPE PCIE_CAP_REG
SL...
Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R PCIE_CAP_NEXT_PTR PCIE_CAP_ID
Reset 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0
Fields
Field Function
31 Reserved
30 Reserved For a description of this standard PCIe register field, see the PCI Express Specification.
RSVD
29-25 PCIe Interrupt Message Number

NXP Semiconductors
PCIe Controller
Field Function
PCIE_INT_MSG For a description of this standard PCIe register field, see the PCI Express Specification.
_NUM
- Wire: No access.
24 PCIe Slot Implemented Valid

PCIE_SLOT_IM For a description of this standard PCIe register field, see the PCI Express Specification.
P
- Wire: No access.
23-20 PCIe device/port type

PCIE_DEV_PO For a description of this standard PCIe register field, see the PCI Express Specification.
RT_TYPE
19-16 PCIE Capability Version Number. For a description of this standard PCIe register field, see the PCI
PCIE_CAP_RE
G
15-8 PCIE Next Capability Pointer

PCIE_CAP_NE For a description of this standard PCIe register field, see the PCI Express Specification.
XT_PTR
- Wire: No access.
7-0 PCIE Capability ID. For a description of this standard PCIe register field, see the PCI Express
Specification.
PCIE_CAP_ID
3.8.25 Device Capabilities (DEVICE_CAPABILITIES_REG)
Offset
Register Offset
_REG
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCIE_ PCIE_ PCIE_CAP_PH PCIE_CAP_MAX_PAYL

R 0
CA... CA... ANTO... OAD_SI...
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Fields
Field Function
31-16 Reserved
Role-based Error Reporting Implemented. For a description of this standard PCIe register field, see the
15
PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access.
PCIE_CAP_RO Note: This register field is sticky.
LE_BASED_ER
R_REPORT
14-6 Reserved
5Extended Tag Field Supported. For a description of this standard PCIe register field, see the PCI
Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note:
PCIE_CAP_EX This register field is sticky.
T_TAG_SUPP
Phantom Functions Supported. For a description of this standard PCIe register field, see the PCI
4-3
PCIE_CAP_PH This register field is sticky.
ANTOM_FUNC
_SUPPORT
Max Payload Size Supported. For a description of this standard PCIe register field, see the PCI Express
2-0
Specification. Note: The access attributes of this field are as follows: - Wire: No access. Note: This
PCIE_CAP_MA register field is sticky.
X_PAYLOAD_S
IZE

NXP Semiconductors
PCIe Controller
3.8.26 Device Control and Status (DEVICE_CONTROL_DEVICE_STATUS)
Offset
Register Offset
DEVICE_CONTROL_DE 78h
VICE_STATUS
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCIE_ PCIE_ PCIE_ PCIE_ PCIE_ PCIE_

R 0
CA... CA... CA... CA... CA... CA...
W W1C W1C W1C W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCIE_ PCIE_ PCIE_ PCIE_

R PCIE_CAP_MAX_READ PCIE_ PCIE_CAP_MAX_PAYL PCIE_ PCIE_ PCIE_ PCIE_ PCIE_
CA... CA... CA... CA...
_REQ_S... CA... OAD_SI... CA... CA... CA... CA... CA...
W
Reset 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0
Fields
Field Function
31-22 Reserved
21 Transactions Pending Status. For a description of this standard PCIe register field, see the PCI Express
Specification.
PCIE_CAP_TR
ANS_PENDING
20 Aux Power Detected Status. For a description of this standard PCIe register field, see the PCI Express
Specification. This bit is derived by sampling the sys_aux_pwr_det input.
PCIE_CAP_AU
X_POWER_DE
TECTED
19 Unsupported Request Detected Status. For a description of this standard PCIe register field, see the PCI
PCIE_CAP_UN
SUPPORTED_
REQ_DETECT
ED

NXP Semiconductors
PCIe Controller
Field Function
18 Fatal Error Detected Status. For a description of this standard PCIe register field, see the PCI Express
Specification.
PCIE_CAP_FA
TAL_ERR_DET
ECTED
17 Non-Fatal Error Detected Status. For a description of this standard PCIe register field, see the PCI
PCIE_CAP_NO
N_FATAL_ERR
_DETECTED
16 Correctable Error Detected Status. For a description of this standard PCIe register field, see the PCI
PCIE_CAP_CO
RR_ERR_DETE
CTED
15 Initiate Function Level Reset (for endpoints). For a description of this standard PCIe register field, see
PCIE_CAP_INI
TIATE_FLR
14-12 Max Read Request Size. For a description of this standard PCIe register field, see the PCI Express
Specification.
PCIE_CAP_MA
X_READ_REQ_
SIZE
11 Enable No Snoop. For a description of this standard PCIe register field, see the PCI Express
Specification. Note: The access attributes of this field are as follows: - Wire: No access.
PCIE_CAP_EN
_NO_SNOOP
10 Aux power PM enable

PCIE_CAP_AU For a description of this standard PCIe register field, see the PCI Express Specification.
X_POWER_PM
This bit is derived by sampling the sys_aux_pwr_det input.
_EN
9 Phantom functions enable

PCIE_CAP_PH For a description of this standard PCIe register field, see the PCI Express Specification.
ANTOM_FUNC
The write value is gated with the PCIE_CAP_PHANTOM_FUNC_SUPPORT field
_EN
of DEVICE_CAPABILITIES_REG.
- Wire: No access.
8 Extended tag field enable

PCIE_CAP_EX For a description of this standard PCIe register field, see the PCI Express Specification.
T_TAG_EN

NXP Semiconductors
PCIe Controller
Field Function
The write value is gated with the PCIE_CAP_EXT_TAG_SUPP field of DEVICE_CAPABILITIES_REG.

- Wire: No access.
7-5 Max Payload Size. Max_Payload_Size . This field sets maximum TLP payload size for the Function.
Permissible values that can be programmed are indicated by the Max_Payload_Size Supported field
PCIE_CAP_MA (PCIE_CAP_MAX_PAYLOAD_SIZE) in the Device Capabilities register (DEVICE_CAPABILITIES_REG).
X_PAYLOAD_S
IZE_CS
4 Enable Relaxed Ordering. For a description of this standard PCIe register field, see the PCI Express
PCIE_CAP_EN
_REL_ORDER
3 Unsupported Request Reporting Enable. For a description of this standard PCIe register field, see the
PCIE_CAP_UN
SUPPORT_RE
Q_REP_EN
2 Fatal Error Reporting Enable. For a description of this standard PCIe register field, see the PCI Express
Specification.
PCIE_CAP_FA
TAL_ERR_REP
ORT_EN
1 Non-fatal Error Reporting Enable. For a description of this standard PCIe register field, see the PCI
PCIE_CAP_NO
N_FATAL_ERR
_REPORT_EN
0 Correctable Error Reporting Enable. For a description of this standard PCIe register field, see the PCI
PCIE_CAP_CO
RR_ERR_REP
ORT_EN
3.8.27 Link Capabilities (LINK_CAPABILITIES_REG)
Offset
Register Offset
LINK_CAPABILITIES_R 7Ch
EG
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCIE_ PCIE_ PCIE_ PCIE_ PCIE_ PCIE_CAP_L1_

R PCIE_CAP_PORT_NUM 0
CA... CA... CA... CA... CA... EXI...
Reset 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCIE_ PCIE_CAP_L0S_EXIT_L PCIE_CAP_AC

R PCIE_CAP_MAX_LINK_WIDTH PCIE_CAP_MAX_LINK_SPEED
CA... ATEN... TIVE...
Reset 0 1 1 0 1 0 0 0 0 0 1 0 0 0 1 1
Fields
Field Function
31-24 Port Number. For a description of this standard PCIe register field, see the PCI Express Specification.
Note: The access attributes of this field are as follows: - Wire: No access.
PCIE_CAP_PO
RT_NUM
23 Reserved
22 ASPM Optionality Compliance. For a description of this standard PCIe register field, see the PCI Express
PCIE_CAP_AS
PM_OPT_COM
PLIANCE
21Link Bandwidth Notification Capable. For a description of this standard PCIe register field, see the PCI
PCIE_CAP_LIN This register field is sticky.
K_BW_NOT_C
AP
20 Data Link Layer Link Active Reporting Capable. For a description of this standard PCIe register field, see
PCIE_CAP_DLL
_ACTIVE_REP_
CAP
Surprise Down Error Reporting Capable. For a description of this standard PCIe register field, see the
19
PCIE_CAP_SU Note: This register field is sticky.
RPRISE_DOW
N_ERR_REP_C
AP

NXP Semiconductors
PCIe Controller
Field Function
18 Clock power management

PCIE_CAP_CL For a description of this standard PCIe register field, see the PCI Express Specification.
OCK_POWER_
MAN
17-15 L1 exit latency

PCIE_CAP_L1_ For a description of this standard PCIe register field, see the PCI Express Specification.
EXIT_LATENC
There are two each of these register fields, this one and a shadow one at the same address.
Y
The Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register
(LINK_CONTROL_LINK_STATUS_REG) determines which one is used by the controller and which one is
accessed by a read request.
The controller supports Common Clock operation. This operation is enabled in the controller when
you set the Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register
(LINK_CONTROL_LINK_STATUS_REG). The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2
address bit for the AXI bridge) is required to write to the shadow field at this location.
- Wire: No access.
14-12 LOs exit latency

PCIE_CAP_L0S For a description of this standard PCIe register field, see the PCI Express Specification.
_EXIT_LATENC
There are two each of these register fields, this one and a shadow one at the same address.
Y
The Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register
(LINK_CONTROL_LINK_STATUS_REG) determines which one is used by the controller and which one is
accessed by a read request.
Common Clock operation is supported (possible) in the controller and enabled when you
set the Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register
(LINK_CONTROL_LINK_STATUS_REG). The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2
address bit for the AXI bridge) is required to write to the shadow field at this location.
- Wire: No access.
11-10 Level of ASPM (Active State Power Management) Support. For a description of this standard PCIe
register field, see the PCI Express Specification. Note: The access attributes of this field are as follows: -
PCIE_CAP_AC Wire: No access. Note: This register field is sticky.
TIVE_STATE_L
INK_PM_SUPP
ORT
9-4 Maximum link width


NXP Semiconductors
PCIe Controller
Field Function
PCIE_CAP_MA The access attributes of this field are as follows:

X_LINK_WIDTH
- Wire: No access.
3-0 Maximum link speed

PCIE_CAP_MA For a description of this standard PCIe register field, see the PCI Express Specification.
X_LINK_SPEE
D
- Wire: No access.
3.8.28 Link Control and Status (LINK_CONTROL_LINK_STATUS_REG)
Offset
Register Offset
LINK_CONTROL_LINK_ 80h
STATUS_REG
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCIE_ PCIE_ PCIE_ PCIE_ PCIE_

R 0 PCIE_CAP_NEGO_LINK_WIDTH PCIE_CAP_LINK_SPEED
CA... CA... CA... CA... CA...
W W1C W1C
Reset 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCIE_CAP_DR PCIE_ PCIE_ PCIE_ PCIE_ PCIE_

R 0 PCIE_ PCIE_ PCIE_ PCIE_ 0 PCIE_CAP_AC
S_SI... CA... CA... CA... CA... CA...
CA... CA... CA... CA... TIVE...
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31 Link Autonomous Bandwidth Status. For a description of this standard PCIe register field, see the
PCI Express Specification. The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in
PCIE_CAP_LIN LINK_CAPABILITIES_REG.
K_AUTO_BW_S
TATUS
30 Link Bandwidth Management Status. For a description of this standard PCIe register field, see the
PCI Express Specification. The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in
PCIE_CAP_LIN LINK_CAPABILITIES_REG.
K_BW_MAN_S
TATUS
29 Data Link Layer Active. For a description of this standard PCIe register field, see the PCI Express
Specification.
PCIE_CAP_DLL
_ACTIVE
28 Slot Clock Configuration

PCIE_CAP_SL For a description of this standard PCIe register field, see the PCI Express Specification.
OT_CLK_CONF
IG
- Wire: No access.
27 LTSSM is in Configuration or Recovery State. For a description of this standard PCIe register field, see
PCIE_CAP_LIN
K_TRAINING
26 Reserved
25-20 Negotiated Link Width. For a description of this standard PCIe register field, see the PCI Express
Specification.
PCIE_CAP_NE
GO_LINK_WID
TH
19-16 Current Link Speed. For a description of this standard PCIe register field, see the PCI Express
Specification.
PCIE_CAP_LIN
K_SPEED
15-14 DRS signaling control

PCIE_CAP_DR For a description of this standard PCIe register field, see the PCI Express Specification.
S_SIGNALING_
CONTROL
- Wire: No access.
13-12 Reserved

NXP Semiconductors
PCIe Controller
Field Function
11 Link autonomous bandwidth management interrupt enable

K_AUTO_BW_I
The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.
NT_EN
- Wire: No access.
10 Link bandwidth management interrupt enable

K_BW_MAN_IN
The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.
T_EN
- Wire: No access.
9 Hardware Autonomous Width Disable. For a description of this standard PCIe register field, see the PCI
PCIE_CAP_HW
_AUTO_WIDTH
_DISABLE
8 Enable Clock Power Management. For a description of this standard PCIe register field, see the PCI
Express Specification. The write value is gated with the PCIE_CAP_CLOCK_POWER_MAN field in
PCIE_CAP_EN LINK_CAPABILITIES_REG. Note: The access attributes of this field are as follows: - Wire: No access.
_CLK_POWER_ Note: This register field is sticky.
MAN
7 Extended Synch. For a description of this standard PCIe register field, see the PCI Express
Specification.
PCIE_CAP_EX
TENDED_SYN
CH
6 Common Clock Configuration. For a description of this standard PCIe register field, see the PCI Express
Specification.
PCIE_CAP_CO
MMON_CLK_C
ONFIG
5 Initiate link retrain

PCIE_CAP_RE For a description of this standard PCIe register field, see the PCI Express Specification.
TRAIN_LINK
- Wire: No access.
4 Initiate link disable

K_DISABLE

NXP Semiconductors
PCIe Controller
Field Function
In a DSP that supports crosslink, the controller gates the write value with the CROSS_LINK_EN field
in PORT_LINK_CTRL_OFF.
- Wire: No access.
3 Read Completion Boundary (RCB)

PCIE_CAP_RC The access attributes of this field are as follows:
B
- Wire: No access.
2 Reserved
1-0 Active State Power Management (ASPM) Control. Software must not enable L0s in either direction on
a given Link unless components on both sides of the Link each support L0s; otherwise, the result is
PCIE_CAP_AC undefined. For a description of this standard PCIe register field, see the PCI Express Specification.
TIVE_STATE_L
INK_PM_CONT
ROL
3.8.29 Slot Capabilities (SLOT_CAPABILITIES_REG)
Offset
Register Offset
SLOT_CAPABILITIES_R 84h
EG
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCIE_ PCIE_ PCIE_

R PCIE_CAP_PHY_SLOT_NUM
CA... CA... CA...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCIE_ PCIE_ PCIE_ PCIE_ PCIE_ PCIE_ PCIE_ PCIE_

R PCIE_CAP_SLOT_POWER_LIMIT_VALUE
CA... CA... CA... CA... CA... CA... CA... CA...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-19 Physical Slot Number. For a description of this standard PCIe register field, see the PCI Express
PCIE_CAP_PH
Y_SLOT_NUM
18 No Command Completed Support. For a description of this standard PCIe register field, see the PCI
PCIE_CAP_NO
_CMD_CPL_SU
PPORT
17 Electromechanical Interlock Present. For a description of this standard PCIe register field, see the PCI
PCIE_CAP_EL
ECTROMECH_I
NTERLOCK
16-15 Slot Power Limit Scale. For a description of this standard PCIe register field, see the PCI Express
PCIE_CAP_SL
OT_POWER_LI
MIT_SCALE
14-7 Slot Power Limit Value. For a description of this standard PCIe register field, see the PCI Express
PCIE_CAP_SL
OT_POWER_LI
MIT_VALUE
6 Hot Plug Capable. For a description of this standard PCIe register field, see the PCI Express
PCIE_CAP_HO
T_PLUG_CAPA
BLE

NXP Semiconductors
PCIe Controller
Field Function
5 Hot Plug Surprise possible. For a description of this standard PCIe register field, see the PCI Express
PCIE_CAP_HO
T_PLUG_SURP
RISE
4 Power Indicator Present. For a description of this standard PCIe register field, see the PCI Express
PCIE_CAP_PO
WER_INDICAT
OR
3 Attention Indicator Present. For a description of this standard PCIe register field, see the PCI Express
PCIE_CAP_AT
TENTION_INDI
CATOR
2 MRL Present. For a description of this standard PCIe register field, see the PCI Express Specification.
PCIE_CAP_MR
L_SENSOR
1 Power Controller Present. For a description of this standard PCIe register field, see the PCI Express
PCIE_CAP_PO
WER_CONTRO
LLER
0 Attention Button Present. For a description of this standard PCIe register field, see the PCI Express
PCIE_CAP_AT
TENTION_INDI
CATOR_BUTT
ON
3.8.30 Slot Control and Status (SLOT_CONTROL_SLOT_STATUS)
Offset
Register Offset
SLOT_CONTROL_SLOT 88h
_STATUS
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCIE_ PCIE_ PCIE_ PCIE_ PCIE_ PCIE_ PCIE_ PCIE_ PCIE_

R 0
CA... CA... CA... CA... CA... CA... CA... CA... CA...
Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 PCIE_ PCIE_ PCIE_ PCIE_CAP_PO PCIE_CAP_AT PCIE_ PCIE_ PCIE_ PCIE_ PCIE_ PCIE_
W CA... CA... CA... WER_... TENT... CA... CA... CA... CA... CA... CA...
Reset 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0
Fields
Field Function
31-25 Reserved
24 Data Link Layer State Changed. For a description of this standard PCIe register field, see the PCI
PCIE_CAP_DLL
_STATE_CHAN
GED
23 Electromechanical Interlock Status. For a description of this standard PCIe register field, see the PCI
PCIE_CAP_EL
ECTROMECH_I
NTERLOCK_ST
ATUS
22 Presence Detect State. For a description of this standard PCIe register field, see the PCI Express
PCIE_CAP_PR
ESENCE_DET
ECT_STATE
21 MRL Sensor State. For a description of this standard PCIe register field, see the PCI Express
Specification.
PCIE_CAP_MR
L_SENSOR_ST
ATE
20 Command Completed. For a description of this standard PCIe register field, see the PCI Express
Specification.
PCIE_CAP_CM
D_CPLD
19 Presence Detect Changed. For a description of this standard PCIe register field, see the PCI Express
Specification.

NXP Semiconductors
PCIe Controller
Field Function
PCIE_CAP_PR
ESENCE_DET
ECTED_CHAN
GED
18 MRL Sensor Changed. For a description of this standard PCIe register field, see the PCI Express
Specification.
PCIE_CAP_MR
L_SENSOR_CH
ANGED
17 Power Fault Detected. For a description of this standard PCIe register field, see the PCI Express
Specification.
PCIE_CAP_PO
WER_FAULT_D
ETECTED
16 Attention Button Pressed. For a description of this standard PCIe register field, see the PCI Express
Specification.
PCIE_CAP_AT
TENTION_BUT
TON_PRESSE
D
15-13 Reserved
12 Data Link Layer State Changed Enable. For a description of this standard PCIe register field, see the
PCIE_CAP_DLL
_STATE_CHAN
GED_EN
11 Electromechanical Interlock Control. For a description of this standard PCIe register field, see the PCI
PCIE_CAP_EL
ECTROMECH_I
NTERLOCK_C
TRL
10 Power Controller Control. For a description of this standard PCIe register field, see the PCI Express
Specification.
PCIE_CAP_PO
WER_CONTRO
LLER_CTRL
9-8 Power Indicator Control. For a description of this standard PCIe register field, see the PCI Express
Specification.
PCIE_CAP_PO
WER_INDICAT
OR_CTRL

NXP Semiconductors
PCIe Controller
Field Function
7-6 Attention Indicator Control. For a description of this standard PCIe register field, see the PCI Express
Specification.
PCIE_CAP_AT
TENTION_INDI
CATOR_CTRL
5 Hot Plug Interrupt Enable. For a description of this standard PCIe register field, see the PCI Express
Specification.
PCIE_CAP_HO
T_PLUG_INT_E
N
4 Command Completed Interrupt Enable. For a description of this standard PCIe register field, see the
PCI Express Specification. Write value is gated with PCIE_CAP_NO_CMD_CPL_SUPPORT field in
PCIE_CAP_CM SLOT_CAPABILITIES_REG. Note: The access attributes of this field are as follows: - Wire: No access.
D_CPL_INT_EN
3 Presence Detect Changed Enable. For a description of this standard PCIe register field, see the PCI
PCIE_CAP_PR
ESENCE_DET
ECT_CHANGE
_EN
2 MRL Sensor Changed Enable. For a description of this standard PCIe register field, see the PCI Express
Specification.
PCIE_CAP_MR
L_SENSOR_CH
ANGED_EN
1 Power Fault Detected Enable. For a description of this standard PCIe register field, see the PCI Express
Specification.
PCIE_CAP_PO
WER_FAULT_D
ETECTED_EN
0 Attention Button Pressed Enable. For a description of this standard PCIe register field, see the PCI
PCIE_CAP_AT
TENTION_BUT
TON_PRESSE
D_EN
3.8.31 Root Control and Capabilities (ROOT_CONTROL_ROOT_CAPABILITIES_REG)
Offset
Register Offset
ROOT_CONTROL_ROO 8Ch
T_CAPABILITIES_REG

NXP Semiconductors
PCIe Controller
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCIE_
R 0
CA...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCIE_
R 0 PCIE_ PCIE_ PCIE_ PCIE_
CA...
CA... CA... CA... CA...
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-17 Reserved
16 CRS Software Visibility Capable

PCIE_CAP_CR For a description of this standard PCIe register field, see the PCI Express Specification.
S_SW_VISIBILI
TY
- Wire: No access.
15-5 Reserved
4 Configuration request retry status (CRS) software visibility enable

PCIE_CAP_CR For a description of this standard PCIe register field, see the PCI Express Specification.
S_SW_VISIBILI
TY_EN
- Wire: No access.
3 PME interrupt enable

PCIE_CAP_PM For a description of this standard PCIe register field, see the PCI Express Specification.
E_INT_EN
2 System error on fatal error enable


NXP Semiconductors
PCIe Controller
Field Function
PCIE_CAP_SY
S_ERR_ON_FA
TAL_ERR_EN
1 System error on non-fatal error enable

PCIE_CAP_SY For a description of this standard PCIe register field, see the PCI Express Specification.
S_ERR_ON_N
ON_FATAL_ER
R_EN
0 System error on correctable error enable

PCIE_CAP_SY For a description of this standard PCIe register field, see the PCI Express Specification.
S_ERR_ON_C
ORR_ERR_EN
3.8.32 Root Status (ROOT_STATUS_REG)
Offset
Register Offset
ROOT_STATUS_REG 90h
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCIE_ PCIE_
R 0
CA... CA...
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R PCIE_CAP_PME_REQ_ID
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-18 Reserved
17 PME Pending. For a description of this standard PCIe register field, see the PCI Express Specification.
PCIE_CAP_PM
E_PENDING
16 PME Status. For a description of this standard PCIe register field, see the PCI Express Specification.
PCIE_CAP_PM
E_STATUS
15-0 PME Requester ID. For a description of this standard PCIe register field, see the PCI Express
Specification.
PCIE_CAP_PM
E_REQ_ID
3.8.33 Device Capabilities 2 (DEVICE_CAPABILITIES2_REG)
Offset
Register Offset
2_REG
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCIE_CAP_OB PCIE_ PCIE_

R 0
FF_S... CA... CA...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCIE_ PCIE_ PCIE_ PCIE_ PCIE_ PCIE_ PCIE_ PCIE_ PCIE_ PCIE_ PCIE_CAP_CPL_TIMEOUT_RAN
R 0
CA... CA... CA... CA... CA... CA... CA... CA... CA... CA... GE
Reset 0 0 0 0 0 1 0 0 0 0 0 1 1 1 1 1

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-20 Reserved
19-18 (OBFF) Optimized Buffer Flush/fill Supported. For a description of this standard PCIe register field, see
PCIE_CAP_OB
FF_SUPPORT
17 10-Bit Tag Requester Supported. For a description of this standard PCIe register field, see the PCI
PCIE_CAP2_10
_BIT_TAG_RE
Q_SUPPORT
16 10-Bit Tag Completer Supported. For a description of this standard PCIe register field, see the PCI
PCIE_CAP2_10
_BIT_TAG_CO
MP_SUPPORT
15-14 Reserved
PCIE_CAP_TP
H_CMPLT_SUP
PORT_1
PCIE_CAP_TP
H_CMPLT_SUP
PORT_0
11 LTR Mechanism Supported. For a description of this standard PCIe register field, see the PCI Express
Specification.
PCIE_CAP_LT
R_SUPP
10 No Relaxed Ordering Enabled PR-PR Passing. For a description of this standard PCIe register field, see
PCIE_CAP_NO
_RO_EN_PR2P
R_PAR
9 128 Bit CAS Completer Supported. For a description of this standard PCIe register field, see the PCI
PCIE_CAP_128
_CAS_CPL_SU
PP

NXP Semiconductors
PCIe Controller
Field Function
PCIE_CAP_64_
ATOMIC_CPL_
SUPP
PCIE_CAP_32_
ATOMIC_CPL_
SUPP
6 Atomic Operation Routing Supported. For a description of this standard PCIe register field, see the PCI
PCIE_CAP_AT
OMIC_ROUTIN
G_SUPP
5 ARI Forwarding Supported. For a description of this standard PCIe register field, see the PCI Express
Specification.
PCIE_CAP_ARI
_FORWARD_S
UPPORT
4 Completion Timeout Disable Supported. For a description of this standard PCIe register field, see the
PCIE_CAP_CP
L_TIMEOUT_DI
SABLE_SUPPO
RT
3-0 Completion Timeout Ranges Supported. For a description of this standard PCIe register field, see the
PCIE_CAP_CP
L_TIMEOUT_R
ANGE
3.8.34 Device Control 2 and Status 2 (DEVICE_CONTROL2_DEVICE_STATUS2_REG)
Offset
Register Offset
DEVICE_CONTROL2_D 98h
EVICE_STATUS2_REG
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCIE_
R 0 PCIE_ PCIE_CAP_CPL_TIMEOUT_VAL
CA...
CA... UE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-6 Reserved
5 ARI Forwarding Enable. For a description of this standard PCIe register field, see the PCI Express
PCIE_CAP_ARI
_FORWARD_S
UPPORT_CS
4 Completion Timeout Disable

PCIE_CAP_CP Controls the completion-timeout mechanism.
L_TIMEOUT_DI
0b - Enable completion timeout
SABLE
1b - Disable completion timeout
3-0 Completion Timeout Value. For a description of this standard PCIe register field, see the PCI Express
PCIE_CAP_CP
L_TIMEOUT_V
ALUE
3.8.35 Link Capabilities 2 (LINK_CAPABILITIES2_REG)
Offset
Register Offset
LINK_CAPABILITIES2_R 9Ch
EG
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCIE_
R 0 PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR 0
CA...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0
Fields
Field Function
31-9 Reserved
8 Cross Link Supported. For a description of this standard PCIe register field, see the PCI Express
Specification.
PCIE_CAP_CR
OSS_LINK_SU
PPORT
Supported Link Speeds Vector. For a description of this standard PCIe register field, see the PCI
7-1
Express Specification. This field has a default of (PCIE_CAP_MAX_LINK_SPEED == 0100) ? 0001111 :
PCIE_CAP_SU (PCIE_CAP_MAX_LINK_SPEED == 0011) ? 0000111 : (PCIE_CAP_MAX_LINK_SPEED == 0010) ?
PPORT_LINK_ 0000011 : 0000001 where PCIE_CAP_MAX_LINK_SPEED is a field in the LINK_CAPABILITIES_REG
SPEED_VECT register.
OR
0 Reserved
3.8.36 Link Control 2 and Status 2 (LINK_CONTROL2_LINK_STATUS2_REG)
Offset
Register Offset
LINK_CONTROL2_LINK A0h
_STATUS2_REG
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DRS_ DOWNSTREAM_COMP PCIE_ PCIE_ PCIE_ PCIE_ PCIE_ PCIE_

R 0
MES... O_PRESEN... CA... CA... CA... CA... CA... CA...
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCIE_
R PCIE_CAP_COMPLIANCE_PRES PCIE_ PCIE_ PCIE_ PCIE_ PCIE_CAP_TARGET_LINK_SPEE
PCIE_CAP_TX_MARGIN CA...
ET CA... CA... CA... CA... D
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Fields
Field Function
31 DRS Message Received. For a description of this standard PCIe register field, see the PCI Express
Base Specification 4.0. Note: The access attributes of this field are as follows: - Wire: No access.
DRS_MESSAG
E_RECEIVED
30-28 Downstream Component Presence. For a description of this standard PCIe register field, see the PCI
DOWNSTREA
M_COMPO_PR
ESENCE
27-22 Reserved
21 Link Equalization Request 8.0GT/s. For a description of this standard PCIe register field, see the PCI
PCIE_CAP_LIN
K_EQ_REQ
20 Equalization 8.0GT/s Phase 3 Successful. For a description of this standard PCIe register field, see the
PCIE_CAP_EQ
_CPL_P3
PCIE_CAP_EQ
_CPL_P2
PCIE_CAP_EQ
_CPL_P1
17 Equalization 8.0GT/s Complete. For a description of this standard PCIe register field, see the PCI

NXP Semiconductors
PCIe Controller
Field Function
PCIE_CAP_EQ
_CPL
16 Current De-emphasis Level. For a description of this standard PCIe register field, see the PCI Express
Specification. In C-PCIe mode, its contents are derived by sampling the PIPE
PCIE_CAP_CU
RR_DEEMPHA
SIS
15-12 Sets Compliance Preset/De-emphasis for 5 GT/s and 8 GT/s. For a description of this standard PCIe
register field, see the PCI Express Specification. Note: The access attributes of this field are as follows: -
PCIE_CAP_CO Wire: No access. Note: This register field is sticky.
MPLIANCE_PR
ESET
11 Sets Compliance Skip Ordered Sets transmission. For a description of this standard PCIe register field,
see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No
PCIE_CAP_CO access. Note: This register field is sticky.
MPLIANCE_SO
S
10 Enter Modified Compliance. For a description of this standard PCIe register field, see the PCI Express
PCIE_CAP_EN register field is sticky.
TER_MODIFIE
D_COMPLIANC
E
9-7 Controls Transmit Margin for Debug or Compliance. For a description of this standard PCIe register field,
see the PCI Express Specification. Note: This register field is sticky.
PCIE_CAP_TX_
MARGIN
6 Controls Selectable De-emphasis for 5 GT/s

PCIE_CAP_SE For a description of this standard PCIe register field, see the PCI Express Specification.
L_DEEMPHASI
S
- Wire: No access.
5 Hardware Autonomous Speed Disable. For a description of this standard PCIe register field, see the PCI
PCIE_CAP_HW This register field is sticky.
_AUTO_SPEED
_DISABLE
4 Enter Compliance Mode. For a description of this standard PCIe register field, see the PCI Express

NXP Semiconductors
PCIe Controller
Field Function
PCIE_CAP_EN
TER_COMPLIA
NCE
3-0 Target Link Speed. For a description of this standard PCIe register field, see the PCI Express
PCIE_CAP_TA
RGET_LINK_S
PEED
3.8.37 MSI-X Capability ID, Next Pointer, Control (PCI_MSIX_CAP_ID_NEXT_CTRL_REG)
Offset
Register Offset
PCI_MSIX_CAP_ID_NEX B0h
T_CTRL_REG
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R PCI_M PCI_M 0 PCI_MSIX_TABLE_SIZE
W SI... SI...
Reset 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R PCI_MSIX_CAP_NEXT_OFFSET PCI_MSIX_CAP_ID
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1
Fields
Field Function
31 MSI-X Enable. For a description of this standard PCIe register field, see the PCI Express Specification.
PCI_MSIX_ENA
BLE

NXP Semiconductors
PCIe Controller
Field Function
30 Function Mask. For a description of this standard PCIe register field, see the PCI Express Specification.
PCI_MSIX_FUN
CTION_MASK
29-27 Reserved
26-16 MSI-X Table Size

PCI_MSIX_TAB For a description of this standard PCIe register field, see the PCI Express Specification.
LE_SIZE
- Wire: No access.
15-8 MSI-X Next Capability Pointer

_NEXT_OFFSE
T
- Wire: No access.
7-0 MSI-X Capability ID. For a description of this standard PCIe register field, see the PCI Express
Specification.
PCI_MSIX_CAP
_ID
3.8.38 MSI-X Table Offset and BIR (MSIX_TABLE_OFFSET_REG)
Offset
Register Offset
MSIX_TABLE_OFFSET_ B4h
REG
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R PCI_MSIX_TABLE_OFFSET
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R PCI_MSIX_TABLE_OFFSET PCI_MSIX_BIR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Fields
Field Function
MSI-X Table Offset. For a description of this standard PCIe register field, see the PCI Express
31-3
PCI_MSIX_TAB register field is sticky.
LE_OFFSET
2-0MSI-X Table Bar Indicator Register Field. For a description of this standard PCIe register field, see the
PCI_MSIX_BIR Note: This register field is sticky.
3.8.39 MSI-X PBA Offset and BIR (MSIX_PBA_OFFSET_REG)
Offset
Register Offset
MSIX_PBA_OFFSET_R B8h
EG
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R PCI_MSIX_PBA_OFFSET
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R PCI_MSIX_PBA_OFFSET PCI_MSIX_PBA
Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0
Fields
Field Function
MSI-X PBA Offset. For a description of this standard PCIe register field, see the PCI Express
31-3
PCI_MSIX_PBA register field is sticky.
_OFFSET
2-0MSI-X PBA BIR. For a description of this standard PCIe register field, see the PCI Express Specification.
Note: The access attributes of this field are as follows: - Wire: No access. Note: This register field is
PCI_MSIX_PBA sticky.
3.8.40 Advanced Error Reporting Extended Capability Header (AER_EXT_CAP_HDR_OFF)
Offset
Register Offset
AER_EXT_CAP_HDR_O 100h
FF
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset 0 0 0 1 0 1 0 0 1 0 0 0 0 0 1 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CAP_ID
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Fields
Field Function
31-20
NEXT_OFFSET register field is sticky.
19-16
CAP_VERSION register field is sticky.
15-0 AER Extended Capability ID. For a description of this standard PCIe register field, see the PCI Express
CAP_ID register field is sticky.
3.8.41 Uncorrectable Error Status (UNCORR_ERR_STATUS_OFF)
Offset
Register Offset
UNCORR_ERR_STATU 104h
S_OFF
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TLP_P INTER UNSU ECRC MALF_ REC_ UNEX

R 0 0 0
RF... NA... PPO... _ER... TL... OVE... P_C...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPL CMPL FC_PR POIS_ SURP DL_PR

R 0 0
T_A... T_T... OT... TL... RIS... OT...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-26 Reserved
25 TLP Prefix Blocked Error Status. For a description of this standard PCIe register field, see the PCI
Express Specification. Note: Not supported.
TLP_PRFX_BL
OCKED_ERR_
STATUS
24-23 Reserved
Uncorrectable Internal Error Status. For a description of this standard PCIe register field, see the PCI
22
Express Specification. The controller sets this bit when your application asserts app_err_bus[9]. It does
INTERNAL_ER not set this bit when it detects internal uncorrectable internal errors such as parity and ECC failures. You
R_STATUS should use the outputs from these errors to drive the app_err_bus[9] input.
21 Reserved
20 Unsupported Request Error Status. For a description of this standard PCIe register field, see the PCI
UNSUPPORTE
D_REQ_ERR_S
TATUS
19 ECRC Error Status. For a description of this standard PCIe register field, see the PCI Express
Specification.
ECRC_ERR_ST
ATUS
18 Malformed TLP Status. For a description of this standard PCIe register field, see the PCI Express
Specification.

NXP Semiconductors
PCIe Controller
Field Function
MALF_TLP_ER
R_STATUS
17 Receiver Overflow Status. For a description of this standard PCIe register field, see the PCI Express
Specification.
REC_OVERFL
OW_ERR_STA
TUS
16 Unexpected Completion Status. For a description of this standard PCIe register field, see the PCI
UNEXP_CMPL
T_ERR_STATU
S
15 Completer Abort Status. For a description of this standard PCIe register field, see the PCI Express
Specification.
CMPLT_ABOR
T_ERR_STATU
S
14 Completion Timeout Status. For a description of this standard PCIe register field, see the PCI Express
Specification.
CMPLT_TIMEO
UT_ERR_STAT
US
13 Flow Control Protocol Error Status. For a description of this standard PCIe register field, see the PCI
FC_PROTOCO
L_ERR_STATU
S
12 Poisoned TLP Status. For a description of this standard PCIe register field, see the PCI Express
Specification.
POIS_TLP_ER
R_STATUS
11-6 Reserved
5 Surprise Down Error Status (Optional). For a description of this standard PCIe register field, see the PCI
SURPRISE_DO
WN_ERR_STA
TUS
4 Data Link Protocol Error Status. For a description of this standard PCIe register field, see the PCI
DL_PROTOCO
L_ERR_STATU
S

NXP Semiconductors
PCIe Controller
Field Function
3-0 Reserved
3.8.42 Uncorrectable Error Mask (UNCORR_ERR_MASK_OFF)
Offset
Register Offset
UNCORR_ERR_MASK_ 108h
OFF
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TLP_P ATOMI
RF... C_...
NA... PPO... _ER... TL... OVE... P_C...
W
Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SURP
RIS...
T_A... T_T... OT... TL... OT...
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-26 Reserved
TLP Prefix Blocked Error Mask. For a description of this standard PCIe register field, see the PCI
25
Express Specification. Note: Not supported. Note: The access attributes of this field are as follows: -
TLP_PRFX_BL Wire: No access. Note: This register field is sticky.
OCKED_ERR_
MASK

NXP Semiconductors
PCIe Controller
Field Function
24 AtomicOp Egress Block Mask (Optional). For a description of this standard PCIe register field, see the
ATOMIC_EGRE Note: This register field is sticky.
SS_BLOCKED_
ERR_MASK
23 Reserved
22 Uncorrectable Internal Error Mask (Optional). For a description of this standard PCIe register field, see
INTERNAL_ER
R_MASK
21 Reserved
20 Unsupported Request Error Mask. For a description of this standard PCIe register field, see the PCI
UNSUPPORTE
D_REQ_ERR_
MASK
19 ECRC Error Mask (Optional). For a description of this standard PCIe register field, see the PCI Express
ECRC_ERR_M register field is sticky.
ASK
18 Malformed TLP Mask. For a description of this standard PCIe register field, see the PCI Express
MALF_TLP_ER
R_MASK
17 Receiver Overflow Mask (Optional). For a description of this standard PCIe register field, see the PCI
REC_OVERFL
OW_ERR_MAS
K
16 Unexpected Completion Mask. For a description of this standard PCIe register field, see the PCI Express
UNEXP_CMPL
T_ERR_MASK
15 Completer Abort Error Mask (Optional). For a description of this standard PCIe register field, see the PCI
CMPLT_ABOR
T_ERR_MASK
14 Completion Timeout Error Mask. For a description of this standard PCIe register field, see the PCI

NXP Semiconductors
PCIe Controller
Field Function
CMPLT_TIMEO
UT_ERR_MAS
K
13 Flow Control Protocol Error Mask. For a description of this standard PCIe register field, see the PCI
FC_PROTOCO
L_ERR_MASK
12 Poisoned TLP Error Mask. For a description of this standard PCIe register field, see the PCI Express
POIS_TLP_ER
R_MASK
11-6 Reserved
5 Surprise down error mask

SURPRISE_DO For a description of this standard PCIe register field, see the PCI Express Specification.
WN_ERR_MAS
K
- Wire: No access.
4 Data Link Protocol Error Mask. For a description of this standard PCIe register field, see the PCI Express
DL_PROTOCO
L_ERR_MASK
3-0 Reserved
3.8.43 Uncorrectable Error Severity (UNCORR_ERR_SEV_OFF)
Offset
Register Offset
UNCORR_ERR_SEV_O 10Ch
FF
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TLP_P ATOMI
RF... C_...
NA... PPO... _ER... TL... OVE... P_C...
W
Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SURP
RIS...
T_A... T_T... OT... TL... OT...
W
Reset 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0
Fields
Field Function
31-26 Reserved
TLP Prefix Blocked Error Severity (Optional). For a description of this standard PCIe register field, see
25
the PCI Express Specification. Note: Not supported. Note: The access attributes of this field are as
TLP_PRFX_BL follows: - Wire: No access. Note: This register field is sticky.
OCKED_ERR_
SEVERITY
AtomicOp Egress Blocked Severity (Optional). For a description of this standard PCIe register field, see
24
the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access.
ATOMIC_EGRE Note: This register field is sticky.
SS_BLOCKED_
ERR_SEVERIT
Y
23 Reserved
22 Uncorrectable Internal Error Severity (Optional). For a description of this standard PCIe register field, see
INTERNAL_ER
R_SEVERITY
21 Reserved
20 Unsupported Request Error Severity. For a description of this standard PCIe register field, see the PCI
UNSUPPORTE
D_REQ_ERR_S
EVERITY

NXP Semiconductors
PCIe Controller
Field Function
19 ECRC Error Severity (Optional). For a description of this standard PCIe register field, see the PCI
ECRC_ERR_S This register field is sticky.
EVERITY
18 Malformed TLP Severity. For a description of this standard PCIe register field, see the PCI Express
MALF_TLP_ER
R_SEVERITY
17 Receiver Overflow Error Severity (Optional). For a description of this standard PCIe register field, see the
REC_OVERFL
OW_ERR_SEV
ERITY
16 Unexpected Completion Error Severity. For a description of this standard PCIe register field, see the PCI
UNEXP_CMPL
T_ERR_SEVER
ITY
15 Completer Abort Error Severity (Optional). For a description of this standard PCIe register field, see the
CMPLT_ABOR
T_ERR_SEVER
ITY
14 Completion Timeout Error Severity. For a description of this standard PCIe register field, see the PCI
CMPLT_TIMEO
UT_ERR_SEVE
RITY
13 Flow Control Protocol Error Severity (Optional). For a description of this standard PCIe register field, see
FC_PROTOCO
L_ERR_SEVER
ITY
12 Poisoned TLP Severity. For a description of this standard PCIe register field, see the PCI Express
POIS_TLP_ER
R_SEVERITY
11-6 Reserved
5 Surprise down error severity (optional)

SURPRISE_DO For a description of this standard PCIe register field, see the PCI Express Specification.
WN_ERR_SVRI
TY
- Wire: No access.

NXP Semiconductors
PCIe Controller
Field Function
4 Data Link Protocol Error Severity. For a description of this standard PCIe register field, see the PCI
DL_PROTOCO
L_ERR_SEVER
ITY
3-0 Reserved
3.8.44 Correctable Error Status (CORR_ERR_STATUS_OFF)
Offset
Register Offset
CORR_ERR_STATUS_ 110h
OFF
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HEAD CORR ADVIS RPL_T REPL BAD_ BAD_T RX_E

R 0 0
ER_... ECT... OR... IM... AY_... DLL... LP... RR_...
W W1C W1C W1C W1C W1C W1C W1C W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-16 Reserved

NXP Semiconductors
PCIe Controller
Field Function
15 Header Log Overflow Error Status (Optional). For a description of this standard PCIe register field, see
HEADER_LOG
_OVERFLOW_
STATUS
14 Corrected Internal Error Status (Optional). For a description of this standard PCIe register field, see the
CORRECTED_I
NT_ERR_STAT
US
13 Advisory Non-Fatal Error Status. For a description of this standard PCIe register field, see the PCI
ADVISORY_NO
N_FATAL_ERR
_STATUS
12 Replay Timer Timeout Status. For a description of this standard PCIe register field, see the PCI Express
Specification.
RPL_TIMER_TI
MEOUT_STAT
US
11-9 Reserved
8 REPLAY_NUM Rollover Status. For a description of this standard PCIe register field, see the PCI
REPLAY_NO_R
OLEOVER_ST
ATUS
7 Bad DLLP Status. For a description of this standard PCIe register field, see the PCI Express
Specification.
BAD_DLLP_ST
ATUS
6 Bad TLP Status. For a description of this standard PCIe register field, see the PCI Express Specification.
BAD_TLP_STA
TUS
5-1 Reserved
0 Receiver Error Status (Optional). For a description of this standard PCIe register field, see the PCI
RX_ERR_STAT
US

NXP Semiconductors
PCIe Controller
3.8.45 Correctable Error Mask (CORR_ERR_MASK_OFF)
Offset
Register Offset
CORR_ERR_MASK_OF 114h
F
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R HEAD CORR ADVIS RPL_T 0 REPL BAD_ BAD_T 0 RX_E
W ER_... ECT... OR... IM... AY_... DLL... LP... RR_...
Reset 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-16 Reserved
15 Header Log Overflow Error Mask (Optional). For a description of this standard PCIe register field, see
HEADER_LOG
_OVERFLOW_
MASK
14 Corrected Internal Error Mask (Optional). For a description of this standard PCIe register field, see the
CORRECTED_I
NT_ERR_MAS
K
13 Advisory Non-Fatal Error Mask. For a description of this standard PCIe register field, see the PCI
ADVISORY_NO
N_FATAL_ERR
_MASK

NXP Semiconductors
PCIe Controller
Field Function
12 Replay Timer Timeout Mask. For a description of this standard PCIe register field, see the PCI Express
RPL_TIMER_TI
MEOUT_MASK
11-9 Reserved
8 REPLAY_NUM Rollover Mask. For a description of this standard PCIe register field, see the PCI Express
REPLAY_NO_R
OLEOVER_MA
SK
7 Bad DLLP Mask. For a description of this standard PCIe register field, see the PCI Express
BAD_DLLP_MA
SK
6 Bad TLP Mask. For a description of this standard PCIe register field, see the PCI Express Specification.
BAD_TLP_MAS
K
5-1 Reserved
0 Receiver Error Mask (Optional). For a description of this standard PCIe register field, see the PCI
RX_ERR_MAS
K
3.8.46 Advanced Error Capabilities and Control (ADV_ERR_CAP_CTRL_OFF)
Offset
Register Offset
ADV_ERR_CAP_CTRL_ 118h
OFF
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MULTI MULTI ECRC ECRC

R 0 ECRC ECRC FIRST_ERR_POINTER
PL... PL... _CH... _GE...
_CH... _GE...
W
Reset 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0
Fields
Field Function
31-11 Reserved
10 Multiple Header Recording Enable. For a description of this standard PCIe register field, see the PCI
MULTIPLE_HE
ADER_EN
9 Multiple Header Recording Capable. For a description of this standard PCIe register field, see the PCI
MULTIPLE_HE
ADER_CAP
8 ECRC Check Enable. For a description of this standard PCIe register field, see the PCI Express
ECRC_CHECK
_EN
7 ECRC Check Capable. For a description of this standard PCIe register field, see the PCI Express
ECRC_CHECK
_CAP
6 ECRC Generation Enable. For a description of this standard PCIe register field, see the PCI Express
ECRC_GEN_E
N
5 ECRC Generation Capable. For a description of this standard PCIe register field, see the PCI Express
ECRC_GEN_C
AP
4-0 First Error Pointer. For a description of this standard PCIe register field, see the PCI Express
FIRST_ERR_P
OINTER

NXP Semiconductors
PCIe Controller
3.8.47 Header Log Register 0 (HDR_LOG_0_OFF)
Offset
Register Offset
HDR_LOG_0_OFF 11Ch
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R FIRST_DWORD_FOURTH_BYTE FIRST_DWORD_THIRD_BYTE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R FIRST_DWORD_SECOND_BYTE FIRST_DWORD_FIRST_BYTE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
FIRST_DWOR
D_FOURTH_BY
TE
FIRST_DWOR
D_THIRD_BYT
E
FIRST_DWOR
D_SECOND_B
YTE
FIRST_DWOR
D_FIRST_BYTE

NXP Semiconductors
PCIe Controller
Offset
Register Offset
HDR_LOG_1_OFF 120h
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R SECOND_DWORD_FOURTH_BYTE SECOND_DWORD_THIRD_BYTE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R SECOND_DWORD_SECOND_BYTE SECOND_DWORD_FIRST_BYTE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
SECOND_DWO
RD_FOURTH_
BYTE
SECOND_DWO
RD_THIRD_BY
TE
SECOND_DWO
RD_SECOND_
BYTE
SECOND_DWO
RD_FIRST_BY
TE

NXP Semiconductors
PCIe Controller
Offset
Register Offset
HDR_LOG_2_OFF 124h
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R THIRD_DWORD_FOURTH_BYTE THIRD_DWORD_THIRD_BYTE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R THIRD_DWORD_SECOND_BYTE THIRD_DWORD_FIRST_BYTE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
THIRD_DWOR
D_FOURTH_BY
TE
THIRD_DWOR
D_THIRD_BYT
E
THIRD_DWOR
D_SECOND_B
YTE
THIRD_DWOR
D_FIRST_BYTE

NXP Semiconductors
PCIe Controller
Offset
Register Offset
HDR_LOG_3_OFF 128h
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R FOURTH_DWORD_FOURTH_BYTE FOURTH_DWORD_THIRD_BYTE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R FOURTH_DWORD_SECOND_BYTE FOURTH_DWORD_FIRST_BYTE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
FOURTH_DWO
RD_FOURTH_
BYTE
FOURTH_DWO
RD_THIRD_BY
TE
FOURTH_DWO
RD_SECOND_
BYTE
FOURTH_DWO
RD_FIRST_BY
TE

NXP Semiconductors
PCIe Controller
3.8.51 Root Error Command (ROOT_ERR_CMD_OFF)
Offset
Register Offset
ROOT_ERR_CMD_OFF 12Ch
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 FATAL NON_ CORR
W _E... FAT... _ER...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-3 Reserved
2 Fatal Error Reporting Enable. For a description of this standard PCIe register field, see the PCI Express
Specification.
FATAL_ERR_R
EPORTING_EN
1 Non-Fatal Error Reporting Enable. For a description of this standard PCIe register field, see the PCI
NON_FATAL_E
RR_REPORTIN
G_EN
0 Correctable Error Reporting Enable. For a description of this standard PCIe register field, see the PCI
CORR_ERR_R
EPORTING_EN

NXP Semiconductors
PCIe Controller
3.8.52 Root Error Status (ROOT_ERR_STATUS_OFF)
Offset
Register Offset
ROOT_ERR_STATUS_O 130h
FF
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R ADV_ERR_INT_MSG_NUM 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FATAL NON_ FIRST MUL_ ERR_F MUL_ ERR_

R 0
_E... FAT... _U... ERR... AT... ERR... COR...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-27 Advanced Error Interrupt Message Number

ADV_ERR_INT For a description of this standard PCIe register field, see the PCI Express Specification.
_MSG_NUM
- Wire: No access.
26-7 Reserved
6 One or more Fatal Error Messages Received. For a description of this standard PCIe register field, see
FATAL_ERR_M
SG_RX
5 One or more Non-Fatal Error Messages Received. For a description of this standard PCIe register field,
see the PCI Express Specification.

NXP Semiconductors
PCIe Controller
Field Function
NON_FATAL_E
RR_MSG_RX
4 First Uncorrectable Error is Fatal. For a description of this standard PCIe register field, see the PCI
FIRST_UNCOR
R_FATAL
3 Multiple Fatal or Non-Fatal Errors Received. For a description of this standard PCIe register field, see the
MUL_ERR_FAT
AL_NON_FATA
L_RX
2 Fatal or Non-Fatal Error Received. For a description of this standard PCIe register field, see the PCI
ERR_FATAL_N
ON_FATAL_RX
1 Multiple Correctable Errors Received. For a description of this standard PCIe register field, see the PCI
MUL_ERR_CO
R_RX
0 Correctable Error Received. For a description of this standard PCIe register field, see the PCI Express
Specification.
ERR_COR_RX
3.8.53 Error Source Identification (ERR_SRC_ID_OFF)
Offset
Register Offset
ERR_SRC_ID_OFF 134h
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R ERR_FATAL_NON_FATAL_SOURCE_ID
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ERR_COR_SOURCE_ID
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-16 Source of Fatal/Non-Fatal Error. For a description of this standard PCIe register field, see the PCI
ERR_FATAL_N
ON_FATAL_SO
URCE_ID
15-0 Source of Correctable Error. For a description of this standard PCIe register field, see the PCI Express
ERR_COR_SO
URCE_ID
3.8.54 TLP Prefix Log Register 1 (TLP_PREFIX_LOG_1_OFF)
Offset
Register Offset
FF
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
CFG_TLP_PFX
_LOG_1_FOUR
TH_BYTE
CFG_TLP_PFX
_LOG_1_THIRD
_BYTE
CFG_TLP_PFX
_LOG_1_SECO
ND_BYTE
CFG_TLP_PFX
_LOG_1_FIRST
_BYTE
Offset
Register Offset
TLP_PREFIX_LOG_2_O 13Ch
FF
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
CFG_TLP_PFX
_LOG_2_FOUR
TH_BYTE
CFG_TLP_PFX
_LOG_2_THIRD
_BYTE
CFG_TLP_PFX
_LOG_2_SECO
ND_BYTE
CFG_TLP_PFX
_LOG_2_FIRST
_BYTE
Offset
Register Offset
FF
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
CFG_TLP_PFX
_LOG_3_FOUR
TH_BYTE
CFG_TLP_PFX
_LOG_3_THIRD
_BYTE
CFG_TLP_PFX
_LOG_3_SECO
ND_BYTE
CFG_TLP_PFX
_LOG_3_FIRST
_BYTE
Offset
Register Offset
FF
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
CFG_TLP_PFX
_LOG_4_FOUR
TH_BYTE
CFG_TLP_PFX
_LOG_4_THIRD
_BYTE
CFG_TLP_PFX
_LOG_4_SECO
ND_BYTE
CFG_TLP_PFX
_LOG_4_FIRST
_BYTE
3.8.58 SPCIE Capability Header (SPCIE_CAP_HEADER_REG)
Offset
Register Offset
SPCIE_CAP_HEADER_ 148h
REG
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset 0 0 0 1 0 1 0 1 1 0 0 0 0 0 0 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R EXTENDED_CAP_ID
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1
Fields
Field Function
31-20
19-16
15-0 Secondary PCI Express Extended Capability ID. For a description of this standard PCIe register field,
EXTENDED_C access. Note: This register field is sticky.
AP_ID
3.8.59 Link control 3 (LINK_CONTROL3_REG)
Offset
Register Offset
LINK_CONTROL3_REG 14Ch
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 EQ_R PERF
W EQ_... ORM...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-2 Reserved
1 Link equalization request interrupt enable

EQ_REQ_INT_ For a description of this standard PCIe register field, see the PCI Express Specification.
EN
- Wire: No access.
0 Perform equalization
PERFORM_EQ For a description of this standard PCIe register field, see the PCI Express Specification.
- Wire: No access.
3.8.60 Lane Error Status (LANE_ERR_STATUS_REG)
Offset
Register Offset
LANE_ERR_STATUS_R 150h
EG
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LANE_ERR_ST
R 0
ATUS
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-2 Reserved
1-0 Lane Error Status Bits per Lane. For a description of this standard PCIe register field, see the PCI
LANE_ERR_ST
ATUS
3.8.61 Lane Equalization Control Register For Lanes 1 And 0 (SPCIE_CAP_OFF_0CH_REG)
Offset
Register Offset
SPCIE_CAP_OFF_0CH_ 154h
REG
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1 1
Reset 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0
Reset 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
Fields
Field Function
31 Reserved
Upstream Port 8.0 GT/s Receiver Preset Hint 1. The write value is gated with the
30-28
PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this
USP_RX_PRES standard PCIe register field, see the PCI Express Specification. Note: The access attributes of this
ET_HINT1 field are as follows: - Wire: No access.
Upstream Port 8.0 GT/s Transmitter Preset 1. The write value is gated with the
27-24
USP_TX_PRES standard PCIe register field, see the PCI Express Specification. Note: The access attributes of this
ET1 field are as follows: - Wire: No access.
23 Reserved
Downstream Port 8.0 GT/s Receiver Preset Hint 1. For a description of this standard PCIe register field,
22-20
DSP_RX_PRES access.
ET_HINT1
Downstream Port 8.0 GT/s Transmitter Preset 1. For a description of this standard PCIe register field,
19-16
DSP_TX_PRES access.
ET1
15 Reserved
Upstream Port 8.0 GT/s Receiver Preset Hint 0. The write value is gated with the
14-12
USP_RX_PRES standard PCIe register field, see the PCI Express Specification. Note: The access attributes of this
ET_HINT0 field are as follows: - Wire: No access.

NXP Semiconductors
PCIe Controller
Field Function
Upstream Port 8.0 GT/s Transmitter Preset 0. The write value is gated with the
11-8
USP_TX_PRES standard PCIe register field, see the PCI Express Specification. Note: The access attributes of this
ET0 field are as follows: - Wire: No access.
7 Reserved
Downstream Port 8.0 GT/s Receiver Preset Hint 0. For a description of this standard PCIe register field,
6-4
DSP_RX_PRES access.
ET_HINT0
Downstream Port 8.0 GT/s Transmitter Preset 0. For a description of this standard PCIe register field,
3-0
DSP_TX_PRES access.
ET0
3.8.62 Vendor-Specific Extended Capability Header (RAS_DES_CAP_HEADER_REG)
Offset
Register Offset
RAS_DES_CAP_HEADE 158h
R_REG
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R EXTENDED_CAP_ID
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-20
19-16
15-0 PCI Express Extended Capability ID. For a description of this standard PCIe register field, see the PCI
EXTENDED_C This register field is sticky.
AP_ID
3.8.63 Vendor-Specific Header (VENDOR_SPECIFIC_HEADER_REG)
Offset
Register Offset
VENDOR_SPECIFIC_H 15Ch
EADER_REG
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VSEC_ID
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Fields
Field Function
31-20 VSEC Length. For a description of this standard PCIe register field, see the PCI Express Specification.
VSEC_LENGT
H

NXP Semiconductors
PCIe Controller
Field Function
19-16 VSEC Rev. For a description of this standard PCIe register field, see the PCI Express Specification.
VSEC_REV
15-0 VSEC ID. For a description of this standard PCIe register field, see the PCI Express Specification.
VSEC_ID
3.8.64 Event Counter Control (EVENT_COUNTER_CONTROL_REG)
Offset
Register Offset
EVENT_COUNTER_CO 160h
NTROL_REG
Function
This is a viewport control register. - Setting the EVENT_COUNTER_EVENT_SELECT and
EVENT_COUNTER_LANE_SELECT fields in this register determine the Event Counter data returned by the
EVENT_COUNTER_DATA_REG viewport register. - Setting the EVENT_COUNTER_ENABLE field in this register enables
the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields
in this register. - Setting the EVENT_COUNTER_CLEAR field in this register clears the Event Counter selected by
the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. - Reading the
EVENT_COUNTER_STATUS field in this register returns the Enable status of the Event Counter selected by the
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
EVENT_COUNTER_EVENT_SELECT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EVEN
R 0 0
EVENT_COUNTER_LANE_SELE T_C...
CT EVENT_COUNTER_ENA EVENT_COUN
W
BLE TER_C...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-28 Reserved
27-16 Event Counter Data Select

EVENT_COUN This field in conjunction with the EVENT_COUNTER_LANE_SELECT field indexes the Event Counter data
TER_EVENT_S returned by the EVENT_COUNTER_DATA_REG register.
ELECT
• 27-24: Group number(4-bit: 0..0x7)
• 23-16: Event number(8-bit: 0..0x13) within the Group
For example:
• 0x000: Ebuf Overflow
• 0x001: Ebuf Underrun
• ...
• 0x700: Tx Memory Write
• 0x713: Rx Message TLP
For detailed definitions of Group number and Event number, see RAS Debug, Error Injection, and Statistics
(DES)†.
15-12 Reserved
11-8Event Counter Lane Select. This field in conjunction with EVENT_COUNTER_EVENT_SELECT indexes
the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 0x0: Lane0 - 0x1:
EVENT_COUN Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note: This register field is sticky.
TER_LANE_SE
LECT
7 Event Counter Status. This register returns the current value of the Event Counter selected by the
following fields: - EVENT_COUNTER_EVENT_SELECT - EVENT_COUNTER_LANE_SELECT Note:
EVENT_COUN This register field is sticky.
TER_STATUS
6-5 Reserved
Event Counter Enable. Enables/disables the Event Counter selected by the

4-2
EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. By
EVENT_COUN default, all event counters are disabled. You can enable/disable a specific Event Counter by writing the
TER_ENABLE 'per event off' or 'per event on' codes. You can enable/disable all event counters by writing the 'all on' or
'all off' codes. The read value is always '0'. - 000: no change - 001: per event off - 010: no change - 011:
per event on - 100: no change - 101: all off - 110: no change - 111: all on
1-0 Event Counter Clear. Clears the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT
and EVENT_COUNTER_LANE_SELECT fields in this register. You can clear the value of a specific

NXP Semiconductors
PCIe Controller
Field Function
EVENT_COUN Event Counter by writing the 'per clear' code and you can clear all event counters at once by writing the
TER_CLEAR 'all clear' code. The read value is always '0'. - 00: no change - 01: per clear - 10: no change - 11: all clear
- Other: reserved
3.8.65 Event Counter Data (EVENT_COUNTER_DATA_REG)
Offset
Register Offset
EVENT_COUNTER_DA 164h
TA_REG
Function
This viewport register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in
EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG For
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
Event Counter Data. This register returns the data selected by the following
31-0
fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG -
EVENT_COUN EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG Note: This register field is
TER_DATA sticky.

NXP Semiconductors
PCIe Controller
3.8.66 Time-based Analysis Control (TIME_BASED_ANALYSIS_CONTROL_REG)
Offset
Register Offset
TIME_BASED_ANALYSI 168h
S_CONTROL_REG
Function
Controls the measurement of RX/TX data throughput and time spent in each low-power LTSSM state. For more details, see RAS
Debug, Error Injection, and Statistics (DES)†.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
TIME_BASED_REPORT_SELECT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 TIMER
TIME_BASED_DURATION_SELECT
W _S...
Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
Fields
Field Function
31-24 Time-based Report Select

TIME_BASED_ Selects what type of data is measured for the selected duration (TIME_BASED_DURATION_SELECT), and
REPORT_SELE returned in TIME_BASED_ANALYSIS_DATA.
CT
Each type of data is measured using one of three types of units:
• Core_clk cycles. Total time in ps is [Value of TIME_BASED_ANALYSIS_DATA returned when
TIME_BASED_REPORT_SELECT=0h] * TIME_BASED_ANALYSIS_DATA.
• Aux_clk cycles. Total time in ps is [Period of platform specific clock] *
TIME_BASED_ANALYSIS_DATA.
• Data bytes. Actual amount of bytes is 16 * TIME_BASED_ANALYSIS_DATA.
0000_0000b - Duration of 1 Core_clk cycle
0000_0001b - TxL0s (measured in Core_clk cycles)
0000_0010b - RxL0s (measured in Core_clk cycles)

NXP Semiconductors
PCIe Controller
Field Function
0000_0011b - L0 (measured in Core_clk cycles)

0000_0100b - L1 (measured in Core_clk cycles; reserved when aux_clk is supplied from the
platform specific clock during L1, L1.1 or L1.2)
0000_0111b - Configuration/recovery (measured in Core_clk cycles)
0010_0000b - Tx TLP data payload (measured in data bytes)
0010_0001b - Rx TLP data payload (measured in data bytes)
23-16 Reserved
15-8 Time-based Duration Select

TIME_BASED_ Selects the duration of time-based analysis.
DURATION_SE
If you require manual control, you must follow this procedure:
LECT
1. Select TIME_BASED_DURATION_SELECT=0b.
2. Start the analysis by writing 1b to PE0_GEN_CTRL_4[CFG_RAS_DES_TBA_CTRL].
3. Stop the analysis by writing 10b to PE0_GEN_CTRL_4[CFG_RAS_DES_TBA_CTRL].
0000_0000b - Manual control
0000_0001b - 1 ms
0000_0010b - 10 ms
0000_0011b - 100 ms
0000_0100b - 1 s
0000_0101b - 2 s
0000_0110b - 4 s
7-1 Reserved
0 Timer Start
TIMER_START This field returns to 0 automatically when the measurement finishes.
The app_ras_des_tba_ctrl input also sets the contents of this field and controls the measurement start/stop.
This field has no effect when TIME_BASED_DURATION_SELECT=0b. Instead, use the procedure
described in TIME_BASED_DURATION_SELECT.

NXP Semiconductors
PCIe Controller
Field Function

0b - Stop
1b - Start/restart
3.8.67 Time-Based Analysis Data (TIME_BASED_ANALYSIS_DATA_REG)
Offset
Register Offset
TIME_BASED_ANALYSI 16Ch
S_DATA_REG
Function
Contains the measurement results of RX/TX data throughput and time spent in each low-power LTSSM state.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0
Fields
Field Function
31-0 Time-Based Analysis Data

TIME_BASED_ Returns the data selected by
ANALYSIS_DA TIME_BASED_ANALYSIS_CONTROL_REG[TIME_BASED_REPORT_SELECT]. For more details, see
TA RAS Debug, Error Injection, and Statistics (DES)†.
This field contains the sum of previous and latest values of TBA event counters. To obtain only the latest
value, you must deduct the previous value from the current value of this field.

NXP Semiconductors
PCIe Controller
3.8.68 Error Injection Enable (EINJ_ENABLE_REG)
Offset
Register Offset
EINJ_ENABLE_REG 188h
Function
Error Injection Enable. Each type of error insertion is enabled by the corresponding bit in this register. The specific injection
controls for each type of error are defined in the following registers: - 0: CRC Error: EINJ0_CRC_REG - 1: Sequence Number
Error: EINJ1_SEQNUM_REG - 2: DLLP Error: EINJ2_DLLP_REG - 3: Symbol DataK Mask Error or Sync Header Error:
EINJ3_SYMBOL_REG - 4: FC Credit Update Error: EINJ4_FC_REG - 5: TLP Duplicate/Nullify Error: EINJ5_SP_TLP_REG - 6:
Specific TLP Error: EINJ6_COMPARE_*_REG/EINJ6_CHANGE_*_REG/EINJ6_TLP_REG After the errors have been inserted
by controller, it will clear each bit here. For more details, see RAS Debug, Error Injection, and Statistics (DES)†.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 Reserv ERRO ERRO ERRO ERRO ERRO ERRO
W ed R_I... R_I... R_I... R_I... R_I... R_I...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-7 Reserved
6 Reserved
5 Error Injection5 Enable (TLP Duplicate/Nullify Error). Enables insertion of duplicate/nullified TLPs. For
more details, see the EINJ5_SP_TLP_REG register. Note: This register field is sticky.
ERROR_INJEC
TION5_ENABL
E
4 Error Injection4 Enable (FC Credit Update Error). Enables insertion of errors into UpdateFCs. For more
details, see the EINJ4_FC_REG register. Note: This register field is sticky.

NXP Semiconductors
PCIe Controller
Field Function
ERROR_INJEC
TION4_ENABL
E
3 Error Injection3 Enable (Symbol DataK Mask Error or Sync Header Error). Enables DataK masking of
special symbols or the breaking of the sync header. For more details, see the EINJ3_SYMBOL_REG
ERROR_INJEC register. Note: This register field is sticky.
TION3_ENABL
E
2 Error Injection2 Enable (DLLP Error). Enables insertion of DLLP errors. For more details, see the
EINJ2_DLLP_REG register. Note: This register field is sticky.
ERROR_INJEC
TION2_ENABL
E
1 Error Injection1 Enable (Sequence Number Error). Enables insertion of errors into sequence numbers.
For more details, see the EINJ1_SEQNUM_REG register. Note: This register field is sticky.
ERROR_INJEC
TION1_ENABL
E
0 Error Injection0 Enable (CRC Error). Enables insertion of errors into various CRC. For more details, see
the EINJ0_CRC_REG register. Note: This register field is sticky.
ERROR_INJEC
TION0_ENABL
E
3.8.69 Error Injection Control 0 (CRC Error) (EINJ0_CRC_REG)
Offset
Register Offset
EINJ0_CRC_REG 18Ch
Function
Controls the insertion of errors into the CRC, and parity of ordered sets for the selected type of the packets as follows: -
LCRC. Bad TLP will be detected at the receiver side; receiver responds with NAK DLLP; Data Link Retry starts. - 16-bit CRC
of ACK/NAK DLLPs. Bad DLLP occurs at the receiver side; Replay NUM Rollover occurs. - 16-bit CRC of UpdateFC DLLPs.
Error insertion continues for the specific time; LTSSM transitions to the Recovery state because of the UpdateFC timeout (if
the timeout is implemented at the receiver of the UpdateFCs). - ECRC. If ECRC check is enabled, ECRC error is detected at
the receiver side. - FCRC. Framing error will be detected, TLP is discarded, and the LTSSM transitions to Recovery state. -
Parity of TSOS. Error insertion continues for the specific time; LTSSM Recovery/Configuration timeout will occur. - Parity of
SKPOS. Lane error will be detected at the receiver side.

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
EINJ0_CRC_TYPE EINJ0_COUNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-12 Reserved
Error injection type. Selects the type of CRC error to be inserted. Tx Path - 0000b: New TLP's LCRC
11-8
error injection - 0001b: 16bCRC error injection of ACK/NAK DLLP - 0010b: 16bCRC error injection of
EINJ0_CRC_TY Update-FC DLLP - 0011b: New TLP's ECRC error injection - 0100b: TLP's FCRC error injection (128b/
PE 130b) - 0101b: Parity error of TSOS (128b/130b) - 0110b: Parity error of SKPOS (128b/130b) Rx Path -
1000b: LCRC error injection - 1011b: ECRC error injection - Others: Reserved Note: This register field is
sticky.
Error injection count. Indicates the number of errors. This register is decremented when the errors have
7-0
been inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION0_ENABLE in
EINJ0_COUNT EINJ_ENABLE_REG returns 0b. - If the counter value is 0x00 and ERROR_INJECTION0_ENABLE=1,
3.8.70 Error Injection Control 1 (Sequence Number Error) (EINJ1_SEQNUM_REG)
Offset
Register Offset
EINJ1_SEQNUM_REG 190h
Function
Controls the sequence number of the specific TLPs and ACK/NAK DLLPs. Data Link Protocol Error will be detected at the Rx
side of ACK/NAL DLLPs when one of these conditions is true: - ((NEXT_TRANSMIT_SEQ -1) - AckNak_Seq_Num) mod 4096
> 2048 - (AckNak_Seq_Num - ACKD_SEQ) mod 4096 >= 2048 TLP is treated as Duplicate TLP at the Rx side when all these
conditions are true: - Sequence Number != NEXT_RCV_SEQ - (NEXT_RCV_SEQ - Sequence Number) mod 4096 <= 2048
TLP is treated as Bad TLP at the Rx side when all these conditions are true: - Sequence Number != NEXT_RCV_SEQ and -
(NEXT_RCV_SEQ - Sequence Number) mod 4096 > 2048

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
EINJ1_BAD_SEQNUM
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 EINJ1_
EINJ1_COUNT
W S...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-29 Reserved
28-16Bad sequence number. Indicates the value to add/subtract from the naturally-assigned sequence
numbers. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1
EINJ1_BAD_SE - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 - .. - 0x1001: -4095 For example: - Set Type, SEQ# and Count --
QNUM EINJ1_SEQNUM_TYPE =0 (Insert errors into new TLPs) -- EINJ1_BAD_SEQNUM =0x1FFD (represents
-3) -- EINJ1_COUNT =1 - Enable Error Injection -- ERROR_INJECTION1_ENABLE =1 - Send a TLP
From the Core's Application Interface -- Assume SEQ#5 is given to the TLP. - The SEQ# is Changed to
#2 by the Error Injection Function in Layer2. -- 5 + (-3) = 2 - The TLP with SEQ#2 is Transmitted to PCIe
Link. Note: This register field is sticky.
15-9 Reserved
8 Sequence number type. Selects the type of sequence number. - 0b: Insertion of New TLP's SEQ# error -
1b: Insertion of ACK/NAK DLLP's SEQ# Error Note: This register field is sticky.
EINJ1_SEQNU
M_TYPE
7-0
EINJ1_COUNT EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION1_ENABLE=1,
3.8.71 Error Injection Control 2 (DLLP Error) (EINJ2_DLLP_REG)
Offset
Register Offset
EINJ2_DLLP_REG 194h

NXP Semiconductors
PCIe Controller
Function
Controls the transmission of DLLPs and inserts the following errors: - If "ACK/NAK DLLP's transmission block" is selected,
replay timeout error will occur at the transmitter of the TLPs and then Data Link Retry will occur. - If "Update FC DLLP's
transmission block" is selected, LTSSM will transition to the Recovery state because of the UpdateFC timeout (if the timeout
is implemented at the receiver of the UpdateFCs). - If "Always Transmission for NAK DLLP" is selected, Data Link Retry will
occur at the transmitter of the TLPs. Furthermore, Replay NUM Rollover will occur when the transmitter has been requested
four times to send the TLP with the same sequence number.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 EINJ2_DLLP_T
EINJ2_COUNT
W YPE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-10 Reserved
9-8DLLP Type. Selects the type of DLLP errors to be inserted. - 00b: ACK/NAK DLLP's transmission block
- 01b: Update FC DLLP's transmission block - 10b: Always Transmission for NAK DLLP - 11b: Reserved
EINJ2_DLLP_T Note: This register field is sticky.
YPE
7-0
being inserted. - If the counter value is 0x01 and the error is inserted, ERROR_INJECTION2_ENABLE
EINJ2_COUNT in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION2_ENABLE =1,
the errors are inserted until ERROR_INJECTION2_ENABLE is set to '0'. This register is affected only
when EINJ2_DLLP_TYPE =2'10b. Note: This register field is sticky.
3.8.72 Error Injection Control 3 (Symbol Error) (EINJ3_SYMBOL_REG)
Offset
Register Offset
EINJ3_SYMBOL_REG 198h
Function
When 8b/10b encoding is used, this register controls error insertion into the special (K code) symbols.
• If TS1/TS2/FTS/E-Idle/SKP is selected, it affects whole of the ordered set. It might cause timeout of the LTSSM.

NXP Semiconductors
PCIe Controller
• If END/EDB/STP/SDP is selected, TLP/DLLP will be discarded at the receiver side.

When 128b/130b encoding is used, this register controls error insertion into the sync-header.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
EINJ3_SYMBOL_TYPE EINJ3_COUNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-11 Reserved
10-8 Error Type

EINJ3_SYMBO • 8b/10b encoding - Mask K symbol.
L_TYPE
— 000b: Reserved
— 011b: COM/FTS(FTS Order set)
— 100b: COM/IDL(E-Idle Order set)
— 101b: END/EDB Symbol
— 110b: STP/SDP Symbol
— 111b: COM/SKP(SKP Order set)
• 128b/130b encoding - Change sync header.
— 000b: Invert sync header
— Others: Reserved
7-0 Error Injection Count

EINJ3_COUNT Indicates the number of errors.
This register is decremented as the errors are being inserted.

NXP Semiconductors
PCIe Controller
Field Function
• If the counter value is 0x01 and error is inserted, ERROR_INJECTION3_ENABLE in

EINJ_ENABLE_REG returns '0'.
• If the counter value is 0x00 and ERROR_INJECTION3_ENABLE =1, the errors are inserted until
ERROR_INJECTION3_ENABLE is set to '0'.
3.8.73 Error Injection Control 4 (FC Credit Error) (EINJ4_FC_REG)
Offset
Register Offset
EINJ4_FC_REG 19Ch
Function
Controls error insertion into the credit value in the UpdateFCs. It is possible to insert errors for any of the following types:
- Posted TLP Header credit - Non-Posted TLP Header credit - Completion TLP Header credit - Posted TLP Data credit -
Non-Posted TLP Data credit - Completion TLP Data credit These errors are not correctable while error insertion is enabled.
Receiver buffer overflow error might occur.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
EINJ4_BAD_UPDFC_VALUE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0
EINJ4_VC_NUMBER EINJ4_UPDFC_TYPE EINJ4_COUNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-29 Reserved
28-16 Bad update-FC credit value. Indicates the value to add/subtract from the UpdateFC credit. This value is
represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF:
-1 - 0x1FFE: -2 - .. - 0x1001: -4095 Note: This register field is sticky.

NXP Semiconductors
PCIe Controller
Field Function
EINJ4_BAD_UP
DFC_VALUE
15 Reserved
14-12 VC Number. Indicates target VC Number. Note: This register field is sticky.
EINJ4_VC_NU
MBER
11 Reserved
10-8Update-FC type. Selects the credit type. - 000b: Posted TLP Header Credit value control - 001b:
Non-Posted TLP Header Credit value control - 010b: Completion TLP Header Credit value control -
EINJ4_UPDFC_ 011b: Reserved - 100b: Posted TLP Data Credit value control - 101b: Non-Posted TLP Data Credit value
TYPE control - 110b: Completion TLP Data Credit value control - 111b: Reserved Note: This register field is
sticky.
7-0Error injection count. Indicates the number of errors. This register is decremented as the errors are
3.8.74 Error Injection Control 5 (Specific TLP Error) (EINJ5_SP_TLP_REG)
Offset
Register Offset
EINJ5_SP_TLP_REG 1A0h
Function
Controls the generation of specified TLPs. Correctable errors will occur which will be fixed by the PCIe protocol. - For
Duplicate TLP, the controller initiates Data Link Retry by handling ACK DLLP as NAK DLLP. These TLPs will be duplicate
TLPs at the receiver side. - For Nullified TLP, the TLPs that the controller transmits are changed into nullified TLPs and the
original TLPs are stored in the retry buffer. The receiver of these TLPs will detect the lack of seq# and send NAK DLLP at
the next TLP. Then the original TLPs are sent from retry buffer and the data controls are recovered. For 128 bit controller or
more than 128 bit, the controller inserts errors the number of times of EINJ5_COUNT but doesn't ensure that the errors are
continuously inserted into TLPs.

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 EINJ5_
EINJ5_COUNT
W S...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-9 Reserved
8 Specified TLP. Selects the specified TLP to be inserted. - 0: Generates duplicate TLPs by handling ACK
DLLP as NAK DLLP. - 1: Generates Nullified TLP (Original TLP will be stored in retry buffer). Note: This
EINJ5_SPECIFI register field is sticky.
ED_TLP
7-0
3.8.75 Error Injection Control 6 (Compare Point Header DWORD #0)

Offset
Register Offset
T_H0_REG
Function
Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when
you program this register. Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TLP_DW0[31:24] The Packet
Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding
bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and
EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP. The type and number of errors are specified by
the EINJ6_TLP_REG register.

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
Packet Compare Point: 1st DWORD. Specifies which Tx TLP header DWORD#0 bits to compare with
31-0

Offset
Register Offset
T_H1_REG
Function
Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
Packet Compare Point: 2nd DWORD. Specifies which Tx TLP header DWORD#1 bits to compare with
31-0

Offset
Register Offset
EINJ6_COMPARE_POIN 1ACh
T_H2_REG
Function
Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
Packet Compare Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to compare with
31-0

Offset
Register Offset
EINJ6_COMPARE_POIN 1B0h
T_H3_REG
Function
Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
Packet Compare Point: 4th DWORD. Specifies which Tx TLP header DWORD#3 bits to compare with
31-0
3.8.79 Error Injection Control 6 (Compare Value Header DWORD #0)

Offset
Register Offset
UE_H0_REG
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
Packet Compare Value: 1st DWORD. Specifies the value to compare against Tx the TLP header
31-0
RE_VALUE_H0

Offset
Register Offset
UE_H1_REG
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
Packet Compare Value: 2nd DWORD. Specifies the value to compare against Tx the TLP header
31-0
RE_VALUE_H1

Offset
Register Offset
EINJ6_COMPARE_VAL 1BCh
UE_H2_REG
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
Packet Compare Value: 3rd DWORD. Specifies the value to compare against Tx the TLP header
31-0
RE_VALUE_H2

Offset
Register Offset
EINJ6_COMPARE_VAL 1C0h
UE_H3_REG
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
Packet Compare Value: 4th DWORD. Specifies the value to compare against Tx the TLP header
31-0
RE_VALUE_H3
3.8.83 Error Injection Control 6 (Change Point Header DWORD #0)

Offset
Register Offset
_H0_REG
Function
Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits
in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the
EINJ6_TLP_REG register. Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
Packet Change Point: 1st DWORD. Specifies which Tx TLP header DWORD#0 bits to replace with the
31-0
E_POINT_H0

Offset
Register Offset
_H1_REG
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
Packet Change Point: 2nd DWORD. Specifies which Tx TLP header DWORD#1 bits to replace with the
31-0
E_POINT_H1

Offset
Register Offset
EINJ6_CHANGE_POINT 1CCh
_H2_REG
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
Packet Change Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to replace with the
31-0
E_POINT_H2

Offset
Register Offset
EINJ6_CHANGE_POINT 1D0h
_H3_REG
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
Packet Change Point: 4th DWORD. Specifies which Tx TLP header DWORD#3 bits to replace with the
31-0
E_POINT_H3
3.8.87 Error Injection Control 6 (Change Value Header DWORD #0)

Offset
Register Offset
E_H0_REG
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
Packet Change Value: 1st DWORD. Specifies replacement values for the Tx TLP header DWORD#0
31-0
E_VALUE_H0

Offset
Register Offset
E_H1_REG
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
Packet Change Value: 2nd DWORD. Specifies replacement values for the Tx TLP header DWORD#1
31-0
E_VALUE_H1

Offset
Register Offset
EINJ6_CHANGE_VALU 1DCh
E_H2_REG
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
Packet Change Value: 3rd DWORD. Specifies replacement values for the Tx TLP header DWORD#2
31-0
E_VALUE_H2

Offset
Register Offset
EINJ6_CHANGE_VALU 1E0h
E_H3_REG
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
Packet Change Value: 4th DWORD. Specifies replacement values for the Tx TLP header DWORD#3
31-0
E_VALUE_H3
3.8.91 Error Injection Control 6 (Packet Error) (EINJ6_TLP_REG)
Offset
Register Offset
EINJ6_TLP_REG 1E4h
Function
The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the
corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx
TLP header and EINJ6_COMPARE_VALUE*) match, the controller inserts errors into the TLP. The type and number of errors
are specified by the this register. The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header
bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and
number of errors are specified by the this register. Only applies when EINJ6_INVERTED_CONTROL in this register =0. The
TLP into that errors are injected will not arrive at the transaction layer of the remote device when all of the following conditions
are true. - Using 128b/130b encoding - Injecting errors into TLP Length field / TLP digest bit

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 EINJ6_
EINJ6_PACKET_TYPE EINJ6_COUNT
W I...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-12 Reserved
11-9 Packet type. Selects the TLP packets to inject errors into. - 0: TLP Header - 1: TLP Prefix 1st
4-DWORDs - 2: TLP Prefix 2nd -DWORDs - Else: Reserved Note: This register field is sticky.
EINJ6_PACKET
_TYPE
8 Inverted Error Injection Control. - 0: EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace bits specified

by EINJ6_CHANGE_POINT_H[0/1/2/3]. - 1: EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and inverts
EINJ6_INVERT bits specified by EINJ6_CHANGE_POINT_H[0/1/2/3]. Note: This register field is sticky.
ED_CONTROL
Error Injection Count. Indicates the number of errors to insert. This counter is decremented while errors
7-0
are been inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION6_ENABLE
EINJ6_COUNT in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION6_ENABLE=1,
errors are inserted until ERROR_INJECTION6_ENABLE is set to '0'. Note: This register field is sticky.
Offset
Register Offset
SD_CONTROL1_REG 1F8h
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 LOW_POWER_ 0 FORC
TX_EIOS_NUM
W INTER... E_D...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
FORCE_DETECT_LANE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-24 Reserved
Low Power Entry Interval Time. Interval Time that the controller starts monitoring RXELECIDLE signal
23-22
after L0s/L1/L2 entry. You should set the value according to the latency from receiving EIOS to,
LOW_POWER_ RXELECIDLE assertion at the PHY. - 0x0: 40ns - 0x1: 160ns - 0x2: 320ns - 0x3: 640ns Note: This
INTERVAL register field is sticky.
Number of Tx EIOS. This register sets the number of transmit EIOS for L0s/L1 entry and Disable/
21-20
Loopback/Hot-reset exit. The controller selects the greater value between this register and the value
TX_EIOS_NUM defined by the PCI-SIG specification. 2.5GT/s, 8.0GT/s or higher: - 0x0: 1 - 0x1: 4 - 0x2: 8 - 0x3: 16
5.0GT/s: - 0x0: 2 - 0x1: 8 - 0x2: 16 - 0x3: 32 Note: This register field is sticky.
19-17 Reserved
16 Force Detect Lane Enable. When this bit is set, the controller ignores receiver detection from PHY during
LTSSM Detect state and uses FORCE_DETECT_LANE. Note: This register field is sticky.
FORCE_DETE
CT_LANE_EN
15-0 Force Detect Lane. When the FORCE_DETECT_LANE_EN field is set, the controller ignores receiver
detection from PHY during LTSSM Detect state and uses this value instead. - 0: Lane0 - 1: Lane1 - 2:
FORCE_DETE Lane2 - .. - 15: Lane15 Note: This register field is sticky.
CT_LANE
Offset
Register Offset
SD_CONTROL2_REG 1FCh

NXP Semiconductors
PCIe Controller
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 FRAMI
W NG...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0
DIREC DIREC DIREC NOAC HOLD
T_... T_... T_... K_F... RECO _LT...
W
VER...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-17 Reserved
16 Framing Error Recovery Disable. This bit disables a transition to Recovery state when a Framing Error is
occurred. Note: This register field is sticky.
FRAMING_ERR
_RECOVERY_
DISABLE
15-11 Reserved
10 Direct Loopback Slave To Exit. When this bit is set and the LTSSM is in Loopback Slave Active State,
the LTSSM transitions to Loopback Slave Exit state. Note: This register field is sticky.
DIRECT_LPBK
SLV_TO_EXIT
9 Direct Polling.Compliance to Detect. When this bit is set and the LTSSM is in Polling Compliance State,
the LTSSM transitions to Detect state. Note: This register field is sticky.
DIRECT_POLC
OMP_TO_DET
ECT
8 Direct Recovery.Idle to Configuration. When this bit is set and the LTSSM is in Recovery Idle State, the
LTSSM transitions to Configuration state. Note: This register field is sticky.
DIRECT_RECI
DLE_TO_CONF
IG
7-3 Reserved

NXP Semiconductors
PCIe Controller
Field Function
2 Force LinkDown. When this bit is set and the controller detects REPLY_NUM rolling over 4 times, the
LTSSM transitions to Detect State. Note: This register field is sticky.
NOACK_FORC
E_LINKDOWN
1 Recovery Request. When this bit is set to '1' in L0 or L0s, the LTSSM starts transitioning to Recovery
State. This request does not cause a speed change or re-equalization.
RECOVERY_R
EQUEST
0 Hold and Release LTSSM. For as long as this register is '1', the controller stays in the current LTSSM.
HOLD_LTSSM
3.8.94 Silicon Debug Status (Layer1 Per-lane) (SD_STATUS_L1LANE_REG)
Offset
Register Offset
SD_STATUS_L1LANE_ 208h
REG
Function
This viewport register returns the data selected by the following field: - LANE_SELECT in SD_STATUS_L1LANE_REG For
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PIPE_ PIPE_ PIPE_ PIPE_ PIPE_

R DESKEW_POINTER 0
TX... RX... RX... DE... RX...
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
LANE_SELECT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-24 Deskew Pointer. Indicates Deskew pointer of internal Deskew buffer of selected lane
DESKEW_POI
NTER
23-21 Reserved
20 PIPE:TxElecIdle. Indicates PIPE TXELECIDLE signal of selected lane number(LANE_SELECT). Note:

PIPE_TXELECI
DLE
19 PIPE:RxElecIdle. Indicates PIPE RXELECIDLE signal of selected lane number(LANE_SELECT). Note:

PIPE_RXELECI
DLE
18 PIPE:RxValid. Indicates PIPE RXVALID signal of selected lane number(LANE_SELECT). Note: This
PIPE_RXVALID
17 PIPE:Detect Lane. Indicates whether PHY indicates receiver detection or not on selected lane
PIPE_DETECT
_LANE
16 PIPE:RxPolarity. Indicates PIPE RXPOLARITY signal of selected lane number(LANE_SELECT). Note:

PIPE_RXPOLA
RITY
15-4 Reserved
3-0 Lane Select. Lane Select register for Silicon Debug Status Register of Layer1-PerLane. - 0x0: Lane0 -
0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note: This register field is sticky.
LANE_SELECT
3.8.95 Silicon Debug Status (Layer1 LTSSM) (SD_STATUS_L1LTSSM_REG)
Offset
Register Offset
SD_STATUS_L1LTSSM 20Ch
_REG
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R LTSSM_VARIABLE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LANE_ FRAMI
R 0 PIPE_POWER_DOWN FRAMING_ERR_PTR
RE... NG...
W W1C
Reset 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
Fields
Field Function
LTSSM Variable. Indicates internal LTSSM variables defined in the PCI Express Base
31-16
Specification. C-PCIe Mode: - 0: directed_speed_change - 1: changed_speed_recovery
LTSSM_VARIA - 2: successful_speed_negotiation - 3: upconfigure_capable; Set to '1' if both
BLE ports advertised the UpConfigure capability in the last Config.Complete. - 4:
select_deemphasis - 5: start_equalization_w_preset - 6: equalization_done_8GT_data_rate - 7:
equalization_done_16GT_data_rate - 15:8: idle_to_rlock_transitioned Note: This register field is sticky.
15 Lane Reversal Operation. Receiver detected lane reversal. This field is only valid in the L0 LTSSM state.
LANE_REVERS
AL
14-11 Reserved
10-8 PIPE:PowerDown. Indicates PIPE PowerDown signal. Note: This register field is sticky.
PIPE_POWER_
DOWN
7 Framing Error. Indicates Framing Error detection status.
FRAMING_ERR
6-0 First Framing Error Pointer

FRAMING_ERR Identifies the first Framing Error using the following encoding. The field contents are only valid value when
_PTR FRAMING_ERR =1.
• Received Unexpected Framing Token
— 01h: When non- STP/SDP/IDL Token was received and it was not in TLP/DLLP reception
— 02h: When current token was not a valid EDB token and previous token was an EDB. (128/256
bit controller only)

NXP Semiconductors
PCIe Controller
Field Function
— 03h: When SDP token was received but not expected. (128 bit & (x8 | x16) controller only)
— 04h: When STP token was received but not expected. (128 bit & (x8 | x16) controller only)
— 05h: When EDS token was expected but not received or whenever an EDS token was received
but not expected.
— 06h: When a framing error was detected in the deskew block while a packet has been in
progress in token_finder.
• Received Unexpected STP Token
— 11h: When Framing CRC in STP token did not match
— 12h: When Framing Parity in STP token did not match.
— 13h: When Framing TLP Length in STP token was smaller than 5 DWORDs.
• Received Unexpected Block
— 21h: When Receiving an OS Block following SDS in Datastream state
— 22h: When Data Block followed by OS Block different from SKP, EI, EIE in Datastream state
— 23h: When Block with an undefined Block Type in Datastream state
— 24h: When Data Stream without data over three cycles in Datastream state
— 25h: When OS Block during Data Stream in Datastream state
— 26h: When RxStatus Error was detected in Datastream state
— 27h: When Not all active lanes receiving SKP OS starting at same cycle time in SKPOS state
— 28h: When a 2-Block timeout occurs for SKP OS in SKPOS state
— 29h: When Receiving consecutive OS Blocks within a Data Stream in SKPOS state
— 2Ah: When Phy status error was detected in SKPOS state
— 2Bh: When Not all active lanes receiving EIOS starting at same cycle time in EIOS state
— 2Ch: When At least one Symbol from the first 4 Symbols is not EIOS Symbol in EIOS state
— 2Dh: When Not all active lanes receiving EIEOS starting at same cycle time in EIEOS state
— 2Eh: When Not full 16 eieos symbols are received in EIEOS state
All other values not listed above are reserved.
3.8.96 Silicon Debug Status (PM) (SD_STATUS_PM_REG)
Offset
Register Offset
SD_STATUS_PM_REG 210h
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 LATCHED_NFTS
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PME_
R 0 INTERNAL_PM_SSTATE 0 INTERNAL_PM_MSTATE
RES...
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-24 Reserved
23-16 Latched N_FTS. Indicates the value of N_FTS in the received TS Ordered Sets from the Link Partner
LATCHED_NFT
S
15-13 Reserved
PME Re-send flag. When the DUT sends a PM_PME message TLP, the DUT sets PME_Status bit.
12
If host software does not clear PME_Status bit for 100ms(+50%/-5%), the DUT resends the PM_PME
PME_RESEND Message. This bit indicates that a PM_PME was resent.
_FLAG
Internal PM State(Slave). Indicates internal state machine of Power Management Slave controller.
11-8
- 0h: S_IDLE - 1h: S_RESPOND_NAK - 2h: S_BLOCK_TLP - 3h: S_WAIT_LAST_TLP_ACK -
INTERNAL_PM 4h: S_WAIT_EIDLE - 5h: S_LINK_ENTR_L1 - 6h: S_L1 - 7h: S_L1_EXIT - 8h: S_L23RDY
_SSTATE - 9h: S_LINK_ENTR_L23 - Ah: S_L23RDY_WAIT4ALIVE - Bh: S_ACK_WAIT4IDLE - Ch:
S_WAIT_LAST_PMDLLP Note: This register field is sticky.
7-5 Reserved
Internal PM State(Master). Indicates internal state machine of Power Management Master controller. -
4-0
00h: IDLE - 01h: L0 - 02h: L0S - 03h: ENTER_L0S - 04h: L0S_EXIT - 05h: WAIT_PMCSR_CPL_SENT
INTERNAL_PM - 08h: L1 - 09h: L1_BLOCK_TLP - 0Ah: L1_WAIT_LAST_TLP_ACK - 0Bh: L1_WAIT_PMDLLP_ACK
_MSTATE - 0Ch: L1_LINK_ENTR_L1 - 0Dh: L1_EXIT - 0Fh: PREP_4L1 - 10h: L23_BLOCK_TLP - 11h:
L23_WAIT_LAST_TLP_ACK - 12h: L23_WAIT_PMDLLP_ACK - 13h: L23_ENTR_L23 - 14h: L23RDY -
15h: PREP_4L23 - 16h: L23RDY_WAIT4ALIVE - 17h: L0S_BLOCK_TLP - 18h: WAIT_LAST_PMDLLP -
19h: WAIT_DSTATE_UPDATE Note: This register field is sticky.

NXP Semiconductors
PCIe Controller
Offset
Register Offset
SD_STATUS_L2_REG 214h
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FC_INI FC_INI
R 0 DLCMSM RX_ACK_SEQ_NO
T2 T1
Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RX_ACK_SEQ_NO TX_TLP_SEQ_NO
Reset 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-28 Reserved
FC_INIT2
FC_INIT1
25-24 DLCMSM. Indicates the current DLCMSM. - 00b: DL_INACTIVE - 01b: DL_FC_INIT - 11b: DL_ACTIVE
DLCMSM
23-12 Tx Ack Sequence Number. Indicates ACKD_SEQ which is updated by receiving ACK/NAK DLLP. Note:
RX_ACK_SEQ_
NO
11-0 Tx Tlp Sequence Number. Indicates next transmit sequence number for transmit TLP. Note: This register
field is sticky.
TX_TLP_SEQ_
NO

NXP Semiconductors
PCIe Controller
3.8.98 Silicon Debug Status (Layer3 FC) (SD_STATUS_L3FC_REG)
Offset
Register Offset
SD_STATUS_L3FC_RE 218h
G
Function
The CREDIT_DATA[0/1] fields in this viewport register return the data for the VC and TLP Type selected by the following
fields: - CREDIT_SEL_VC - CREDIT_SEL_CREDIT_TYPE - CREDIT_SEL_TLP_TYPE - CREDIT_SEL_HD For more details,
see RAS Debug, Error Injection, and Statistics (DES)†.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R CREDIT_DATA1 CREDIT_DATA0
Reset 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CREDIT_DATA0 0 CREDI CREDIT_SEL_T CREDI

CREDIT_SEL_VC
W T_... LP_... T_...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
Credit Data1. Current FC credit data selected by the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE,

31-20
CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Allocated Value -
CREDIT_DATA Tx: Credit Limit Value. This value is valid when DLCMSM=0x3(DL_ACTIVE). Note: This register field is
1 sticky.
Credit Data0. Current FC credit data selected by the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE,

19-8
CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Received Value -
CREDIT_DATA Tx: Credit Consumed Value Note: This register field is sticky.
0
7 Reserved
6 Credit Select(HeaderData). This field in conjunction with the CREDIT_SEL_VC,

CREDIT_SEL_CREDIT_TYPE, and CREDIT_SEL_TLP_TYPE viewport-select fields determines that
CREDIT_SEL_ data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: Header Credit -
HD 0x1: Data Credit Note: This register field is sticky.
5-4 Credit Select(TLP Type). This field in conjunction with the CREDIT_SEL_VC,
CREDIT_SEL_CREDIT_TYPE, and CREDIT_SEL_HD viewport-select fields determines that data that

NXP Semiconductors
PCIe Controller
Field Function
CREDIT_SEL_T is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: Posted - 0x1: Non-Posted -
LP_TYPE 0x2: Completion Note: This register field is sticky.
3Credit Select(Credit Type). This field in conjunction with the CREDIT_SEL_VC,

CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields determines that data that is
CREDIT_SEL_ returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: Rx - 0x1: Tx Note: This register
CREDIT_TYPE field is sticky.
2-0 Credit Select(VC). This field in conjunction with the CREDIT_SEL_CREDIT_TYPE,

CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields determines that data that is
CREDIT_SEL_ returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: VC0 - 0x1: VC1 - 0x2: VC2 - .. -
VC 0x7: VC7 Note: This register field is sticky.
Offset
Register Offset
SD_STATUS_L3_REG 21Ch
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MFTLP
R 0 MFTLP_POINTER
_S...
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-8 Reserved

NXP Semiconductors
PCIe Controller
Field Function
7 Malformed TLP Status. Indicates malformed TLP has occurred.
MFTLP_STATU
S
First Malformed TLP Error Pointer. Indicates the element of the received first malformed TLP. This
6-0
pointer is validated by MFTLP_STATUS. - 01h: AtomicOp address alignment - 02h: AtomicOp operand
MFTLP_POINT - 03h: AtomicOp byte enable - 04h: TLP length miss match - 05h: Max payload size - 06h: Message
ER TLP without TC0 - 07h: Invalid TC - 08h: Unexpected route bit in Message TLP - 09h: Unexpected CRS
status in Completion TLP - 0Ah: Byte enable - 0Bh: Memory Address 4KB boundary - 0Ch: TLP prefix
rules - 0Dh: Translation request rules - 0Eh: Invalid TLP type - 0Fh: Completion rules - 7Fh: Application -
Else: Reserved Note: This register field is sticky.
Offset
Register Offset
G
Function
This is a viewport control register. Setting the EQ_RATE_SEL and EQ_LANE_SEL fields in this register determine the per-lane
Silicon Debug EQ Status data returned by the SD_EQ_STATUS[1/2/3] viewport registers. For more details, see RAS Debug,
Error Injection, and Statistics (DES)†.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R FOM_ 0 EVAL_INTERV
FOM_TARGET
W TAR... AL_T...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 EXT_EQ_TIME 0 EQ_R
EQ_LANE_SEL
W OUT ATE...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
FOM Target. Indicates figure of merit target criteria value of EQ Master(DSP in EQ Phase3/USP in
31-24
EQ Phase2). This field is only valid when GEN3_EQ_FB_MODE is 0001b(Figure Of Merit). Note: This
FOM_TARGET register field is sticky.
23 FOM Target Enable. Enables the FOM_TARGET fields. Note: This register field is sticky.
FOM_TARGET
_ENABLE
22-18 Reserved
Eval Interval Time. Indicates interval time of RxEqEval assertion. - 00: 500ns - 01: 1us - 10: 2us - 11:
17-16
4us This field is used for EQ Master(DSP in EQ Phase3/USP in EQ Phase2). Note: This register field is
EVAL_INTERV sticky.
AL_TIME
15-10 Reserved
9-8Extends EQ Phase2/3 Timeout. This field is used when the Ltssm is in Recovery.EQ2/3. When this field
is set, the value of EQ2/3 timeout is extended. EQ Master(DSP in EQ Phase3/USP in EQ Phase2). - 00:
EXT_EQ_TIME 24ms (default) - 01: 48ms (x2) - 10: 240ms (x10) - 11: No timeout EQ Slave(DSP in EQ Phase2/USP
OUT in EQ Phase3). - 00: 32ms (default) - 01: 56ms (32ms+24ms) - 10: 248ms (32ms +9*24ms) - 11: No
timeout Note: This register field is sticky.
7-5 Reserved
4 EQ Status Rate Select. Setting this field in conjunction with the EQ_LANE_SEL field determines the per-
EQ_RATE_SEL viewport registers. - 0x0: 8.0GT/s Speed - 0x1: 16.0GT/s Speed Note: This register field is sticky.
3-0EQ Status Lane Select. Setting this field in conjunction with the EQ_RATE_SEL field determines the per-
EQ_LANE_SEL viewport registers. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note: This register field is
sticky.
Offset
Register Offset
SD_EQ_CONTROL2_RE 22Ch
G
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 FORC FORC FORC 0 FORCE_LOCAL_RX_HI FORCE_LOCA

FORCE_LOCAL_TX_PRESET
W E_L... E_L... E_L... NT L_TX_...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R FORCE_LOCAL_TX_POST_CUR
FORCE_LOCAL_TX_CURSOR FORCE_LOCAL_TX_PRE_CURSOR
W SOR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31 Reserved
30 Force Local Transmitter Preset Enable. Enables the FORCE_LOCAL_TX_PRESET field. Note: This
FORCE_LOCA
L_TX_PRESET
_ENABLE
29 Force Local Receiver Preset Hint Enable. Enables the FORCE_LOCAL_RX_HINT field. Note: This
FORCE_LOCA
L_RX_HINT_EN
ABLE
Force Local Transmitter Coefficient Enable. Enables the following

28
fields: - FORCE_LOCAL_TX_PRE_CURSOR - FORCE_LOCAL_TX_CURSOR -
FORCE_LOCA FORCE_LOCAL_TX_POST_CURSOR Note: This register field is sticky.
L_TX_COEF_E
NABLE
27-24 Force Local Transmitter Preset. Indicates initial preset value of USP in EQ Slave(EQ Phase2) instead of
receiving EQ TS2. Note: This register field is sticky.
FORCE_LOCA
L_TX_PRESET
23-21 Reserved
20-18 Force Local Receiver Preset Hint. Indicates the RxPresetHint value of EQ Slave(DSP in EQ
Phase2/USP in EQ Phase3), instead of received or set value. Note: This register field is sticky.
FORCE_LOCA
L_RX_HINT

NXP Semiconductors
PCIe Controller
Field Function
Force Local Transmitter Post-Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ

17-12
FORCE_LOCA sticky.
L_TX_POST_C
URSOR
11-6 Force Local Transmitter Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in
EQ Phase3), instead of the value instructed from link partner. Note: This register field is sticky.
FORCE_LOCA
L_TX_CURSOR
5-0 Force Local Transmitter Pre-cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP
FORCE_LOCA
L_TX_PRE_CU
RSOR
Offset
Register Offset
G
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 FORC 0 FORCE_REMO
W E_R... TE_TX...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R FORCE_REMOTE_TX_POST_CU
FORCE_REMOTE_TX_CURSOR FORCE_REMOTE_TX_PRE_CURSOR
W RSOR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-29 Reserved
28 Force Remote Transmitter Coefficient Enable. Enables the following

fields: - FORCE_REMOTE_TX_PRE_CURSOR - FORCE_REMOTE_TX_CURSOR -
FORCE_REMO FORCE_REMOTE_TX_POST_CURSOR Note: This register field is sticky.
TE_TX_COEF_
ENABLE
27-18 Reserved
Force Remote Transmitter Post-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ

17-12
FORCE_REMO sticky.
TE_TX_POST_
CURSOR
11-6 Force Remote Transmitter Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP
FORCE_REMO
TE_TX_CURSO
R
5-0Force Remote Transmitter Pre-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ

FORCE_REMO sticky.
TE_TX_PRE_C
URSOR
Offset
Register Offset
Function
This viewport register returns the first of three words of Silicon Debug EQ Status data for the rate and lane selected by the
EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. The following fields are available when
Equalization finished unsuccessfully(EQ_CONVERGENCE_INFO=2). - EQ_RULEA_VIOLATION - EQ_RULEB_VIOLATION -
EQ_RULEC_VIOLATION - EQ_REJECT_EVENT For more details, see RAS Debug, Error Injection, and Statistics (DES)†.

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EQ_R EQ_R EQ_R EQ_R EQ_CONVERG EQ_S

R 0 0
EJE... ULE... ULE... ULE... ENCE_... EQU...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-8 Reserved
7 EQ Reject Event
EQ_REJECT_E Indicates that the controller receives two consecutive TS1 OS w/Reject=1b during EQ Master
VENT phase(DSP in EQ Phase3/USP in EQ Phase2). This bit is automatically cleared when the controller
starts EQ Master phase again. Note: This register field is sticky.
6 EQ Rule C Violation
EQ_RULEC_VI Indicates that coefficients rule C violation is detected in the values provided by PHY using direction
OLATION change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rule
C correspond to the rules c) from section "Rules for Transmitter Coefficents" in the PCI Express Base
Specification. This bit is automatically cleared when the controller starts EQ Master phase again. Note:
5 EQ Rule B Violation.
EQ_RULEB_VI Indicates that coefficients rule B violation is detected in the values provided by PHY using direction
OLATION change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules
B correspond to the rules b) from section "Rules for Transmitter Coefficents" in the PCI Express Base
4 EQ Rule A Violation
EQ_RULEA_VI Indicates that coefficients rule A violation is detected in the values provided by PHY using direction
OLATION change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules
A correspond to the rules a) from section "Rules for Transmitter Coefficents" in the PCI Express Base
3 Reserved

NXP Semiconductors
PCIe Controller
Field Function
2-1 EQ Convergence Info

EQ_CONVERG Indicates equalization convergence information. - 0x0: Equalization is not attempted - 0x1: Equalization
ENCE_INFO finished successfully - 0x2: Equalization finished unsuccessfully - 0x3: Reserved This bit is automatically
cleared when the controller starts EQ Master phase again. Note: This register field is sticky.
0 EQ Sequence
EQ_SEQUENC Indicates that the controller is starting the equalization sequence. Note: This register field is sticky.
E
Offset
Register Offset
SD_EQ_STATUS2_REG 23Ch
Function
This viewport register returns the second of three words of Silicon Debug EQ Status data for the rate and lane selected by the
†.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EQ_LOCAL_PO
R EQ_LOCAL_FOM_VALUE 0 EQ_LOCAL_RX_HINT
ST_C...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R EQ_LOCAL_POST_CURSOR EQ_LOCAL_CURSOR EQ_LOCAL_PRE_CURSOR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-24 EQ Local Figure of Merit. Indicates Local maximum Figure of Merit value. Note: This register field is
sticky.

NXP Semiconductors
PCIe Controller
Field Function
EQ_LOCAL_FO
M_VALUE
23-21 Reserved
20-18 EQ Local Receiver Preset Hint. Indicates Local Receiver Preset Hint value. Note: This register field is
sticky.
EQ_LOCAL_RX
_HINT
17-12 EQ Local Post-Cursor. Indicates Local post cursor coefficient value. Note: This register field is sticky.
EQ_LOCAL_PO
ST_CURSOR
11-6 EQ Local Cursor. Indicates Local cursor coefficient value. Note: This register field is sticky.
EQ_LOCAL_CU
RSOR
5-0 EQ Local Pre-Cursor. Indicates Local pre cursor coefficient value. Note: This register field is sticky.
EQ_LOCAL_PR
E_CURSOR
Offset
Register Offset
Function
This viewport register returns the third of three words of Silicon Debug EQ Status data for the rate and lane selected by the
†.

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EQ_REMOTE_
R 0 EQ_REMOTE_FS EQ_REMOTE_LF
POST_...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R EQ_REMOTE_POST_CURSOR EQ_REMOTE_CURSOR EQ_REMOTE_PRE_CURSOR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-30 Reserved
29-24 EQ Remote FS. Indicates Remote FS value. Note: This register field is sticky.
EQ_REMOTE_
FS
23-18 EQ Remote LF. Indicates Remote LF value. Note: This register field is sticky.
EQ_REMOTE_
LF
17-12 EQ Remote Post-Cursor. Indicates Remote post cursor coefficient value. Note: This register field is
sticky.
EQ_REMOTE_
POST_CURSO
R
11-6 EQ Remote Cursor. Indicates Remote cursor coefficient value. Note: This register field is sticky.
EQ_REMOTE_
CURSOR
5-0 EQ Remote Pre-Cursor. Indicates Remote pre cursor coefficient value. Note: This register field is sticky.
EQ_REMOTE_
PRE_CURSOR

NXP Semiconductors
PCIe Controller
3.8.106 PCIe Extended Capability ID, Capability Version And Next Capability Offset
(RASDP_EXT_CAP_HDR_OFF)
Offset
Register Offset
RASDP_EXT_CAP_HDR 258h
_OFF
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R NEXT_OFFSET CAP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ID
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1
Fields
Field Function
Next Capability Offset. For a description of this standard PCIe register, see the PCI Express
31-20
19-16 Capability Version. For a description of this standard PCIe register, see the PCI Express Specification.
CAP sticky.
15-0 PCI Express Extended Capability ID. For a description of this standard PCIe register, see the PCI
ID This register field is sticky.

NXP Semiconductors
PCIe Controller
3.8.107 Vendor Specific Header (RASDP_VENDOR_SPECIFIC_HDR_OFF)
Offset
Register Offset
RASDP_VENDOR_SPE 25Ch
CIFIC_HDR_OFF
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VSEC_ID
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Fields
Field Function
31-20 VSEC Length. For a description of this standard PCIe register, see the PCI Express Specification. Note:
VSEC_LENGT
H
19-16 VSEC Rev. For a description of this standard PCIe register, see the PCI Express Specification. Note:
VSEC_REV
15-0 VSEC ID. For a description of this standard PCIe register, see the PCI Express Specification. Note: This
VSEC_ID
3.8.108 ECC error correction control (RASDP_ERROR_PROT_CTRL_OFF)
Offset
Register Offset
RASDP_ERROR_PROT 260h
_CTRL_OFF

NXP Semiconductors
PCIe Controller
Function
Allows you to disable ECC error correction for RAMs and datapath. When the AXI Bridge Module is implemented and the
master / slave clocks are asynchronous to the PCIe native controller clock (core_clk), you must not write this register while
operations are in progress in the AXI master / slave interface.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-23 Reserved
22 Error correction disable for ADM Rx path. Note: This register field is sticky.
ERROR_PROT
_DISABLE_AD
M_RX
ERROR_PROT
_DISABLE_LAY
ER3_RX
ERROR_PROT
_DISABLE_LAY
ER2_RX
19 Error correction disable for DMA read engine. Note: This register field is sticky.
ERROR_PROT
_DISABLE_DM
A_READ
18 Error correction disable for AXI bridge inbound request path. Note: This register field is sticky.
ERROR_PROT
_DISABLE_AXI

NXP Semiconductors
PCIe Controller
Field Function
_BRIDGE_INB
OUND_REQUE
ST
17 Error correction disable for AXI bridge inbound completion composer. Does not disable the error
detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky.
ERROR_PROT
_DISABLE_AXI
_BRIDGE_INB
OUND_COMPL
ETION
16 Global error correction disable for all Rx layers. Note: This register field is sticky.
ERROR_PROT
_DISABLE_RX
15-7 Reserved
6 Error correction disable for Adm Tx path. Note: This register field is sticky.
ERROR_PROT
_DISABLE_AD
M_TX
ERROR_PROT
_DISABLE_LAY
ER3_TX
ERROR_PROT
_DISABLE_LAY
ER2_TX
3 Error correction disable for DMA write engine. Note: This register field is sticky.
ERROR_PROT
_DISABLE_DM
A_WRITE
2 Error correction disable for AXI bridge outbound request path. Note: This register field is sticky.
ERROR_PROT
_DISABLE_AXI
_BRIDGE_OUT
BOUND
1 Error correction disable for AXI bridge master completion buffer. Note: This register field is sticky.

NXP Semiconductors
PCIe Controller
Field Function
ERROR_PROT
_DISABLE_AXI
_BRIDGE_MAS
TER
0 Global error correction disable for all Tx layers. Does not disable the error detection reporting for 1-bit
and 2-bit ECC errors. Note: This register field is sticky.
ERROR_PROT
_DISABLE_TX
3.8.109 Corrected error (1-bit ECC) counter selection and control

Offset
Register Offset
ER_CTRL_OFF
Function
This is a viewport control register. Setting the CORR_COUNTER_SELECTION_REGION and
CORR_COUNTER_SELECTION fields in this register determine the counter data returned by the
RASDP_CORR_COUNT_REPORT_OFF viewport data register.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R CORR_COUNTER_SELECTION_ 0
CORR_COUNTER_SELECTION
W REGION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CORR
R 0 CORR 0
_CL...
_EN...
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Fields
Field Function
31-24 Counter selection. This field selects the counter ID (within the region defined
by CORR_COUNTER_SELECTION_REGION) whose contents can be read from the

NXP Semiconductors
PCIe Controller
Field Function
CORR_COUNT RASDP_CORR_COUNT_REPORT_OFF register. You can cycle this field value from 0 to 255 to access
ER_SELECTIO all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/
N DWC_pcie/latest/doc/RASDP_CheckPoints.pdf
Select correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3
23-20
CORR_COUNT select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion
ER_SELECTIO composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8:
N_REGION Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for
19-5 Reserved
4 Enable correctable errors counters. - 1: counters increment when the controller detects a correctable
error - 0: counters are frozen The counters are enabled by default.
CORR_EN_CO
UNTERS
3-1 Reserved
0 Clear all correctable error counters.
CORR_CLEAR
_COUNTERS
3.8.110 Corrected error (1-bit ECC) counter data (RASDP_CORR_COUNT_REPORT_OFF)
Offset
Register Offset
_REPORT_OFF
Function
This viewport register returns the counter data selected by the CORR_COUNTER_SELECTION_REGION and
CORR_COUNTER_SELECTION fields in the RASDP_CORR_COUNTER_CTRL_OFF register.

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CORR_COUNTER_SELECTED_R
R CORR_COUNTER_SELECTED 0
EGION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 CORR_COUNTER
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-24 Counter selection. Returns the value set in the CORR_COUNTER_SELECTION field of the
CORR_COUNT
ER_SELECTED
Selected correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for
23-20
CORR_COUNT - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound
ER_SELECTED completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path
_REGION - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select
19-8 Reserved
7-0 Current corrected error count for the selected counter.
CORR_COUNT
ER
3.8.111 Uncorrected error (2-bit ECC and parity) counter selection and control
(RASDP_UNCORR_COUNTER_CTRL_OFF)
Offset
Register Offset
RASDP_UNCORR_COU 26Ch
NTER_CTRL_OFF

NXP Semiconductors
PCIe Controller
Function
This is a viewport control register. Setting the UNCORR_COUNTER_SELECTION_REGION and
UNCORR_COUNTER_SELECTION fields in this register determine the counter data returned by the
RASDP_UNCORR_COUNT_REPORT_OFF viewport data register.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R UNCORR_COUNTER_SELECTIO 0
UNCORR_COUNTER_SELECTION
W N_REGION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UNCO
R 0 UNCO 0
RR_...
RR_...
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Fields
Field Function
31-24
by UNCORR_COUNTER_SELECTION_REGION) whose contents can be read from the
UNCORR_COU RASDP_UNCORR_COUNT_REPORT_OFF register. You can cycle this field value from 0 to 255 to
NTER_SELECT access all counters according to the detailed report of check points at http://www.synopsys.com/dw/
ION doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf
Select uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for
23-20
ION_REGION - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select
19-5 Reserved
4 Enable uncorrectable errors counters. - 1: enables the counters to increment on detected correctable
errors - 0: counters are frozen The counters are enabled by default.
UNCORR_EN_
COUNTERS
3-1 Reserved
0 Clear uncorrectable errors counters. When asserted causes all counters tracking the uncorrectable
errors to be cleared.
UNCORR_CLE
AR_COUNTER
S

NXP Semiconductors
PCIe Controller
3.8.112 Uncorrected error (2-bit ECC and parity) counter data

Offset
Register Offset
RASDP_UNCORR_COU 270h
NT_REPORT_OFF
Function
This viewport register returns the counter data selected by the UNCORR_COUNTER_SELECTION_REGION and
UNCORR_COUNTER_SELECTION fields in the RASDP_UNCORR_COUNTER_CTRL_OFF register.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UNCORR_COUNTER_SELECTE
R UNCORR_COUNTER_SELECTED 0
D_REGION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 UNCORR_COUNTER
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-24 Counter selection. Returns the value set in the UNCORR_COUNTER_SELECTION field of the
UNCORR_COU
NTER_SELECT
ED
Selected uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for
23-20
ED_REGION - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select
19-8 Reserved
7-0 Current uncorrected error count for the selected counter

NXP Semiconductors
PCIe Controller
Field Function
UNCORR_COU
NTER
3.8.113 Error injection control (RASDP_ERROR_INJ_CTRL_OFF)
Offset
Register Offset
RASDP_ERROR_INJ_C 274h
TRL_OFF
Function
Error injection control for the following features: - 1-bit or 2-bit injection - Continuous or fixed-number (n) injection modes -
Global enable/disable - Selectable location where injection occurs
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
ERROR_INJ_LOC
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 ERROR_INJ_T 0 ERRO
ERROR_INJ_COUNT
W YPE R_I...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-24 Reserved
23-16 Error injection location. Selects where error injection takes place. You can cycle this field value
from 0 to 255 to access all locations according to the detailed report of check points at http://
ERROR_INJ_L www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf
OC
15-8 Error injection count. - 0: errors are inserted in every TLP until you clear ERROR_INJ_EN. - 1: one errors
injected - 2: two errors injected - n: amount of errors injected
ERROR_INJ_C
OUNT

NXP Semiconductors
PCIe Controller
Field Function
7-6 Reserved
5-4 Error injection type: - 0: none - 1: 1-bit - 2: 2-bit
ERROR_INJ_T
YPE
3-1 Reserved
0 Error injection global enable. When set enables the error insertion logic.
ERROR_INJ_E
N
3.8.114 Corrected errors locations (RASDP_CORR_ERROR_LOCATION_OFF)
Offset
Register Offset
RASDP_CORR_ERROR 278h
_LOCATION_OFF
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R LOC_LAST_CORR_ERROR REG_LAST_CORR_ERROR 0
Reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R LOC_FIRST_CORR_ERROR REG_FIRST_CORR_ERROR 0
Reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
Location/ID of the last corrected error within the region defined by REG_LAST_CORR_ERROR. You can
31-24
cycle this field value from 0 to 255 to access all counters according to the detailed report of check points
LOC_LAST_CO at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf
RR_ERROR
Region of the last corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3
23-20
REG_LAST_CO select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion
RR_ERROR composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8:
19-16 Reserved
15-8 Location/ID of the first corrected error within the region defined by REG_FIRST_CORR_ERROR. You
can cycle this field value from 0 to 255 to access all counters according to the detailed report of check
LOC_FIRST_C points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf
ORR_ERROR
7-4Region of the first corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3
REG_FIRST_C select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion
ORR_ERROR composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8:
3-0 Reserved
3.8.115 Uncorrected errors locations (RASDP_UNCORR_ERROR_LOCATION_OFF)
Offset
Register Offset
RASDP_UNCORR_ERR 27Ch
OR_LOCATION_OFF
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R LOC_LAST_UNCORR_ERROR REG_LAST_UNCORR_ERROR 0
Reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R LOC_FIRST_UNCORR_ERROR REG_FIRST_UNCORR_ERROR 0
Reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0
Fields
Field Function
Location/ID of the last uncorrected error within the region defined by REG_LAST_UNCORR_ERROR.
31-24
LOC_LAST_UN check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf
CORR_ERROR
Region of the last uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for
23-20
REG_LAST_UN - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound
CORR_ERROR completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path
- 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select
19-16 Reserved
15-8 Location/ID of the first uncorrected error within the region defined by REG_FIRST_UNCORR_ERROR.
LOC_FIRST_U check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf
NCORR_ERRO
R
Region of the first uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for
7-4
REG_FIRST_U - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound
NCORR_ERRO completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path
R - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select
3-0 Reserved

NXP Semiconductors
PCIe Controller
3.8.116 RASDP error mode enable (RASDP_ERROR_MODE_EN_OFF)
Offset
Register Offset
_EN_OFF
Function
The controller enters RASDP error mode (if ERROR_MODE_EN =1) upon detection of the first uncorrectable error. During this
mode: - Rx TLPs that are forwarded to your application are not guaranteed to be correct; you must discard them. For more
details, see RAS data protection (DP)†.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 AUTO_ ERRO
W LI... R_M...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Fields
Field Function
31-2 Reserved
1 Write '1' to enable the controller to bring the link down when the controller enters RASDP error mode.
AUTO_LINK_D
OWN_EN
0 Write '1' to enable the controller enter RASDP error mode when it detects an uncorrectable error. Note:
ERROR_MODE
_EN

NXP Semiconductors
PCIe Controller
3.8.117 Exit RASDP error mode (RASDP_ERROR_MODE_CLEAR_OFF)
Offset
Register Offset
_CLEAR_OFF
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRO
R 0
R_M...
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-1 Reserved
0 Write '1' to take the controller out of RASDP error mode. The controller will then report uncorrectable
errors (through AER internal error reporting) and also stop nullifying/discarding TLPs.
ERROR_MODE
_CLEAR
3.8.118 RAM Address where a corrected error (1-bit ECC) has been detected
Offset
Register Offset
RASDP_RAM_ADDR_C 288h
ORR_ERROR_OFF

NXP Semiconductors
PCIe Controller
Function
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RAM_INDEX_CORR_ERROR 0 RAM_ADDR_CORR_ERROR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RAM_ADDR_CORR_ERROR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-28 RAM index where a corrected error (1-bit ECC) has been detected.
RAM_INDEX_C
ORR_ERROR
27 Reserved
26-0 RAM Address where a corrected error (1-bit ECC) has been detected.
RAM_ADDR_C
ORR_ERROR
3.8.119 RAM Address where an uncorrected error (2-bit ECC) has been detected
(RASDP_RAM_ADDR_UNCORR_ERROR_OFF)
Offset
Register Offset
RASDP_RAM_ADDR_U 28Ch
NCORR_ERROR_OFF
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RAM_INDEX_UNCORR_ERROR 0 RAM_ADDR_UNCORR_ERROR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RAM_ADDR_UNCORR_ERROR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-28 RAM index where an uncorrected error (2-bit ECC) has been detected.
RAM_INDEX_U
NCORR_ERRO
R
27 Reserved
26-0 RAM Address where an uncorrected error (2-bit ECC) has been detected.
RAM_ADDR_U
NCORR_ERRO
R
3.8.120 Ack Latency Timer and Replay Timer (ACK_LATENCY_TIMER_OFF)
Offset
Register Offset
ACK_LATENCY_TIMER 700h
_OFF

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
REPLAY_TIME_LIMIT
W
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ROUND_TRIP_LATENCY_TIME_LIMIT
W
1. When the chip resets, this field resets to 1846h. However, the field is not accessible until later, when the PCIe reset
finishes. At that moment, this field's value becomes C0h. Therefore, you can treat C0h as this register's usable reset value.
2. When the chip resets, this field resets to 817h. However, the field is not accessible until later, when the PCIe reset finishes.
At that moment, this field's value becomes 40h. Therefore, you can treat 40h as this register's usable reset value.
Fields
Field Function
Replay Timer Limit. The replay timer expires when it reaches this limit. The controller initiates a
31-16
replay upon reception of a NAK or when the replay timer expires. For more details, see "Transmit
REPLAY_TIME Replay". You can modify the effective timer limit with the TIMER_MOD_REPLAY_TIMER field of the
_LIMIT TIMER_CTRL_MAX_FUNC_NUM_OFF register. After reset, the controller updates the default according
to the Negotiated Link Width, Max_Payload_Size, and speed. The value is determined from Tables 3-4,
3-5, and 3-6 of the PCIe 3.0 specification. If there is a change in the payload size or link speed, the
controller will override any value that you have written to this register field, and reset the field back to the
specification-defined value. It will not change the value in the TIMER_MOD_REPLAY_TIMER field of the
TIMER_CTRL_MAX_FUNC_NUM_OFF register.
Ack Latency Timer Limit. The Ack latency timer expires when it reaches this limit. For more details, see
15-0
"Ack Scheduling". You can modify the effective timer limit with the TIMER_MOD_ACK_NAK field of the
ROUND_TRIP_ TIMER_CTRL_MAX_FUNC_NUM_OFF register. After reset, the controller updates the default according
LATENCY_TIM to the Negotiated Link Width, Max_Payload_Size, and speed. The value is determined from Tables 3-7,
E_LIMIT 3-8, and 3-9 of the PCIe 3.0 specification. The limit must reflect the round trip latency from requester to
completer. If there is a change in the payload size or link width, the controller will override any value that
you have written to this register field, and reset the field back to the specification-defined value. It will
not change the value in the TIMER_MOD_ACK_NAK field of the TIMER_CTRL_MAX_FUNC_NUM_OFF
register.
3.8.121 Vendor Specific DLLP (VENDOR_SPEC_DLLP_OFF)
Offset
Register Offset
VENDOR_SPEC_DLLP_ 704h
OFF

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
VENDOR_SPEC_DLLP
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
VENDOR_SPEC_DLLP
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Fields
Field Function
Vendor Specific DLLP Register. Used to send a specific PCI Express DLLP. Your application
31-0
writes the 8-bit DLLP Type and 24-bits of Payload data into this register, then sets the field
VENDOR_SPE VENDOR_SPECIFIC_DLLP_REQ of PORT_LINK_CTRL_OFF to send the DLLP. - [7:0] = Type - [31:8]
C_DLLP = Payload (24 bits) The dllp type is in bits [7:0] while the remainder is the vendor defined payload. Note:
3.8.122 Port Force Link (PORT_FORCE_OFF)
Offset
Register Offset
PORT_FORCE_OFF 708h
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 DO_D 0
LINK_STATE
W ESK...
Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FORC
R 0
E_EN FORCED_LTSSM LINK_NUM
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-24 Reserved
23Use the transitions from TS2 to Logical Idle Symbol, SKP OS to Logical Idle Symbol, and FTS Sequence
to SKP OS to do deskew for SRIS instead of using received SKP OS if DO_DESKEW_FOR_SRIS is set
DO_DESKEW_ to 1. Note: This register field is sticky.
FOR_SRIS
22 Reserved
21-16 Forced LTSSM State. The LTSSM state that the controller is forced to when you set the FORCE_EN
bit (Force Link). LTSSM state encoding is defined by the lts_state variable in workspace/src/Layer1/
LINK_STATE smlh_ltssm.v. Note: This register field is sticky.
15 Force Link. The controller supports a testing and debug capability to allow your software to force
the LTSSM state machine into a specific state, and to force the controller to transmit a specific Link
FORCE_EN Command. Asserting this bit triggers the following actions: - Forces the LTSSM to the state specified by
the Forced LTSSM State field. - Forces the controller to transmit the command specified by the Forced
Link Command field. This is a self-clearing register field. Reading from this register field always returns a
"0".
14-12 Reserved
Forced Link Command. The link command that the controller is forced to transmit when you set
11-8
FORCE_EN bit (Force Link). Link command encoding is defined by the ltssm_cmd variable in
FORCED_LTSS workspace/src/Layer1/smlh_ltssm.v. Note: This register field is sticky.
M
7-0 Link Number. Not used for endpoint. Note: This register field is sticky.
LINK_NUM
3.8.123 Ack Frequency and L0-L1 ASPM Control (ACK_F_ASPM_CTRL_OFF)
Offset
Register Offset
ACK_F_ASPM_CTRL_O 70Ch
FF

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 ENTE L1_ENTRANCE_LATEN L0S_ENTRANCE_LATE COMMON_CLK_N_FTS
W R_A... CY NCY
Reset 0 0 0 1 1 0 1 1 1 0 1 1 0 1 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ACK_N_FTS ACK_FREQ
W
Reset 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31 Reserved
ASPM L1 Entry Control. - 1: Core enters ASPM L1 after a period in which it has been idle. - 0: Core
30
enters ASPM L1 only after idle period during which both receive and transmit are in L0s. Note: This
ENTER_ASPM register field is sticky.
L1 Entrance Latency. Value range is: - 000: 1 us - 001: 2 us - 010: 4 us - 011: 8 us - 100: 16 us - 101: 32
29-27
us - 110 or 111: 64 us Note: Programming this timer with a value greater that 32us has no effect unless
L1_ENTRANCE extended sync is used, or all of the credits are infinite. Note: This register field is sticky.
_LATENCY
26-24 L0s Entrance Latency. Values correspond to: - 000: 1 us - 001: 2 us - 010: 3 us - 011: 4 us - 100: 5 us -
101: 6 us - 110 or 111: 7 us Note: This register field is sticky.
L0S_ENTRANC
E_LATENCY
23-16 Common Clock N_FTS

COMMON_CLK This is the N_FTS when common clock is used.
_N_FTS
The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0.
The maximum number of FTS ordered-sets that a component can request is 255.
The controller does not support a value of zero; a value of zero can cause the LTSSM to go into the recovery
state when exiting from L0s.
- Wire: R
15-8 N_FTS. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from
L0s to L0. The maximum number of FTS ordered-sets that a component can request is 255. The
ACK_N_FTS controller does not support a value of zero; a value of zero can cause the LTSSM to go into the recovery
state when exiting from L0s. Note: This register field is sticky.
7-0 Ack Frequency. The controller accumulates the number of pending ACKs specified here (up to 255)
before sending an ACK DLLP. - 0: Indicates that this Ack frequency control feature is turned off. The
ACK_FREQ controller schedules a low-priority ACK DLLP for every TLP that it receives. - 1-255: Indicates that the

NXP Semiconductors
PCIe Controller
Field Function
controller will schedule a high-priority ACK after receiving this number of TLPs. It might schedule the
ACK before receiving this number of TLPs, but never later. For a typical system, you do not have to
modify the default setting. For more details, see "ACK/NAK Scheduling". Note: This register field is
sticky.
3.8.124 Port Link Control (PORT_LINK_CTRL_OFF)
Offset
Register Offset
PORT_LINK_CTRL_OFF 710h
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 TRAN EXTE CORR BEAC 0

LINK_CAPABLE
W SMI... NDE... UPT... ON_...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VEND
R 0 FAST_ LINK_ DLL_LI 0 RESE LOOP SCRA
LINK_RATE OR_...
LI... DI... N... T_A... BAC... MBL...
W W1C
Reset 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0
Fields
Field Function
31-28 Reserved
27 TRANSMIT_LANE_REVERSALE_ENABLE is an internally reserved field. Do not use. Note: This register

field is sticky.
TRANSMIT_LA
NE_REVERSAL
E_ENABLE
26 EXTENDED_SYNCH is an internally reserved field. Do not use. Note: This register field is sticky.
EXTENDED_S
YNCH
25 CORRUPT_LCRC_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky.

NXP Semiconductors
PCIe Controller
Field Function
CORRUPT_LC
RC_ENABLE
24 BEACON_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky.
BEACON_ENA
BLE
23-22 Reserved
21-16 Link Mode Enable

LINK_CAPABL Sets the number of lanes in the link that you want to connect to the link partner. When you have unused
E lanes in your system, then you must change the value in this register to reflect the number of lanes. You must
also change the value in the "Predetermined Number of Lanes" field of the "Link Width and Speed Change
Control Register". For more information, see "How to Tie Off Unused Lanes". For information on upsizing
and downsizing the link width, see "Link Establishment".
• 000001: x1
• 000011: x2
• 000111: x4
• 001111: x8
• 011111: x16
• 111111: x32 (not supported)
15-12 Reserved
11-8 LINK_RATE is an internally reserved field. Do not use. Note: This register field is sticky.
LINK_RATE
7 Fast Link Mode. Sets all internal LTSSM millisecond timers to Fast Mode for speeding up simulation.
Forces the LTSSM training (link initialization) to use shorter time-outs and to link up faster. The
FAST_LINK_M default scaling factor can be changed using the DEFAULT_FAST_LINK_SCALING_FACTOR parameter
ODE or through the FAST_LINK_SCALING_FACTOR field in the TIMER_CTRL_MAX_FUNC_NUM_OFF
register. Fast Link Mode can also be activated by setting the diag_ctrl_bus[2] pin to '1'. For more details,
see the "Fast Link Simulation Mode" section in the "Integrating the Core with the PHY or Application RTL
or Verification IP" chapter of the User Guide. Note: This register field is sticky.
6 LINK_DISABLE is an internally reserved field. Do not use. Note: This register field is sticky.
LINK_DISABLE
5 DLL Link Enable. Enables link initialization. When DLL Link Enable =0, the controller does not transmit
InitFC DLLPs and does not establish a link. Note: This register field is sticky.
DLL_LINK_EN

NXP Semiconductors
PCIe Controller
Field Function
4 Reserved
3 Reset Assert. Triggers a recovery and forces the LTSSM to the hot reset state (downstream port only).
RESET_ASSER
T
2 Loopback Enable. Turns on loopback. For more details, see "Loopback". Note: This register field is
sticky.
LOOPBACK_E
NABLE
1 Scramble Disable. Turns off data scrambling. Note: This register field is sticky.
SCRAMBLE_DI
SABLE
0 Vendor Specific DLLP Request. When software writes a '1' to this bit, the controller transmits the
DLLP contained in the VENDOR_SPEC_DLLP field of VENDOR_SPEC_DLLP_OFF. Reading from this
VENDOR_SPE self-clearing register field always returns a '0'.
CIFIC_DLLP_R
EQ
3.8.125 Lane Skew (LANE_SKEW_OFF)
Offset
Register Offset
LANE_SKEW_OFF 714h
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R DISAB GEN3 ACK_ FLOW

IMPLEMENT_NUM_LANES INSERT_LANE_SKEW
W LE... 4_E... NAK... _CT...
Reset 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
INSERT_LANE_SKEW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31 Disable Lane-to-Lane Deskew. Causes the controller to disable the internal Lane-to-Lane deskew logic.
DISABLE_LAN
E_TO_LANE_D
ESKEW
Implementation-specific Number of Lanes. Set the implementation-specific number of lanes. Allowed

30-27
values are: - 4'b0000: 1 lane - 4'b0001: 2 lanes - 4'b0011: 4 lanes - 4'b0111: 8 lanes - 4'b1111: 16 lanes
IMPLEMENT_N The number of lanes to be used when in Loopback Master. The number of lanes programmed must be
UM_LANES equal to or less than the valid number of lanes set in LINK_CAPABLE field. You must configure this field
before initiating Loopback by writing in the LOOPBACK_ENABLE field. The controller will transition from
Loopback.Entry to Loopback.Active after receiving two consecutive TS1 Ordered Sets with the Loopback
bit asserted on the implementation specific number of lanes configured in this field. Note: This register
field is sticky.
26 Selects Elasticity Buffer operating mode in Gen3 or Gen4 rate: 0: Nominal Half Full Buffer mode 1:
Nominal Empty Buffer Mode This register bit only affects Gen3 or Gen4 operating rate. For Gen1 or
GEN34_ELASTI Gen2 operating rate the Elasticity Buffer operating mode is always the Nominal Half Full Buffer mode.
C_BUFFER_M Note: This register field is sticky.
ODE
25 Ack/Nak Disable. Prevents the controller from sending ACK and NAK DLLPs. Note: This register field is
sticky.
ACK_NAK_DIS
ABLE
24 Flow Control Disable. Prevents the controller from sending FC DLLPs. Note: This register field is sticky.
FLOW_CTRL_D
ISABLE
23-0 INSERT_LANE_SKEW is an internally reserved field. Do not use. Note: This register field is sticky.
INSERT_LANE
_SKEW
3.8.126 Timer Control and Max Function Number (TIMER_CTRL_MAX_FUNC_NUM_OFF)
Offset
Register Offset
TIMER_CTRL_MAX_FU 718h
NC_NUM_OFF

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 FAST_LINK_SC TIMER_MOD_REPLAY_
UPDATE_FREQ_TIMER TIMER_MOD_ACK_NAK
W ALI... TIMER
Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R TIMER_MOD_R 0
MAX_FUNC_NUM
W EPLA...
Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31 Reserved
Fast Link Timer Scaling Factor. Sets the scaling factor of LTSSM timer when FAST_LINK_MODE field in
30-29
PORT_LINK_CTRL_OFF is set to '1'. - 0: Scaling Factor is 1024 (1ms is 1us) - 1: Scaling Factor is 256
FAST_LINK_SC (1ms is 4us) - 2: Scaling Factor is 64 (1ms is 16us) - 3: Scaling Factor is 16 (1ms is 64us) Default is set
ALING_FACTO by the hidden configuration parameter DEFAULT_FAST_LINK_SCALING_FACTOR which defaults to '0'.
R Note: This register field is sticky.
28-24 UPDATE_FREQ_TIMER is an internally reserved field. Do not use. Note: This register field is sticky.
UPDATE_FRE
Q_TIMER
Ack Latency Timer Modifier. Increases the timer value for the Ack latency timer in increments of 64
23-19
clock cycles. A value of "0" represents no modification to the timer value. For more details, see the
TIMER_MOD_A ROUND_TRIP_LATENCY_TIME_LIMIT field of the ACK_LATENCY_TIMER_OFF register. Note: This
CK_NAK register field is sticky.
18-14 Replay timer limit modifier

TIMER_MOD_R Increases the time-out value for the replay timer in increments of 64 clock cycles at Gen1 or Gen2 speed,
EPLAY_TIMER and in increments of 256 clock cycles at Gen3 speed. A value of "0" represents no modification to the timer
limit. For more details, see the REPLAY_TIME_LIMIT field of the ACK_LATENCY_TIMER_OFF register. At
Gen3 speed, the controller automatically changes the value of this field to DEFAULT_GEN3_REPLAY_ADJ.
13-8 Reserved
7-0 Maximum function number that can be used in a request. Configuration requests targeted at function
numbers above this value are returned with UR (unsupported request). Note: This register field is sticky.
MAX_FUNC_N
UM

NXP Semiconductors
PCIe Controller
3.8.127 Symbol Timer and Filter Mask 1 (SYMBOL_TIMER_FILTER_1_OFF)
Offset
Register Offset
SYMBOL_TIMER_FILTE 71Ch
R_1_OFF
Function
Modifies the RADM filtering and error handling rules. For more details, see the following table and Receive filtering†. In each
case, '0' applies the associated filtering rule and '1' masks the associated filtering rule.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MASK_RADM_1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DISAB
EIDLE_TIMER SKP_INT_VAL
W LE...
Reset 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0
Fields
Field Function
31-16 Filter Mask 1

15 Disable FC Watchdog Timer. Note: This register field is sticky.
DISABLE_FC_
WD_TIMER
14-11 EIDLE_TIMER is an internally reserved field. Do not use. Note: This register field is sticky.
EIDLE_TIMER
10-0 SKP Interval Value. The number of symbol times to wait between transmitting SKP ordered sets. Note
that the controller actually waits the number of symbol times in this register plus 1 between transmitting
SKP_INT_VAL SKP ordered sets. Your application must program this register accordingly. For example, if 1536 were
programmed into this register (in a 250 MHz controller), then the controller actually transmits SKP
ordered sets once every 1537 symbol times. The value programmed to this register is actually clock
ticks and not symbol times. In a 125 MHz controller, programming the value programmed to this register

NXP Semiconductors
PCIe Controller
Field Function
should be scaled down by a factor of 2 (because one clock tick = two symbol times in this case). Note:
This value is not used at Gen3 speed; the skip interval is hardcoded to 370 blocks. Note: This register
field is sticky.
3.8.128 Filter Mask 2 (FILTER_MASK_2_OFF)
Offset
Register Offset
FILTER_MASK_2_OFF 720h
Function
Modifies the RADM filtering and error handling rules. For more details, see Receive filtering†. In each case, '0' applies the
associated filtering rule and '1' masks the associated filtering rule.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MASK_RADM_2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MASK_RADM_2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0 Filter Mask 2


NXP Semiconductors
PCIe Controller
3.8.129 AMBA Multiple Outbound Decomposed NP SubRequests Control

Offset
Register Offset
AMBA_MUL_OB_DECO 724h
MP_NP_SUB_REQ_CTR
L_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 OB_R
W D_S...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Fields
Field Function
31-1 Reserved
0 Enable AMBA Multiple Outbound Decomposed NP SubRequests

OB_RD_SPLIT_ This bit when set to "0" disables the possibility of having multiple outstanding non-posted requests
BURST_EN that were derived from decomposition of an outbound AMBA request. You should not clear
this register unless your application master is requesting an amount of read data greater than
Max_Read_Request_Size, and the remote device (or switch) is reordering completions that have
different tags. Note: The access attributes of this field are as follows: - Wire: No access. Note: This
Offset
Register Offset
PL_DEBUG0_OFF 728h

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R DEB_REG_0
Reset 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DEB_REG_0
Reset 1 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0
Fields
Field Function
31-0 The bits in this field have the following meaning:

DEB_REG_0 Bits 31:26: Reserved
Bit 25: Receiver is receiving logical idle
Bit 24: 2n symbol is also idle (16bit PHY interface only)
Bits 23:8: PIPE transmit data
Bits 7:6: PIPE transmit K indication
Bits 5:0: LTSSM current state
Offset
Register Offset
PL_DEBUG1_OFF 72Ch
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R DEB_REG_1
Reset 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DEB_REG_1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-0 The bits in this field have the following meaning:

DEB_REG_1 Bit 31: Scrambling disabled for the link
Bit 30: TSSM in DISABLE state; link inoperable
Bit 29: LTSSM performing link training
Bit 28: LTSSM is in Polling.Configuration state
Bit 27: LTSSM-negotiated link reset
Bit 22: Reserved
Bit 21: PIPE transmit electrical idle request
Bit 20: PIPE transmit compliance request
Bit 19: Application request to initiate training reset
Bits 18:6: Reserved
Bit 5: A skip ordered set has been transmitted
Bit 4: LTSSM reports PHY link up or LTSSM is in Loopback.Active for Loopback Master
Bits 3:0: Reserved
3.8.132 Transmit Posted FC Credit Status (TX_P_FC_CREDIT_STATUS_OFF)
Offset
Register Offset
TX_P_FC_CREDIT_STA 730h
TUS_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 TX_P_HEADER_FC_CREDIT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R TX_P_HEADER_FC_CREDIT TX_P_DATA_FC_CREDIT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-20 Reserved
Transmit Posted Header FC Credits. The posted Header credits advertised by the receiver at the
19-12
other end of the link, updated with each UpdateFC DLLP. Default value depends on the number
TX_P_HEADER of advertised credits for header and data [12'b0, xtlh_xadm_ph_cdts, xtlh_xadm_pd_cdts]; When the
[12'b0, 8'hFF, 12'hFFF].
Transmit Posted Data FC Credits. The posted Data credits advertised by the receiver at the other end of
11-0
the link, updated with each UpdateFC DLLP. Default value depends on the number of advertised credits
TX_P_DATA_F for header and data [12'b0, xtlh_xadm_ph_cdts, xtlh_xadm_pd_cdts]; When the number of advertised
C_CREDIT completion credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].
3.8.133 Transmit Non-Posted FC Credit Status (TX_NP_FC_CREDIT_STATUS_OFF)
Offset
Register Offset
TX_NP_FC_CREDIT_ST 734h
ATUS_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 TX_NP_HEADER_FC_CREDIT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R TX_NP_HEADER_FC_CREDIT TX_NP_DATA_FC_CREDIT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-20 Reserved
19-12 Transmit Non-Posted Header FC Credits. The non-posted Header credits advertised by the receiver at

NXP Semiconductors
PCIe Controller
Field Function
TX_NP_HEADE of advertised credits for header and data [12'b0, xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts]; When the
R_FC_CREDIT number of advertised completion credits (both header and data) are infinite, then the default would be
[12'b0, 8'hFF, 12'hFFF].
Transmit Non-Posted Data FC Credits. The non-posted Data credits advertised by the receiver at the
11-0
TX_NP_DATA_ advertised credits for header and data [12'b0, xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts]; When the
FC_CREDIT number of advertised completion credits (both header and data) are infinite, then the default would be
[12'b0, 8'hFF, 12'hFFF].
3.8.134 Transmit Completion FC Credit Status (TX_CPL_FC_CREDIT_STATUS_OFF)
Offset
Register Offset
TX_CPL_FC_CREDIT_S 738h
TATUS_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 TX_CPL_HEADER_FC_CREDIT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R TX_CPL_HEADER_FC_CREDIT TX_CPL_DATA_FC_CREDIT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-20 Reserved
Transmit Completion Header FC Credits. The Completion Header credits advertised by the receiver at
19-12
TX_CPL_HEAD of advertised credits for header and data [12'b0, xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts]; When the
ER_FC_CREDI number of advertised completion credits (both header and data) are infinite, then the default would be
T [12'b0, 8'hFF, 12'hFFF].

NXP Semiconductors
PCIe Controller
Field Function
Transmit Completion Data FC Credits. The Completion Data credits advertised by the receiver at the
11-0
TX_CPL_DATA advertised credits for header and data [12'b0, xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts]; When the
[12'b0, 8'hFF, 12'hFFF].
3.8.135 Queue Status (QUEUE_STATUS_OFF)
Offset
Register Offset
QUEUE_STATUS_OFF 73Ch
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R TIMER 0
TIMER_MOD_FLOW_CONTROL
W _M...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX_SE RX_SE RX_SE RX_Q RX_Q TX_RE RX_TL

R 0
RI... RI... RI... UEU... UEU... TR... P_...
W W1C W1C W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
FC Latency Timer Override Enable. When this bit is set, the value from the "FC Latency Timer Override
31
Value" field in this register will override the FC latency timer value that the controller calculates according
TIMER_MOD_F to the PCIe specification. Note: This register field is sticky.
LOW_CONTRO
L_EN
30-29 Reserved
FC Latency Timer Override Value. When you set the "FC Latency Timer Override Enable" in this register,
28-16
the value in this field will override the FC latency timer value that the controller calculates according to
TIMER_MOD_F the PCIe specification. For more details, see "Flow Control". Note: This register field is sticky.
LOW_CONTRO
L

NXP Semiconductors
PCIe Controller
Field Function
15 Receive Serialization Read Error. Indicates the serialization queue has attempted to read an incorrectly
formatted TLP.
RX_SERIALIZA
TION_Q_READ
_ERR
14 Receive Serialization Queue Write Error. Indicates insufficient buffer space available to write to the
serialization queue.
RX_SERIALIZA
TION_Q_WRIT
E_ERR
13 Receive Serialization Queue Not Empty. Indicates there is data in the serialization queue.
RX_SERIALIZA
TION_Q_NON_
EMPTY
12-4 Reserved
3 Receive Credit Queue Overflow. Indicates insufficient buffer space available to write to the P/NP/CPL
credit queue.
RX_QUEUE_O
VERFLOW
2 Receive Credit Queue Not Empty. Indicates there is data in one or more of the receive buffers.
RX_QUEUE_N
ON_EMPTY
1 Transmit Retry Buffer Not Empty. Indicates that there is data in the transmit retry buffer.
TX_RETRY_BU
FFER_NE
0 Received TLP FC Credits Not Returned. Indicates that the controller has received a TLP but has not yet
sent an UpdateFC DLLP indicating that the credits for that TLP have been restored by the receiver at the
RX_TLP_FC_C other end of the link.
REDIT_NON_R
ETURN
Offset
Register Offset

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
Fields
Field Function
31-24 WRR Weight for VC3. Note: The access attributes of this field are as follows: - Wire: No access.
WRR_WEIGHT
_VC_3
WRR_WEIGHT
_VC_2
WRR_WEIGHT
_VC_1
WRR_WEIGHT
_VC_0
Offset
Register Offset

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
WRR_WEIGHT
_VC_7
WRR_WEIGHT
_VC_6
WRR_WEIGHT
_VC_5
WRR_WEIGHT
_VC_4
3.8.138 Segmented-Buffer VC0 Posted Receive Queue Control (VC0_P_RX_Q_CTRL_OFF)
Offset
Register Offset
VC0_P_RX_Q_CTRL_O 748h
FF

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R VC_O TLP_T VC0_P_DATA_ VC0_P_HDR_S RESE VC0_P_HEADER_CREDIT

RESERVED5 VC0_P_TLP_Q_MODE
W RDE... YP... SCALE CALE RVE...
Reset 0 1 0 0 0 1 0 1 0 0 1 0 0 0 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VC0_P_HEADER_CREDIT VC0_P_DATA_CREDIT
Reset 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0
Fields
Field Function
31 VC Ordering for Receive Queues. Determines the VC ordering rule for the receive queues, used only in
the segmented-buffer configuration: - 1: Strict ordering, higher numbered VCs have higher priority - 0:
VC_ORDERIN Round robin Note: This register field is sticky.
G_RX_Q
TLP Type Ordering for VC0. Determines the TLP type ordering rule for VC0 receive queues, used only in
30
the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted,
TLP_TYPE_OR completion, then non-posted Note: This register field is sticky.
DERING_VC0
RESERVED5
27-26 VC0 Scale Posted Data Credites. Note: This register field is sticky.
VC0_P_DATA_
SCALE
25-24 VC0 Scale Posted Header Credites. Note: This register field is sticky.
VC0_P_HDR_S
CALE
VC0_P_TLP_Q_
MODE
RESERVED4
VC0 Posted Header Credits. The number of initial posted header credits for VC0, used only in the
19-12
segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No
VC0_P_HEADE access. Note: This register field is sticky.
R_CREDIT

NXP Semiconductors
PCIe Controller
Field Function
VC0 Posted Data Credits. The number of initial posted data credits for VC0, used only in the segmented-
11-0
buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. Note: This
VC0_P_DATA_ register field is sticky.
CREDIT
3.8.139 Segmented-Buffer VC0 Non-Posted Receive Queue Control (VC0_NP_RX_Q_CTRL_OFF)
Offset
Register Offset
VC0_NP_RX_Q_CTRL_ 74Ch
OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R VC0_NP_DATA VC0_NP_HDR_ RESE VC0_NP_HEADER_CREDIT

RESERVED7 VC0_NP_TLP_Q_MODE
W _SCA... SCALE RVE...
Reset 0 0 0 0 0 1 0 1 0 0 1 0 0 0 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VC0_NP_HEADER_CREDIT VC0_NP_DATA_CREDIT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0
Fields
Field Function
RESERVED7
27-26 VC0 Scale Non-Posted Data Credites. Note: This register field is sticky.
VC0_NP_DATA
_SCALE
25-24 VC0 Scale Non-Posted Header Credites. Note: This register field is sticky.
VC0_NP_HDR_
SCALE

NXP Semiconductors
PCIe Controller
Field Function
VC0_NP_TLP_
Q_MODE
RESERVED6
VC0 Non-Posted Header Credits. The number of initial non-posted header credits for VC0, used only in
19-12
the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No
VC0_NP_HEAD access. Note: This register field is sticky.
ER_CREDIT
VC0 Non-Posted Data Credits. The number of initial non-posted data credits for VC0, used only in
11-0
VC0_NP_DATA access. Note: This register field is sticky.
_CREDIT
3.8.140 Segmented-Buffer VC0 Completion Receive Queue Control (VC0_CPL_RX_Q_CTRL_OFF)
Offset
Register Offset
VC0_CPL_RX_Q_CTRL_ 750h
OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R VC0_CPL_DAT VC0_CPL_HDR VC0_CPL_TLP_Q_MOD RESE VC0_CPL_HEADER_CREDIT

RESERVED9
W A_SC... _SCA... E RVE...
Reset 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VC0_CPL_HEADER_CREDIT VC0_CPL_DATA_CREDIT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
RESERVED9

NXP Semiconductors
PCIe Controller
Field Function
27-26 VC0 Scale CPL Data Credites. Note: This register field is sticky.
VC0_CPL_DAT
A_SCALE
25-24 VC0 Scale CPL Header Credites. Note: This register field is sticky.
VC0_CPL_HDR
_SCALE
VC0_CPL_TLP_
Q_MODE
RESERVED8
VC0 Completion Header Credits. The number of initial Completion header credits for VC0, used only in
19-12
VC0_CPL_HEA access. Note: This register field is sticky.
DER_CREDIT
VC0 Completion Data Credits. The number of initial Completion data credits for VC0, used only in
11-0
VC0_CPL_DAT access. Note: This register field is sticky.
A_CREDIT
3.8.141 Link Width And Speed Change Control (GEN2_CTRL_OFF)
Offset
Register Offset
GEN2_CTRL_OFF 80Ch
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 GEN1_ SEL_D CONFI CONFI DIREC AUTO
W EI... EE... G_... G_... T_... _LA...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
PRE_DET_LANE NUM_OF_LANES FAST_TRAINING_SEQ
W
Reset 0 0 0 0 0 0 1 0 1 0 1 1 0 1 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-22 Reserved
21 Electrical Idle Inference Mode at Gen1 Rate. Programmable mode to determine inferred electrical idle
(EI) in Recovery.Speed or Loopback.Active (as slave) state at Gen1 speed by looking for a "1" value
GEN1_EI_INFE on RxElecIdle instead of looking for a "0" on RxValid. If the PHY fails to deassert the RxValid signal
RENCE in Recovery.Speed or Loopback.Active (because of corrupted EIOS for example), then EI cannot be
inferred successfully in the controller by just detecting the condition RxValid=0. - 0: Use RxElecIdle
signal to infer Electrical Idle - 1: Use RxValid signal to infer Electrical Idle Note: This register field is
sticky.
20 Used to set the de-emphasis level for upstream ports. This bit selects the level of de-emphasis the link
operates at. - 0: -6 dB - 1: -3.5 dB Note: The access attributes of this field are as follows: - Wire: No
SEL_DEEMPH access. Note: This register field is sticky.
ASIS
19 Config Tx Compliance Receive Bit. When set to 1, signals LTSSM to transmit TS ordered sets with the
compliance receive bit assert (equal to "1"). Note: The access attributes of this field are as follows: -
CONFIG_TX_C Wire: No access. Note: This register field is sticky.
OMP_RX
18 Config PHY Tx Swing. Controls the PHY transmitter voltage swing level. The controller drives the
mac_phy_txswing output from this register bit field. - 0: Full Swing - 1: Low Swing Note: The access
CONFIG_PHY_ attributes of this field are as follows: - Wire: No access. Note: This register field is sticky.
TX_CHANGE
17 Directed Speed Change. Writing "1" to this field instructs the LTSSM to initiate a speed change
to Gen2 or Gen3 after the link is initialized at Gen1 speed. When the speed change occurs, the
DIRECT_SPEE controller will clear the contents of this field; and a read to this field by your software will return
D_CHANGE a "0". To manually initiate the speed change: - Write to LINK_CONTROL2_LINK_STATUS2_REG .
PCIE_CAP_TARGET_LINK_SPEED in the local device - Deassert this field - Assert this field If you set
the default of this field using the DEFAULT_GEN2_SPEED_CHANGE configuration parameter to "1",
then the speed change is initiated automatically after link up, and the controller clears the contents
of this field. If you want to prevent this automatic speed change, then write a lower speed value to
the Target Link Speed field of the Link Control 2 register (LINK_CONTROL2_LINK_STATUS2_OFF .
PCIE_CAP_TARGET_LINK_SPEED) through the DBI before link up. Note: The access attributes of this
field are as follows: - Wire: No access.
16 Enable Auto Flipping Of The Lanes

AUTO_LANE_F For more details, see Lane reversal and flipping†.
LIP_CTRL_EN
Note: The access attributes of this field are as follows:
- Wire: No access.
15-13 Predetermined Lane For Auto Flip

PRE_DET_LAN This field defines which physical lane is connected to logical Lane0 by the flip operation performed in Detect.
E Allowed values are shown below.

NXP Semiconductors
PCIe Controller
Field Function
This field is used to restrict the receiver detect procedure to a particular lane when the default detect and
polling procedure performed on all lanes cannot be successful. A notable example of when it is useful to
program this field to a value different from the default, is when a lane is asymmetrically broken, that is, it is
detected in Detect LTSSM state but it cannot exit Electrical Idle in Polling LTSSM state.
000b - Connect logical Lane0 to physical lane 0 or 1, depending on which lane is detected
12-8 Predetermined Number of Lanes. Defines the number of lanes which are connected and not bad. Used
to limit the effective link width to ignore 'broken" or "unused" lanes that detect a receiver. Indicates the
NUM_OF_LAN number of lanes to check for exit from Electrical Idle in Polling.Active and L2.Idle. It is possible that the
ES LTSSM might detect a receiver on a bad or broken lane during the Detect Substate. However, it is also
possible that such a lane might also fail to exit Electrical Idle and therefore prevent a valid link from being
configured. This value is referred to as the "Predetermined Number of Lanes" in section 4.2.6.2.1 of the
PCI Express Base 3.0 Specification, revision 1.0. Encoding is as follows: - 0x01: 1 lane - 0x02: 2 lanes
- 0x03: 3 lanes - .. When you have unused lanes in your system, then you must change the value in
this register to reflect the number of lanes. You must also change the value in the "Link Mode Enable"
field of PORT_LINK_CTRL_OFF. The value in this register is normally the same as the encoded value in
PORT_LINK_CTRL_OFF. If you find that one of your used lanes is bad then you must reduce the value
in this register. For more information, see "How to Tie Off Unused Lanes." For information on upsizing
and downsizing the link width, see "Link Establishment." Note: The access attributes of this field are as
follows: - Wire: No access. Note: This register field is sticky.
7-0 Sets the Number of Fast Training Sequences (N_FTS) that the controller advertises as its N_FTS during
Gen2 or Gen3 link training. This value is used to inform the link partner about the PHY's ability to recover
FAST_TRAININ synchronization after a low power state. The number should be provided by the PHY vendor. Do not
G_SEQ set N_FTS to zero; doing so can cause the LTSSM to go into the recovery state when exiting from L0s.
sticky.
3.8.142 PHY Status (PHY_STATUS_OFF)
Offset
Register Offset
PHY_STATUS_OFF 810h
Function
Memory mapped register from phy_cfg_status GPIO input pins.

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R PHY_STATUS
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R PHY_STATUS
Fields
Field Function
31-0 PHY status

PHY_STATUS Data received directly from the phy_cfg_status bus. These is a GPIO register reflecting the values on
the static phy_cfg_status input signals. The usage is left completely to the user and does not in any way
influence controller functionality. You can use it for any static sideband status signalling requirements that
you have for your PHY.
3.8.143 PHY Control (PHY_CONTROL_OFF)
Offset
Register Offset
PHY_CONTROL_OFF 814h
Function
Memory mapped register to cfg_phy_control GPIO output pins.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
PHY_CONTROL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
PHY_CONTROL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
PHY Control. Data sent directly to the cfg_phy_control bus. These is a GPIO register driving the values
31-0
on the static cfg_phy_control output signals. The usage is left completely to the user and does not
PHY_CONTRO in any way influence controller functionality. You can use it for any static sideband control signalling
L requirements that you have for your PHY. Note: This register field is sticky.
3.8.144 Programmable Target Map Control (TRGT_MAP_CTRL_OFF)
Offset
Register Offset
TRGT_MAP_CTRL_OFF 81Ch
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R TARGET_MAP_RESERVED_21_31
TARGET_MAP_INDEX
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TARGET_MAP_RESER
R 0 TARG
VED_13_... TARGET_MAP_PF
ET_...
W
Reset 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 1
Fields
Field Function
31-21 Reserved Note: The access attributes of this field are as follows: - Wire: No access.
TARGET_MAP_
RESERVED_21
_31
20-16 The number of the PF Function on which the Target Values are set. This register does not respect the
Byte Enable setting. any write will affect all register bits.
TARGET_MAP_
INDEX
15-13 Reserved Note: The access attributes of this field are as follows: - Wire: No access.
TARGET_MAP_
RESERVED_13
_15

NXP Semiconductors
PCIe Controller
Field Function
12-7 Reserved
6 Target Value for the ROM page of the PF Function selected by the index number. This register does not
TARGET_MAP_
ROM
5-0 Target Values for each BAR on the PF Function selected by the index number. This register does not
TARGET_MAP_
PF
3.8.145 Integrated MSI Reception Module (iMRM) Address (MSI_CTRL_ADDR_OFF)
Offset
Register Offset
MSI_CTRL_ADDR_OFF 820h
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MSI_CTRL_ADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MSI_CTRL_ADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
Integrated MSI Reception Module Address. System specified address for MSI memory write transaction
31-0
termination. Within the AXI Bridge, every received Memory Write request is examined to see if it targets
MSI_CTRL_AD the MSI Address that has been specified in this register; and also to see if it satisfies the definition of an
DR MSI interrupt request. When these conditions are satisfied the Memory Write request is marked as an
MSI request. Note: This register field is sticky.

NXP Semiconductors
PCIe Controller
3.8.146 Integrated MSI Reception Module Upper Address (MSI_CTRL_UPPER_ADDR_OFF)
Offset
Register Offset
MSI_CTRL_UPPER_AD 824h
DR_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MSI_CTRL_UPPER_ADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MSI_CTRL_UPPER_ADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
Integrated MSI Reception Module Upper Address. System specified upper address for MSI memory write
31-0
transaction termination. Allows functions to support a 64-bit MSI address. Note: This register field is
MSI_CTRL_UP sticky.
PER_ADDR
3.8.147 Integrated MSI Reception Module Interrupt #0 Enable (MSI_CTRL_INT_0_EN_OFF)
Offset
Register Offset
FF

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MSI_CTRL_INT_0_EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MSI_CTRL_INT_0_EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0
_0_EN
3.8.148 Integrated MSI Reception Module Interrupt #0 Mask (MSI_CTRL_INT_0_MASK_OFF)
Offset
Register Offset
K_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MSI_CTRL_INT_0_MASK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MSI_CTRL_INT_0_MASK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-0
_0_MASK
3.8.149 Integrated MSI Reception Module Interrupt #0 Status (MSI_CTRL_INT_0_STATUS_OFF)
Offset
Register Offset
US_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0
_0_STATUS
Offset
Register Offset
FF

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MSI_CTRL_INT_1_EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MSI_CTRL_INT_1_EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0
_1_EN
Offset
Register Offset
K_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MSI_CTRL_INT_1_MASK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MSI_CTRL_INT_1_MASK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-0
_1_MASK
Offset
Register Offset
US_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0
_1_STATUS
Offset
Register Offset
FF

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MSI_CTRL_INT_2_EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MSI_CTRL_INT_2_EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0
_2_EN
Offset
Register Offset
K_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MSI_CTRL_INT_2_MASK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MSI_CTRL_INT_2_MASK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-0
_2_MASK
Offset
Register Offset
US_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0
_2_STATUS
Offset
Register Offset
FF

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MSI_CTRL_INT_3_EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MSI_CTRL_INT_3_EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0
_3_EN
Offset
Register Offset
K_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MSI_CTRL_INT_3_MASK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MSI_CTRL_INT_3_MASK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-0
_3_MASK
Offset
Register Offset
US_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0
_3_STATUS
Offset
Register Offset
FF

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MSI_CTRL_INT_4_EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MSI_CTRL_INT_4_EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0
_4_EN
Offset
Register Offset
K_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MSI_CTRL_INT_4_MASK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MSI_CTRL_INT_4_MASK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-0
_4_MASK
Offset
Register Offset
US_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0
_4_STATUS
Offset
Register Offset
FF

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MSI_CTRL_INT_5_EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MSI_CTRL_INT_5_EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0
_5_EN
Offset
Register Offset
K_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MSI_CTRL_INT_5_MASK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MSI_CTRL_INT_5_MASK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-0
_5_MASK
Offset
Register Offset
US_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0
_5_STATUS
Offset
Register Offset
FF

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MSI_CTRL_INT_6_EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MSI_CTRL_INT_6_EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0
_6_EN
Offset
Register Offset
K_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MSI_CTRL_INT_6_MASK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MSI_CTRL_INT_6_MASK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-0
_6_MASK
Offset
Register Offset
US_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0
_6_STATUS
Offset
Register Offset
FF

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MSI_CTRL_INT_7_EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MSI_CTRL_INT_7_EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0
_7_EN
Offset
Register Offset
K_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MSI_CTRL_INT_7_MASK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MSI_CTRL_INT_7_MASK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-0
_7_MASK
Offset
Register Offset
US_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0
_7_STATUS
3.8.171 Integrated MSI Reception Module General Purpose IO (MSI_GPIO_IO_OFF)
Offset
Register Offset
MSI_GPIO_IO_OFF 888h

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MSI_GPIO_REG
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MSI_GPIO_REG
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0 MSI GPIO Register. The contents of this register drives the top-level GPIO msi_ctrl_io[31:0] Note: This
MSI_GPIO_RE
G
3.8.172 RADM clock gating enable control (CLOCK_GATING_CTRL_OFF)
Offset
Register Offset
CLOCK_GATING_CTRL 88Ch
_OFF
Function
Using this register you can disable the RADM clock gating feature. The DWC_pcie_clk_rst.v modules uses the en_radm_clk_g
output to gate core_clk and create the radm_clk_g clock input. The controller de-asserts the en_radm_clk_g output when there
is no Rx traffic, Rx queues and pre/post-queue pipelines are empty, RADM completion LUT is empty, and there are no FLR
actions pending. You must set the RADM_CLK_GATING_EN field to enable this functionality; otherwise the en_radm_clk_g
output will always be set to '1'.

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 RADM
W _CL...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Fields
Field Function
31-1 Reserved
0 Enable Radm clock gating feature. - 0: Disable - 1: Enable(default)
RADM_CLK_G
ATING_EN
3.8.173 Gen3 Control (GEN3_RELATED_OFF)
Offset
Register Offset
GEN3_RELATED_OFF 890h
Function
There is no Gen3-specific N_FTS field. The N_FTS field in the "Link Width and Speed Change Control Register" is used for
both Gen2 and Gen3 speed modes. There is no Gen3-specific "Directed Speed Change" field. The "Directed Speed Change"
field in the "Link Width and Speed Change Control Register" is used to change to Gen2 or Gen3 speed. A speed change to
Gen3 occurs if (1) the "Directed Speed Change" field is set to "1" and (2) the "Target Link Speed" field in the Link Control 2
Register is set to Gen3. Gen3 support is advertised by both sides of the link during link training.

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 GEN3_ 0 0 GEN3_ GEN3_ GEN3_
W EQ... DC... DL... EQ...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 RXEQ RXEQ EQ_ EQ_EI EQ_P DISAB 0 GEN3_
W _RG... _PH... REDO EO... HAS... LE... ZR...
Reset 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1
Fields
Field Function
31-24 Reserved
23 Eq InvalidRequest and RxEqEval Different Time Assertion Disable.

GEN3_EQ_INV Disable the assertion of Eq InvalidRequest and RxEqEval at different time.
REQ_EVAL_DI
FF_DISABLE
22-21 Reserved
20-19 Reserved
18 DC Balance Disable
GEN3_DC_BAL Disable DC Balance feature.
ANCE_DISABL
E
17 DLLP Transmission Delay Disable

GEN3_DLLP_X Disable delay transmission of DLLPs before equalization.
MT_DELAY_DI
SABLE
16 Equalization Disable
GEN3_EQUALI Disable equalization feature.
ZATION_DISAB
LE
15-14 Reserved

NXP Semiconductors
PCIe Controller
Field Function
13 When set to '1', the controller as Gen3 EQ master asserts RxEqEval to instruct the PHY to do Rx adaptation
and evaluation after a 500ns timeout from a new preset request.
RXEQ_RGRDL
ESS_RXTS The access attributes of this field are as follows:
- Wire: No access.
0b - mac_phy_rxeqeval asserts after 1us and 2 TS1 received from remote partner.
1b - mac_phy_rxeqeval asserts after 500ns regardless of TS's received or not.
12 Rx Equalization Phase 0/Phase 1 Hold Enable

RXEQ_PH01_E When this bit is set the upstream port holds phase 0 (the downstream port holds phase 1) for 10ms. Holding
N phase 0 or phase 1 can be used to allow sufficient time for Rx Equalization to be performed by the PHY. This
bit is used during Virtex-7 Gen3 equalization. The programmable bits [RXEQ_PH01_EN, EQ_PHASE_2_3]
can be used to obtain the following variations of the equalization procedure:
• 00: Tx equalization only in phase 2/3
• 01: No Tx equalization, no Rx equalization
• 10: Tx equalization in phase 2/3, Rx equalization in phase 0/1
• 11: No Tx equalization, Rx equalization in phase 0/1
- Wire: No access.
11 Equalization Redo Disable

EQ_REDO Disable autonomous mechanism for requesting to redo the equalization process.
10 Equalization EIEOS Count Reset Disable

EQ_EIEOS_CN Disable requesting reset of EIEOS count during equalization.
T
9 Equalization Phase 2 And Phase 3 Disable

EQ_PHASE_2_ This applies to downstream ports only.
3
- Wire: No access
8 Disable Scrambler For Gen3 and Gen4 Data Rate

NXP Semiconductors
PCIe Controller
Field Function
DISABLE_SCR The Gen3 and Gen4 scrambler/descrambler within the controller needs to be disabled when the scrambling
AMBLER_GEN function is implemented outside of the controller (for example within the PHY).
_3
7-1 Reserved
0 Gen3 Receiver Impedance ZRX-DC Not Compliant

GEN3_ZRXDC_ Receivers that operate at 8.0 GT/s with an impedance other than the range defined by the ZRX-DC
NONCOMPL parameter for 2.5 GT/s (40-60 Ohms) must meet additional behavior requirements in the following
LTSSM states:
• Polling
• Rx_L0s
• L1
• L2
• Disabled
0b - The receiver complies with the ZRX-DC parameter for 2.5 GT/s when operating at 8 GT/s or
higher.
1b - The receiver does not comply with the ZRX-DC parameter for 2.5 GT/s when operating at 8
GT/s or higher.
3.8.174 Gen3 EQ Control (GEN3_EQ_CONTROL_OFF)
Offset
Register Offset
GEN3_EQ_CONTROL_ 8A8h
OFF
Function
Controls equalization for Phase2 in an upstream port (USP), or Phase3 in a downstream port (DSP).

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

GEN3_EQ_PSET_REQ_VEC
W RE... EQ... EQ...
Reset 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

GEN3_EQ_PSET_REQ_VEC GEN3_EQ_FB_MODE
W LO... EQ... EQ...
Reset 1 0 0 1 1 1 1 1 0 1 1 1 0 0 0 1
Fields
Field Function
31-27 Reserved
Request controller to send back-to-back EIEOS in Recovery.RcvrLock state until presets to coefficients
26
mapping is complete. - 0: Do not request - 1: request Note: Gen3 and Gen4 share the same register bit
GEN3_REQ_SE and have the same feature. Note: This register field is sticky.
ND_CONSEC_
EIEOS_FOR_P
SET_MAP
25 GEN3_EQ_PSET_REQ_AS_COEF is an internally reserved field. Do not use. Note: This register field is
sticky.
GEN3_EQ_PSE
T_REQ_AS_CO
EF
24 Include Initial FOM

GEN3_EQ_FO Include or not the FOM feedback from the initial preset evaluation performed in the EQ Master, when finding
M_INC_INITIAL the highest FOM among all preset evaluations.
_EVAL
0b - Do not include
1b - Include
Preset Request Vector. Requesting of Presets during the initial part of the EQ Master Phase. Encoding
23-8
scheme is as follows: Bit [15:0] =0x0: No preset is requested and evaluated in EQ Master Phase. Bit
GEN3_EQ_PSE [i] =1: "Preset=i" is requested and evaluated in EQ Master Phase. - 0000000000000000: No preset be
T_REQ_VEC requested and evaluated in EQ Master Phase - 000000xxxxxxxxx1: Preset 0 is requested and evaluated
in EQ Master Phase - 000000xxxxxxxx1x: Preset 1 is requested and evaluated in EQ Master Phase
- 000000xxxxxxx1xx: Preset 2 is requested and evaluated in EQ Master Phase - 000000xxxxxx1xxx:
Preset 3 is requested and evaluated in EQ Master Phase - 000000xxxxx1xxxx: Preset 4 is requested
and evaluated in EQ Master Phase - 000000xxxx1xxxxx: Preset 5 is requested and evaluated in
EQ Master Phase - 000000xxx1xxxxxx: Preset 6 is requested and evaluated in EQ Master Phase -
000000xx1xxxxxxx: Preset 7 is requested and evaluated in EQ Master Phase - 000000x1xxxxxxxx:

NXP Semiconductors
PCIe Controller
Field Function
Preset 8 is requested and evaluated in EQ Master Phase - 00000x1xxxxxxxxx: Preset 9 is requested

and evaluated in EQ Master Phase - 000001xxxxxxxxxx: Preset 10 is requested and evaluated in EQ
Master Phase - All other encodings: Reserved Note: You must contact your PHY vendor to ensure 24 ms
timeout does not occur in presets requests in EQ master phase, i.e., you must set a proper value to the
GEN3_EQ_PSET_REQ_VEC register so that the EQ tunning for Figure of Merit in the EQ master phase
completes before 24 ms timeout. Note: This register field is sticky.
7 Reserved
6 Support EQ redo and lower rate change: - 0: not support - 1: support Note: Gen3 and Gen4 share the
same register bit and have the same feature. Note: This register field is sticky.
GEN3_LOWER
_RATE_EQ_RE
DO_ENABLE
5 Phase2_3 2 ms Timeout Disable

GEN3_EQ_EVA Determine behavior in Phase2 for USP (Phase3 if DSP) when the PHY does not respond within 2ms to the
L_2MS_DISABL assertion of RxEqEval.
E
0b - Abort the current evaluation, stop any attempt to modify the remote transmitter settings,
Phase2 is terminated by the 24ms timeout
1b - ignore the 2ms timeout and continue as normal. This is used to support PHYs that require
more than 2ms to respond to the assertion of RxEqEval.
4 Behavior After 24 ms Timeout (When Optimal Settings Are Not Found)

GEN3_EQ_PHA For a USP: Determine next LTSSM state from Phase2 after 24ms Timeout
SE23_EXIT_M
ODE
• 1: Recovery.Equalization.Phase3
For a DSP: Determine next LTSSM state from Phase3 after 24ms Timeout
• 1: Recovery.Equalization.RcvrLock

NXP Semiconductors
PCIe Controller
Field Function
GEN3_EQ_PHASE23_EXIT_MODE = 1 affects Direction Change feed back mode. EQ requests for Figure
Of Merit mode complete before 24 ms timeout. Please see GEN3_EQ_PSET_REQ_VEC Register for more.
3-0 Feedback Mode

GEN3_EQ_FB_ This field is sticky.
MODE
0000b - Direction Change
0001b - Figure Of Merit
3.8.175 Gen3 EQ Direction Change Feedback Mode Control

Offset
Register Offset
GEN3_EQ_FB_MODE_D 8ACh
IR_CHANGE_OFF
Function
Equalization controls to be used in Phase2 (USP) or Phase 3 (DSP), when you set the Feedback Mode in "Gen3 EQ Control
Register" to "Direction Change." These fields allow control over the initial starting point for the search of optimal coefficient
settings, and allow control over the criteria used to determine when the optimal settings have been achieved. The values are
applied to all the lanes.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 GEN3_EQ_FM
W DC_MA...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R GEN3_EQ_FM GEN3_EQ_FMDC_MAX_PRE_CU
GEN3_EQ_FMDC_N_EVALS GEN3_EQ_FMDC_T_MIN_PHASE23
W DC_MA... SROR_DEL...
Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-18 Reserved
17-14 Convergence Window Aperture For C+1

GEN3_EQ_FM Post-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0,1,2,..15.
DC_MAX_POS
T_CUSROR_D
ELTA
13-10 Convergence Window Aperture For C-1

GEN3_EQ_FM Pre-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0,1,2,..15.
DC_MAX_PRE_
CUSROR_DEL
TA
9-5 Convergence Window Depth

GEN3_EQ_FM Number of consecutive evaluations considered in Phase 2/3 when determining if optimal coefficients have
DC_N_EVALS been found. Allowed range: 0,1,2,.. up to a maximum of 8.
When set to 0, EQ Master is performed without sending any requests to the remote partner in Phase 2 for
USP and Phase 3 for DSP. Therefore, the remote partner will not change its transmitter coefficients and will
move to the next state.
4-0 Minimum Time (in ms) To Remain in EQ Master Phase

GEN3_EQ_FM The LTSSM stays in EQ Master phase for at least this amount of time, before starting to check for
DC_T_MIN_PH convergence of the coefficients. Allowed values 0,1,...,24.
ASE23
3.8.176 Order Rule Control (ORDER_RULE_CTRL_OFF)
Offset
Register Offset
ORDER_RULE_CTRL_O 8B4h
FF

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CPL_PASS_P NP_PASS_P
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-16 Reserved
15-8 Completion Passing Posted Ordering Rule Control. Determines if CPL can pass halted P queue. - 0:
CPL can not pass P (recommended) - 1: CPL can pass P
CPL_PASS_P
7-0 Non-Posted Passing Posted Ordering Rule Control. Determines if NP can pass halted P queue. - 0 : NP
can not pass P (recommended). - 1 : NP can pass P
NP_PASS_P
3.8.177 PIPE Loopback Control (PIPE_LOOPBACK_CONTROL_OFF)
Offset
Register Offset
PIPE_LOOPBACK_CON 8B8h
TROL_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R PIPE_ 0
RXSTATUS_LANE
W LO...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
LPBK_RXVALID
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

NXP Semiconductors
PCIe Controller
Fields
Field Function
31 PIPE Loopback Enable. Note: This register field is sticky.
PIPE_LOOPBA
CK
30-22 Reserved
21-16 RXSTATUS_LANE is an internally reserved field. Do not use. Note: This register field is sticky.
RXSTATUS_LA
NE
15-0 LPBK_RXVALID is an internally reserved field. Do not use. Note: This register field is sticky.
LPBK_RXVALI
D
3.8.178 DBI Read-Only Write Enable (MISC_CONTROL_1_OFF)
Offset
Register Offset
MISC_CONTROL_1_OF 8BCh
F
Function
Table 14. Other registers and fields affected when MISC_CONTROL_1_OFF[DBI_RO_WR_EN] = 1
Register Fields
Device ID And Vendor ID (TYPE1_DEV_ID_VEND_ID_REG) All
Class Code And Revision ID (TYPE1_CLASS_CODE_REV_ID_REG) All
Secondary Status, I/O Limit, And Base IO_DECODE_BIT8

(SEC_STAT_IO_LIMIT_IO_BASE_REG)
Prefetchable Memory Limit And Base PREF_MEM_DECODE

(PREF_MEM_LIMIT_PREF_MEM_BASE_REG)
Prefetchable Base Upper 32 Bits (PREF_BASE_UPPER_REG) PREF_MEM_BASE_UPPER
Prefetchable Limit Upper 32 Bits (PREF_LIMIT_UPPER_REG) PREF_MEM_LIMIT_UPPER
I/O Limit And Base Upper 16 Bits All

(IO_LIMIT_UPPER_IO_BASE_UPPER_REG)
Capabilities Pointer (TYPE1_CAP_PTR_REG) CAP_POINTER

NXP Semiconductors
PCIe Controller
Register Fields
Bridge Control, Interrupt Pin, And Interrupt Line INT_PIN

(BRIDGE_CTRL_INT_PIN_INT_LINE_REG)
SPCIE Capability Header (SPCIE_CAP_HEADER_REG) All
Lane Equalization Control Register For Lanes 1 And 0 All

Vendor-Specific Extended Capability Header All

PCIe Extended Capability ID, Capability Version And Next Capability All
Power Management Capabilities (CAP_ID_NXT_PTR_REG) • PM_NEXT_POINTER

• PM_SPEC_VER
• DSI
• AUX_CURR
• D1_SUPPORT
• D2_SUPPORT
• PME_SUPPORT
Power Management Control And Status (CON_STATUS_REG) NO_SOFT_RST
PCI Express Capabilities, ID, Next Pointer • PCIE_CAP_NEXT_PTR

• PCIE_SLOT_IMP
• PCIE_INT_MSG_NUM
Device Capabilities (DEVICE_CAPABILITIES_REG) All
Link Capabilities (LINK_CAPABILITIES_REG) All
Link Control and Status (LINK_CONTROL_LINK_STATUS_REG) • PCIE_CAP_RCB

• PCIE_CAP_SLOT_CLK_CONFIG
Slot Capabilities (SLOT_CAPABILITIES_REG) All
Root Control and Capabilities PCIE_CAP_CRS_SW_VISIBILITY

(ROOT_CONTROL_ROOT_CAPABILITIES_REG)
Link Control 2 and Status 2 (LINK_CONTROL2_LINK_STATUS2_REG) PCIE_CAP_SEL_DEEMPHASIS
Advanced Error Reporting Extended Capability Header All

Root Error Status (ROOT_ERR_STATUS_OFF) ADV_ERR_INT_MSG_NUM
MSI Capability ID, Next Pointer, Capability And Control • PCI_MSI_CAP_NEXT_OFFSET

(PCI_MSI_CAP_ID_NEXT_CTRL_REG)
• PCI_MSI_MULTIPLE_MSG_CAP
• PCI_MSI_64_BIT_ADDR_CAP

NXP Semiconductors
PCIe Controller
Register Fields
• PCI_MSI_EXT_DATA_CAP
MSI-X Capability ID, Next Pointer, Control • PCI_MSIX_CAP_NEXT_OFFSET

• PCI_MSIX_TABLE_SIZE
MSI-X Table Offset and BIR (MSIX_TABLE_OFFSET_REG) All
MSI-X PBA Offset and BIR (MSIX_PBA_OFFSET_REG) All
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 ARI_D 0 SIMPL UR_C DEFA DBI_R
W EV... IF... A_M... ULT... O_...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-6 Reserved
5 When ARI is enabled, this field enables use of the device ID. Note: This register field is sticky.
ARI_DEVICE_N
UMBER
4 Reserved
3 Enables Simplified Replay Timer (Gen4). Simplified Replay Timer Values are: - A value from 24,000 to
31,000 Symbol Times when Extended Synch is 0b. - A value from 80,000 to 100,000 Symbol Times
SIMPLIFIED_R when Extended Synch is 1b. Must not be changed while link is in use. Note: This register field is sticky.
EPLAY_TIMER
This field only applies to request TLPs (with UR filtering status) that you have chosen to forward to the
2
application (when you set DEFAULT_TARGET in this register). - When you set this field to '1', the core
UR_CA_MASK_ suppresses error logging, Error Message generation, and CPL generation (for non-posted requests). You
4_TRGT1 should set this if you have set the Default Target port logic register to '1'. Note: This register field is
sticky.

NXP Semiconductors
PCIe Controller
Field Function
1Default target a received IO or MEM request with UR/CA/CRS is sent to by the controller. - 0: The
controller drops all incoming I/O or MEM requests (after corresponding error reporting). A completion
DEFAULT_TAR with UR status will be generated for non-posted requests. - 1: The controller forwards all incoming
GET I/O or MEM requests with UR/CA/CRS status to your application Default value is DEFAULT_TARGET
configuration parameter. Note: This register field is sticky.
0 Write To Read-Only Fields Using DBI

DBI_RO_WR_E When this field is 1, the read-only fields specified in Table 14 become writable from the local application
N through the DBI.
3.8.179 UpConfigure Multi-lane Control (MULTI_LANE_CONTROL_OFF)
Offset
Register Offset
MULTI_LANE_CONTRO 8C0h
L_OFF
Function
Used when upsizing or downsizing the link width through Configuration state without bringing the link down. For more details,
see Link establishment†.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 UPCO DIREC
TARGET_LINK_WIDTH
W NFI... T_...
Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
Fields
Field Function
31-8 Reserved

NXP Semiconductors
PCIe Controller
Field Function
7 Upconfigure Support. The controller sends this value as the Link Upconfigure Capability in TS2 Ordered
Sets in Configuration.Complete state. Note: This register field is sticky.
UPCONFIGUR
E_SUPPORT
6 Directed Link Width Change. The controller always moves to Configuration state through
Recovery state when this bit is set to '1'. - If the upconfigure_capable variable is '1' and
DIRECT_LINK_ the PCIE_CAP_HW_AUTO_WIDTH_DISABLE bit in LINK_CONTROL_LINK_STATUS_REG is '0', the
WIDTH_CHAN controller starts upconfigure or autonomous width downsizing (to the TARGET_LINK_WIDTH value) in
GE the Configuration state. - If TARGET_LINK_WIDTH value is 0x0, the controller does not start upconfigure
or autonomous width downsizing in the Configuration state. The controller self-clears this field when the
controller accepts this request.
Target Link Width. Values correspond to: - 6'b000000: Core does not start upconfigure or autonomous
5-0
width downsizing in the Configuration state. - 6'b000001: x1 - 6'b000010: x2 - 6'b000100: x4 -
TARGET_LINK 6'b001000: x8 - 6'b010000: x16 - 6'b100000: x32
_WIDTH
3.8.180 PHY Interoperability Control (PHY_INTEROP_CTRL_OFF)
Offset
Register Offset
PHY_INTEROP_CTRL_ 8C4h
OFF
Function
This register is reserved for internal use. You should not write to this register and change the default unless specifically
instructed by Synopsys support.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
L1_NO
R 0 L1_CL 0 0
WA... RXSTANDBY_CONTROL
K_...
W
Reset 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-11 Reserved
10 L1 Clock control bit. - 1: Controller does not request aux_clk switch and core_clk gating in L1. - 0:
Controller requests aux_clk switch and core_clk gating in L1. Note: This register field is sticky.
L1_CLK_SEL
9 L1 entry control bit. - 1: Core does not wait for PHY to acknowledge transition to P1 before entering
L1. - 0: Core waits for the PHY to acknowledge transition to P1 before entering L1. Note: The access
L1_NOWAIT_P attributes of this field are as follows: - Wire: No access. Note: This register field is sticky.
1
8 Reserved
7 Reserved
6-0 Rxstandby Control. Bits 0..5 determine if the controller asserts the RxStandby signal
(mac_phy_rxstandby) in the indicated condition. Bit 6 enables the controller to perform the RxStandby/
RXSTANDBY_ RxStandbyStatus handshake. - [0]: Rx EIOS and subsequent T TX-IDLE-MIN - [1]: Rate Change - [2]:
CONTROL Inactive lane for upconfigure/downconfigure - [3]: PowerDown=P1orP2 - [4]: RxL0s.Idle - [5]: EI Infer in
L0 - [6]: Execute RxStandby/RxStandbyStatus Handshake Note: This register field is sticky.
3.8.181 TRGT_CPL_LUT Delete Entry Control (TRGT_CPL_LUT_DELETE_ENTRY_OFF)
Offset
Register Offset
TRGT_CPL_LUT_DELE 8C8h
TE_ENTRY_OFF
Function
Using this register you can delete one entry in the target completion LUT. You should only use this register when you know
that your application will never send the completion because of an FLR or any other reason. Note:: The target completion
LUT (and associated target completion timeout event) is watching for completions (from your application on AXI master read
channel) corresponding to previously received non-posted requests from the PCIe wire.

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DELET
R
E_... LOOK_UP_ID
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
LOOK_UP_ID
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31 This is a one-shot bit. A '1' write to this bit triggers the deletion of the target completion LUT entry that
is specified in the LOOK_UP_ID field. This is a self-clearing register field. Reading from this register field
DELETE_EN always returns a '0'.
30-0 This number selects one entry to delete of the TRGT_CPL_LUT.
LOOK_UP_ID
3.8.182 Link Reset Request Flush Control (LINK_FLUSH_CONTROL_OFF)
Offset
Register Offset
LINK_FLUSH_CONTRO 8CCh
L_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
RSVD_I_8
W
Reset 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 AUTO_
W FL...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-24 This is an internally reserved field. Do not use. Note: This register field is sticky.
RSVD_I_8
23-1 Reserved
0Enables automatic flushing of pending requests before sending the reset request to the application logic
to reset the PCIe controller and the AXI Bridge. The flushing process is initiated if any of the following
AUTO_FLUSH_ events occur: - Hot reset request. A downstream port (DSP) can "hot reset" an upstream port (USP) by
EN sending two consecutive TS1 ordered sets with the hot reset bit asserted. - Warm (Soft) reset request.
Generated when exiting from D3 to D0 and cfg_pm_no_soft_rst=0. - Link down reset request. A high to
low transition on smlh_req_rst_not indicates the link has gone down and the controller is requesting a
reset. If you disable automatic flushing, your application is responsible for resetting the PCIe controller
and the AXI Bridge. Note: This register field is sticky.
3.8.183 AXI Bridge Slave Error Response (AMBA_ERROR_RESPONSE_DEFAULT_OFF)
Offset
Register Offset
AMBA_ERROR_RESPO 8D0h
NSE_DEFAULT_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 AMBA_ERROR AMBA 0 AMBA

AMBA_ERROR_RESPONSE_MAP
W _RESP... _ER... _ER...
Reset 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-16 Reserved

NXP Semiconductors
PCIe Controller
Field Function
15-10 AXI Slave Response Error Map. Allows you to selectively map the errors received from the PCIe
completion (for non-posted requests) to the AXI slave responses, slv_rresp or slv_bresp. The
AMBA_ERROR recommended setting is SLVERR. CRS is always mapped to OKAY. - [0] -- 0: UR (unsupported request)
_RESPONSE_ -> DECERR -- 1: UR (unsupported request) -> SLVERR - [1] -- 0: CRS (configuration retry status) ->
MAP DECERR -- 1: CRS (configuration retry status) -> SLVERR - [2] -- 0: CA (completer abort) -> DECERR
-- 1: CA (completer abort) -> SLVERR - [3]: Reserved - [4]: Reserved - [5]: -- 0: Completion Timeout
-> DECERR -- 1: Completion Timeout -> SLVERR The AXI bridge internally drops (processes internally
but not passed to your application) a completion that has been marked by the Rx filter as UC or MLF,
and does not pass its status directly down to the slave interface. It waits for a timeout and then signals
"Completion Timeout" to the slave interface. The controller sets the AXI slave read databus to 0xFFFF
for all error responses. Note: This register field is sticky.
9-5 Reserved
4-3 CRS Slave Error Response Mapping

AMBA_ERROR Determines the AXI slave response for CRS completions.
_RESPONSE_
CRS
00b - OKAY
01b - OKAY with all FFFF_FFFF data for all CRS completions
10b - OKAY with FFFF_0001 data for CRS completions to vendor ID read requests, OKAY with
FFFF_FFFF data for all other CRS completions
2 Vendor ID Non-existent Slave Error Response Mapping

AMBA_ERROR Determines the AXI slave response for errors on reads to non-existent Vendor ID register.
_RESPONSE_V
ENDORID
0b - OKAY (with FFFF data)
1 Reserved
0 Global Slave Error Response Mapping

AMBA_ERROR Determines the AXI slave response for all error scenarios on non-posted requests.
_RESPONSE_
The error response mapping is not applicable to Non-existent Vendor ID register reads.
GLOBAL
0b - OKAY (with FFFF data for non-posted requests)

NXP Semiconductors
PCIe Controller
Field Function

3.8.184 Link Down AXI Bridge Slave Timeout (AMBA_LINK_TIMEOUT_OFF)
Offset
Register Offset
AMBA_LINK_TIMEOUT_ 8D4h
OFF
Function
If your application AXI master issues outbound requests to the AXI bridge slave interface before the PCIe link is operational,
the controller starts a "flush" timer. The timeout value of the timer is set by this register. The timer will timeout and then
flush the bridge TX request queues after this amount of time. The timer counts when there are pending outbound AXI slave
interface (or DMA) requests and the PCIe TX link is not transmitting any of these requests.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 LINK_
LINK_TIMEOUT_PERIOD_DEFAULT
W TI...
Reset 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0
Fields
Field Function
31-9 Reserved
8 Disable Flush. You can disable the flush feature by setting this field to "1". Note: This register field is
sticky.
LINK_TIMEOUT
_ENABLE_DEF
AULT

NXP Semiconductors
PCIe Controller
Field Function
Timeout Value (ms). The timer will timeout and then flush the bridge TX request queues after this
7-0
amount of time. The timer counts when there are pending outbound AXI slave interface requests and
LINK_TIMEOUT the PCIe TX link is not transmitting any of these requests. The timer is clocked by core_clk. Note: This
_PERIOD_DEF register field is sticky.
AULT
3.8.185 AMBA Ordering Control (AMBA_ORDERING_CTRL_OFF)
Offset
Register Offset
AMBA_ORDERING_CT 8D8h
RL_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 AX_M 0 AX_MSTR_OR 0 AX_SN 0
W STR... DR_P_... P_...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-8 Reserved
7 AXI Master Zero Length Read Forward To The Application

AX_MSTR_ZER The PCIe controller's AXI bridge is able to terminate in order with the Posted transactions the zero length
OLREAD_FW read, implementing the PCIe express flush semantics of the Posted transactions.
0b - The zero-length read terminates at the PCIe AXI bridge master
1b - The zero-length read is forwarded to the application
6-5 Reserved

NXP Semiconductors
PCIe Controller
Field Function
4-3 AXI Master Posted Ordering Event Selector

AX_MSTR_OR Selects how the master interface determines when a P write is completed when enforcing the PCIe ordering
DR_P_EVENT_ rule, "NP must not pass P" at the AXI Master Interface.
SEL
The AXI protocol does not support ordering between channels. Therefore, NP reads can pass P on your AXI
bus fabric. This can result in an ordering violation when the read overtakes a P that is going to the same
address. Therefore, the bridge master does not issue any NP requests until all outstanding P writes reach
their destination. It does this by waiting for the all of the write responses on the B channel. This can affect
the performance of the master read channel.
For scenarios where the interconnect serializes the AXI master "AW", "W" and "AR" channels, you can
increase the performance by reducing the need to wait until the complete Posted transaction has effectively
reached the application slave.
This setting does not affect:
• MSI interrupt catcher and P data ordering; this is always driven by the B'last event
• DMA read engine TLP ordering; this is always driven by the B'last event
• NP write transactions which are always serialized with P write transactions
00b - B'last event: wait for the all of the write responses on the B channel, thereby ensuring that
the complete Posted transaction has effectively reached the application slave
01b - AW'last event: wait until the complete Posted transaction has left the AXI address channel
at the bridge master
2 Reserved
1 AXI Serialize Non-Posted Requests Enable

AX_SNP_EN This field enables the AXI Bridge to serialize same ID Non-Posted Read/Write Requests on the wire.
Serialization implies one outstanding same ID NP Read or Write on the wire and used to avoid AXI RAR and
WAW hazards at the remote link partner.
0 Reserved
Offset
Register Offset
L_1_OFF

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 CFG_
W MEM...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
Boundary Lower Address For Memory Type. Bits [31:0] of dword-aligned address of the boundary for
31-2
Memory type. The two lower address LSBs are "00". Addresses up to but not including this value are
CFG_MEMTYP in the lower address space region; addresses equal or greater than this value are in the upper address
E_BOUNDARY space region. Note: This register field is sticky.
_LOW_ADDR
1 Reserved
0 Sets the memory type for the lower and upper parts of the address space: - 0: lower = Peripheral; upper
= Memory - 1: lower = Memory type; upper = Peripheral Note: This register field is sticky.
CFG_MEMTYP
E_VALUE
Offset
Register Offset
L_2_OFF

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0 Boundary Upper Address For Memory Type. Bits [63:32] of the 64-bit dword-aligned address of the
boundary for Memory type. Note: This register field is sticky.
CFG_MEMTYP
E_BOUNDARY
_HIGH_ADDR
Offset
Register Offset
L_3_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CFG_MSTR_AWCACHE_VALUE CFG_MSTR_ARCACHE_VALUE
W WDOMA... RDOMA...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFG_MSTR_AWCACHE_MODE CFG_MSTR_ARCACHE_MODE
W WDOMA... RDOMA...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31 Reserved
30-27 Master Write CACHE Signal Value. Value of the individual bits in mstr_awcache when
CFG_MSTR_AWCACHE_MODE is '1'. Note: not applicable to message requests; for message requests
CFG_MSTR_A the value of mstr_awcache is always "0000" Note: This register field is sticky.
WCACHE_VAL
UE
26 Reserved
25-24 Master Write DOMAIN Signal Value. Value of the individual bits in mstr_awdomain when
CFG_MSTR_AWDOMAIN_MODE is '1'. Note: not applicable to message requests; for message requests
CFG_MSTR_A the value of mstr_awdomain is always "11" Note: This register field is sticky.
WDOMAIN_VA
LUE
23 Reserved
22-19 Master Read CACHE Signal Value. Value of the individual bits in mstr_arcache when
CFG_MSTR_ARCACHE_MODE is '1'. Note: This register field is sticky.
CFG_MSTR_A
RCACHE_VAL
UE
18 Reserved
17-16 Master Read DOMAIN Signal Value. Value of the individual bits in mstr_ardomain when
CFG_MSTR_ARDOMAIN_MODE is '1' Note: This register field is sticky.
CFG_MSTR_A
RDOMAIN_VAL
UE
15 Reserved
14-11 Master Write CACHE Signal Behavior. Defines how the individual bits in mstr_awcache are controlled:
CFG_MSTR_A CFG_MSTR_AWCACHE_VALUE field Note: for message requests the value of mstr_awcache is always
WCACHE_MO "0000" regardless of the value of this bit Note: This register field is sticky.
DE
10 Reserved

NXP Semiconductors
PCIe Controller
Field Function
9-8Master Write DOMAIN Signal Behavior. Defines how the individual bits in mstr_awdomain[1:0] are
controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of
CFG_MSTR_A the CFG_MSTR_AWDOMAIN_VALUE field Note:: for message requests the value of mstr_awdomain is
WDOMAIN_MO always "11" regardless of the value of this bit Note: This register field is sticky.
DE
7 Reserved
6-3 Master Read CACHE Signal Behavior. Defines how the individual bits in mstr_arcache are controlled:
CFG_MSTR_A CFG_MSTR_ARCACHE_VALUE field Note: This register field is sticky.
RCACHE_MOD
E
2 Reserved
1-0 Master Read DOMAIN Signal Behavior. Defines how the individual bits in mstr_ardomain[1:0] are
controlled: - 0: set automatically by the AXI master - 1: set the value of the corresponding bit of the
CFG_MSTR_A CFG_MSTR_ARDOMAIN_VALUE field Note: This register field is sticky.
RDOMAIN_MO
DE
3.8.189 Lower 20 bits of the programmable AXI address where Messages coming from wire are
mapped to (AXI_MSTR_MSG_ADDR_LOW_OFF)
Offset
Register Offset
_LOW_OFF
Function
Bits [11:0] of the register are tied to zero for the address to be 4k-aligned. In previous releases, the third and fourth DWORDs
of a message (Msg/MsgD) TLP header were delivered though the AXI master address bus (mstr_awaddr). These DWORDS
are now supplied through the mstr_awmisc_info_hdr_34dw[63:0] output; and the value on mstr_awaddr is driven to the value
you have programmed into the AXI_MSTR_MSG_ADDR_LOW_OFF and AXI_MSTR_MSG_ADDR_HIGH_OFF registers.

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
CFG_AXIMSTR_MSG_ADDR_LOW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CFG_AXIMSTR_MSG_ADDR_LO CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED
W W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-12 Lower 20 bits of the programmable AXI address for Messages. Note: This register field is sticky.
CFG_AXIMSTR
_MSG_ADDR_L
OW
11-0 Reserved for future use. Note: This register field is sticky.
CFG_AXIMSTR
_MSG_ADDR_L
OW_RESERVE
D
3.8.190 Upper 32 bits of the programmable AXI address where Messages coming from wire are
mapped to (AXI_MSTR_MSG_ADDR_HIGH_OFF)
Offset
Register Offset
_HIGH_OFF

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0 Upper 32 bits of the programmable AXI address for Messages. Note: This register field is sticky.
CFG_AXIMSTR
_MSG_ADDR_
HIGH
3.8.191 PCIe Controller IIP Release Version Number (PCIE_VERSION_NUMBER_OFF)
Offset
Register Offset
PCIE_VERSION_NUMB 8F8h
ER_OFF
Function
The version number is given in hex format. You should convert each pair of hex characters to ASCII to interpret. Using
4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which translates to 470* - VERSION_TYPE = 0x67612a2a
which translates to ga** Using 4.70a-ea01 as an example: - VERSION_NUMBER = 0x3437302a which translates to 470* -
VERSION_TYPE = 0x65613031 which translates to ea01 GA is a general release available on www.designware.com EA is an
early release available on a per-customer basis.

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R VERSION_NUMBER
Reset 0 0 1 1 0 1 0 1 0 0 1 1 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VERSION_NUMBER
Reset 0 0 1 1 0 0 0 0 0 0 1 0 1 0 1 0
Fields
Field Function
31-0 Version Number.
VERSION_NU
MBER
3.8.192 PCIe Controller IIP Release Version Type (PCIE_VERSION_TYPE_OFF)
Offset
Register Offset
PCIE_VERSION_TYPE_ 8FCh
OFF
Function
The type is given in hex format. You should convert each pair of hex characters to ASCII to interpret. Using 4.70a (GA) as
an example: - VERSION_NUMBER = 0x3437302a which translates to 470* - VERSION_TYPE = 0x67612a2a which translates
to ga** Using 4.70a-ea01 as an example: - VERSION_NUMBER = 0x3437302a which translates to 470* - VERSION_TYPE
= 0x65613031 which translates to ea01 GA is a general release available on www.designware.com EA is an early release
available on a per-customer basis.

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R VERSION_TYPE
Reset 0 1 1 0 1 1 0 0 0 1 1 1 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VERSION_TYPE
Reset 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 1
Fields
Field Function
31-0 Version Type.
VERSION_TYP
E
3.8.193 Interface Timer Control (INTERFACE_TIMER_CONTROL_OFF)
Offset
Register Offset
INTERFACE_TIMER_C 930h
ONTROL_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 FORC INTERFACE_TI INTER INTER
W E_P... MER... FA... FA...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-5 Reserved
4 Writing to this bit forces the value of the pending flags. Note: This register field is sticky.
FORCE_PENDI
NG
3-2Interface timer scaling. This field can be used to reduce the timer duration for verification purpose. This
field should only be programmed when the INTERFACE_TIMER_EN bit is set to 1'b0. Note: This register
INTERFACE_TI field is sticky.
MER_SCALING
1 Interface timer AER generation enable. Note: This register field is sticky.
INTERFACE_TI
MER_AER_EN
0 Interface timer enable. Note: This register field is sticky.
INTERFACE_TI
MER_EN
3.8.194 Interface Timer Target (INTERFACE_TIMER_TARGET_OFF)
Offset
Register Offset
INTERFACE_TIMER_TA 934h
RGET_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
INTERFACE_TIMER_TARGET
W
Reset 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-16 Reserved
15-0 Interface timer target value. This field should only be programmed when the INTERFACE_TIMER_EN bit
is set to 1'b0. Note: This register field is sticky.
INTERFACE_TI
MER_TARGET
3.8.195 Interface Timer Status (INTERFACE_TIMER_STATUS_OFF)
Offset
Register Offset
INTERFACE_TIMER_ST 938h
ATUS_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SLAVE SLAVE SLAVE MAST MAST CLIEN CLIEN CPL_I MESS

R 0 0 0
_R... _W... _W... ER_... ER_... T2... T1... NT... AGE...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-12 Reserved
11 Slave read address channel timeout.
SLAVE_RD_AD
D_TIMEOUT
10 Slave write data channel timeout.

NXP Semiconductors
PCIe Controller
Field Function
SLAVE_WR_D
ATA_TIMEOUT
9 Slave write address channel timeout.
SLAVE_WR_A
DD_TIMEOUT
8-7 Reserved
6 Master read data channel timeout.
MASTER_RD_
DATA_TIMEOU
T
5 Master write response channel timeout.
MASTER_WR_
RES_TIMEOUT
CLIENT2_INTE
RFACE_TIMEO
UT
CLIENT1_INTE
RFACE_TIMEO
UT
2 Reserved
1 CPL interface timeout.
CPL_INTERFA
CE_TIMEOUT
0 Message interface timeout.
MESSAGE_INT
ERFACE_TIME
OUT

NXP Semiconductors
PCIe Controller
3.8.196 MSI-X Address Match Low (MSIX_ADDRESS_MATCH_LOW_OFF)
Offset
Register Offset
H_LOW_OFF
Function
AXI application writes (MWr) to the address defined in this register (and MSIX_ADDRESS_MATCH_HIGH_OFF), the controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MSIX_ADDRESS_MATCH_LOW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSIX_
R MSIX_
MSIX_ADDRESS_MATCH_LOW AD...
AD...
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-2 MSI-X Address Match Low Address. Note: This register field is sticky.
MSIX_ADDRES
S_MATCH_LO
W
MSIX_ADDRES
S_MATCH_RE
SERVED_1
0 MSI-X Match Enable. Enable the MSI-X Address Match feature when the AXI bridge is present. Note:
MSIX_ADDRES
S_MATCH_EN

NXP Semiconductors
PCIe Controller
3.8.197 MSI-X Address Match High (MSIX_ADDRESS_MATCH_HIGH_OFF)
Offset
Register Offset
H_HIGH_OFF
Function
AXI application writes (MWr) to the address defined in this register (and MSIX_ADDRESS_MATCH_LOW_OFF), the controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0 MSI-X Address Match High Address. Note: This register field is sticky.
MSIX_ADDRES
S_MATCH_HIG
H
3.8.198 MSI-X Doorbell (MSIX_DOORBELL_OFF)
Offset
Register Offset
MSIX_DOORBELL_OFF 948h
Function
When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1), the controller implements the logic and RAM required to
generate MSI-X requests. For more details, see Interrupts†.

NXP Semiconductors
PCIe Controller
For AXI configurations: when your local application writes (MWr) to the address defined in MSIX_ADDRESS_MATCH_LOW_OFF,
the controller will load this register with the contents of the MWr and subsequently create and send MSI-X TLPs.
For non-AMBA configurations: when your local application writes to this register, the controller will create and send MSI-X TLPs.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSIX_DOORBELL_RES
W MSIX_DOORBELL_PF MSIX_DOORBELL_VF
ERVED_...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSIX_ MSIX_
W MSIX_DOORBELL_TC MSIX_DOORBELL_VECTOR
DO... DO...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-29 Reserved
MSIX_DOORB
ELL_RESERVE
D_29_31
28-24 MSIX Doorbell Physical Function. This register determines the Physical Function for the MSI-X
transaction.
MSIX_DOORB
ELL_PF
23-16 MSIX Doorbell Virtual Function. This register determines the Virtual Function for the MSI-X transaction.
MSIX_DOORB
ELL_VF
15 MSIX Doorbell Virtual Function Active. This register determines whether a Virtual Function is used to
generate the MSI-X transaction.
MSIX_DOORB
ELL_VF_ACTIV
E
14-12 MSIX Doorbell Traffic Class. This register determines which traffic class to generate the MSI-X
transaction with.
MSIX_DOORB
ELL_TC
11 Reserved

NXP Semiconductors
PCIe Controller
Field Function
MSIX_DOORB
ELL_RESERVE
D_11
10-0 MSI-X Doorbell Vector. This register determines which vector to generate the MSI-X transaction for.
MSIX_DOORB
ELL_VECTOR
3.8.199 MSI-X RAM Power Mode And Debug Control (MSIX_RAM_CTRL_OFF)
Offset
Register Offset
MSIX_RAM_CTRL_OFF 94Ch
Function
to generate MSI-X requests. For more details, see Interrupts†.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R MSIX_RAM_CTRL_RESERVED_26_31 MSIX_ MSIX_ MSIX_RAM_CTRL_RESERVED_17_23 MSIX_
W RA... RA... RA...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R MSIX_RAM_CTRL_RESERVED_10_15 MSIX_ MSIX_ MSIX_RAM_CTRL_RESERVED_2_7 MSIX_ MSIX_
W RA... RA... RA... RA...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
MSIX_RAM_CT
RL_RESERVE
D_26_31

NXP Semiconductors
PCIe Controller
Field Function
25 MSIX PBA RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access
to the PBA. Use can also use the dbg_pba input to activate debug mode. Debug mode turns off the
MSIX_RAM_CT PF/VF/Offset-based addressing into the RAM and maps the entire table linearly from the base address of
RL_DBG_PBA the BAR (indicated by the BIR) in function 0. Note: This register field is sticky.
24 MSIX Table RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write
access to the Table. Use can also use the dbg_table input to activate debug mode. Debug mode turns
MSIX_RAM_CT off the PF/VF/Offset-based addressing into the RAM and maps the entire table linearly from the base
RL_DBG_TABL address of the BAR (indicated by the BIR) in function 0. Note: This register field is sticky.
E
MSIX_RAM_CT
RL_RESERVE
D_17_23
16 MSIX RAM Control Bypass. The bypass field, when set, disables the internal generation of low power
signals for both RAMs. It is up to the application to ensure the RAMs are in the proper power state before
MSIX_RAM_CT trying to access them. Moreover, the application needs to observe all timing requirements of the RAM
RL_BYPASS low power signals before trying to use the MSIX functionality. Note: This register field is sticky.
MSIX_RAM_CT
RL_RESERVE
D_10_15
9 MSIX PBA RAM Shut Down. Set this bit to drive the cfg_msix_pba_sd output to signal your external logic
to place the MSIX PBA RAM in Shut Down low-power mode. Note: This register field is sticky.
MSIX_RAM_CT
RL_PBA_SD
8 MSIX PBA RAM Deep Sleep. Set this bit to drive the cfg_msix_pba_ds output to signal your external
logic to place the MSIX PBA RAM in Deep Sleep low-power mode. Note: This register field is sticky.
MSIX_RAM_CT
RL_PBA_DS
MSIX_RAM_CT
RL_RESERVE
D_2_7
1 MSIX Table RAM Shut Down. Set this bit to drive the cfg_msix_table_sd output to signal your external
logic to place the MSIX Table RAM in Shut Down low-power mode. Note: This register field is sticky.
MSIX_RAM_CT
RL_TABLE_SD
0 MSIX Table RAM Deep Sleep. Set this bit to drive the cfg_msix_table_ds output to signal your external
logic to place the MSIX Table RAM in Deep Sleep low-power mode. Note: This register field is sticky.
MSIX_RAM_CT
RL_TABLE_DS

NXP Semiconductors
PCIe Controller
3.8.200 Masks for functional safety interrupt events (SAFETY_MASK_OFF)
Offset
Register Offset
SAFETY_MASK_OFF 960h
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 SAFET SAFET SAFET SAFET SAFET SAFET
W Y_... Y_... Y_... Y_... Y_... Y_...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-6 Reserved
5 Mask for functional safety interrupt event 5 (RASDP correctable). Note: This register field is sticky.
SAFETY_INT_
MASK_5
4 Mask for functional safety interrupt event 4 (PCIe correctable). Note: This register field is sticky.
SAFETY_INT_
MASK_4
3 Mask for functional safety interrupt event 3 (PCIe uncorrectable). Note: This register field is sticky.
SAFETY_INT_
MASK_3
2 Mask for functional safety interrupt event 2 (Interface timers). Note: This register field is sticky.
SAFETY_INT_
MASK_2
1 Mask for functional safety interrupt event 1 (CDM register checker). Note: This register field is sticky.
SAFETY_INT_
MASK_1

NXP Semiconductors
PCIe Controller
Field Function
0 Mask for functional safety interrupt event 0 (RASDP). Note: This register field is sticky.
SAFETY_INT_
MASK_0
3.8.201 Status for functional safety interrupt events. (SAFETY_STATUS_OFF)
Offset
Register Offset
SAFETY_STATUS_OFF 964h
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAFET SAFET SAFET SAFET SAFET SAFET

R 0
Y_... Y_... Y_... Y_... Y_... Y_...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-6 Reserved
5 Status for functional safety interrupt event 5 (RASDP correctable).
SAFETY_INT_S
TATUS_5
4 Status for functional safety interrupt event 4 (PCIe correctable).
SAFETY_INT_S
TATUS_4
3 Status for functional safety interrupt event 3 (PCIe uncorrectable).

NXP Semiconductors
PCIe Controller
Field Function
SAFETY_INT_S
TATUS_3
2 Status for functional safety interrupt event 2 (Interface timers).
SAFETY_INT_S
TATUS_2
1 Status for functional safety interrupt event 1 (CDM register checker).
SAFETY_INT_S
TATUS_1
0 Status for functional safety interrupt event 0 (RASDP).
SAFETY_INT_S
TATUS_0
3.8.202 CDM Register Checking Control and Status (PL_CHK_REG_CONTROL_STATUS_OFF)
Offset
Register Offset
PL_CHK_REG_CONTR B20h
OL_STATUS_OFF
Function
Controls register checking and displays status of register checking.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHK_ CHK_ CHK_

R 0
REG... REG... REG...
W W1C W1C W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 CHK_ CHK_
W REG... REG...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-19 Reserved
18 The system has completed a checking cycle.
CHK_REG_CO
MPLETE
17 The system has detected an error in its own checking logic.
CHK_REG_LO
GIC_ERROR
16 The system has detected that there is a bit error in the CDM Register Data.
CHK_REG_CO
MPARISON_ER
ROR
15-2 Reserved
1 Set Continuous Checking Sequence. Note: This register field is sticky.
CHK_REG_CO
NTINUOUS
0 Begins a checking sequence. Note: This register field is sticky.
CHK_REG_STA
RT
3.8.203 CDM Register Checking First and Last address to check (PL_CHK_REG_START_END_OFF)
Offset
Register Offset
PL_CHK_REG_START_ B24h
END_OFF

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
CHK_REG_END_ADDR
W
Reset 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CHK_REG_START_ADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-16 The last address that is checked by the system. Note: This register field is sticky.
CHK_REG_EN
D_ADDR
15-0 The first address that is checked by the system. Note: This register field is sticky.
CHK_REG_STA
RT_ADDR
3.8.204 CDM Register Checking Error Address. (PL_CHK_REG_ERR_ADDR_OFF)
Offset
Register Offset
PL_CHK_REG_ERR_AD B28h
DR_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R CHK_REG_ERR_ADDR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CHK_REG_ERR_ADDR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-0 The address at which an error has been detected. Valid only when the CDM Register Checker
CHK_REG_ER
R_ADDR
3.8.205 CDM Register Checking error PF and VF Numbers (PL_CHK_REG_ERR_PF_VF_OFF)
Offset
Register Offset
PL_CHK_REG_ERR_PF B2Ch
_VF_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 CHK_REG_VF_ERR_NUMBER
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 CHK_REG_PF_ERR_NUMBER
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-28 Reserved
27-16 The VF number at which the error was detected. Valid only when the CDM Register Checker
CHK_REG_VF_
ERR_NUMBER
15-5 Reserved
4-0 The PF number at which the error was detected. Valid only when the CDM Register Checker
CHK_REG_PF_
ERR_NUMBER

NXP Semiconductors
PCIe Controller
3.8.206 Auxiliary Clock Frequency Control (AUX_CLK_FREQ_OFF)
Offset
Register Offset
AUX_CLK_FREQ_OFF B40h
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
AUX_CLK_FREQ
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0
Fields
Field Function
31-10 Reserved
The aux_clk frequency in MHz. This value is used to provide a 1 us reference for counting time during
9-0
low-power states with aux_clk when the PHY has removed the pipe_clk. Frequencies lower than 1 MHz
AUX_CLK_FRE are possible but with a loss of accuracy in the time counted. If the actual frequency (f) of aux_clk does
Q not exactly match the programmed frequency (f_prog), then there is an error in the time counted by the
controller that can be expressed in percentage as: err% = (f_prog/f-1)*100. For example if f=2.5 MHz
and f_prog=3 MHz, then err% =(3/2.5-1)*100 =20%, meaning that the time counted by the controller
on aux_clk will be 20% greater than the time in us programmed in the corresponding time register (for
example T_POWER_ON). Note: This register field is sticky.
Offset
Register Offset
BAR0_MASK 2_0010h
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCI_T
YP...
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Fields
Field Function
31-1 BAR0 Mask

R0_MASK
0 BAR0 Mask Enabled

R0_ENABLED
0b - Disabled
1b - Enabled
Offset
Register Offset
BAR1_MASK 2_0014h
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCI_T
YP...
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Fields
Field Function
31-1 BAR1 Mask

R1_MASK
0 BAR1 Mask Enabled

R1_ENABLED
0b - Disabled
1b - Enabled
Offset
Register Offset
BAR2_MASK 2_0018h
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCI_T
YP...
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Fields
Field Function
31-1 BAR2 Mask

R2_MASK
0 BAR2 Mask Enabled

R2_ENABLED
0b - Disabled
1b - Enabled
Offset
Register Offset
BAR3_MASK 2_001Ch
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCI_T
YP...
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Fields
Field Function
31-1 BAR3 Mask

R3_MASK
0 BAR3 Mask Enabled

R3_ENABLED
0b - Disabled
1b - Enabled
Offset
Register Offset
BAR4_MASK 2_0020h
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCI_T
YP...
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Fields
Field Function
31-1 BAR4 Mask

R4_MASK
0 BAR4 Mask Enabled

R4_ENABLED
0b - Disabled
1b - Enabled
Offset
Register Offset
BAR5_MASK 2_0024h
Function

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCI_T
YP...
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Fields
Field Function
31-1 BAR5 Mask

R5_MASK
0 BAR5 Mask Enabled

R5_ENABLED
0b - Disabled
1b - Enabled

Offset
Register Offset
_OFF_OUTBOUND_0

NXP Semiconductors
PCIe Controller
Register Offset
_OFF_OUTBOUND_1
_OFF_OUTBOUND_2
_OFF_OUTBOUND_3
_OFF_OUTBOUND_4
_OFF_OUTBOUND_5
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 0
CTRL_1_FUNC_NUM
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 INCRE 0
ATTR TD TC TYPE
W AS...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-23 Reserved
22-20 Function Number

CTRL_1_FUNC When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the "iATU
_NUM Control 2 Register" is '0', then the function number used in generating the function part of the requester ID
(RID) field of the TLP is taken from this 5-bit register. The value in this register must be 0h.
When you are using the AXI Bridge, then this field is swapped before AXI decomposition occurs so that the
correct "Max_Read_Request_Size" and "Max_Payload_Size" values are used.
19-14 Reserved

NXP Semiconductors
PCIe Controller
Field Function

GION_SIZE
0b - Maximum ATU region size is 4 GB
1b - Maximum ATU region size is 1 TB
12-11 Reserved
10-9 When the address of an outbound TLP is matched to this region, then the ATTR field of the TLP is
ATTR
8 When the address of an outbound TLP is matched to this region, then the TD field of the TLP is changed
TD
7-5 When the address of an outbound TLP is matched to this region, then the TC field of the TLP is changed
TC
4-0 When the address of an outbound TLP is matched to this region, then the TYPE field of the TLP is
TYPE

Offset
Register Offset
_OFF_OUTBOUND_0
_OFF_OUTBOUND_1
_OFF_OUTBOUND_2
_OFF_OUTBOUND_3
_OFF_OUTBOUND_4
_OFF_OUTBOUND_5

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R REGIO 0 INVER CFG_ DMA_ 0 HEAD INHIBI 0 FUNC 0 TAG_S

SNP
W N_... T_... SHI... BYP... ER_... T... _BY... UB...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
TAG Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
sticky.
REGION_EN
30 Reserved
Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs
29
28 CFG Shift Mode

CFG_SHIFT_M The iATU uses bits [27:12] of the untranslated address (on the AXI slave interface address) to form the BDF
ODE number of the outgoing CFG TLP. This supports the Enhanced Configuration Address Mapping (ECAM)
mechanism (Section 7.2.2 of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing
I/O and MEM TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB
region of the PCIe configuration space.
DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the
27
iATU untranslated. Note: This field is reserved for the SW product. You must set it to '0'. Note: This
DMA_BYPASS register field is sticky.
26-24 Reserved
Header Substitute Enable. When enabled and region address is matched, the iATU fully substitutes
23
bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header
HEADER_SUB with the contents of the LWR_TARGET_RW field in IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i.
STITUTE_EN - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill
bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP
header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms
the new address of the translated region. Note: This register field is sticky.

NXP Semiconductors
PCIe Controller
Field Function
22 Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When
enabled and region address is matched, the iATU marks all TLPs as having no payload data by forcing
INHIBIT_PAYL the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. - 1: Fmt[1] =0 so
OAD that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1
so that TLPs with or without data can be sent. Note: This register field is sticky.
21 Reserved
20 Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID Non-
Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted
SNP Requests outstanding. Note: This register field is sticky.
19 Function Number Translation Bypass. In this mode, the function number of the translated TLP is taken
from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the "iATU Control
FUNC_BYPAS 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register." Note: This register field is sticky.
S
18-17 Reserved
16 TAG Substitute Enable

TAG_SUBSTIT When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP
UTE_EN header with the contents of the TAG field in this register. The expected usage scenario is translation from
AXI MWr to Vendor Defined Msg/MsgD.
15-8 TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set.
TAG
7-0 Reserved
3.8.215 iATU Lower Base Address (IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 -

IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5)
Offset
Register Offset
R_OFF_OUTBOUND_0
R_OFF_OUTBOUND_1

NXP Semiconductors
PCIe Controller
Register Offset
R_OFF_OUTBOUND_2
R_OFF_OUTBOUND_3
R_OFF_OUTBOUND_4
IATU_LWR_BASE_ADD 6_0A08h
R_OFF_OUTBOUND_5
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
LWR_BASE_RW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R LWR_BASE_HW
LWR_BASE_RW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
W
W

NXP Semiconductors
PCIe Controller
3.8.216 iATU Upper Base Address (IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 -

IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5)
Offset
Register Offset
DDR_OFF_OUTBOUND
_0
DDR_OFF_OUTBOUND
_1
DDR_OFF_OUTBOUND
_2
DDR_OFF_OUTBOUND
_3
DDR_OFF_OUTBOUND
_4
IATU_UPPER_BASE_A 6_0A0Ch
DDR_OFF_OUTBOUND
_5
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
UPPER_BASE_RW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
UPPER_BASE_RW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with
31-0
a 32-bit address space, this register is not used and therefore writing to this register has no effect. Note:
UPPER_BASE_ This register field is sticky.
RW

NXP Semiconductors
PCIe Controller
3.8.217 iATU Limit Address (IATU_LIMIT_ADDR_OFF_OUTBOUND_0 -

IATU_LIMIT_ADDR_OFF_OUTBOUND_5)
Offset
Register Offset
_OUTBOUND_0
_OUTBOUND_1
_OUTBOUND_2
_OUTBOUND_3
_OUTBOUND_4
IATU_LIMIT_ADDR_OFF 6_0A10h
_OUTBOUND_5
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
LIMIT_ADDR_RW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R LIMIT_ADDR_HW
LIMIT_ADDR_RW
W
Reset 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
Fields
Field Function
W
W

NXP Semiconductors
PCIe Controller
3.8.218 iATU Lower Target Address (IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0 -

IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5)
Offset
Register Offset
DDR_OFF_OUTBOUND
_0
DDR_OFF_OUTBOUND
_1
DDR_OFF_OUTBOUND
_2
DDR_OFF_OUTBOUND
_3
DDR_OFF_OUTBOUND
_4
IATU_LWR_TARGET_A 6_0A14h
DDR_OFF_OUTBOUND
_5
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0 When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0'

(normal operation):

NXP Semiconductors
PCIe Controller
Field Function
LWR_TARGET • LWR_TARGET_RW[31:12] forms MSB's of the Lower Target part of the new address of the
_RW_OUTBOU translated region
ND
• LWR_TARGET_RW[11:0] are not used. (The start address must be aligned to a 4 KB boundary, so
the lower bits of the start address of the new address of the translated region [bits 11:0] are always
'0').
When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1',
LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword header) or bytes 12-15 (for 4 dword header)
of the outbound TLP header. Usage scenarios include the transmission of Vendor Defined Messages where
the controller determines the content of bytes 12 to 15 of the TLP header.
3.8.219 iATU Upper Target Address (IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 -

IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5)
Offset
Register Offset
_ADDR_OFF_OUTBOU
ND_0
_ADDR_OFF_OUTBOU
ND_1
_ADDR_OFF_OUTBOU
ND_2
_ADDR_OFF_OUTBOU
ND_3
_ADDR_OFF_OUTBOU
ND_4
IATU_UPPER_TARGET 6_0A18h
_ADDR_OFF_OUTBOU
ND_5

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
UPPER_TARGET_RW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
UPPER_TARGET_RW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0 Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region.
UPPER_TARG
ET_RW
3.8.220 iATU Upper Limit Address (IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0 -

IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5)
Offset
Register Offset
R_OFF_OUTBOUND_0
R_OFF_OUTBOUND_1
R_OFF_OUTBOUND_2
R_OFF_OUTBOUND_3
R_OFF_OUTBOUND_4
IATU_UPPR_LIMIT_ADD 6_0A20h
R_OFF_OUTBOUND_5
Function
The maximum size of an address translation region is 1 TB. This register is only used when the INCREASE_REGION_SIZE
field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1'.

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UPPR_LIMIT_ADDR_RW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-8
systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_OUTBOUND_i
UPPR_LIMIT_A is '1'. These bits are always '0'.
DDR_HW
UPPR_LIMIT_A IATU_REGION_CTRL_1_OFF_OUTBOUND_i is '1' Note: This register field is sticky.
DDR_RW

Offset
Register Offset
_OFF_INBOUND_0
_OFF_INBOUND_1
_OFF_INBOUND_2
_OFF_INBOUND_3

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 0
CTRL_1_FUNC_NUM
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 INCRE 0
ATTR TD TC TYPE
W AS...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-23 Reserved
Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a
22-20
MEM-I/O transaction matches a BAR in the function corresponding to this value, then address translation
CTRL_1_FUNC proceeds. This check is only performed if the "Function Number Match Enable" bit of the "iATU Control
_NUM 2 Register" is set. - CFG0/CFG1: When the destination function number as specified in the routing ID of
the TLP header matches the function, then address translation proceeds. This check is only performed if
the "Function Number Match Enable" bit of the "iATU Control 2 Register" is set. Note: This register field
is sticky.
19-14 Reserved

GION_SIZE
0b - Maximum ATU Region size is 4 GB
1b - Maximum ATU Region size is 1 TB
12-11 Reserved
10-9 When the ATTR field of an inbound TLP is matched to this value, then address translation proceeds
(when all other enabled field-matches are successful). This check is only performed if the "ATTR Match
ATTR Enable" bit of the "iATU Control 2 Register" is set. Note: This register field is sticky.
8 When the TD field of an inbound TLP is matched to this value, then address translation proceeds (when
all other enabled field-matches are successful). This check is only performed if the "TD Match Enable" bit
TD of the "iATU Control 2 Register" is set. Note: This register field is sticky.
7-5 When the TC field of an inbound TLP is matched to this value, then address translation proceeds (when
all other enabled field-matches are successful). This check is only performed if the "TC Match Enable" bit
TC of the "iATU Control 2 Register" is set. Note: This register field is sticky.

NXP Semiconductors
PCIe Controller
Field Function
4-0 When the TYPE field of an inbound TLP is matched to this value, then address translation proceeds
(when all other enabled field-matches are successful). Note: This register field is sticky.
TYPE

Offset
Register Offset
_OFF_INBOUND_0
_OFF_INBOUND_1
_OFF_INBOUND_2
_OFF_INBOUND_3
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R REGI MATC INVER CFG_ FUZZ 0 RESPONSE_C SINGL 0 Reserv 0 FUNC 0 ATTR_
W ON_... H_M... T_... SHI... Y_T... ODE E_... ed _NU... MA...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R TD_M TC_M MSG_ 0

BAR_NUM Reserved
W ATC... ATC... TYP...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
sticky.
REGION_EN
Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that
30
is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: - 0: Address Match Mode.
MATCH_MODE The iATU operates using addresses as in the outbound direction. The Region Base and Limit Registers

NXP Semiconductors
PCIe Controller
Field Function
must be setup. - 1:BAR Match Mode. BAR matching is used. The "BAR Number" field is relevant. Not
used for RC. For CFG0 TLPs, this field is interpreted as follows: - 0: Routing ID Match Mode. The iATU
interprets the Routing ID (Bytes 8 to 11 of TLP header) as an address. This corresponds to the upper 16
bits of the address in MEM-I/O transactions. The Routing ID of the TLP must be within the base and limit
of the iATU region for matching to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions
as address matches. The routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0
TLPs should be processed regardless of the Bus number. For MSG/MSGD TLPs, this field is interpreted
as follows: - 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound
MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. -
1: Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU
ignores the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header,
but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits [15:0] of
the Region Upper Base register should be programmed with the required Vendor ID. The lower Base
and Limit Register should be programmed to translate TLPs based on vendor specific information in
the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN = 1 AND
MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored. Note: This register field is sticky.
29 Invert Mode. When set the address matching region is inverted. Therefore, an address match occurs
28 CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits
[27:12] of the address to the bus/device and function number. This allows a CFG configuration space
CFG_SHIFT_M to be located in any 256MB window of your application memory space using a 28-bit effective address.
ODE Shifts bits [31:16] of the untranslated address to form bits [27:12] of the translated address. Note: This
27 Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of the TLP TYPE field against
the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0
FUZZY_TYPE_ and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical - The Routing field of Msg/MsgD TLPs
MATCH_CODE is ignored - FetchAdd, Swap and CAS are seen as identical. For example, CFG0 in the TYPE field in the
"iATU Control 1 Register" matches against an inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP. Note:
26 Reserved
25-24 Response Code. Defines the type of response to give for accesses matching this region. This overrides
the normal RADM filter response. Note that this feature is not available for any region where Single
RESPONSE_C Address Location Translate is enabled. - 00 - Normal RADM filter response is used. - 01 - Unsupported
ODE request (UR) - 10 - Completer abort (CA) - 11 - Not used / undefined / reserved. Note: This register field
is sticky.
23 Single Address Location Translate Enable. When enabled, Rx TLPs can be translated to a single
address location as determined by the target address register of the iATU region. The main usage
SINGLE_ADDR scenario is translation of Messages (such as Vendor Defined or ATS Messages) to MWr TLPs when the
_LOC_TRANS_ AXI bridge is enabled. Note: This register field is sticky.
EN
22 Reserved

NXP Semiconductors
PCIe Controller
Field Function
21 Reserved
20 Reserved
19 Function Number Match Enable. Ensures that a successful Function Number TLP field comparison
match (see Function Number field of the "iATU Control 1 Register") occurs (in MEM-I/O and CFG0/CFG1
FUNC_NUM_M transactions) for address translation to proceed. Note: This register field is sticky.
ATCH_EN
18-17 Reserved
16 ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field
of the "iATU Control 1 Register") occurs for address translation to proceed. Note: This register field is
ATTR_MATCH_ sticky.
EN
15 TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the "iATU
TD_MATCH_E
N
14 TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the "iATU
TC_MATCH_E
N
13 Message Type Match Mode. When enabled, and if single address location translate enable is set, then
inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound
MSG_TYPE_M register (=>TYPE[4:3]=2'b10) will be translated. Message type match mode overrides any value of
ATCH_MODE MATCH_MODE field in this register. Usage scenarios for this are translation of VDM or ATS messages
when AXI bridge is configured on client interface. Note: This register field is sticky.
12-11 Reserved
10-8 BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the normal
internal BAR address matching mechanism " is the same as this field, address translation proceeds
BAR_NUM (when all other enabled field-matches are successful). This check is only performed if the "Match Mode"
bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 - 010b - BAR2 - 011b - BAR3
- 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO translation would require either
00100b or 00101b in the inbound TLP TYPE; the BAR Number set in the range 000b - 101b and that
BAR configured as an IO BAR. Note: This register field is sticky.
7-0 Reserved

NXP Semiconductors
PCIe Controller
3.8.223 iATU Lower Base Address (IATU_LWR_BASE_ADDR_OFF_INBOUND_0 -

IATU_LWR_BASE_ADDR_OFF_INBOUND_3)
Offset
Register Offset
R_OFF_INBOUND_0
R_OFF_INBOUND_1
R_OFF_INBOUND_2
R_OFF_INBOUND_3
Function
The minimum size of an address translation region is 4 KB. The lower 12 bits are zero.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
LWR_BASE_RW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R LWR_BASE_HW
LWR_BASE_RW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
W
W

NXP Semiconductors
PCIe Controller
3.8.224 iATU Upper Base Address (IATU_UPPER_BASE_ADDR_OFF_INBOUND_0 -

IATU_UPPER_BASE_ADDR_OFF_INBOUND_3)
Offset
Register Offset
DDR_OFF_INBOUND_0
DDR_OFF_INBOUND_1
DDR_OFF_INBOUND_2
DDR_OFF_INBOUND_3
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
UPPER_BASE_RW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
UPPER_BASE_RW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0 Forms bits [63:32] of the start (and end) address of the address region to be translated. Note: This
UPPER_BASE_
RW
3.8.225 iATU Limit Address (IATU_LIMIT_ADDR_OFF_INBOUND_0 -

IATU_LIMIT_ADDR_OFF_INBOUND_3)
Offset
Register Offset
_INBOUND_0

NXP Semiconductors
PCIe Controller
Register Offset
_INBOUND_1
_INBOUND_2
_INBOUND_3
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
LIMIT_ADDR_RW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R LIMIT_ADDR_HW
LIMIT_ADDR_RW
W
Reset 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
Fields
Field Function
W
W

NXP Semiconductors
PCIe Controller
3.8.226 iATU Lower Target Address (IATU_LWR_TARGET_ADDR_OFF_INBOUND_0 -

IATU_LWR_TARGET_ADDR_OFF_INBOUND_3)
Offset
Register Offset
DDR_OFF_INBOUND_0
DDR_OFF_INBOUND_1
DDR_OFF_INBOUND_2
DDR_OFF_INBOUND_3
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
LWR_TARGET_RW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R LWR_TARGET_HW
LWR_TARGET_RW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-12 Forms MSB's of the Lower Target part of the new address of the translated region.
LWR_TARGET These bits are always '0'.
_RW
11-0 Forms the LSB's of the Lower Target part of the new address of the translated region.
LWR_TARGET The start address must be aligned to a 4 KB boundary (in address match mode); and to the Bar size
_HW boundary (in BAR match mode) so that these bits are always '0'. If the BAR is smaller than the iATU region
size, then the iATU target address must align to the iATU region size; otherwise it must align to the BAR size.

NXP Semiconductors
PCIe Controller
3.8.227 iATU Upper Target Address (IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0 -

IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3)
Offset
Register Offset
_ADDR_OFF_INBOUND
_0
_ADDR_OFF_INBOUND
_1
_ADDR_OFF_INBOUND
_2
_ADDR_OFF_INBOUND
_3
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
UPPER_TARGET_RW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
UPPER_TARGET_RW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In
31-0
systems with a 32-bit address space, this register is not used and therefore writing to this register has no
UPPER_TARG effect. Note: This register field is sticky.
ET_RW

NXP Semiconductors
PCIe Controller
3.8.228 iATU Upper Limit Address (IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0 -

IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3)
Offset
Register Offset
R_OFF_INBOUND_0
R_OFF_INBOUND_1
R_OFF_INBOUND_2
R_OFF_INBOUND_3
Function
The maximum size of an address translation region is 1 TB. This register is only used when the INCREASE_REGION_SIZE field
in IATU_REGION_CTRL_1_OFF_INBOUND_i is '1'.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UPPR_LIMIT_ADDR_RW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-8
systems and when the INCREASE_REGION_SIZE field in IATU_REGION_CTRL_1_OFF_INBOUND_i is
UPPR_LIMIT_A '1'. These bits are always '0'.
DDR_HW
UPPR_LIMIT_A IATU_REGION_CTRL_1_OFF_INBOUND_i is '1' Note: This register field is sticky.
DDR_RW

NXP Semiconductors
PCIe Controller
3.9 Functional description

The PCI Express protocol relies on a requestor/completer relationship where one device requests that some desired action be
performed by some target device and the target device completes the task and responds. Usually the requests and responses
occur through a network of links, but to the requester and to the completer, the intermediate components are transparent.
Intermediate Ultimate
Requester Link Link
component(s) completer
Figure 8. Requester/completer relationship
Each PCI Express device is divided into two halves -- transmit (TX) and receive (RX). Each of these halves is further divided into
three layers -- transaction, data link, and physical, as shown in the following figure.
Figure 9. PCI Express high-level layering
Packets are formed in the transaction layer (TLPs) and data link layer (DLLPs), and each subsequent layer adds the necessary
encodings and framing, as shown in the following figure. As packets are received, they are decoded and processed by the same
layers but in reverse order, so they may be processed by the layer or by the device application software.
Figure 10. PCI Express packet flow

NXP Semiconductors
PCIe Controller
3.9.1 Transaction layer

The transaction layer sends and receives transaction layer packets (TLPs) between the data link layer and the internal platform.
It also controls the ordering of both received and transmitted TLPs and exchanges flow control information with the transaction
layer of the device on the other side of the link. The transaction layer is responsible for the following tasks:
• Processes read/write requests from software
• Processes inbound packets from link partner
• Split transaction protocol modeling
• Handles PCI-Express ordering rules
• 32-bit and 64-bit memory addressing
• 32-bit addresses use 3 DW (4-byte) TLPs
• 64-bit addresses use 4 DW (4-byte) TLPs
• Four address spaces: memory, I/O, configuration and message
• Implements flow control logic for for both transmit and receive direction
• [DIP_PCIE_SS_HW_IP_0002]Transaction layer error detection and logging[end]
• Optional 32-bit end-to-end CRC (ECRC) support
3.9.2 Data Link Layer

The primary responsiblity of the data link layer is to ensure data integrity of a packet. On the transmit side, it does this by appending
a link CRC ( LCRC) to the packet received from the transaction layer and passes it to the physical layer. On the receive side, a
packet received from the physical layer is checked to make sure that the LCRC is correct before passing it to the transaction layer.
The data link layer is responsible for the following tasks:
• Ensures reliable delivery of packet across the link
• [DIP_PCIE_SS_HW_IP_0002]Data integrity, error detection and management[end]
• Accepts power management request from the transaction layer and conveys power managed state to the transaction layer
• Flow control initialization
• Data link layer packet (DLLP) for link support

NXP Semiconductors
PCIe Controller
3.9.3 MAC Layer
Figure 11. PCI Express Character to Symbol Mapping
Figure 12. Bit Transmission Order on Physical Lane-x1 Example
3.9.4 Architecture
This section describes implementation details of the PCI Express controller.
3.9.4.1 PCI Express Transactions

The following table contains the list of transactions that the PCI Express controller supports as an initiator and a target.
Table 15. PCI Express Transactions
PCI Express Supported as Supported as Definition

Transaction an Initiator a Target
Mrd Yes Yes Memory Read Request

NXP Semiconductors
PCIe Controller
Table 15. PCI Express Transactions (continued)
PCI Express Supported as Supported as Definition

Transaction an Initiator a Target
MRdLk No No Memory Read Lock. As a target, CplLk with UR status is returned.
MWr Yes Yes Memory Write Request to memory-mapped PCI-Express space
IORd Yes (RC only) No I/O Read request. As a target, Cpl with UR status is returned.
IOWr Yes (RC only) No I/O Write Request. As a target, Cpl with UR status is returned.
CfgRd0 Yes (RC only Yes Configuration Read Type 0.
CfgWr0 Yes (RC only) Yes Configuration Write Type 0.
CfgRd1 Yes (RC only) No Configuration Read Type 1. As a target, Cpl with UR status is returned.
CfgWr1 Yes (RC only) No Configuration Write Type 1. As a target, Cpl with UR status is returned.
Msg Yes Yes Message Request. Message without data is not forwarded to memory.
MsgD Yes (RC only) Yes (EP only) Message Request with Data payload. Note that Set_Slot_Power_Limit is the
only message with data that is supported and then only when the controller is an
initiator and in RC mode or a target and in EP mode.
Cpl Yes Yes Completion without Data
CplD Yes Yes Completion with Data
CplLk No Yes Completion for Locked Memory Read without Data. The only time that CplLk is
returned with UR status is when the controller receives a MRdLk command.
CplDLk No No Completion for Locked Memory Read with Data
3.9.4.2 Lane reversal

This controller supports an x2 link width. It also supports PCIe lane reversal as part of the PCIe training operations.
3.9.4.3 Transaction ordering rules

In general, transactions are serviced in the order that they are received. However, transactions can be reordered as they are
sent due to a stalled condition such as a full internal buffer. The following table describes the transaction ordering rules for this
device.

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PCIe Controller
Table 16. PCI Express controller TLP transaction ordering rules
Row pass column? Posted request Non-posted request Completion
Memory write or Read request I/O or Read I/O or

message (Col 3) Configuration completion (Col configuration
request (col 2) write request 5) write completion
(col 4) (col 6)
Posted request Memory write or a) No1 Yes Yes a) Yes2 a) Yes2

message
b) No1 b) N/A3 b) N/A3
request (row A)
Non-posted Read request No No No a) No4 a) No4

request (row B)
b) Yes5 b)Yes5
I/O or No No No a) No4 a) No4

configuration
b) Yes5 b) Yes5
write request
(Row C)
Completion Read a) No6 Yes Yes a) No8 No

completion (row
b) Yes7 b) No8
D)
I/O or a) No6 Yes Yes No No

configuration
b) Yes7
write completion
(row E)
1. Regardless of the setting of the relaxed ordering (RO) bit, a posted request cannot bypass another posted request.
2. Regardless of the setting of the relaxed ordering bit, a posted request can always bypass a completion.
3. N/A indicates that the original rules at these entries defined by the PCI Express Base Specification do not apply to RC or
EP.
4. A non-posted request cannot bypass a completion if the relaxed ordering bit is cleared (that is, RO = 0).
5. A non-posted request can bypass a completion if the relaxed ordering bit is set (that is, RO = 1).
6. A read completion, I/O write completion, or configuration write completion cannot bypass a posted request if the relaxed
ordering bit is cleared (that is, RO = 0).
7. A read completion, I/O write completion, or configuration write completion can bypass a posted request if the relaxed
ordering bit is set (that is, RO = 1).
8. Regardless of the setting of the relaxed ordering bit, a read completion cannot bypass another read completion.
In general, the following points summarize the ordering rules for sending the next outstanding request:
• A posted request can bypass all other transactions except another posted request.
• A non-posted request cannot bypass posted or other non-posted requests, but it can bypass a completion if the relaxed
ordering (RO) bit is set. (See Table 16).
• A completion can bypass posted requests if the relaxed ordering (RO) bit is set and can bypass non-posted transactions.
However, a completion cannot bypass other completions.
3.9.5 Reliability, availability, and serviceability (RAS)†

This section discusses how the controller maintains the integrity of the link using different methods at different points. It also
discusses error injection and traffic, error, and state logging.

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PCIe Controller
3.9.5.1 RAS wire protection (ECRC)†

The controller uses the optional ECRC checksum, as defined in the PCIe specification, to protect the wire part of the link. The
controller inserts the ECRC in the transmit logic and checks it in the receive logic.
3.9.5.1.1 Generation†
It is expected that the ECRC is not present in traffic that your application is presenting on the transmit interfaces of the controller.
The controller generates and inserts the ECRC. When you are not using the AXI bridge, then you should set client0_tlp_td
=0. To enable ECRC insertion, set the ECRC_GEN_EN field of the ADV_ERR_CAP_CTRL_OFF register.
When you select the address alignment feature (GLOB_ADDR_ALIGN_EN =1) and you are not using the AXI bridge, your
application must set clientN_addr_align_en =0 for those TLPs that contain ECRC (TD bit =1).
3.9.5.1.2 Checking†
When the ECRC is present, the controller checks it and removes it from the TLP. To enable ECRC checking, set the
ECRC_CHECK_EN field of the ADV_ERR_CAP_CTRL_OFF AER register.
By default, when the controller detects a TLP with an ECRC error, it performs the following:
• Discards[3] the TLP
• Generates a completion (for non-posted requests) with the completion status set to CA or UR
• Sets the status in the PCI-compatible status register
• Sets the status in the AER registers (when you enable AER)
• Generates an error message (upstream port only)
3.9.5.2 RAS data protection (DP)†

For the parts of the controller outside of ECRC/LCRC protection, you can use the RAS DP feature consisting of:
• Datapath Protection (ECC or Parity)
For Tx traffic, your local application logic must add ECC or parity protection codes[4] to traffic using:
— client0_tlp_hdr_prot and client1_tlp_hdr_prot for the TLP header.
— Additional MSBs on client0_tlp_data and client1_tlp_data for the TLP data.
— Additional MSBs on client0_tlp_prfx and client1_tlp_prfx for the TLP prefixes.
— For AXI configurations: use slv_awaddrp, slv_araddrp, slv_wdatap, and slv_rdatap.
For Rx traffic, your local application must check the protection codes on:
— radm_trgt1_hdr_prot and radm_bypass_hdr_prot for the TLP header.
— The MSBs on radm_trgt1_tlp_data and radm_bypass_tlp_data for the TLP data.
— The MSBs on radm_trgt1_tlp_ptfx and radm_bypass_tlp_prfx for the TLP prefixes.
— For AXI configurations: mstr_awaddrp, mstr_araddrp, mstr_wdatap, and mstr_rdatap.
• RAM Protection (ECC on data and Parity on address)
An ECC checksum is calculated and added to data that is written to the RAM. When the data is read from the RAM, then the
controller recalculates the ECC and compares it against the value read from RAM. RAM ECC protection is provided for all
of the RAMs in the controller, except for the RAS-DES RAM. ECC corrects single-bit errors and reports (without correction)
multi-bit errors.
The basic ECC module is based on http://www.synopsys.com/dw/ipdir.php?c=DW_ecc.
[3] You can program the controller to forward the TLP.

[4] For details on how to calculate the protection codes, see the description of these signals in the Signal Descriptions chapter.

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PCIe Controller
The controller has a set of RAS DP registers as defined in Table 17. For detailed descriptions of how you use them, see PCIE_EP
register descriptions and PCIE_RC register descriptions.
There is one set of common capability registers shared across all physical functions which can be accessed through each function.
The exception is the NEXT_OFFSET field in the capability header register.
Table 17. RAS DP vendor-specific extended capability (VSEC registers)
Register Description
RASDP_EXT_CAP_HDR_OFF Vendor-Specific Extended Capability Header.
RASDP_VENDOR_SPECIFIC_HDR_OFF Vendor Specific Header.
RASDP_ERROR_PROT_CTRL_OFF Error Protection Control.
RASDP_CORR_COUNTER_CTRL_OFF Corrected error (1-bit ECC) counter selection and control.
RASDP_CORR_COUNT_REPORT_OFF Corrected error (1-bit ECC) counter data.
RASDP_UNCORR_COUNTER_CTRL_OFF Uncorrected error (2-bit ECC and parity) counter selection

and control.
RASDP_UNCORR_COUNT_REPORT_OFF Uncorrected error (2-bit ECC and parity) counter data.
RASDP_ERROR_INJ_CTRL_OFF Error injection control.
RASDP_CORR_ERROR_LOCATION_OFF Corrected errors locations.
RASDP_UNCORR_ERROR_LOCATION_OFF Uncorrectable errors locations.
RASDP_ERROR_MODE_EN_OFF RASDP error mode enable.
RASDP_ERROR_MODE_CLEAR_OFF RASDP error mode clear.
RASDP_RAM_ADDR_CORR_ERROR_OFF RAM Address where a corrected error (1-bit ECC) has

been detected.
RASDP_RAM_ADDR_UNCORR_ERROR_OFF RAM Address where an uncorrected error (2-bit ECC) has

been detected.

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CORR_CLEAR _COUNTERS
CORR_EN_COUNTERS
CORR_COUNTER_SELECTION _REGION [3:0]
CORR_COUNTER_SELECTION [7:0]
Counter j
Software Write
Counter0
RST
EN
Region i
Counter j
error
RASDP_CORR_COUNTER_CONTROL_OFF
CORR_COUNTER_SELECTED [7:0]
Region 0
Counters CORR_COUNTER_SELECTION _REGION [3:0]
Software
. CORR_COUNTER[7:0]
Read
.
. Counter j
RASDP_CORR_COUNT_REPORT_OFF
Counter0
RST
EN
error
Region i
Counters
Figure 13. RAS DP register access to error counters (same method applies to uncorrectable errors)
3.9.5.2.1 RAM protection features†
Table 18. RAM protection features
Feature Availability
RAM Data Protection ECC1
RAM Types Protected Internal/External
# Errors Detectable 1, 2
# Errors Correctable 1
1-bit errors are Correctable Yes
2-bit errors are Uncorrectable Yes
Programmable Correction Enable/Disable Per Region2 Yes

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Table 18. RAM protection features (continued)
Corrected Data Rewritten to RAM No
Core Regenerates ECC Code at Output of RAM When Uncorrectable (2-bit) Error Detected No
ECC Protection Range
32-bit for 32-bit controller datapath width Yes
64-bit all other controller datapath widths Yes
ECC Code Size (8 bits ECC per 64 bits of RAM data)
<= 26-bit RAM Data 6 bits
Optional Pipeline Stage No
RAM Address Protection Parity
Number of Bits per Address Bus 1
Address Parity Generated by Core Yes
Address Parity Checked by Core3 No
1. See Limitations.
2. Using the RASDP_ERROR_PROT_CTRL_OFF register.
3. The core does not check the address parity. RAM address parity checking and error handling is application specific.
3.9.5.2.2 Datapath/interface protection features†
Table 19. Datapath/interface protection features
Datapath (Header and Data) Protection Parity/ECC
Protection From Application Interfaces1to LCRC Insertion/Extraction
Core Expects Application to Supply Parity/ECC on TX Path Interfaces Yes
Core Strips Parity/ECC After LCRC Insertion on TX Path Yes
Core Inserts Parity/ECC Before LCRC Extraction on RX Path Yes
Core Passes Parity/ECC to Application on RX Path Yes
Core Checks and Recalculates Protection Codes at all Internal Processing (Data Manipulation) Steps2 Yes

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Table 19. Datapath/interface protection features (continued)
# Errors Detectable
ECC 1,2
Parity 1
# Errors Correctable
ECC 1
Parity 03
Programmable ECC Correction Enable/Disable Per Region4 Yes
Configurable ECC Correction On/Off using 8-bit odd parity Yes
ECC Protection Range
32-bit for 32-bit controller datapath width Yes
64-bit all other controller datapath widths Yes
ECC Code Size (8 bits ECC per 64 bits5of datapath)
32-bit Datapath 7 bits
Parity Protection Range
8-bit Yes
32-bit No
64-bit No
Selectable Odd/Even Parity Yes
1. See Limitations.
2. Detailed report of all check points is available at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/
5.00a/doc/RASDP_CheckPoints.pdf.
3. The controller pulses app_parity_err[2:0]output bus. Your application can OR the bus bits and drive the Uncorrectable
Error bit of the app_err_bus input. This is not required when RASDP error mode is enabled because the controller handles the
parity error as an uncorrectable error in this mode.
4. Using the RASDP_ERROR_PROT_CTRL_OFF register.
5. Except for 32-bit datapath.

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3.9.5.2.3 Error handling (RAM and datapath/interface protection)†
Table 20. Error handling (RAM and datapath/interface protection)
Core Enters RASDP Error Mode1Upon Detection of First Uncorrectable Error
Core sets cfg_rasdp_error_mode =1 (or slv_rasdp_error_mode/mstr_rasdp_error_mode) Yes
Wire Access to CDM/ELBI Registers Suspended (to Prevent Corruption of the Register Config Space) Yes
Rx Errored TLPs are Forwarded to Your Application Yes
• Subsequent Rx TLPs not Guaranteed to be Correct; you Must Discard all TLPs2 Yes
Tx TLP Handling (32-bit, 64-bit Datapath configurations)
• Bad TLP is Nullified3 (EDB Inserted and LCRC Inverted) and Transmitted Yes
• Subsequent TLPs are Nullified and Transmitted Yes
• In-progress Replay is Nullified and Transmitted Yes
• Subsequent Replays are Silently Dropped Yes
Tx TLP Handling (128-bit, 256-bit Datapath configurations which can carry two TLPs per clock cycle
• Bad TLP is Silently Dropped4 Yes
• Subsequent TLPs are Silently Dropped Yes
• In-progress Replay is Nullified and Transmitted Yes
• Subsequent Replays are Silently Dropped Yes
Credits Accuracy Retained5 No
Uncorrectable6 Error is Logged Yes
Uncorrectable Internal Error Reported (AER) Yes7
Instruct Core to Exit Error Mode by Writing to RASDP_ERROR_MODE_CLEAR_OFF Register Through DBI Yes
Uncorrectable Errors Propagate and Cause an Error in Some Subsequent Check Points (Error Pollution) Yes
Note: The controller attempts a best-effort recovery in RASDP Error Mode (after detection of an uncorrectable error). For more
information, see footnotes j, k, l, and m. Synopsys reserves the right to modify this best-effort behavior if deemed necessary.
Correctable8Error Handling
Correctable Error is Logged Yes
Correctable Internal Error Reported (AER) Yes
TLP is Modified/Corrected. Yes

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Table 20. Error handling (RAM and datapath/interface protection) (continued)
Errors Reported When Detected (Immediately) Yes
Error Correction Enable/Disable Control (Per TX/RX Direction and Per-Layer) Yes
9
1. You can disable RASDP error mode by writing to the to RASDP_ERROR_MODE_EN_OFF register. This is not recommended.
2. In RASDP error mode, TLPs are not guaranteed to be correct. You must discard all TLPs when this signal is high.
3. The controller might nullify TLPs that were received prior to the bad TLP.
4. The controller might drop TLPs that were received prior to the bad TLP.
5. The controller implements a best-effort approach in accounting for credits under uncorrectable error conditions. However,
credit inaccuracies are unavoidable in such conditions. This might result in performance degradation or triggering of overflow
protection mechanisms.
6. 2-bit ECC and all parity errors.
7. The core only reports uncorrectable errors when it exits RASDP error mode.
8. 1-bit ECC errors.
9. If the controller is capable of single bit error correction, disabling ECC error correction does not change the nature of the
errors and their reporting. A single-bit error is reported as a correctable error although correction might be disabled.
3.9.5.2.4 Statistics and error injection features†
Table 21. Statistics and error injection features
Error Injection (Per TLP)
Programmable1 1-bit or 2-bit Injection Yes
Programmable Continuous or Fixed-Number (n) Injection Modes Yes
Programmable Global Enable/Disable Yes
Programmable Selectable Location Where Injection Occurs Yes
Error Statistics2
Counts # Correctable Errors Yes
Counts # Uncorrectable Errors Yes
Reports Location of First and Last Errors (Correctable and Uncorrectable) Yes
Reports RAM Addresses3 of Detected Errors (Correctable and Uncorrectable) Yes
1. Using the RASDP_ERROR_INJ_CTRL_OFF register.

2. A single RASDP error might increment more than one counter.
3. RASDP_RAM_ADDR_UNCORR_ERROR_OFF and RASDP_RAM_ADDR_UNCORR_ERROR_OFF registers.

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3.9.5.2.5 Limitations†
Table 22. Limitations
Module or datapath Protected by RAS

DES?
iMSIX-TX module RAMs No
RAS DES RAM No
LBC datapath (DBI or wire access to CDM/ELBI) No
MSI or MSI-X interfaces No
Vendor message interface (VMI) No
iMSIX-TX module datapath No
With AXI configuration1,2
ECC (RAM)3 Yes
ECC (datapath) No
Parity (datapath) on payload data Yes
Parity (datapath) on header4 Yes
Error injection No
With DMA configuration
ECC (read buffer RAM)5 Yes
ECC (DMA context RAM) Yes
ECC (datapath) No
Parity (datapath) Yes
Error injection No
1. When RAS is enabled RTRGT1 address width (FLT_Q_ADDR_WIDTH) can be either 32 or 64, other values are not
supported by the controller.
2. When an uncorrectable RAS.DP error is detected by the AXI logic, the following scenarios apply:
• If the payload data is corrupted but the bridge is functional, no reset is required to resume normal operation.
• If the header is corrupted and bridge is in an inconsistent state a hot/cold reset is required to resume normal operation.
3. RAM protection cannot be enabled without datapath protection.
4. The complete TLP payload data is protected, but only the address part of the header is fully protected inside the AXI
bridge. The remainder of the header (carried on the *_misc_info_* signals) is not protected everywhere inside the AXI
bridge and is routed without parity or ECC. It is however fully protected in the rest (native part) of the controller. The
applied countermeasures protect against unintentional hazards, but not necessarily against intentional threats (attacks) by
humans.
5. A single RASDP error might increment more than one counter.
3.9.5.3 RAS Debug, Error Injection, and Statistics (DES)†

The RAS DES feature consists of:
• General Diagnostic Support (Legacy Internal Probe Points).
• Event Counter Support (Error and Non-Error).
• Error Injection Support (ECRC, LCRC, SEQ#, Nullify, Header, Ack/Nak block, Ksymbol, FC Update)
• Time-based Analysis Support (RX/TX data throughput and time spent in each low-power LTSSM state)

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• Silicon Debug Support (Control and Status of PIPE, Deskew, Ack/Nak, Reversal, FC, EQ, LTSSM, Replay)
3.9.5.3.1 Event counter support†

Your application can use the registers in Table 23.
Table 23. Event Counter VSEC Registers
RAS_DES_CAP_HEADER_REG Vendor-Specific Extended Capability Header.
VENDOR_SPECIFIC_HEADER_REG Vendor-Specific Header.
EVENT_COUNTER_CONTROL_REG Event Counter Control.
EVENT_COUNTER_DATA_REG Event Counter Data.

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PCIe Controller
EVENT_COUNTER_CLEAR [1:0] 1:0
EVENT_COUNTER_ENABLE [2:0] 4:2
EVENT_COUNTER_EVENT_SELECTION [11:8] 27:24
EVENT_COUNTER_EVENT_SELECTION [7:0] 23:16
EVENT_COUNTER_LANE_SELECT [3:0] 11:8
Group i
RST
EN
Event j
Lane k
event
Software Write
Event Counter
* Group 0
* Event 0
* Lane 0
EVENT_COUNTER_CONTROL_REG
▪
▪
▪
RST
EN
Software Read
event
Event Counter EVENT_COUNTER_DATA_REG

* Group i
* Event j
* Lane k
Figure 14. Event Counter Register Access
3.9.5.3.2 Event counter data details†

The following tables provide the Group/Event numbers which are required when using the EVENT_COUNTER_CONTROL_REG
viewport control register to read each of the event counters. Some of the event counters only exist for specific configurations.
Groups 5-7 are implemented in RAM as indicated. The group # is set by EVENT_COUNTER_EVENT_SELECTION[11:8]and the
event # is set by EVENT_COUNTER_EVENT_SELECTION[7:0]
Table 24. Event Counter Group #0 (4-bit Layer1 Error Counter Per-Lane)
Event # Description Note
0x00 EBUF Overflow -

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PCIe Controller
Table 24. Event Counter Group #0 (4-bit Layer1 Error Counter Per-Lane) (continued)
0x01 EBUF Under-run -
0x02 Decode Error -
0x03 Running Disparity Error -
0x04 SKP OS Parity Error Gen3
0x05 SYNC Header Error Gen3
0x06 Rx Valid de-assertion RxValid de-assertion without EIOS(s).
Table 25. Event Counter Group #1 (8-bit Layer1 Error Counter Common-Lane)
0x00 Reserved -
0x01 Reserved -
0x02 Reserved -
0x03 Reserved -
0x04 Reserved -
0x05 Detect EI Infer -
0x06 Receiver Error -
0x07 Rx Recovery Request When the controller receives TS1 OS in L0(s) state.
0x08 N_FTS Timeout Timeout when the controller's Rx condition is in Rx_L0s.FTS.
0x09 Framing Error Gen3
0x0A Deskew Error -
0x00 BAD TLP -
0x01 LCRC Error -
0x02 BAD DLLP -
0x03 Replay Number Rollover -
0x04 Replay Timeout -

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PCIe Controller
Table 26. Event Counter Group #2 (8-bit Layer2 Error Counter Common-Lane) (continued)
0x05 Rx Nak DLLP -
0x06 Tx Nak DLLP -
0x07 Retry TLP -
Event1 # Description Note
0x00 FC Timeout -
0x01 Poisoned TLP Any function
0x02 ECRC Error Any function
0x03 Unsupported Request Any function
0x04 Completer Abort Any function
0x05 Completion Timeout Any function
1. Malformed TLP, FC & DL Protocol errors are excluded because of low frequency.
Table 28. Event Counter Group #4 (4-bit Layer1 Non-Error Counter Per-Lane)
0x00 EBUF SKP Add -
0x01 EBUF SKP Del -
Table 29. Event Counter Group #5 (32-bit Layer1 Non-Error Counter [RAM] Common Lane)
0x00 L0 to Recovery Entry -
0x01 L1 to Recovery Entry -
0x02 Tx L0s Entry -
0x03 Rx L0s Entry -
0x04 ASPM L1 reject RC: Send PM_Active_State_Nak

EP: Received PM_Active_State_Nak
0x05 L1 Entry -
0x0B L2 Entry -

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PCIe Controller
Table 29. Event Counter Group #5 (32-bit Layer1 Non-Error Counter [RAM] Common Lane) (continued)
0x0C Speed Change Gen2
0x0D Link width Change x2
0x0E Reserved -
Table 30. Event Counter Group #6 (32-bit Layer2 Non-Error Counter [RAM])
0x00 Tx Ack DLLP -
0x01 Tx Update FC DLLP -
0x02 Rx Ack DLLP -
0x03 Rx Update FC DLLP -
0x04 Rx Nullified TLP -
0x05 Tx Nullified TLP -
0x06 Rx Duplicate TLP -
Table 31. Event Counter Group #7 (32-bit Layer3 Non-Error Counter [RAM])
0x00 Tx Memory Write -
0x01 Tx Memory Read -
0x02 Tx Config Write -
0x03 Tx Config Read -
0x04 Tx IO Write -
0x05 Tx IO Read -
0x06 Tx Completion without data -
0x07 Tx Completion w data -
0x08 Tx Message TLP -
0x09 Tx Atomic -
0x0A Tx TLP with Prefix -
0x0B Rx Memory Write -

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Table 31. Event Counter Group #7 (32-bit Layer3 Non-Error Counter [RAM]) (continued)
0x0C Rx Memory Read -
0x0D Rx Config Write -
0x0E Rx Config Read -
0x0F Rx IO Write -
0x10 Rx IO Read -
0x11 Rx Completion without data -
0x12 Rx Completion w data -
0x13 Rx Message TLP -
0x14 Rx Atomic -
0x15 Rx TLP with Prefix -
3.9.5.3.3 Error injection support†

Your application can use the registers in the following table.
Table 32. Error Injection Vendor Specific Extended Capability (VSEC) Registers
.........other registers (e.g. Event Counter, Time-based Analysis, Error Injection) .........
EINJ_ENABLE_REG Error Injection Enable.
EINJ0_CRC_REG Error Injection Control 0 (CRC Error).
EINJ1_SEQNUM_REG Error Injection Control 1 (SeqNum Error).
EINJ2_DLLP_REG Error Injection Control 2 (DLLP Error).
EINJ3_SYMBOL_REG Error Injection Control 3 (Symbol Error).
EINJ4_FC_REG Error Injection Control 4 (FC Credit Error).
EINJ5_SP_TLP_REG Error Injection Control 5 (Specific TLP Error).
EINJ6_COMPARE_POINT_H0_REG Error Injection Control 6 (Compare Point H0).

NXP Semiconductors
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Table 32. Error Injection Vendor Specific Extended Capability (VSEC) Registers (continued)
EINJ6_COMPARE_VALUE_H0_REG Error Injection Control 6 (Compare Value H0).
EINJ6_CHANGE_POINT_H0_REG Error Injection Control 6 (Change Point H0).
EINJ6_CHANGE_VALUE_H0_REG Error Injection Control 6 (Change Value H0).
EINJ6_TLP_REG Error Injection Control 6 (Packet Error).
3.9.5.3.4 Time-based analysis support†

Table 33. Time-based Analysis Vendor Specific Extended Capability (VSEC) Registers
RAS_DES_CAP_HEADER_REG Vendor-Specific Extended Capability Header
.........other registers (e.g. Event Counter).........
TIME_BASED_ANALYSIS_CONTROL_REG Time-based Analysis Control.
TIME_BASED_ANALYSIS_DATA_REG Time-based Analysis Data.

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aux_clk
app_ras_des_tba_ctrl [1:0] = 01 (start)
TIMER_START = 1 (start) app_ras_des_tba_ctrl [1:0] = 10 (stop)
TIMER_START = 0 (stop) 0 0
(auto-reset at end of measurement duration)

0
TIME_BASED_DURATION_SELECT [7:0] 15:8

Software Write
TIME_BASED_REPORT_SELECT [15:0] 31:24
TIME_BASED_ANALYSIS_CONTROL_REG
Counter
▪
▪
▪
32
Software Read
Counter TIME_BASED_ANALYSIS_DATA_REG
Figure 15. Time-based Analysis Register Access
The counters measure For example, what percentage of time does the controller stay in L0 in a one second window (configurable
through TIME_BASED_DURATION_SELECT field. The results are undefined when the controller (PMC) is running on aux_clk.
Table 34. Time-based Analysis Counter Group #0 (32-bit Low-Power Cycle Counter ([RAM])
Event # % of Measurement Window Spent in LTSSM State
0x01 Tx L0s
0x02 Rx L0s
0x03 L0
0x04 L1
0x05 L1.1
0x06 L1.2
0x07 Config/Recovery
Table 35. Time-based Analysis Counter Group #1 (32-bit Throughput 4-DWORD Counter [RAM])
Event # Amount of Data Processed (Units of 16 bytes)
0x01 Tx TLP Data Payload
0x02 Rx TLP Data Payload

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3.9.5.3.5 Silicon debug support†

Table 36. Silicon Debug Vendor Specific Extended Capability (VSEC) Registers
SD_CONTROL1_REG on Silicon Debug Control1.
SD_CONTROL2_REG on Silicon Debug Control2.
SD_STATUS_L1LANE_REG Silicon Debug Status(Layer1 Per-lane).
SD_STATUS_L1LTSSM_REG Silicon Debug Status(Layer1 LTSSM).
SD_STATUS_PM_REG Silicon Debug Status(PM).
SD_STATUS_L2_REG Silicon Debug Status(Layer2).
SD_STATUS_L3FC_REG Silicon Debug Status(Layer3 FC).
SD_EQ_CONTROL1_REG Silicon Debug EQ Control1.
SD_EQ_STATUS1_REG Silicon Debug EQ Status1.
In addition, you can also use the registers in Table 37 that always exist regardless of parameter settings.
Table 37. Pre-existing Silicon Debug Outputs
Output
rdlh_link_up
brdg_slv_xfer_pending
edma_xfer_pending
radm_xfer_pending
rtlh_rfc_upd
rtlh_rfc_data
radm_q_not_empty
radm_qoverflow

NXP Semiconductors
PCIe Controller
Table 37. Pre-existing Silicon Debug Outputs (continued)
Output
cxpl_debug_info[63:0]
cxpl_debug_info_ei[15:0]
There is one set of common capability registers shared across all physical functions which can be accessed through each function.
The exception is the NEXT_OFFSET field in the capability header register.
3.9.6 Messages†
This section describes the processing of messages through the controller.
For a proper understanding of messages you should be familiar with Section 2.2.8, “Message Request Rules” of the PCI Express
Base Specification, Revision 4.0, Version 0.9.
• Messages (Msg/MsgD[5]) are posted transactions.
• Vendor Defined and PTM messages are Msg / MsgD.
• Set Slot Power Limit messages are MsgD.
• All other messages are Msg.
For more details, see Interrupts†.
3.9.6.1 Message generation†

Messages that are transmitted by the controller are derived from the following sources:
• The controller (automatically)
• The controller (under the control of your application)
• Your application
• The host/client software
For internally generated messages, or for messages generated at any of the SII interfaces:
• ID Based Ordering (IDO) is not supported.
• The controller does not check the messages for TLP errors; instead it sends the TLP as presented on the message interfaces.
[5] With payload.

NXP Semiconductors
PCIe Controller
RAM RX PIPE
RADM
iATU
PHY
CXPL Core
Indirect supply of any
4a
class of Msg/MsgD
RAM
Direct supply of any
4 AXI
class of Msg/MsgD
AXI
Bridge
XADM TX PIPE
Module
CPU (SLAVE)
RAM
Application Logic:
Tx Vendor Messages 2 Error Signalling
5 Vendor Defined VMI
Application Logic:
Optional System Status/
13 PTM Request
Control Registers
Legacy PCI
7 SII: Interrupt Signals
Interrupt
MSG_GEN
9 LTR Request SII: LTR Message Generation Signals
Power PTM
1 SII: Power Management Signals
Management
App Error CLK/RST

8 SII: Transmit Control Signals 3 LTR Clear
Signalling
12 DRS/FRS
Optional
Customer Logic
PMC
PCIe Protocol
Synopsys Specific
Figure 16. Message transmission: EP mode

NXP Semiconductors
PCIe Controller
RAM RX PIPE
RADM
LBC
CDM Core
Registers
CXPL Core PHY
Slot
Capabilities
iATU
Indirect supply of any

4a
class of Msg/MsgD
RAM DBI
Direct supply of any
4 AXI
class of Msg/MsgD
AXI
Bridge
Module XADM RAM TX PIPE
(SLAVE)
CPU
Application Logic:
Tx Vendor Messages 11 Set_Slot_Power_Limit
5 Vendor Defined VMI
Application Logic:
Optional System Status/
Control Registers
MSG_GEN
Locked 13 PTM Response
6 SII: PM, Unlock, and Error Messages
Transaction
Power
1 SII: Power Management Signals PTM
Management
CLK/RST
10 OBFF SII: OBFF Message Generation
Optional
Customer Logic
PCIe Protocol
Synopsys Specific
Figure 17. Message transmission: RC mode
For definitions of acronyms used for block and interface names, see Terms and abbreviations.
Table 38. Types of transmitted messages
Index Message source (type) EP mode RC mode
1 Power Management For more details, see For more details, see Power management†.
interface (Msg) Power management†.

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PCIe Controller
Table 38. Types of transmitted messages (continued)
2 Error Signaling inside the COR_ERR / n/a

controller (Msg) ERR_NONFATAL / ERR_FATAL.
For more details, see Reliability,
availability, and serviceability (RAS)† for
more details.
4 Direct Supply of any class AXI

of message (Msg/MsgD)
For details on how to generate a message at the AXI interface, see Application Msg/MsgD
programming examples†.
4a Indirect Supply of For more details on generating Msg/MsgD from MWr/IOWr using an internal address
any class of message translation unit (ATU), see iATU outbound MSG handling†.
(Msg/MsgD)
For more details on the supported methods of Msg/MsgD generation, see Table 39 and
Table 40.
5 Vendor Defined (Msg1) The controller generates Vendor Defined messages in response to requests on the VMI
(see Vendor message interface (VMI)†.
6 Locked Transaction (Msg) n/a Unlock message, triggered by root

complex application logic through the
app_unlock_msg pin in.
7 Legacy PCI SII interrupt signals sys_int. n/a

Interrupt (Msg)
8 Error Signaling from the The controller generates Error Signaling n/a
application (Msg) messages in response to application
requests on the SII app_err* I/O.
It is also possible to generate Error
messages through the client interfaces.
For more details, see items 4and 4a in
this table.
11 Set_Slot_Power_Limit n/a Set_Slot_Power_Limit message, triggered by

(MsgD) writing to the Slot Capabilities register through
the DBI, or when LTSSM enters L0
1. MsgD transmission not possible on Vendor Message Interface (VMI). For more details, see Vendor-defined message (VDM)
generation†. However, it is possible through (4).
3.9.6.1.1 Vendor-defined message (VDM) generation†

VDMs can be generated by your application using any of the following methods:
• The controller generates VDMs in response to requests on the VMI.
• The VMI can be used to send Msg only. It does not support message with payload (MsgD).
• The inputs ven_msg_fmt[1:0]and ven_msg_len[9:0] should be set to 0x1 and 0x0 respectively to indicate 4-DWORD
header and no payload.
• VDMs created by you at the VMI are always subject to translation by the iATU (see Internal Address Translation Unit (iATU)†).
• Direct supply of Msg and MsgD TLPs at AXI bridge slave.

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PCIe Controller
• Direct supply of I/O and MEM TLPs at AXI bridge slave to be converted to VDM. The optional internal address translation unit
(iATU) can convert I/O and MEM TLPs to VDM TLPs. For more details, see iATU outbound MSG handling†.
You must use 64-bit addressing when you are using the Direct supply method of VDM generation. For more details, see Figure 18.
It is preferable to use the SII interface to send a VDM. The AXI bridge slave can also support message transmission of a VDM
without any modifications.
3.9.6.1.2 Application Msg/MsgD programming examples†

The following tables enumerate the different ways that your application can generate Msg and MsgD TLPs.
Table 39. Msg without payload transmission methods
Application Description Application I/O signals

interface
AXI Direct Supply using a Msg transaction. slv_awmisc_info[4:0] =MSG

slv_wstrb[3:0] =0000
slv_awmisc_info[20:13] = message code
slv_awmisc_info_p_tag[5:0] = tag
slv_awmisc_info_hdr_34dw[63:32] = 3rd TLP
header DWORD
slv_awmisc_info_hdr_34dw[31:0] = 4th TLP
header DWORD
VMI The controller generates Vendor Defined messages in response to requests on the VMI (see Vendor
message interface (VMI)†)
Table 40. Msg with payload transmission methods
Application Description Application I/O signals

interface
AXI Direct supply using an MsgD transaction. slv_amisc_info[4:0] =MSG

slv_awmisc_info[20:13] = message code
slv_awmisc_info_p_tag[5:0] = tag
slv_awmisc_info_hdr_34dw[63:32]= 3rd TLP
header DWORD
slv_awmisc_info_hdr_34dw[31:0]= 4th TLP
header DWORD
Indirect Supply (iATU) using a MWra transaction. slv_amisc_info[4:0] =MEM

The iATU1 needs to be configured to translate MWr to slv_awmisc_info_hdr_34dw[63:32] = 3rd TLP
MsgD TLPs. header DWORD
slv_awmisc_info_hdr_34dw[31:0] = 4th TLP
header DWORD
VMI MsgD is not supported.
1. When the “payload inhibit” feature of the iATU is used, then slv_wstrb does not need to be set. Similarly, for iATU header
and tag substitution; the iATU can be set up to fill these fields in the outgoing TLP.

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PCIe Controller
3.9.6.1.3 Byte mapping of third and fourth message header DWORDs at I/O interfaces†
The following figure indicates the byte mapping between the message generation interfaces and the third and fourth DWORDs
of the message TLP header.
31
bytes 12-15
63
bytes 8-11
32
VMI
(ven_msg_data)
31
bytes 12-15
0
AXI
Slave
Core
Logic PIPE
63
1
32
bytes 8-11
31
0
0
0x0 0
bytes 12-15
4-dword header Byte 15 is in position [7:0]

for 4-dword headers
Figure 18. Transmitted 3rd and 4th DWORD message header byte mapping at interfaces (with AXI bridge)
In 32-bit address AXI configurations; the controller transmits all '0's instead of slv_awmisc_info_hdr_34dw[63:32].
3.9.6.2 Message reception†

The PCI Express controller can receive the following types of messages. The index in the first column refers to the circled numbers
in the following diagrams.
Table 41. Types of received messages
1 Power Management (Msg). For more details, see For more details, see Power management†.
Power management†.
1a Slot Power Limit (MsgD) Set_Slot_Power_Limit Support message n/a
2 Error Signalling n/a COR_ERR /

from Downstream ERR_NONFATAL / ERR_FATAL
Component (Msg).
3 Vendor Defined (Msg/MsgD). For more details, see Routing of received messages†

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PCIe Controller
Table 41. Types of received messages (continued)
4 Locked Transaction (Msg). Unlock message n/a
5 Legacy PCI Interrupts from n/a sys_int*

Downstream Devices (Msg).
8 ATS Invalidate See the PCI Express Address n/a

Request (Msg). Translation Services 1.1 Specification,
January 26 2009
9 ATS Request (Msg). n/a See the PCI Express Address Translation
Services 1.1 Specification, January 26
ATS Invalidation 2009
Completion (Msg).
ATS Invalidate
8
AXI Request
Bridge RADM RX PIPE
AXI TRGT1
Module
(MASTER)
3 Vendor Defined 11 PTM Response
Application Logic: PHY

VMI
Rx Vendor Messages CXPL Core
Locked
4 PTM
Transaction
SII: PM, Unlock and Error Messages
Slot Power
1a
Limit
SII: Power Management Signals

TX PIPE
Application Logic:
Optional System Status/ 7 OBFF
Control Registers RAM
SII: OBFF Message Generation
Power
1
Management CLK/RST
SII: Power Management Signals

PMC
Customer Logic
PCIe Protocol
Synopsys Specific
Figure 19. Message reception: EP mode

NXP Semiconductors
PCIe Controller
AXI
Bridge RADM RX PIPE
AXI TRGT1
Module
(MASTER)
3 Vendor Defined 11 PTM Request
Application Logic: PHY

VMI
Rx Vendor Messages CXPL Core
2 Error Signalling PTM
SII: PM, Unlock and Error Messages
Legacy PCI
5
Interrupt
10 DRS/FRS
SII: lnterrupt Signals
TX PIPE
LTR FRSQ
6
Request/Clear RAM
Application Logic:
Optional System Status/ SII: LTR Message Generation Signals
Control Registers
ATS Request/
9
Completion
CLK/RST
SII: Messages
Power
1
Management
SII: Power Management Signals PMC
Customer Logic
PCIe Protocol
Synopsys Specific
Figure 20. Message reception: RC mode
For definitions of acronyms used for block and interface names, see Terms and abbreviations.
3.9.6.2.1 Message reception I/O interfaces†

The RADM filter provides a message interface that is grouped as part of the System Information Interface (SII)to handle the
message TLPs received from the upstream component. The RADM filter processes the message and decodes the header before
sending it to your application logic on the SII. Some of the message reception signals are also used in Interrupts† and Reliability,
availability, and serviceability (RAS)†.
3.9.6.2.2 Routing of received messages†

All error-free MSG requests except for PTM and DRS/FRS are decoded internally, signaled on the SII interface, and then
dropped (not forwarded to your application[6] on TRGT1(or AXI bridge Master when present). When a MSG request is filtered with
UR/CA/CRS status, the TLP is always dropped.
By default received messages except PTM and DRS/FRS (Msg/MsgD) are delivered (without the payload for MsgD) on the SII
interface and are not delivered on the TRGT1 (or AXI bridge master) interface. The exception to this is an ATS Invalidation Request
(in EP mode) which is too big and is delivered on the TRGT1 interface regardless of filter mask settings.
[6] Vendor TYPE0 messages generate an UR error.

NXP Semiconductors
PCIe Controller
The SII message reception interface provides the requester ID and message type (from the first and second TLP DWORDs) and
the contents of the third and fourth TLP DWORDs.
If you also want the message delivered on the TRGT1 (or AXI bridge Master) interface, then you must clear the corresponding filter
mask bit. For EP mode, Msg is message without payload. That is all messages except VDM with payload, set_slot_power_limit,
and ATS Invalidate request. For RC mode, Msg is message without payload. That is all messages except VDM with payload.
3.9.6.2.3 Further information†

For specific details how the handling of a message is affected by its error status, see Advanced filtering and routing of TLPs†.
For information on optional address translation of VDMs, see iATU inbound MSG handling†.
3.9.7 Interrupts†
The following section describes the processing of interrupts in the controller. You should be familiar with the different types
of interrupts as specified in Sections 6.1.1, “Rationale for PCI Express Interrupt Model”, 6.1.4, “Message Signaled Interrupt
(MSI/MSI-X) Support”, 6.1.2, “PCI Compatible INTx Emulation”, and 6.1.3, “INTx Emulation Software Model” of the PCI Express
Base Specification, Revision 4.0, Version 0.9.
3.9.7.1 Interrupt generation (USP)†

An USP creates MSI’s using MWr requests. Your application logic issues MSI requests through the MSI interface; the controller
then generates the corresponding memory write. Alternatively, your application logic can create the MSI MWr and supply it on an
AXI slave interface.

NXP Semiconductors
PCIe Controller
MSI Generation Method A MSI Generation Method B

(SII MSI Interface) (Normal Traffic Interface)
PCIe core PCIe core
Traffic Arbiter Traffic Arbiter

Normal Traffic Normal Traffic
Lo Lo
A Tx A Tx
MWr MWr
D D
Message Generator Hi Hi
MSI Capability AXI MSI Capability

1 Slave Interface 1
Capability/Control Capability/Control
Lower Address A Lower Address
Request/ A
Upper Address Upper Address
Grant D D
Handshake Data Data
Mask Bits 5 Mask Bits 5
Pending Bits Pending Bits
cfg_msi_pending[31:0]
cfg_msi_pending[31:0]
ven_msi_vector[4:0]
cfg_msi_mask[31:0]
cfg_msi_mask[31:0]
cfg_msi_addr[63:0]
cfg_msi_data[15:0]
ven_msi_grant
ven_msi_req
cfg_msi_en
cfg_msi_en
Your Your
Application Application
Logic Logic
3 3
MSI FSM MSI FSM
5 5
Priority Encoder Priority Encoder
4 4
Clear Clear
Pending Pending
Bit Bit
Pending Bit Array [31:0] Pending Bit Array [31:0]
2 Example for 64-bit with PVM; 2

32 32
Single-function non -VF
Local Interrupt Lines Local Interrupt Lines
Figure 21. Example MSI application logic (MSI_CAP_ENABLE =1)
An MSI-X interrupt is identical to an MSI, except that it: supports more than 32 vectors (2048) through the use of multiple address
and data pairs that are written by software to an MSI-X Table. Your application logic issues MSI requests through the MSI interface;
the controller then generates the corresponding memory write. Alternatively, your application logic can create the MSI MWr and
supply it on an AXI slave interface.

NXP Semiconductors
PCIe Controller
MSI Generation Method A

(SII MSI Interface)
Traffic Arbiter PCIe

Normal Traffic core
Lo
A Tx
MWr
D
Message Generator Hi
PCI Header BARS

MSI-X Capability BAR 5
1
Capability/Control BAR 4
Request/
Table Offset BIR BAR 3
Grant
Handshake PBA Offset BIR BAR 2
BAR 1
BAR 0
ven_msi_grant
ven_msi_req
cfg_msix_en =1
cfg_msix_func_mask =0
N = cfg_msix_table_size[]
msix_addr[63:0]
msix_data[31:0]
cfg_msix_table_bir[2:0]
cfg_bar5_start/limit[31:0]
cfg_msix_pba_bir[2:0]
cfg_msix_table_offset[28:0]
cfg_msix_pba_offset[28:0]
5
MSI-X FSM
5 + +
Address Address
Priority Encoder 3 Decoder Decoder
D,A
rdata raddr r/waddr
Host Read
MSI-X Table PBA
Clear Access
(N) r/wdata
Pending
Bit mask
Host Write
1
Access
Set/clear pending
bit control
2 N
Local Interrupt Lines Your Application Logic Example for single -function non -VF.
Figure 22. Example MSI-X application logic using SII MSI interface (MSIX_CAP_ENABLE =1)

NXP Semiconductors
PCIe Controller
MSI Generation Method B

(Normal Traffic Interface)
Traffic Arbiter PCIe

Normal Traffic core
Lo
A Tx
MWr
D
Hi
AXI PCI Header BARS

Slave Interface
MSI-X Capability 1 BAR 5
Capability/Control BAR 4
Table Offset BIR BAR 3
PBA Offset BIR BAR 2
BAR 1
BAR 0
cfg_msix_en = 1
cfg_msix_func_mask = 0
4
MSI-X FSM
5 + +
D,A
Address Address
Priority Encoder 3 Decoder Decoder
5 rdata raddr r/waddr

Host Read
MSI-X Table PBA
Clear Access
(N entries) r/wdata
Pending
Bit mask
Host Write
1
Access
Set/clear pending
bit control
2 N
Local Interrupt Lines Your Application Logic Example for single -function non -VF.
Figure 23. Example MSI-X application logic using normal Tx interfaces
MSI/MSI-X requests created at the MSI interface are given higher Tx priority than traffic at the AXI slave interface.
To preserve ordering, you should supply MSI/MSI-X MWr requests at the AXI slave interface.
3.9.7.1.1 PCI legacy interrupts (USP)†

Your USP application asserts the level-sensitive sys_int input to notify the controller that it should send an interrupt message.
The controller generates two message TLPs, Assert_INTx and Deassert_INTx, in response to the assertion and the de-assertion
of this input. Your application needs to de-assert the virtual interrupt inputs when the link has been placed in a low power state.
The controller does not automatically send a Deassert_INTx interrupt message when the power state changes.

NXP Semiconductors
PCIe Controller
SWDSP SWUSP
radm_int_*
Interrupt Application Interrupt
Message Switch Logic Message
Decoding Generation
dp_int*
Msg
Assert_INTx/
Deassert_INTx
sys_int*
HotPlug Events
Figure 24. PCI legacy interrupts
3.9.7.1.2 iMSIX-TX: Integrated MSIX transmit (USP)†

The upstream controller implements the logic and RAM required to generate MSI-X requests. When your local application updates
MSIX_DOORBELL_OFF, the controller extracts the vector and TC information from the payload and creates the MSI-X request.
The AXI bridge must access the DBI interface by setting either, DBI_4SLAVE_POPULATED or SHARED_DBI_ENABLED, to hit the
MSI-X doorbell.

NXP Semiconductors
PCIe Controller
PCIe Controller
AXI Configurations Only Traffic Arbiter

For non-AXI configurations, your local application must write to Normal Traffic
MSIX_DOORBELL_OFF 0 Lo
3 Tx (wire)
AXI A
MWr
AXI Slave interface A D
MWr 1 Message Generator Hi
D
MWr Address Check
9 PCI Header BARS
2 Port Logic Registers Routed
internally MSI-X Capability 0 BAR 5 DBI
MSIX_ADDRESS_MATCH_LOW_OFF to DBI Capability/Control BAR 4
== Rx (wire)
MSIX_ADDRESS_MATCH_HIGH_OFF 4 Table Offset BIR BAR 3
PBA Offset BIR BAR 2
A BAR 1
MWr
D
BAR 0
MWr Payload Format
cfg_msix_en = 1
cfg_msix_func_mask = 0
31:29 28:24 23:16 15 14:12 11 10:0
Rsvd PF VF Vf Active TC Rsvd Vector
MSIX_DOORBELL_OFF Register Field Layout
ELBI
MSIX_DOORBELL_OFF
Vector
A write to this Port Logic register
PF, TC, D,A
triggers an MSI-X generation event
VF
6
5 Start
MSI-X FSM
5 + +
Priority Address Address

8 Decoder Decoder
Encoder
rdata raddr r/waddr
TC Vec Data Msg Addr Pending Bits 63..0 Internal
MSI-X Table TC Vec Data Msg Addr Pending Bits 127..64 PBA extension
Clear RAM RAM of
Pending ELBI
Bit mask r/wdata
Host Write 1 Host Read
Access Access
7
Set/clear pending
bit control
Integrated MSI-X Generation Module
MSI-X Request Generation Flow in AXI Bridge Configuration
0 Read the MSI-X Capability Structure registers through the DBI/Wire to get the value of MSI-X Table Size, Table BIR, Table Offset, PBA Offset, PBA Offset, and PBA BIR. Get the starting address of the
MSI-X Table as follows; MSI-X Table Start Address = Start Address of BARn + Table Offset ; where ‘n’ = Table BIR.
1 Populate the MSI-X TAble (by writing over the wire or DBI) with the required Message Address, Message Data, and Vector Control information for each entry
For example, to populate entry 0 of the MSI-X Table, perform four consecutive 32-bit writes from DBI/WIRE to ‘’MSI-X Table Start Address’’ with Data0 = Message Address, Data1 = Message
Upper Address, Data2 = Message Data, and Data3 = Vector Control Similarly to populate entry 2 write to ‘’MSI-X Table Start Address + 2’’.
2 Program the MSIX_ADDRESS_MATCH * port logic registers with the required address (not matching any iATU region, if iATU is enabled)
Program MSIX_ADDRESS_MATCH_LOW_OFF [0] = 1, to set the MSI-X Match Enable bit.
3 Issue a write from AXI Slave interface to the address programmed in MSIX_ADDRESS_MATCH_LOW_OFF and MSIX_ADDRESS_MATCH_HIGH_OFF. The write data should be provided in the
format specified in the MSIX_DOORBELL_OFF register.
4 If the address of the AXI Write request matches the address programmed in MSIX_ADDRESS_MATCH * registers, the write request is internally routed away from the controller’s normal
datapath to the MSIX_DOORBELL_OFF register, and 5 an MSI-X generation request is triggered.
6 The MSI-X FSM checks the following:

• if PCI_MSIX_FUNCTION_MASK field in PCI_MSIX_CAP_ID_NEXT_CTRL_REG is set, the corresponding pending bit is set in PBA RAM 7 , and no MSI-X is generated.
8 if PCI_MSIX_FUNCTION_MASK field in PCI_MSIX_CAP_ID_NEXT_CTRL_REG is not set, the MSI-X Table RAM entry corresponding to the requested vector is read
• If Vector Mask of the MSI-X Table entry is set, the corresponding pending bit is set in PBA RAM 7 , and no MSI-X is generated.
• If Vector Mask of the MSI-X Table entry is not set, MSI-X generation 9 is initiated (using the MSI-X address and data of the MSI-X Table RAM entry.
Figure 25. iMSIX-TX: MSIX transmit (MSIX_TABLE_EN =1)
Table 42. Limitations
Limitation Details
General • Table BIR must be identical1 for VFs and PFs.

• PBA BIR must be identical for VFs and PFs.
• Table Offset must be identical for VFs and PFs.
• PBA Offset must be identical for VFs and PFs.
• Table Offset must be aligned to 8 KB boundary. Recommended by PCI specification.
• PBA Offset must be aligned to 4KB boundary. Recommended by PCI specification.
• MSIX_TABLE_SIZE (used to size Table RAM) must be identical for all PFs.

NXP Semiconductors
PCIe Controller
Table 42. Limitations (continued)
Limitation Details
ELBI • ELBI width must be 32-bit; this feature communicates with the rest of the controller using an internal extension
of the ELBI bus.
• All accesses by your host or local application to the RAMs must be 32-bits wide.
• The ELBI address range available for application registers is the full ELBI interface address range minus the
space in bytes claimed by the MSI-X tables, which is:
3 * (MSIX_TABLE_SIZE +1) * 16
3 * ((MSIX_TABLE_SIZE/64) +1) * 8
The exact addresses claimed depend on the programming of the MSI-X table and PBA offsets in the MSI-X
capability registers.
1. One value for all VFs and PFs in the controller. PFs cannot have different values.
3.9.7.2 Interrupt reception (DSP)†
3.9.7.2.1 PCI legacy interrupts (DSP)†

The controller decodes received Assert_INTx/Deassert_INTx messages and pulses the radm_inti_asserted and
radm_inti_deasserted outputs where i=a,b,c,d.
3.9.7.2.2 PCI Express hot-plug logic interrupt and wakeup (DSP)†

When MSI or MSI-X is enabled, the controller asserts the hp_msi output upon detection of any of these HP events:
• Power Fault Detected
• MRL Sensor Changed
• Presence Detect Changed
• Command Completed
• Attention Button Pressed
• Electromechanical Interlock Status Changed
• Data Link Layer State Changed
When INTx interrupt mode is enabled, the controller asserts the hp_intoutput upon detection of any of the hot-plug events. When
PME mode is enabled, the controller asserts the hp_pme output upon detection of any of the hot-plug events. The controller does
not check if the PM state is D1, D2, or D3hot. Your application must check the value on pm_dstate to make sure the device is in
D1, D2, or D3hot upon receipt of a hp_pme notification.
3.9.7.2.3 iMSI-RX: Integrated MSI receiver [AXI bridge] (DSP)†

The AXI bridge provides an integrated MSI reception module to detect and terminate inbound MSI requests (received on the RX
wire). Rather than propagating MSI MWr TLPs onto the AXI bus through the master interface, the MSI packets are captured,
terminated in the AXI bridge, and an interrupt is signaled locally through the msi_ctrl_int output.
The iMSI-RX is programmed with an address (MSI_CTRL_ADDR_OFF and MSI_CTRL_UPPER_ADDR_OFF) that is used as the
system MSI address. When an inbound MWr request is passed to the AXI bridge and matches this address as well as the

NXP Semiconductors
PCIe Controller
conditions specified for an MSI memory write request, an MSI interrupt is detected. When this MWr is about to be driven onto the
AXI bridge master interface[7], it is dropped and never appears on the AXI bus.
The MSI interrupt is generated on msi_ctrl_int after the previous Posted transaction's AXI B response is received. It is then
synchronized with core_clk. Therefore, the subsequent NP write transaction might appear sooner than MSI interrupt in the AXI
mstr_aclk domain.
The iMSI-RX decodes the MSI MWr data payload to determine which endpoint device (EP) sent the MSI and which interrupt vector
the MSI corresponds to. When a valid interrupt has been decoded, the msi_ctrl_int output is asserted. This output remains
asserted when any MSI interrupt is pending. It is only de-asserted when there is no MSI interrupt pending.
3.9.7.2.3.1 Features†
• Provides support for up to eight EPs. Each supported EP has a set of interrupt enable, mask, and status
registers (MSI_CTRL_INT_*).
• Guarantees correct AXI ordering with respect to other inbound posted writes by generating the MSI interrupt only after your
application AXI slave acknowledges responses of previous posted TLPs.
• A maximum of 32 interrupts are supported per EP.
• Optional 32-bit register driven general purpose outputs (msi_ctrl_io[31:0]). For more details, see the
MSI_GPIO_IO_OFF register.
3.9.7.2.3.2 MSI request detection criteria†

An MSI interrupt request is detected when the controller receives a MWr TLP that satisfies these conditions:
• Header attributes bits are 0x0. No snoop (NS) and relaxed ordering (RO) fields must be 0x0.
• Length field is 0x01 to indicate a payload of one DWORD.
• First byte enable (FBE) is 4bxx11 (enabling the first two bytes of the payload.)
• Last byte enable (LBE) is 4b0000.
• TLP address corresponds to systems chosen MSI address as programmed in the MSI_CTRL_ADDR_OFF and
MSI_CTRL_UPPER_ADDR_OFF port logic registers. This register is not the MSI Lower 32 Bits Address Register which
is part of the PCIe MSI capability register.
In addition to these criteria the MWr must also pass the receive filtering rules as outlined in Receive filtering†.
3.9.7.2.3.3 Programming and usage model†

• The host CPU configures the MSI capabilities of all endpoints through the local DBI bus (or through CFG requests from the
remote link partner).
— Program the MSI Data Register (MSI_CAP_OFF_08H_REG or MSI_CAP_OFF_0CH_REG in the MSI capability) as
follows to allow the iMSI-RX to decode the interrupt source.
Table 43. MSI data register (MSI_CAP_OFF_08H_REG or MSI_CAP_OFF_0CH_REG) programming
15:8 7:5 4:0
Not Used EP Number Interrupt Vector Number

Allows each EP to be identified within the system, For • Identifies the interrupt source within each EP
example, EP#5 is programmed with 3b101
• Programmed to 5b00000.
[7] To guarantee Posted requested ordering.

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Table 43. MSI data register (MSI_CAP_OFF_08H_REG or MSI_CAP_OFF_0CH_REG) programming
15:8 7:5 4:0
• Set by MSI generation logic to identify each interrupt

source in real time
• Supports up to 32 Vectors
• Program the MSI Capability Lower 32 Bits Address Register (MSI_CAP_OFF_04H_REG) of every EP with one common
MSI address.
• The host CPU configures the iMSI-RX through the local DBI bus (or through CFG requests from the remote link partner).
— Program the iMSI-RX’s MSI_CTRL_ADDR_OFF and MSI_CTRL_UPPER_ADDR_OFF registers with the same value as
in MSI_CAP_OFF_04H_REG.
— Read the MSI capability of each EP to determine the number of vectors enabled in each EP and uses this information
to program the iMSI-RX’s interrupt enable register (MSI_CTRL_INT_0_EN_OFF). This register allows up to 32 MSI
interrupt vectors to be enabled within the iMSI-RX for a given EP. It is the responsibility of the host CPU to read
the contents of the Multiple Message Enable field in an EPs MSI capability structure and program that EPs Interrupt
Enable register in the iMSI-RX appropriately. For example when the Multiple Message Enable is 3b100 for endpoint
#0 (which corresponds to 16 enabled interrupt vectors), the host CPU should program MSI_CTRL_INT_0_EN_OFF
with 0x0000FFFF.
iMSI-RX is active and terminates all received MSI MemWr unless you deactivate it. iMSI-RX is deactivated when all of the eight
MSI_CTRL_INT_0_EN_OFF .... MSI_CTRL_INT_7_EN_OFF registers have a value of 0x0. The iMSI-RX is also deactivated when
it is not in RC mode (device_type !=0x4).
3.9.7.2.3.4 Processing of detected interrupts†

The MSI controller decodes the MSI MWr data payload to determine which EP sent the MSI and to which interrupt vector
it corresponds.

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DECODE
32 4:0
Interrupt Vector
EP Number
7:5
Data Payload
DEMUX Inbound(Received)
MemWr
MSI Detected Address Match plus
other checks
MSI_CTRL_ADDR field in
MSI_CTRL_ADDR_OFF
MSI_CTRL_UPPER_ADDR field in
X8 MSI_CTRL_UPPER_ADDR_OFF
32 MSI_CTRL_INT_0_STATUS_OFF 1
X8 D Q msi_ctrl_int
32 32
S 32 1
x32
x32
32
32
R
MSI_CTRL_INT_0_MASK_OFF
x32
S (set) takes msi_ctrl_int_vec[7:0]
32 1 32
precedence
over R(reset)
MSI_CTRL_INT_0_EN_OFF from DBI write
data bus
from DBI write select for

MSI_CTRL_INT_0_STATUS_OFF
Figure 26. Architectural representation: iMSI-RX interrupt detection process
• When the decoded interrupt vector is enabled and not masked, then the controller sets the corresponding bit in the iMSI-RX
Interrupt#0 Status Register (MSI_CTRL_INT_0_STATUS_OFF) and asserts the top-level controller output msi_ctrl_int.
This signal remains asserted until the host CPU clears the status bit by writing a 1 to the status bit. Writing a 0 has no effect.
• When any status bit remains set, then msi_ctrl_int remains asserted. The interrupt status register provides a status bit
for up to 32 interrupt vectors per endpoint. When the decoded interrupt vector is enabled but is masked, then the controller
sets the corresponding bit in interrupt status register but the it does not assert the top-level controller output msi_ctrl_int.
• When an MSI interrupt vector is received from an endpoint but that vector has not been enabled in the corresponding iMSI-RX
Interrupt#0 Enable Register (MSI_CTRL_INT_0_EN_OFF), then the controller does not set any bit in the interrupt status
register and it does not assert msi_ctrl_int.
• In addition, when no interrupts have been enabled in any of the eight interrupt enable registers, then all MSI detection logic
is disabled and valid MSI MWr request TLPs are not terminated in the bridge but are passed by the AXI master interface to
the AXI bus.
• The iMSI-RX Interrupt#0 Mask Register (MSI_CTRL_INT_0_MASK_OFF) allows the host to mask a given MSI interrupt
vector. When a MSI interrupt vector is received for a masked interrupt vector, then the controller sets the corresponding bit
in the interrupt status register but it does not assert msi_ctr_intl because the interrupt vector is masked.
• Note: This masking is local to the iMSI-RX and is not part of Per Vector Masking (PVM) in any of the downstream endpoints.
The contents of the interrupt mask and interrupt status registers are used to drive the msi_ctrl_int output.
• When any status bit is set and the interrupt vector is not masked, then the controller asserts msi_ctrl_int. As long as any
interrupt status bit is set and not masked, msi_ctrl_int remains asserted.

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3.9.7.2.3.5 Alternative data register programming†

The programming of the MSI Data Register (MSI_CAP_OFF_08H_REG or MSI_CAP_OFF_0CH_REG) as described in Table 43
assumes that each endpoint enables 32 vectors. When one or more endpoints only support 16 or less interrupt vectors, then it is
possible to share a single set of interrupt enable, interrupt mask, and interrupt status registers among those endpoints.
For example, assume that endpoint #1 enables 16 interrupt vectors and endpoint #2 also enables 16 interrupt vectors. When the
MSI data register for endpoint #1 is programmed to 0x20 and the MSI data register for endpoint#2 is programmed to 0x30, as
in Table 44, then the status for each endpoint is in interrupt status register#1. Endpoint#1s vectors are in the lower 16 bits and
endpoint#2s vectors are in the upper 16 bits. Manipulating the MSI data register format in this manner allows the interrupt controller
to support more than eight endpoints using the eight interrupt status registers provided.
Table 44. Alternative data register programming
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Not Used Reg N EP# Interrupt Vector Number
Endpoint #1 0 0 1 0 0 0 0 0
Endpoint #2 0 0 1 1 0 0 0 0
3.9.8 Internal Address Translation Unit (iATU)†

The controller uses the iATU to implement a local address translation scheme that replaces the TLP address and TLP header
fields in the current TLP request header.
3.9.8.1 Outbound features†

Address translation is used for mapping different address ranges to different memory spaces supported by your application. A
typical example maps your application memory space to PCI memory space. The iATU also supports type translation. Without
address translation, your application address is passed unmodified to the TLPs directly through the Tx application interface. You
can program the iATU to implement your own outbound address translation scheme without external logic.
• Address Match mode operation for MEM and I/O, CFG, and MSG TLPs. No translation for completions.
• Supports type translation through TLP type header field replacement for MEM or I/O types to MSG/CFG types.
— Includes posted to non-posted translation (for example, MWr to CfgWr0)
— No translation from completions
• Programmable TLP header field replacement.
— TYPE/TD/TC/AT/ATTR/MSG-Code/TH/PH/ST
— Function Number
• Multiple address regions programmable for location and size.
• Programmable enable/disable per region.
• Automatic FMT field translation between three DWORDs and four DWORDs for 64-bit addresses.
• Invert Address Matching mode to translate accesses outside of a successful address match.
• Configuration Shift mode. Optimizes the memory footprint of CFG accesses destined for the Rx application interface in a
multifunction device.
• Response code which defines the completion status to return for accesses matching a region.
• Supports regions from 4 KB to 16 ZB in size.
• Payload Inhibit marks all TLPs as having no payload data.

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• Header Substitution replaces bytes 8 to 11 (for 3 DWORD header) or bytes 12 to 15 (for 4 DWORD header), inclusive, of the
outbound TLP header.
• Tag Substitution of the outbound TLP tag field.
• Function number bypass mode to allow function number information to be supplied from your application transmit interface
while translating the address and other attributes of the TLP.
• DMA bypass mode to allow TLPs which are initiated by the embedded DMA engine, to pass through the iATU untranslated.
The default behavior of the ATU when there is no address match in the outbound direction or no TLP attribute match in the inbound
direction, is to pass the transaction through.
3.9.8.2 Outbound basic operation (Address Match mode)†

The address field of each request MEM and I/O TLP is checked to see if it falls into any of the enabled[8] address regions defined
by the Start and End addresses as defined in Figure 29. When an address match is found, then the TLP address field is modified
as follows:
Translated Address = Original Address - Base Address + Target Address
and the TYPE, TD, TC, AT, TH, PH, ST, Function Number, and ATTR header fields are replaced with the corresponding fields
in the IATU_REGION_CTRL_1_OFF_OUTBOUND_0 register. When your application address field matches more than one of the
address regions, then the first enabled region to be matched is used. For details on what happens when there is no address match,
see No address match result†. This operational mode is called Address Match mode and is always used for outbound translation.
Figure 27 provides more details on this translation process.
The iATU does not translate DBI requests.
Untranslated Translated Region Size =

Upper Base Address Limit Address Address Map Address Map End Address - Start Address
31 0 31 12 0
0xFFFF
63 End Address 0
Region #n
Region #n
63 0
0x0000
63 Start Address 0 31 0 31 12 0
Upper Target Address Lower Target Address
0x0000
31 0 31 12 0
Upper Base Address Lower Base Address
Figure 27. 64-bit region mapping: outbound and inbound (Address Match mode); INCREASE_REGION_SIZE=0
[8] When the Region Enable bit of the Region Control 2 register is ‘0’, then that region is not used for address matching.

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Upper Upper
Base Limit Untranslated Translated Region Size =
Address Address Limit Address Address Map Address Map End Address - Start Address
31 # 0 31 12 0
0xFFFF
63 End Address 0
Region #n
Region #n
63 0
0x0000
63 Start Address 0 31 0 31 12 0
0x0000
31 0 31 12 0
Upper Base Address Lower Base Address
Figure 28. 64-bit region mapping: outbound and inbound (Address Match mode); INCREASE_REGION_SIZE=1
CAUTION
The combination of region size and number of regions must not consume the maximum space that is addressable
with your 32-bit or 64-bit system address.
Untranslated Translated Region Size =

Limit Address Address Map Address Map End Address - Start Address
31 12 0
0xFFFF
31 End Address 0
The resulting translated address
Region #n space can be 64-bits or 32 bits.
Region #n
63 0
0x0000
31 Start Address 0 31 0 31 12 0
0x0000
31 12 0
Lower Base Address
Figure 29. 32-bit region mapping: outbound and inbound (Address Match mode)
3.9.8.3 Outbound detailed operation†
3.9.8.3.1 RID BDF number replacement†

When there is a successful address match on an outbound TLP, then the function number used in generating
the function part of the requester ID[9] field of the TLP is taken from the 3-bit Function Number field of the
IATU_REGION_CTRL_1_OFF_OUTBOUND_i register. The value in this field must be 0x0 unless multifunction operation in
the controller is enabled.To override this behavior, use the information in Function number translation bypass feature†.
[9] Uses the 8:5:3 bit PCI Bus.Device.Function (BDF) format.

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When the Virtual Function Active field of the IATU_REGION_CTRL_3_OFF_OUTBOUND_i register is set, then the function part
of the requester ID[10] field of the TLP is formed from the function number of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i
register, VF Offset, VF Stride, Primary Bus number, and the 8-bit[11] Virtual Function Number field of the
IATU_REGION_CTRL_3_OFF_OUTBOUND_i register.
3.9.8.3.2 iATU outbound MSG handling†

The iATU supports TYPE translation/conversion of MEM and I/O TLPs to Msg/MsgD TLPs. This supports applications
that are unable to directly generate Msg/MsgD TLPs.When there is a successful address match on an outbound MEM
TLP, and the translated TLP type field is MSG (that is, the type field of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i
register is 10xxx), then the message code field of the TLP is set to the value in the Message Code field of the
IATU_REGION_CTRL_2_OFF_OUTBOUND_i register. A MWr with an effective length of ‘0’ is converted to Msg and all other MWr
TLPs are converted to MsgD. For more information on generating messages, see Message generation†.
The iATU does not translate outbound messages.
3.9.8.3.3 MEM-CFG type translation†

The iATU supports translation of I/O and MEM TLPs to CFG TLPs. This is useful for applications that are unable to generate CFG
TLPs.The 16-bit BDF is located at bits [31:16] of the translated address where:
Translated Address = Original Address - Base Address + Target Address
As an example
Original Address[31:16] = {13h0,function_no[2:0]}

Base Address[31:16] = 16h0
Target Address[31:16] = {bus_no[7:0],device_no[4:0],3h0}
then
Translated Address[31:16] = BDF ={bus_no[7:0],device_no[4:0],function_no[2:0]}
To handle eight functions (as the previous example indicates), you should use a 19-bit wide region size.
For CFG transactions created directly by your application (as opposed to the iATU), you must ensure that the BDF field does not
match any programmed iATU address region or else unintentional type translation could occur.
3.9.8.3.4 CFG shift feature†

Inbound CFG transactions routed to the Rx application interface can exist anywhere in address space, because the
PCIe controller filter processes the routing ID (BDF) as bits [31:16] of an address. This BDF changes according on
the PCIe bus topology. A compressor feature (CFG Shift Feature) can be enabled by setting the CFG Shift bit in the
IATU_REGION_CTRL_2_OFF_INBOUND_i register. Bits [15:12] of the third DWORD1 of CFG TLPs are reserved. The
compressor feature uses this fact to reduce the memory requirement. This shifts/maps the BDF (bits [31:16] of the third
header DWORD, which would be matched against the Base and Limit addresses) of the incoming CfgRd0/CfgWr0 down to
bits[27:12]of the translated address.
3.9.8.3.5 FMT translation†

The iATU automatically sets the TLP format field for three DWORDs when it detects all zeroed in the upper 32 bits of the translated
address. Otherwise it sets it to four DWORDs when it detects a 64-bit address (when there is a 1 in the upper 32 bits of the
[10] When SR-IOV is enabled, the Alternative Routing-ID Interpretation (ARI) scheme is used. This uses the 8:0:8 bit BDF format,
where the device number is assumed to be zero.
[11] The maximum size of this field is 8 bits, but the actual size depends on the number of VFs used as denoted by 2NVF_WD

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translated address). When the original address and the translated address are of a different format then the iATU ensures that
the TLP header size matches the translated address format.
3.9.8.3.6 Invert feature†

Normally an address match on an inbound TLP occurs when the untranslated address is in the region bounded by the Base
address and Limit address. When the Invert feature is activated, an address match occurs when the untranslated address is
not in the region bounded by the Base address and Limit address. This feature is activated by setting the Invert field of the
IATU_REGION_CTRL_OFF_2_INBOUND_i register.
3.9.8.3.7 DMA bypass feature†

When you do not want the iATU to translate outbound requests that are generated by the DMA, you must implement one of the
following approaches:
• Ensure that the combination of DMA channel address programming and iATU control register programming causes no
translation of DMA traffic to be done in the iATU.
• Activate the DMA bypass mode to allow request TLPs which are initiated by the embedded DMA controller to pass
through the iATU untranslated. You can activate the DMA bypass mode by setting the DMA Bypass field of the
IATU_REGION_CTRL_2_OFF_OUTBOUND_i register to 1.
3.9.8.3.8 Function number translation bypass feature†

In this mode the function number of the translated TLP is taken from your application transmit interface and not from
the Function Number field of the IATU_REGION_CTRL_1_OFF_OUTBOUND_i register or the Virtual Function field of the
IATU_REGION_CTRL_3_OFF_OUTBOUND_i register. You can activate the function number bypass mode by setting the Function
Number Translation Bypass Enable field in the IATU_REGION_CTRL_2_OFF_OUTBOUND_i to ‘1’.
Note: If the iATU is programmed to allow a TLP to be matched to more than one iATU outbound regions, the Function Number
Translation Bypass field of the IATU_REGION_CTRL_2_OFF_OUTBOUND_i register should be same for every region where that
TLP can be matched.
This is useful for AXI-based SR-IOV applications where the upper bits of the AXI ID are used to identify the source (PF or VF) of
a request. These upper bits of the ID can be mapped to the function number of the slave request PF/VF misc_info buses of the
controller. There is then no need for the iATU to translate the PF and VF information.
You can directly map an AXI ID to a PCIe function number as follows:
• Concatenate the AXI ID onto the MSBs of the AXI slave address (you need to configure the controller for a 64-bit AXI address).
• Use these upper MSBs to match to a unique region, with each region being assigned to a different function number.
3.9.8.3.9 General bypass†

When you set client0_tlp_iatu_bypass (AXI: slv_*misc_info_atu_bypass), the iATU will not process
that transaction.
3.9.8.3.10 Payload inhibit (Tx)†

When enabled and region address is matched, the iATU converts transactions with data payload to TLPs without payload data by
forcing the TLP header Fmt[1] bit =0, regardless of the application inputs such as slv_wstrb. The expected usage scenario is
Vendor Defined Msg (without data); your application sends a MWr over the AXI interface but does not set the byte write enables
to 0. This feature is enabled using the INHIBIT_PAYLOAD field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.
3.9.8.3.11 Header substitution (Tx)†

When enabled and region address is matched, the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or
bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW field in
IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. The expected usage scenario is for Vendor Defined Msg/MsgD and ATS

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transactions over the AXI bridge which is normally inefficient requiring a very large iATU region. Enabled using the
HEADER_SUBSTITUTE_EN field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.
3.9.8.3.12 Tag substitution (Tx)†

When enabled and region address is matched, the iATU substitutes the TAG field of the outbound TLP header with the contents
of the TAG field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i. The expected usage scenario is translation from AXI MWr to
Vendor Defined Msg/MsgD.Enabled using the TAG_SUBSTITUTE_EN field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i.
Your application must not attempt to perform TAG substitution for outgoing non-posted TLPs.
If the iATU is programmed to allow a TLP to be matched to more than one iATU outbound regions, the Function Number
Translation Bypass field of the IATU_REGION_CTRL_2_OFF_OUTBOUND_i register should be same for every region where that
TLP can be matched.
3.9.8.3.13 No address match result†

When there is no address match then the address is untranslated but the TLP header information (for fields that are
programmable) comes from the relevant fields on the application transmit interface AXI slave.
3.9.8.3.14 Writing to a MRdLk region†

When there is a successful address match for an outbound write and the type header field in the
IATU_REGION_CTRL_1_OFF_OUTBOUND_i register is “00001” indicating a locked MEM transfer, then the controller sets
the type field to “0000” (MEM).
3.9.8.4 Outbound programming†

This section discusses the register programming interface and provides details of programming examples.
3.9.8.4.1 iATU outbound programming overview†

You can access the iATU registers through the DBI interface or through BAR Matched Mem/IO requests. The following registers
are used for programming the iATU.
Table 45. iATU Register Map
Address Label (i = 0 to 5) Description
0x000 IATU_REGION_CTRL_1_OFF_OUTBOUND_i Region Control 1
0x004 IATU_REGION_CTRL_2_OFF_OUTBOUND_i Region Control 2
0x008 ATU_LWR_BASE_ADDR_OFF_OUTBOUND_i Lower Base Address
0x00C IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_i Upper Base Address
0x010 IATU_LIMIT_ADDR_OFF_OUTBOUND_i Limit Address
0x014 IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i Lower Target Address
0x018 IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_i Upper Target Address
0x01C IATU_REGION_CTRL_3_OFF_OUTBOUND_i Region Control 3
0x020 IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_i Upper Limit Address
The detailed descriptions for each register are given in the register descriptions elsewhere in this document.

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Table 46. iATU Register Address Bus Layout
Register Bit 31-20 1 18-17 16-9 8 7-2 1 0

9
Value Not used 0 Reserved Region Inbound/ Register Address 0 1

Outbound
Table 47. Example: Address Table for Accessing iATU Outbound Region 1 Configuration Registers
Address Register Name Register Bit Value
31-20 1 18-17 16-9 8 7-2 1 0

9
0x200 Region Control 1 0 0 0 1 000
0x208 Lower Base Address 0 0 0 1 008
0x20C Upper Base Address 0 0 0 1 00C
0x210 Limit Address 0 0 0 1 010
0x214 Lower Target Address 0 0 0 1 014
0x218 Upper Target Address 0 0 0 1 018
When the bridge slave interface clock (hresetn or slv_aclk) is asynchronous to the PCIe native controller clock (core_clk), you
must not update the iATU registers while operations are in progress on the AXI bridge slave interface. The iATU registers are in the
core_clk clock domain. The register outputs are used in the AXI bridge slave interface clock domain. There is no synchronization
logic between these registers and the AXI bridge slave interface.
3.9.8.4.2 Outbound iATU programming example†

Define Outbound Region 1 as:
64 kB I/O region from 0x80000000_d000000 to 0x80000000_d000ffff, to be mapped to 0x00010000 in the PCIe I/O space.
1. Setup the Region Base and Limit Address Registers.
Write 0xd0000000 to Address {0x208} to set the Lower Base Address.
Write 0x80000000 to Address {0x20C} to set the Upper Base Address.
Write 0xd000ffff to Address {0x210} to set the Limit Address.
2. Setup the Target Address Registers.
Write 0x00010000 to Address {0x214} to set the Lower Target Address.
Write 0x00000000 to Address {0x218} to set the Upper Target Address.
3. Configure the region through the Region Control 1 Register.
Write 0x00000002 to Address {0x200} to define the type of the region to be I/O.
4. Enable the region.
Write 0x80000000 to Address {0x204} to enable the region.
3.9.8.5 Inbound features†

Address translation is used for mapping different address ranges to different memory spaces supported by your application. A
typical example maps your application memory space to PCI memory space. The iATU supports type translation. Without address

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translation, your application address is passed from the TLPs directly through the TRGT1 application interface. You can program
the iATU to implement your own inbound address translation scheme without external logic.
• Programmable Match mode operation for MEM, I/O, CFG, and MSG TLPs. No translation for completions.
• Selectable BAR Match mode operation for I/O and MEM TLPs.
— TLPs destined for the internal CDM (or ELBI) in an upstream port are not translated.
— TLPs that are not error-free (ECRC, malformed and so on) are not translated.
• Selectable VF BAR Match mode operation for I/O and MEM TLPs which target VF BARs.
— The VF BAR match mode enables all VFs in a PF which match a BAR to be matched with a single ATU region instead
of an ATU region per VF.
• Programmable TLP header field matching.
— TYPE/TD/TC/AT/ATTR/MSG-Code/TH/PH/ST
— Function Number
• Multiple (up to 256) address regions programmable for location and size.
• Programmable enable/disable per region.
• Automatic FMT field translation between three DWORDs and four DWORDs for 64-bit addresses.
• Invert Address Matching mode to translate accesses outside of a successful address match.
• ECAM Configuration Shift mode to allow a 256 MB CFG1 space to be located anywhere in the 64-bit address space.
• Supports regions from 4 KB to 16 ZB in size.The minimum and maximum region sizes are 4 KB and 1 TB, respectively. Smaller
region sizes consume extra decode logic.
• Single Address Location to allow all TLPs to be translated to a single address location.
• Msg Type Match Mode to allow matching of any TLP of type Message.
The default behavior of the ATU when there is no address match in the outbound direction or no TLP attribute match in the inbound
direction, is to pass the transaction through.
3.9.8.6 Inbound limitations†

The iATU does not support generation of ATS requests and messages (no facility to insert NW and iTAG fields).
3.9.8.7 Inbound basic operation†

This section discusses how the iATU processes inbound requests.
3.9.8.7.1 Overview†
The main difference between inbound and outbound iATU operation is that the TLP type is never changed in the inbound
direction. Instead, the type field is used for more precise matching. Other fields can also be optionally used to further refine the
matching process.
Another difference is that for MEM and I/O TLPs, you can select between address matching (as used in outbound operation)
or BAR matching. Normally, an endpoint uses BAR match mode, and a root complex uses address mode as an root complex
normally does not implement BARs.
The following translation rules and limitations apply:
• When there is no match, then the address is untranslated. In addition
• TLPs destined for the internal CDM or ELBI in an upstream port are not translated.
• TLPs that are not error-free (ECRC, malformed and so on) are not translated.

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• Address translation of all TLP types (MEM, I/O, CFG, and MSG) except completion is supported in Address Match mode. In
BAR Match mode, only translation of I/O and MEM is supported.
The setting of the MATCH_MODE field in IATU_REGION_CTRL_2_OFF_INBOUND_0 determines how iATU inbound matching is
done for each TLP type.
Table 48. Determination of match mode
TLP Type MATCH_MODE =0 MATCH_MODE =1
MEM or I/O Address Match Mode BAR Match Mode
CFG0 Routing ID Match Mode Accept Mode
MSG/MSGD Address Match Mode Vendor ID Match Mode
3.9.8.7.2 I/O and MEM match modes†

Inbound address translation for I/O and MEM TLPs operates in one of two matching modes as determined by the “Inbound Match
Mode” field in the IATU_REGION_CTRL_2_OFF_INBOUND_0 register.
3.9.8.7.2.1 Address match mode†

The operation is similar to Outbound basic operation (Address Match mode)†. The address field of each request TLP is checked
to see if it falls into any of the enabled[12] address regions as shown in Figure 31. When an address match is found then the TLP
address field is modified as follows:
Address = Address - Base Address + Target Address
When the TLP address field matches more than one of the four address regions, then the first (lowest of the numbers from 0 to
3) enabled region to be matched is used.
3.9.8.7.2.2 BAR match mode†

Looking for an address match is a two-step process.
1. The standard internal PCI Express BAR Matching Mechanism checks if the address field of any MEM and I/O request TLP
falls into any address region defined by the enabled BAR addresses and masks.
2. When a matched BAR is found, then the iATU compares the BAR ID to the BAR Number field in the
IATU_REGION_CTRL_2_OFF_INBOUND_0 register for all enabled regions. Figure 30 and Figure 31 provide more details
on inbound translation in BAR Match Mode.
BAR Match Mode can only be used for MEM and I/O transactions.
When the PCIe controller is operating with 64-bit BARs, the operation is defined as in Figure 30 where * is log2(BAR_MASK+1).
[12] When the Region Enable bit of the Region Control 2 Register is 0, then that region is not used for address matching.

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Region Size = set by the BAR Mask

of the matched-BAR.
Untranslated Translated
Address Map Address Map
x = Matched-BAR number

Region #x space can be 64-bits or 32 bits.
Region #x
63 0
0x0000
63 Start Address 0 31 0 31 * 0
eATU Region#x Register eATU Region#x Register
63 0
BAR#x
Figure 30. iATU address region mapping: Inbound (BAR match mode), 64-bit BAR
In address match mode, when the address range does not match one of its BAR ranges in an upstream port, then the device
rejects the request with unsupported request (UR) completion status and no translation occurs. When the PCIe controller is
operating with 32-bit BARs, the operation is defined as in Figure 31.
Region Size = set by the BAR Mask

of the matched-BAR.
Untranslated Translated
Address Map Address Map
x = Matched-BAR number

Region #x space can be 64-bits or 32 bits.
Region #x
63 0
0x0000
31 Start Address 0 31 0 31 * 0
eATU Region#x Register eATU Region#x Register
31 * 0
BAR #x % is determined by BAR#x Mask Register
Figure 31. iATU address region mapping: Inbound (BAR match mode), 32-bit BAR
3.9.8.8 Inbound detailed operation†
3.9.8.8.1 VF BAR Match mode (upstream port)†

Like BAR Match mode, VF BAR Match mode is a two step process:
1. The standard internal PCI Express and SR-IOV BAR Matching Mechanism checks if the address field of any MEM request
TLP falls into any address region defined by the enabled VF BAR addresses and masks.
2. When a matched VF BAR is found, then the iATU compares the BAR ID to the BAR Number field in the
IATU_REGION_CTRL_2_OFF_INBOUND_i register for all enabled regions.
For VF BAR Match Mode, there is one region allocated for all VFs associated with any given PF. When VF BAR Match Mode is
not enabled, then one iATU region must be allocated to each VF.

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associated
PFi VF0 VF1 VFj
PF
1 x iATU region
region region
limit limit
address address
Figure 32. VF BAR Match mode
When SR-IOV is enabled, the PF function number matching FUNC_NUM_MATCH_EN field in the
IATU_REGION_CTRL_2_OFF_INBOUND_i register is made sensitive to VF BAR matching. Therefore, PF function number
match will be successful if any of the following occur:
• VF_MATCH_EN =1: When the Function Number TLP field matches the Function Number field of the iATU Control 1 Register
and when there is a successful VF BAR match.
• FBAR_MATCH_MODE_EN =1: When the Function Number TLP field matches the Function Number field of the iATU Control 1
Register and when there is a successful VF BAR match.
• VF_MATCH_EN = VFBAR_MATCH_MODE_EN =0: When the Function Number TLP field matches the Function Number field of
the iATU Control 1 Register and when there is not a successful VF BAR match.
3.9.8.8.2 Single address location†

When enabled and region address is matched, the TLPs can be translated to a single address location as determined by
the target address register of the iATU region. This feature can be enabled using the SINGLE_ADDR_LOC_TRANS_EN field
in IATU_REGION_CTRL_2_OFF_INBOUND_i.
Bytes 8 to 15 of the received TLPs header destined for TRGT1 are made available on radm_trgt1_ hdr_uppr_bytes
irrespective of TLP translation. When radm_trgt1_hdr_uppr_bytes_valid is asserted your application should use
radm_trgt1_hdr_uppr_bytes along with radm_trgt1_data.The radm_trgt1_hdr_uppr_bytes_valid is set only
when an ATU match occurs for Single Address Location enabled region.
For example, if a received MsgD matches a Single Address Location enabled ATU region, bytes 8 to 15 of the MsgD
header are available on radm_trgt1_hdr_uppr_bytes when radm_trgt1_hdr_uppr_bytes_valid is asserted, and
radm_trgt1_hv is true. The available radm_trgt1_hdr_uppr_bytes can be concatenated with radm_trgt1_data and
used by your application.
The width of radm_trgt1_ hdr_uppr_bytes is FLT_Q_ADDR_WIDTH bits.
For radm_trgt1_hdr_uppr_bytes[63:32] to exist FLT_Q_ADDR_WIDTH must be 64.
If 32 < FLT_Q_ADDR_WIDTH < 64, radm_trgt1_hdr_uppr_bytes[FLT_Q_ADDR_WIDTH-1:32] = 0.
3.9.8.8.3 CFG handling (upstream port)†

The controller normally routes CFG TLPs (to the internal CDM or ELBI) without translation. The iATU only translates
CFG0 TLPs that the controller has routed to the Rx application interface. Inbound address translation for CFG0
TLPs operates in one of two matching modes as determined by the Inbound CFG0 Match Mode field in the
IATU_REGION_CTRL_2_OFF_INBOUND_i register.
3.9.8.8.3.1 Accept mode†

The controller always accepts CFG0 TLPs even when the CFG bus number does not match the current bus number of the device.
This mode follows that behavior. The routing ID of received CFG0 TLPs are ignored when determining a match.

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3.9.8.8.3.2 Routing ID Match mode†

The operation is similar to Outbound basic operation (Address Match mode)†. The routing ID of the inbound CFG0 TLP must fall
within the Base and Limit of the defined iATU region for matching to proceed. The iATU interprets the routing ID (Bytes[13] 8-11
of TLP header) as an address. This corresponds to the upper 16 bits of the address in MEM and I/O transactions.
3.9.8.8.3.3 CFG shift feature†

Inbound CFG transactions routed to the Rx application interface can exist anywhere in address space, because the
PCIe controller filter processes the routing ID (BDF) as bits [31:16] of an address. This BDF changes according on
the PCIe bus topology. A compressor feature (CFG Shift Feature) can be enabled by setting the CFG Shift bit in the
IATU_REGION_CTRL_2_OFF_INBOUND_i register. Bits [15:12] of the third DWORD1 of CFG TLPs are reserved. The
compressor feature uses this fact to reduce the memory requirement. This shifts/maps the BDF (bits [31:16] of the third
header DWORD, which would be matched against the Base and Limit addresses) of the incoming CfgRd0/CfgWr0 down to
bits[27:12]of the translated address.
3.9.8.8.3.4 CFG1 transactions†

For CfgRd1/CfgWr1 transactions, the base and limit addresses could enclose the entire 32-bit 4 GB memory space with the routing
ID forming the upper 16 bits. The target address maps these CFG transactions to anywhere in application address space.
3.9.8.8.4 Optional matching fields†

In address and BAR match modes, a successful address/BAR match can be optionally gated by successful matching of the
following programmable TLP header fields (per region):
• TYPE/TD/TC/AT/ATTR/TH/PH/ST
• MSG Code (MSG TLPs only)
• Function number (MEM, I/O, or CFG TLPs only)
• Virtual function number (MEM or I/O TLPs only)
For each of the previous fields in the IATU_REGION_CTRL_1_OFF_INBOUND_i register, there is an associated Match Enable
bit in the IATU_REGION_CTRL_2_OFF_INBOUND_i register. Address translation only proceeds when compares on all enabled
field are successful.
3.9.8.8.5 Response code feature†

When the Response Code field of the IATU_REGION_CTRL_REG_2_INBOUND_i register is set to a value other than 00, the
controller uses it to determine the completion status field of completion TLPs sent in response to successfully matched non-posted
TLPs. This can be set to unsupported request (UR) or completer abort (CA). When the error response field is set to 2b00, then
the normal receive filter response for this TLP is used.
Response Code feature is not available in regions where Single Address Location Enable is set.
3.9.8.8.6 iATU inbound MSG handling†

Inbound message (Msg/MsgD) transactions can use one of two matching modes:
[13] For more details, see Figure 2-18 Request Header Format for Configuration Transactions in Section 2.2.7 Memory, I/O, and
Configuration Request Rules of the PCI Express Base Specification.

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Table 49. Matching modes
Mode Description
Address Match The third and fourth header DWORDs are treated as an
address and are compared against the iATU Region Base
and Limit Address registers. For vendor defined messages
this allows specific messages to be filtered into memory at
the target address. The Upper Base address should be set to
Bus.Device.Function (BDF) and Vendor ID. The Lower Base
address can be used as a filter for specific messages.
Vendor ID Match This mode is relevant for ID-routed vendor defined messages.
The iATU ignores the routing ID (BDF) in bits [31:16] of the
third DWORD of the TLP header1, but compares it against the
vendor ID in bits [15:0] of the third DWORD of the TLP header
(bytes1 10 and 11). This allows vendor defined messages
to be filtered against specific vendor IDs without needing to
know the BDF number which might vary depending on the PCI
topology. Bits [15:0] of the Region Upper Base register should
be programmed with the required vendor ID as follows:
Region Upper Base[15:8] =byte 10

Region Upper Base[7:0] =byte 11
The lower base and limit register should be programmed to

translate TLPs based on vendor-specific information in the
fourth DWORD of the TLP header.
1. In Figure 2-25 Header for Vendor_Defined Messages in Section 2.2.8.6, Vendor_Defined Message of the PCI Express
Base Specification.
For more information on generating messages, see Message generation†.

For a proper understanding of messages, you should be familiar with Section 2.2.8, Message Request Rules of the PCI Express
Base Specification.
3.9.8.8.7 Msg Type Match mode†

Inbound message (Msg/MsgD) transactions can also use Msg Type Matching mode. When this mode is
enabled and Single address location† is enabled, the iATU matches Msg TLP Type field with TYPE field of
IATU_REGION_CTRL_1_OFF_INBOUND_i register.
If Fuzzy Type Match mode† is also enabled, then any Msg received will be matched (that is, Msg Type's sub-field r[2:0], which
specifies the Message routing mechanism, is ignored).
The Message should be consumed by your application before the next message arrives as all messages go to the same address.
If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN is set for any region, then you must ensure that the same TLP
cannot be matched in any other region where SINGLE_ADDRESS_LOCATION_TRANSLATE_EN is not set. If this happens
radm_trgt1_hdr_uppr_bytes could have incorrect data.
3.9.8.8.8 Fuzzy Type Match mode†

When enabled, the iATU relaxes the matching of the TLP type field against the expected type field so that:
• CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1.

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• MWr, MRd and MRdLk TLPs are seen as identical.

• The routing field of MsgD TLPs is ignored.
• Atomic Ops TLPs - FetchAdd, Swap, and CAS are seen as identical.
For example, CFG0 in the type field in the IATU_REGION_CTRL_1_OFF_INBOUND_i register matches against an
inbound CfgRd0, CfgRd1, CfgWr0, or CfgWr1 TLP. To enable this feature, set the Fuzzy Type Match Mode bit of the
3.9.8.8.9 FMT translation†

The iATU automatically sets the TLP format field for three DWORDs when it detects all zeroed in the upper 32 bits of the translated
address. Otherwise it sets it to four DWORDs when it detects a 64-bit address (when there is a 1 in the upper 32 bits of the
translated address). When the original address and the translated address are of a different format then the iATU ensures that
the TLP header size matches the translated address format.
3.9.8.8.10 Invert feature†

Normally an address match on an inbound TLP occurs when the untranslated address is in the region bounded by the Base
address and Limit address. When the Invert feature is activated, an address match occurs when the untranslated address is
not in the region bounded by the Base address and Limit address. This feature is activated by setting the Invert field of the
3.9.8.9 Inbound programming†

This section discusses the register programming interface and provides details of programming examples.
You can access the iATU registers through the DBI interface or through BAR Matched Mem/IO requests. The following registers
are used for programming the iATU.
Table 50. iATU register map
Address Label (i = 0 to 3) Description
0x100 IATU_REGION_CTRL_1_OFF_INBOUND_i Region Control 1
0x104 IATU_REGION_CTRL_2_OFF_INBOUND_i Region Control 2
0x108 ATU_LWR_BASE_ADDR_OFF_INBOUND_i Lower Base Address
0x10C IATU_UPPER_BASE_ADDR_OFF_INBOUND_i Upper Base Address
0x110 IATU_LIMIT_ADDR_OFF_INBOUND_i Limit Address
0x114 IATU_LWR_TARGET_ADDR_OFF_INBOUND_i Lower Target Address
0x118 IATU_UPPER_TARGET_ADDR_OFF_INBOUND_i Upper Target Address
0x11C IATU_REGION_CTRL_3_OFF_INBOUND_i Region Control 1
0x120 IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_i Upper Limit Address

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Table 51. iATU register address bus layout
Register Bit 31-20 19 18-17 16-9 8 7-2 1 0
Value Not used 0 Reserved Region Inbound/ Register Address 0 1

Outbound
Table 52. Example: address table for accessing iATU inbound region 1 configuration registers
Address Register Name Register Bit Value
31-20 19 18-17 16-9 8 7-2 1 0
0x308 Lower Base Address 0 0 0 1 108
0x30C Upper Base Address 0 0 0 1 10C
0x310 Limit Address 0 0 0 1 110
0x314 Lower Target Address 0 0 0 1 114
0x318 Upper Target Address 0 0 0 1 118
0x31C Region Control 3 0 0 0 1 118
0x320 Upper Limit Address 0 0 0 1 118
When the bridge slave interface clock (hresetn or slv_aclk) is asynchronous to the PCIe native controller clock (core_clk), you must
not update the iATU registers while operations are in progress on the AXI bridge slave interface. The iATU registers are in the
core_clk clock domain. The register outputs are used in the AXI bridge slave interface clock domain. There is no synchronization
logic between these registers and the AXI bridge slave interface.
3.9.9 Gen2/3 speed modes†
3.9.9.1 Gen2 5.0 GT/s operation†

The controller supports all of the non-optional Gen2 5.0 GT/s features defined in the PCI Express Base Specification, Revision
4.0, Version 0.9. The interface between the controller and the PHY is compliant with PIPE Specification for PCI Express, Version
4.4.1. The controller supports two different mechanisms of achieving the Gen2 rate: dynamic frequency and dynamic width.
• For dynamic frequency configurations, the number of active symbols on the PIPE is constant and the frequency of the
controller doubles each time as the controller transitions from Gen1 -> Gen2 rate.
• When supporting dynamic width, the clock frequency of the controller remains constant and the number of active symbols on
the PIPE doubles each time as the controller transitions from Gen1 -> Gen2 rate.
3.9.9.1.1 Speed changing†

When you set the default of the Directed Speed Change field of the Link Width and Speed Change Control register
(GEN2_CTRL_OFF . DIRECT_SPEED_CHANGE) using the DEFAULT_GEN2_SPEED_CHANGE configuration parameter to 1,
then the speed change is initiated automatically after link up, and the controller clears the contents of GEN2_CTRL_OFF .
DIRECT_SPEED_CHANGE. If you want to prevent this automatic speed change, then write a lower speed value to the Target Link
Speed field of the Link Control 2 register (LINK_CONTROL2_LINK_STATUS2_REG . PCIE_CAP_TARGET_LINK_SPEED) through
the DBI before link up.
To manually initiate the speed change then:
• Write to LINK_CONTROL2_LINK_STATUS2_REG . PCIE_CAP_TARGET_LINK_SPEED in the local device

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• Deassert GEN2_CTRL_OFF . DIRECT_SPEED_CHANGE in the local device

• Assert GEN2_CTRL_OFF . DIRECT_SPEED_CHANGE in the local device
The controller uses the mac_phy_rate output to negotiate the link data rate. It changes the rate signal and waits for a pulse on
the phy_mac_phystatus signal to confirm that the PHY has accepted the requested rate.
As per the PCI Express Base Specification, Revision 4.0, Version 0.9, the controller does not implement the optional Compliance
Receive bit for Gen1 configurations.
3.9.9.2 Gen3 8.0 GT/s operation†

The controller supports all of the non-optional Gen3 8.0 GT/s features defined in the PCI Express Base Specification, Revision
4.0, Version 0.9. The interface between the controller and the PHY is compliant with PIPE Specification for PCI Express, Version
4.4.1. The controller supports two different mechanisms of achieving the Gen3 rate: dynamic frequency and dynamic width.
• For dynamic frequency configurations, the number of active symbols on the PIPE is constant and the frequency of the
controller doubles each time as the controller transitions from Gen1 -> Gen2 -> Gen3 rates.
• When supporting dynamic width, the clock frequency of the controller remains constant and the number of active symbols on
the PIPE doubles each time as the controller transitions from Gen1 -> Gen2 -> Gen3 rates.
3.9.9.2.1 Gen3 speed changing†

See Speed changing†.
3.9.9.2.2 Gen3 8.0 GT/s transmitter equalization†

The controller performs link equalization during link training to improve signal quality by adjusting the transmitter and receiver
equalization parameters for each lane on each side of the link.
This controller uses the Dynamic PHY mode for mapping of presets to coefficients. In this mode, the coefficients are dynamically
mapped in the PHY.
There are two feedback modes for determining the optimal equalization settings, programmable using the Gen3 EQ Control
Register (GEN3_EQ_CONTROL_OFF).
• Figure of merit (FOM)
• Direction change with optional convergence support
3.9.10 Power management†

This section discusses the power management (PM) features of the controller. For a proper understanding of PCIe power
management, you should read Chapter 5, Power Management, of the PCI Express Base Specification, Revision 4.0, Version 0.9.
3.9.10.1 Overview†
The controller supports two categories of PM operations to control the device state (D-state) and link state.
3.9.10.1.1 Software PCI-compatible PM (PCI-PM)†

• D-state PM of Function. The host software can direct the function to enter any of the D1, D2, or D3 low-power states. It does
this by writing to the Power Management Control and Status Register (PMCSR) in the PCI-PM capability structure.
• D-state PM of Link. Link states are not visible to PCI-PM legacy compatible software, and are derived from the power
management D-states of the components connected to that link. The action of changing the D-state in the PMCSR indirectly
causes a change in the link power state. The L1 state is entered whenever all functions of a USP on a link are programmed
to a non-D0 state. The entry into L2 and L3 states is initiated by the DSP.
• Clock PM (L1 with REFCLK removal/PLL Off). This is an optional feature that enables components on a link to further reduce
idle power consumption while the link is in L1, by turning off the PLL.

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3.9.10.1.2 Native PCIe PM mechanisms†

• Active State PM (ASPM). When the USP is in L0 and detects idleness on the link for a specific amount of time, it automatically
transitions the link to the L0s or L1 (optional) power state.
• L1 Substates. This is an optional PCIe feature that enables components on a link to further reduce idle power consumption
while the link is in L1, including almost complete removal of power for the high speed PHY circuits.
3.9.10.1.3 Relationship between D-state, link state, and PHY state†

The link state and D-state determine what power and clock supplies are on or off.
Table 53. Power/clock supply status in low-power states of interest (DSP or single function non-ARI USP)
D-State Permissible Link State Change Active Power Active Clock pipe_clk PHY State
Quiescent Link Trigger (see Table Supplies Supplies1 core_clk
States 54)
D0unitialized L0 n/a Vmain REFCLK ON P0, P0S

Vaux AUXCLK
D0active L0 ASPM
L0S
L1 ON P1
D1, D2, D3hot L1 PCI-PM
D3cold2 L2 PCI-PM Vaux AUXCLK OFF P2/OFF
L33 None None
1. REFCLK is the platform reference clock for the PHY TX PLL. AUXCLK is the platform low-power clock.
2. Transitioned from D3hot to D3cold by removal of Vmain. D3cold is entered by the controller in response to
PME_Turn_Off MSG
3. A function can be transitioned from L2 to L3 by the removal of Vaux.
D0 is divided into two distinct substates, the uninitialized substate and the active substate. When a component comes out of
conventional reset or FLR, it defaults to the D0uninitialized state. A function enters the D0active state whenever any of the functions
Memory Space Enable, I/O Space Enable, or Bus Master Enable bits have been enabled by system software.
Table 54. Link-state-change trigger capabilities for each port type
Port Type Can Trigger L0/L0s Can Trigger L1 Entry Can Trigger L2/L3 Entry
Entry
USP Yes Yes, on any of these triggers1: No

• Software programs non-D0 state (PCI-PM)
• USPs idle timer expires (ASPM)
• Application requests the USP to enter L12
DSP No No3 Yes4
1. You can prevent/delay the controller from entering L1-ASPM (not L1-PCI-PM) by asserting app_xfer_pending.
2. USP application asserts the app_req_entr_l1 input. A DSP controller ignores this input.
3. DSP can indirectly initiate L1 by writing non-D0 value to PMCSR of the USP link partner. A non-D0 write to the USP PMCSR
always triggers a transition to L1.

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4. L2/L3 entry is initiated after the RC PM software transitions a device into a D3 state and subsequently instructs the DSP to
transmit PME_Turn_Off message TLP to initiate the removal of power and clocks.
Table 55 indicates the different levels of power savings (obtained by switching off circuits outside the controller) that can be
expected from executing L1 in different ways. Higher exit latencies are associated with higher power savings. Power saving and
latency are PHY implementation specific, and may be determined by consulting your PHY documentation.
Table 55. L1 execution modes and permissible power states of PHY circuits
L1 Execution Mode Permissible Power States for PHY Circuits
PLL/REFCLK RX Electrical Idle Detector TX Common Mode
L1 without Clock PM ON ON ON
L1 with Clock PM OFF ON ON
L1.1 OFF OFF ON
L1.2 OFF OFF OFF
3.9.10.1.4 Device state (D-state) power management of a function (USP)†

The host software can direct the downstream device function to enter any of the low-power states:
• D1 (light sleep)
• D2 (deep sleep)
• D3hot (full of; reference clock optionally removed; Vmain normally available)
• D3cold (full of; reference clock removed; Vmain removed; Vaux optionally available)
It does this by writing to the PMCSR in the PCI-PM capability structure. This action also indirectly causes the downstream
component (USP) to change the link power state. The controller negotiates with the link partner using PM TLPs and DLLPs before
entering the corresponding low-power link state. The controller exits the device low-power state (and returns to D0) when it detects
a CFG access to a device function, or when it detects a PME such as an event on the outband_pwrup_cmd[14] input signal. For
a function in device power states D1, D2, and D3hot, the controller only accepts CFG and MSG requests TLPs for that function.
All other incoming request types for that function are treated as unsupported requests (UR). For more details see Section 5.3.3,
“Power Management Event Mechanisms” of the PCI Express Base Specification, Revision 4.0, Version 0.9.
3.9.10.1.5 Active state power management (ASPM)†

You must enable ASPM through the ASPM Control field in the Link Control register. When the USP is in L0 and detects idleness
on the link for a specific amount of time (determined by the L0s Entrance Latency field[15] in the “Ack Frequency and L0-L1 ASPM
Control Register” ACK_F_ASPM_CTRL_OFF), it automatically transitions the link to the L0s power state. Each link direction (TX
and RX) is processed separately. The controller exits L0s when there is traffic waiting to be sent.
When the USP is in L0 or L0s and it detects idleness on the link (both directions) for a specific amount of time (determined by the
L1 Entrance Latency field in ACK_F_ASPM_CTRL_OFF), it automatically transitions the link to the L1 power state. The link partners
must negotiate entry into the L1 link power state using PM TLPs and DLLPs. The L1 state achieves greater power savings but
the exit latency from this state is higher than from L0s. You can also instruct an USP controller (only) to enter L1 by asserting
the app_req_entr_l1 input. The USP exits L1 when there is traffic waiting to be sent or when a PME (such as an event on the
app_req_exit_l1 input) is received.
If the ASPM exit latencies from L0s or L1 are too high for the overall PCIe system data latency requirements, then the host
software can disable ASPM using the ASPM Control Field of the Link Control register. The controller reports the exit latencies
[14] Or on apps_pm_xmt_pme as these inputs are functionally identical.

[15] You set this by writing to this register or by setting DEFAULT_L0S_ENTR_LATENCY or DEFAULT_L1_ENTR_LATENCY.

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using the Link Capability registers. You set these by writing to these registers or by setting the DEFAULT_L0S_EXIT_LATENCY
and DEFAULT_L1_EXIT_LATENCY parameters.
3.9.10.1.6 Registers shadowed in power management controller†

The following lists the registers shadowed in the power management controller (PMC) and the reason for shadowing them.
Table 56. Registers shadowed in PMC
Register Field Description Reason for shadowing
Device Control Register Aux Power PM Enable Enable aux power support for a The PCI Express Base
function. Specification, Revision 4.0,
Version 0.9, specifies that the
value of this bit must be
preserved in the D3cold state. In
L2 when power is removed the
CDM loses its context. This bit is
preserved in the PM under AUX
power and fed back to the CDM.
PMCSR PME_EN Indicates if a function is permitted to PME message request, if

generate a PME. enabled, can trigger a wakeup
from L2 if main power has been
removed.
PMCSR_BSE PowerState Indicates the D-state of a function. Used for entry to low power
states.
Link Capabilities Register Clock Power If set to 1 this indicates that an Used for the removal of reference
Management upstream port tolerates the removal clock in L1 or L2/L3 Ready.
of reference clock when the link is in
L1 or L2/L3 Ready.
AUX_CLK_FREQ_OFF AUX_CLK_FREQ The frequency of the aux_clk in This field is used to scale certain
MHz. timers in the power management
block. It needs to be shadowed
since the CDM is reset when
power is removed in L2.
GEN3_RELATED_OFF GEN3_ZRXDC_NONC GEN3 Receiver impedance zrx-dc This bit enables a 100ms timer
OMPL not compliant. which can trigger exit from L1.
3.9.10.2 L0s entry and exit conditions†

This section discusses the L1 link state.
L0s is a low-power state enabled by ASPM. ASPM controls entry into L0s for the transmitter. The remote device controls entry
into L0s for the receiver.
3.9.10.2.2 L0s entry†

All of these condition must be met in the USP:
• ASPM L0s is enabled through the ASPM Control field in the Link Control register.
• L0s entry conditions as defined in Section 5.4.1.1.1, “Entry into the L0s State” of the PCI Express Base Specification, Revision
4.0, Version 0.9, exist for a duration of time (determined by the L0S_ENTRANCE_LATENCY field in ACK_F_ASPM_CTRL_OFF).

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• No higher stage of power-down requested.
3.9.10.2.3 L0s exit†

Any of these condition can be met in the USP:
• A DLLP or TLP is pending to be sent.
• L1 entry conditions as defined in Section 5.4.1.2.1, “Entry into the L1 State” of the PCI Express Base Specification, Revision
4.0, Version 0.9, are satisfied.
• PCIe link partner requests to enter into link recovery.
3.9.10.2.4 Multifunction and ARI-capable devices (endpoint)†

The prerequisite ASPM control and D-state conditions for ASPM L0s entry for ARI-capable and multifunction devices are:
• Function is in D0
• Policy is determined by ASPM control settings
For more details, see Chapter 5.4.1, "Active State Power Management (ASPM)" of the PCI Express Base Specification, Revision
4.0, Version 0.9.
3.9.10.3 L1 operation (non-substates)†
3.9.10.3.1 L1 (ASPM/PM) entry and exit conditions†

This section discusses the L1 link state. L1 is a low-power state enabled either by ASPM (L1-ASPM) or by the software changing
the D-state (L1-PM). The L1 state is a bi-directional link low-power state and both link partners must negotiate to go to this state.
3.9.10.3.1.1 L1-ASPM overview†

The L1-ASPM entry negotiation handshake uses PM_Active_State_Request_L1 DLLPs, PM_Request_Ack DLLPs, and
PM_Active_State_Nak MSG TLPs. There are three scenarios that cause the controller to enter L1 under ASPM conditions.
3.9.10.3.1.2 L1-ASPM entry (scenario 1): L1 idle timeout in L0s†

• ASPM L1 and L0s are enabled through the ASPM Control field in the Link Control register.
• The ENTER_ASPM field of ACK_F_ASPM_CTRL_OFF is set to ‘0’ and the link state is L0s for both link partners,
or
the ENTER_ASPM field of ACK_F_ASPM_CTRL_OFF is set to ‘1’.
4.0, Version 0.9, exist for a duration of time (determined by the L1_ENTRANCE_LATENCY field in ACK_F_ASPM_CTRL_OFF).
• No higher stage of power-down requested.
• Your USP application is not asserting the app_xfer_pending input.
• There are no in-progress transactions[16] in the controller such as:
— Rx queue P/NP Request TLPs
— Rx queue CPL TLPs
— Outstanding/expected wire completions
[16] Created by your application, or remote link partner, or the embedded DMA. DBI requests do not prevent L1 entry because
the CDM registers (including DMA) are clocked off aux_clk_g.

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— Outstanding/expected application (at the AXI master interface when present) completions
• There are no pending requests at the AXI slave interface, that is, slv_a*valid must be 0.
• There are no pending DMA transfers.
3.9.10.3.1.3 L1-ASPM entry (scenario 2): L1 idle timeout in L0†

• ASPM L1 is enabled and L0s is not enabled through the ASPM Control field in the Link Control register.
• Link state is L0.
4.0, Version 0.9, exist for a duration of time (determined by the L1_ENTRANCE_LATENCY field in ACK_F_ASPM_CTRL_OFF).
• No higher stage of power down-requested.
• There are no in-progress transactions in the controller such as:
3.9.10.3.1.4 L1-ASPM entry (scenario 3): application controlled (USP only)†

• ASPM L1 is enabled through the ASPM Control field in the Link Control register.
• Your application logic pulses the app_req_entr_l1 input.
• There are no in-progress transactions[17] in the controller such as:
3.9.10.3.1.5 L1-ASPM additional information (USP)†

The prerequisite ASPM control and D-state conditions for ASPM L1 entry for ARI-capable and multifunction devices are:
• Function is in D0
• Policy is determined by ASPM control settings
[17] Created by your application or remote link partner, or the embedded DMA. DBI requests do not prevent L1 entry because
the CDM registers (including DMA) are clocked off aux_clk_g.

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For more details, see Chapter 5.4.1, "Active State Power Management (ASPM)" of the PCI Express Base Specification, Revision
4.0, Version 0.9.
3.9.10.3.1.6 L1-PM entry†

The power management state of a link is determined by the D-state of the USP. When you change the device state of the USP
to D1, D2, or D3hot by writing to the PMCSR, the controller must initiate a link state transition to L1. The USP of a non-ARI
multi-function device must not initiate a link state transition to L1 until all of its functions have been programmed to a non-D0
D-state. L1 state is a bi-directional link low-power state. Both link partners must negotiate to go this state. The L1-PM negotiation
handshake uses the following DLLPs:
• PM_Enter_L1
• PM_Request_Ack
All of these condition must be met:
• L1 entry conditions are satisfied as defined in Section 5.3.2.1, “Entry into the L1 State” of the PCI Express Base Specification,
Revision 4.0, Version 0.9.
A USP application asserting the app_xfer_pending input does not prevent L1-PM entry, but will cause immediate exit
from L1-PM.
The D-state prerequisite condition for L1 entry for ARI-capable and multifunction devices is that the function not be in D0.
3.9.10.3.1.7 L1-PM or L1-ASPM exit†

Any of these conditions are met:
• A DLLP or TLP is pending to be sent.
• Your application asserts the app_req_exit_l1 input.
• Your application asserts the app_xfer_pending input.
• Your application asserts the apps_pm_xmt_pme input. When the USP is programmed[18] with capability to support PME;
it sends a PME message to the RC which calls the PM software to transition the USP to the D0 state. Therefore, you
should only use apps_pm_xmt_pme for L1-PM exit.
• Link partner is requesting exit from L1.
• PM software (RC) requests a higher stage of power-down by writing to the PMCSR in the USP.
• Your application is requesting to send traffic by asserting client0_tlp_hv (non-AXI) or slv_a*valid (AXI).
• Your application enables a DMA read or write channel, or DMA controller is requesting data.
NOTE
When you use the PCIe controller in EP mode, you must write 0b to PMCSR[POWER_STATE]
after you enable the DMA doorbell (see DMA_WRITE_DOORBELL_OFF[WR_DOORBELL_NUM] or
DMA_READ_DOORBELL_OFF[RD_DOORBELL_NUM]). If you do not do this, the link reenters the L1 state
and TLPs are blocked on the link.
• Your application (DSP) initiates link disable, or link retrain (by setting PCIE_CAP_LINK_DISABLE or
PCIE_CAP_RETRAIN_LINK field in LINK_CONTROL_LINK_STATUS_REG to 1).
• Your application (DSP) initiates hot reset by any of these:
— Setting RESET_ASSERT field in PORT_LINK_CTRL_OFF to 1
— Setting SBR field in BRIDGE_CTRL_INT_PIN_INT_LINE_REG to 1
— Toggling app_init_rst
[18] PME_ENABLE bit is set in CON_STATUS_REG, and the PME_SUPPORT bit is set in CAP_ID_NXT_PTR_REG for the
corresponding D-state for which the function is currently in.

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• Your application requests a speed change (by setting DIRECT_SPEED_CHANGE field in GEN2_CTRL_OFF to 1).
• Your application requests link width change (by setting DIRECT_LINK_WIDTH_CHANGE field in
MULTI_LANE_CONTROL_OFF is set to 1).
• Your application (USP) requests transmission of VDM, MSI/MSIX[19], or LTR message.
• Your application (DSP) requests transmission of Unlock message.
MSIX accesses cannot be performed when the controller is in L1. To perform MSIX access, the controller must be woken up
from L1.
The CDM space is accessible in L1, but some CDM register bits will not produce the desired results.
Writing to CDM register bits which trigger LTSSM state transitions in L1 will not have the desired effect, because the LTSSM clock
is not running in L1.
Any DMA register can be accessed in L1 because the DMA registers are clocked on aux_clk_g.
When core_clk is removed in L1 substates or L1 clock power management, aux_clk_g is used.
The core acknowledges a maximum of one read and one write Doorbell during L1.
Doorbelling any DMA read/write channel triggers L1 exit.
Writing to other DMA registers does not trigger L1 exit.
During L1 exit, there is a latency in restoring the core_clk. A second read or write Doorbell is not acknowledged until core_clk
is restored.
3.9.10.4 L2 and L3 power down entry and exit conditions (USP)†
L2/L3 entry is initiated[20] after the RC calls power management software to initiate the removal of power and clocks. USPs of
devices in D0, D1, D2, and D3hot must respond to the receipt of a PME_Turn_Off MSG TLP by transmitting a PME_TO_Ack MSG
TLP. The device must then request a link transition to L2/L3_Ready. L2/L3_Ready is a bi-directional link power down state. If your
application is not ready to be shut-down, it must keep the app_ready_entr_l23 input de-asserted. This causes the controller
to delay sending the PM_Enter_L23 DLLP and thereby stalling the negotiation handshake that uses the following DLLPs:
• PM_Enter_L23
• PM_Request_Ack
When your application is eventually ready for transitioning to D3cold, that is, loss of main power and reference clock, L2/L3_Ready
is entered and the downstream device begins preparation for the power and clock removal. After main power has been removed,
the link transitions to L2 if Vaux is provided, or it transitions to L3 if no Vaux is provided.
3.9.10.4.2 L2/L3 entry†

All of these condition must be met:
• PME_Turn_Off/PME_TO_Ack handshake has been completed.
• Your USP application is ready to be turned off; app_ready_entr_l23 =1.
• After sending the PME_TO_Ack, the USP initiates the L2/L3 Ready transition protocol by sending the PM_Enter_L23 DLLP.
The RC responds with the PM_Request_Ack.
[19] This exit mechanism does not apply to legacy interrupts. Before requesting the transmission of a legacy interrupt the
application should use an existing L1 exit mechanism.
[20] In preparation for removing the main power source, your RC application asserts the apps_pm_xmt_turnoff input which
causes the RC to broadcast the PME_Turn_Off MSG TLP to all USPs.

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3.9.10.4.3 L2/L3 exit†

Any of these condition can be met:
• When the USP is programmed[21] with capability to support PME, your application can assert the apps_pm_xmt_pme input
to request the controller to wakeup. The USP then sends a PM_PME MSG TLP to the RC which calls the PM software to
transition the USP out of the D3 state.
• Device is programmed with capability to support PME and your application requests the controller to wakeup by triggering a
native hot-plug event.
• Link partner is requesting exit from L2/L3.
The controller supports beacon signaling by asserting the wake output when a PCIe device initiates a wake-up event.
3.9.11 Signal interfaces†
3.9.11.1 Vendor message interface (VMI)†

The VMI is an interface for sending vendor-defined messages. The VMI protocol is a simple synchronous request/acknowledge
handshake. The VMI can only be used to send a header-only (no payload) vendor-defined message (Msg). MsgD is not supported.
To send a vendor-defined MsgD, you must use one of the transmit client interfaces.
3.9.12 Completion timeout ranges†

Timeout ranges are supported as defined in the PCI Express Base Specification, Revision 4.0,
Version 0.9. The controller supports all ranges. The Device Control 2 Register (Device control 2 and
status 2 (DEVICE_CONTROL2_DEVICE_STATUS2_REG) for EP mode, Device Control 2 and Status 2
(DEVICE_CONTROL2_DEVICE_STATUS2_REG) for RC mode) has a default equal to the default in the specification: 0000b
Default range: 50 µs to 50 ms. When the default is used, then the timeout is in Range B: 0101b: 16 ms to 55 ms. This range was
chosen for the default because the PCI Express Base Specification, Revision 4.0, Version 0.9 states, “It is strongly recommended
that the completion Timeout mechanism not expire in less than 10 ms”. The following table illustrates the specification values
versus the PCI Express controller values for the ranges.
NOTE
As the PCIe specification states, this mechanism is intended to be activated only when there is no reasonable
expectation that the completion is returned, and should never occur under normal operating conditions.
Table 57. Comparison of PCIe specification and Synopsys PCIe core completion timeout ranges
Range Encoding Spec minimum Spec maximum PCIe controller PCIe controller
minimum maximum
Default 0000b 50 µs 50 ms 28 ms 44 ms
A 0001b 50 µs 100 µs 65 µs 99 µs
A 0010b 1 ms 10 ms 4.1 ms 6.2 ms
B 0101b 16 ms 55 ms 28 ms 44 ms
B 0110b 65 ms 210 ms 86 ms 131 ms
C 1001b 260 ms 900 ms 260 ms 390 ms
[21] PME_ENABLE bit is set in CON_STATUS_REG, and the PME_SUPPORT bit is set in CAP_ID_NXT_PTR_REG for the
corresponding D-state for which the function is currently in.

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Table 57. Comparison of PCIe specification and Synopsys PCIe core completion timeout ranges (continued)
Range Encoding Spec minimum Spec maximum PCIe controller PCIe controller
minimum maximum
C 1010b 1s 3.5 s 1.8 s 2.8 s
D 1101b 4s 13 s 5.4 s 8.2 s
D 1110b 17s 64 s 38 s 58 s
3.9.13 Receive TLP processing†

This section describes the flow of received TLPs through the controller.
3.9.13.1 Receive filtering†

The controller contains a filter module that is responsible for the following tasks:
• Determine the status of a received TLP using filtering rules.
• Determine the destination of a received TLP based on the filtering status.
• Indicate the status of the received TLP using outputs.
• Report Errors to AER registers based on filter results. When more than one type of error is detected, Section 6.2.3.2.3, Error
Pollution, of the PCI Express Base Specification, Revision 4.0, Version 0.9, is followed.
The controller filters and routes received TLPs according to a set of rules determined by the TLP type based on the PCI
Express Base Specification, Revision 4.0, Version 0.9, and user-configurable filtering options. The filtering rules for a received
TLP are affected by the configuration parameters (compile-time options), I/O signals (runtime options) and register values
(runtime options).
Trash Queue Filter
TLP Filtering
P
TRGT 1
CXPL
Received CPL
Routing NP
Processing
RBYP
CPL Message
Processing
RTRGT0
MSG
ERR
MSG
DBI
LBC CFG Data CDM
ELBI
Figure 33. RADM block diagram
The following general rules apply to all incoming TLPs that are not malformed. By default:

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• For a function in device power states D1, D2, and D3hot, the controller only accepts CFG and MSG requests TLPs for that
function. All other incoming request types for that function are treated as unsupported requests (UR).
• When the controller detects an error in a received TLP, it normally performs the following:
— Discards the TLP
— Generates a completion (for non-posted requests) with the completion status set to CA or UR
— Sets the status in the PCI-compatible Status register
— Sets the status in the AER registers (when you enable AER)
— Generates an error message (upstream port only)
• All error-free MSG requests are decoded internally, signaled on the SII interface and then dropped. When you want to have
the decoded message also sent to the application interface, then see Routing of received messages†.
For more details on advanced filtering, see Advanced filtering and routing of TLPs†.
3.9.13.2 Error handling†

The controller supports the Baseline Capabilities, AER capabilities, and Advisory Non-Fatal Error Messaging as specified in
Section 6.2, Error Signaling and Logging of the PCI Express Base Specification, Revision 4.0, Version 0.9. These include
Correctable and Uncorrectable (Fatal and Non-Fatal) errors. For an RC port, the reporting of most errors is internal to the root port.
No external error notifications are generated. One exception to this (for example) is unsupported request (UR) completion status.
3.9.13.2.1 Error detection for received TLPs†

The controller performs all mandatory error detections, the error reporting mechanism based on the PCI Express Base
Specification, Revision 4.0, Version 0.9, and some optional error detections (using the ENABLE_OPTIONAL_CHECKS parameter).
For more details of what error conditions contribute toward a UR or CA status, see Advanced filtering and routing of TLPs†. When
the controller detects an error in a received TLP, it normally performs the following:
• Discards the TLP
• Sets the status in the PCI-compatible status register
• Generates an error MSG (upstream port only)
3.9.13.2.2 AER multiple header logging†

The controller supports the AER multiple header logging as specified in Section 6.2.4.2, “Multiple Error Handling (Advanced Error
Reporting Capability)” of the PCI Express Base Specification, Revision 4.0, Version 0.9.
3.9.13.2.3 Physical functions†

By default, each physical function only logs the first header that caused an error. The controller implements a 1-deep FIFO queue
that interfaces with the AER Header Log registers (HDR_LOG_n_OFF). A valid queue entry is never overwritten. When the queue
is full and your software does not read the header log registers fast enough, new header log information will be missed.
3.9.13.2.4 Virtual functions†

By default, each virtual function only logs the first header that caused an error. Each VF has one logged header and the exact
same header log queue depth. Per VF, the controller implements a queue of depth 1 that interfaces with the AER Header Log
registers (VF_HDR_LOG_i_OFF). A valid queue entry is never overwritten. When the queue is full and your software does not read
the header log registers fast enough, new header log information will be missed.

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Table 58. Shared VF header log full behavior
VF First Error VF Shared Header Core Actions

Pointer Status Log Status
Invalid Full • A read to the Header Log returns all 1's.

• A read to the “TLP Prefix Log Present” bit indicates ‘0’.
• The controller sets the Uncorrectable Error Status Register according to the First
Error Pointer.
Valid Full • The controller sets the Uncorrectable Error Status Register according to the First
Error Pointer that is associated with the rejected TLP.
• The Header log can be cleared or updated to the next stored header log, if one
exists, by writing to the bit of the Uncorrectable Status Error Register pointed to
by the First Error Pointer.
• This applies to both when a normally displayed TLP Header is present in
the Header Log Register or when an overflow condition is shown on the
Uncorrectable Status Error Register.
3.9.14 Advanced filtering and routing of TLPs†

This section discusses advanced features and operation associated with Receive filtering†. You should first read to familiarize
yourself with basic information on the filtering and routing of received TLPs.
3.9.14.1 Filtering rules†

These tables describe the filtering rules (based on the PCIe Specification), and the results of the cores filter. When a received TLP
passes all of the filter rules, then it is considered to have no errors, and is routed to the destination that is configured.
This section uses the following notation for filter results:
• UR: Unsupported Request “CPL Status”[22]
• CA: Completer Abort “CPL Status”1
• CRS: Configuration Request Retry Status “CPL Status1”
• SU: Successful Completion “CPL Status”1
• UC: Unexpected CPL
• MLF: Malformed
• MA: (Received) Master Abort set in “PCI-compatible Status Register”
• TA: (Received) Target Abort set in “PCI-compatible Status Register”
• <blank>: Filtering rule does not apply to TLP type
[22] For non-posted TLPs, this filter result also determines the status of the completion that the controller sends back to the
requester.

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Table 59. Result of filtering rules applied to all TLPs: EP mode
Filtering Rule TLP Type
MRd MWr CFG MSG CPL CPL

with with SU
IORd IOWr UR/CA/ status
CRS
status
PowerState is not in D0. UR UR SU SU UC UC
Address is not within any configured memory BAR or I/O BAR UR UR

when it is an I/O request.
TLP header poison bit is set and the filter mask UR UR UR UR SU SU

CX_FLT_MASK_UR_POIS bit is not set.
Address within a BAR that is configured to TRGT0 and TLP DW CA1/ML CA1/ML MLF
length > 1. F F
MRd with lock and filter mask UR

CX_FLT_MASK_LOCKED_RD_AS_UR bit is not set.
The function number of a completer ID within a CFG request does UR

not match an implemented function within the receiver device
and the filter mask CX_FLT_MASK_UR_FUNC_MISMATCH bit is
not set.
Configuration type1 TLP request and the filter mask UR

CX_FLT_MASK_CFG_TYPE1_REQ_AS_UR bit is not set.
Application requests the controller filter to return CRS by CRS

asserting signal app_req_retry_en.
Not Valid message for EP device UR/MLF
Illegal payload length of a message. UR/MLF
Vendor MSG Type0 with filter mask UR

CX_FLT_MASK_VENMSG0_DROP bit not set.
Vendor MSG Type1 with r[2:0] to 3'b010 and {Bus#, Dev#, UR

Func#} mismatch
TLP with ECRC error detected CA CA2 CA
Requester ID mismatch MA/TA MLF
Requester TAG mismatch MA/TA MLF
TAG error (non-pad zero for reserved TAG bits MA/TA MLF
Byte count mismatch (PCIe Gen2) MA/TA UC/MLF
CPL received with status of UR MA
CPL received with status of CA TA
CPL received with status of CRS CRS

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Table 59. Result of filtering rules applied to all TLPs: EP mode (continued)
MRd MWr CFG MSG CPL CPL

with with SU
IORd IOWr UR/CA/ status
CRS
status
CPL received with CRS status and CPL is not a pending MLF
configuration request
1. MLF for IORd/IOWr always. CA for MRd.

2. For IO only.
A complete list of the filtering checks can be referenced in the descriptions of Symbol Timer and Filter Mask 1 register
(SYMBOL_TIMER_FILTER_1_OFF) and Filter Mask 2 register (FILTER_MASK_2_OFF).
Table 60. Result of filtering rules applied to request TLPs and CPL TLPs: RC mode
MRd MWr CFG1 I/O MSG CPL CPL CPL

with with with
UR/CA CRS SU
status status status
Address does not satisfy any of the following conditions: UR UR

1. Within any configured memory BAR.
2. Outside of the memory range AND prefetchable
memory range as determined by the
corresponding Base and Limit fields in the
Type-1 header.
3. The filter mask
CX_FLT_MASK_UR_OUTSIDE_BAR bit is set,
which treats out-of-bar TLPs as supported
requests and indicates a special application
requirement
With AXI bridge: MASTER_BUS_ADDR_WIDTH UR UR UR

=32, FLT_Q_ADDR_WIDTH > 32, and any
upper address bit (above bit position
MASTER_BUS_ADDR_WIDTH-1) is set to 1
TLP header poison bit is set and the filter mask UR UR UR UR UR

CX_FLT_MASK_UR_POIS bit is not set.
MRdLk request received and filter mask UR

CX_FLT_MASK_LOCKED_RD_AS_U R bit is set, which
indicates that you prefer to filter out the MRdLk.
CFG request received and the filter mask UR

CX_FLT_MASK_RC_CFG_DISCARD bit is not set

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Table 60. Result of filtering rules applied to request TLPs and CPL TLPs: RC mode (continued)
MRd MWr CFG1 I/O MSG CPL CPL CPL

with with with
UR/CA CRS SU
status status status
I/O request received and the filter mask UR

CX_FLT_MASK_RC_IO_DISCARD bit is not set
Vendor MSG Type0 with filter mask UR

CX_FLT_MASK_VENMSG0_DROP bit not set.
Not Valid message for RC device UR/ML

F
TLP with ECRC error detected CA CA CA
Requester ID mismatch MA/TA MLF
Requester TAG mismatch MA/TA MLF
TAG error (non-pad zero for reserved TAG bits MA/TA MLF
Byte count mismatch MA/TA MLF
CPL received with status of UR MA
CPL received with status of CA TA
CPL received with CRS status and CPL is not a MLF

pending configuration request
1. DM (in RC mode) should not expect to receive a CFG or I/O request.
A complete list of the filtering checks can be referenced in the descriptions of Symbol Timer and Filter Mask 1 register
(SYMBOL_TIMER_FILTER_1_OFF) and Filter Mask 2 register (FILTER_MASK_2_OFF).
3.9.14.1.1 Filtering rules not defined in PCIe specification†

When a zero-byte request TLP is received, also called "flush" command, the controller can drop (service internally, but not pass to
your application) the zero-byte request. This is designed to support some applications that can not process a zero-byte request.
Applications can dynamically program a bit in the filter mask CX_FLT_MASK_HANDLE_FLUSH bit to turn on/off this rule. If the
controller is programmed to handle the flush, it is the completer’s task to return CPL status.
When the controller receives a four DWORD TLP with the LSB of the format field set to 1 and the upper 32 bits set to 0x0, then
it processes the TLP as a three DWORD TLP.
3.9.14.2 EP mode routing overview†

The possible destinations of a posted or non-posted request TLP are:
• TRGT1 interface
• TRGT0 interface
• Discard:
— Dropped (serviced internally but not passed to your application)
— Terminated
By default:

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• CFG requests are routed to TRGT0 and then to CDM through the LBC.
• BAR-matched MEM and I/O requests are routed to TRGT1.
• MSG requests are decoded internally, signaled on the SII interface and then terminated.
core
config CDM TRGT0 CFG
data LBC
TRGT1 MEM/IO
CXPL
Address/Type Check
BAR
TRGT1
SII MSG
Figure 34. Default request TLP routing (assuming no TLPs with CA/CRS/UR error status)
The possible destinations of a CPL TLP are TRGT1 and discard.

By default, all configuration requests that pass filtering go to TRGT0 for configuration register access. However, your application
can configure the controller to direct certain configuration TLPs to the TRGT1 interface. Your application is responsible for
generating CPLs for configuration requests that are routed to TRGT1.

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core
config CDM
data TRGT0 0
LBC
TRGT0 0 DMUX CFG
ELBI
(external
DMUX 1
application
registers) registers address >
TRGT1 1 CONFIG_LIMIT
TARGET_ABOVE_CONFIG_LIMIT
TRGT0 0
DMUX MEM/IO
TRGT1 1 CXPL
Address/Type Check
FUNCT# and BAR#

of matched BAR
BAR
MEM_FUNC#_BAR#_TARGET_MAP
MEM_FUNC0_BAR1_TARGET_MAP
MEM_FUNC0_BAR0_TARGET_MAP
TRGT1
SII MSG
Figure 35. Configurable request TLP routing (assuming SC status)
3.9.14.3 RC mode routing overview†

The possible destinations of a posted or non-posted request TLP are:
• TRGT1 interface
• Discard:
— Dropped (serviced internally but not passed to your application)
— Terminated
By default:
• MEM requests outside of the memory range and prefetchable memory range as determined by the corresponding Base
and Limit fields in the Type-1 header are routed to TRGT1.
• MSG requests are decoded internally, signaled on the SII interface, and then terminated.
• An RC does not expect to receive CFG or I/O requests.
• BARs should be disabled and not used.
The possible destinations of a completion TLP are TRGT1 and Discard.

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3.9.14.4 Request TLP routing rules†
core
config CDM TRGT0 CFG0
data LBC
TRGT1 CFG1
TRGT1 MEM/IO
CXPL
Type-1 Mem
& IO Base
& Limit
Checks
TRGT1 MEM
BAR Address
Check
BAR
TRGT1
SII MSG
Figure 36. Request TLP routing rules
The next table shows the applicability of routing rules for request TLPs, and indicates whether the destination is as stated by the
rule when the conditions of the rule are met.
In many cases, the standard routing rules can be masked or ignored by setting the corresponding bit in the Symbol Timer and Filter
Mask 1 register (SYMBOL_TIMER_FILTER_1_OFF) and Filter Mask 2 register (FILTER_MASK_2_OFF).
By default, when the controller detects an error[23] in a received TLP, it normally performs the following:
• Discards the TLP
• Sets the status in the PCI-compatible Status register
• Generates an error message (upstream port only)
Notation of routing results:
• No: destination is not as specified in rule, even when conditions of rule are met
• Yes: destination is as specified in rule, when conditions of rule are met
• <blank>: Routing rule does not apply to TLP type
[23] Excluding TLPs targeted for forwarding (and not for local resources) that have ECRC errors.

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Table 61. Routing rules for request TLPs (EP mode)
Routing Rule MRd MWr CFG I/O Vendo Vendo Other

r MSG r MSG MSG
Type0 Type1
When a request is filtered with SU status, and is in BAR range, Yes Yes No Yes
MEM_FUNC#_BAR#_TARGET_MAP parameter determines
the destination.
When a request is filtered with UR/CA/CRS status, and the Yes Yes Yes Yes Yes Yes Yes
DEFAULT_TARGET field is 0, the TLP is dropped. For NP
requests, a CPL is also generated.
When a request is filtered with UR/CA/CRS status, and the No No Yes No Yes Yes Yes
DEFAULT_TARGET field is 1, the TLP is dropped.
When a request is filtered with UR/CA/CRS status, and Yes Yes No Yes No No No
the DEFAULT_TARGET field is 1, the destination is
TRGT1 interface.
When a CFG request is filtered with SU status Yes

and the CFG register address is > CONFIG_LIMIT,
TARGET_ABOVE_CONFIG determines the destination.
When a CFG request is filtered with SU status and the CFG Yes
register address is < CONFIG_LIMIT, TRGT0 interface is
the destination.
The TLP is dropped, when the filter mask Yes

CX_FLT_MASK_MSG_DROP bit is 0 and the non-Vendor MSG
is filtered with SU status.

CX_FLT_MASK_VENMSG0_DROP bit is 0 and the VEN0 MSG

Table 62. Routing rules for request TLPs (RC mode)
Routing Rule MRd MWr CFG1 I/O2 Vendo Vendo Other

r MSG r MSG MSG
Type0 Type1
When a request is filtered with SU status, and is not in BAR Yes Yes No Yes
range, TRGT1 is the destination.
When a request is filtered with SU status, and is in BAR range, Yes Yes No No
MEM_FUNC#_BAR#_TARGET_MAP parameter determines
the destination.3
When a request is filtered with UR/CA status, the TLP is Yes Yes Yes Yes Yes Yes Yes
dropped. For NP requests, a CPL is also generated.

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Table 62. Routing rules for request TLPs (RC mode) (continued)
Routing Rule MRd MWr CFG1 I/O2 Vendo Vendo Other

r MSG r MSG MSG
Type0 Type1

CX_FLT_MASK_MSG_DROP bit is 0 and the non-Vendor MSG


1. DM (in RC mode) should not expect to receive a CFG request.

2. DM (in RC mode) should not expect to receive an I/O request.
3. BARs are not normally used in RC application.
3.9.14.5 Processing illegal CFG TLPs, and CFG1-CFG0 conversion in each PCI Express port type†
Routing IDs, requester IDs, and completer IDs are 16-bit identifiers traditionally composed of three fields: an 8-bit bus number,
a 5-bit device number, and a 3-bit function number. Configuration requests always move downstream, and never travel across a
peer-to-peer connection. An RC or SW downstream port (DSP) never receives configuration requests.
3.9.14.5.1 RC†
3.9.14.5.1.1 Transmit checking†

The controller does not check configuration requests (at your application transmit interface) for valid target Bus.Device.Function
numbers before it transmits them. It does not check that the target bus number > secondary bus number and that target bus
number <= subordinate bus number. Your application must not provide illegal configuration requests to the controller. It must
check all configuration requests from the host software. It can determine the correct range of Bus.Device numbers by snooping
host configuration writes to the RC's Secondary Bus and Subordinate Bus registers.
3.9.14.5.1.2 Conversion†
The controller never does conversion of CFG1 to CFG0 at your application transmit interface, or in the controller. Your application
must do the conversion where necessary.
3.9.14.5.1.3 Bus.Device number assignment†

The assignment of Bus.Device numbers to the devices within a root complex, can be done in an implementation specific way.
3.9.14.5.1.4 Non-existent devices and functions†

Your host should determine the existence (or absence) of devices and functions by reading (CfgRd) from the vendor ID register.
A successful (SU) response with a non-FFFF data value, indicates the existence of the function. When your application logic
receives a unsupported request (UR) response (as forwarded by the controller), then it must change the response data to FFFF,
change the completion status to SU and pass the completion to the host. The AXI bridge does this automatically.
3.9.14.5.2 EP†

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3.9.14.5.2.1 Receive checking†

The controller responds with UR to CfgRd0 requests with an incorrect function number, it never checks the Bus.Device numbers.
The controller responds with UR to all CFG1 requests.
3.9.14.5.2.2 Bus.Device number assignment†

The controller snoops every [completed] CfgWr0 request and updates the Bus.Device numbers in its completer ID. For
multifunction endpoints, the MULTI_DEVICE_AND_BUS_PER_FUNC_EN parameter determines how the completer ID is
determined. By default it is set to 0, as it is assumed that all (physical) functions in a multifunction device are assigned the same
bus and device number by the RC. When it is set to 1, the controller snoops every [completed] CfgWr0 request and updates
the Bus.Device number in its completer ID of the function that was accessed. When it is set to 0, the controller snoops every
[completed] CfgWr0 request and only updates the Bus.Device number in its completer ID of function #0.
3.9.14.5.2.3 Receive routing†

The controller routes all CFG0 requests to TRGT0 (CDM or ELBI, through the LBC).
3.9.15 Link establishment†

The controller implements the LTSSM function according to the PCI Express Base Specification, Revision 4.0, Version 0.9. The
controller supports link widths of x1, x2, x4, x8, and x16. It does not support x12.
3.9.15.1 Lane resizing†

Initially, the controller tries to linkup at maximum width; you can restrict the maximum width as follows:
1. Program the LINK_CAPABLE field of PORT_LINK_CTRL_OFF.
2. Program the NUM_OF_LANES field of GEN2_CTRL.
To conserve power, your PHY should ignore any signaling on the non-operational lanes. The controller supports the PIPE turn off
feature by using the TxElecIdle and TxCompliance signals.
The link partners can change the link width after the link is up. Resizing options are shown in the following table. Resizing (up or
down) only occurs if both link partners advertised the Upconfigure Capability bit. In cases of link reliability, the PCIe specification
permits the remote partner to initiate downsizing regardless of the value of this bit. You must set the UPCONFIGURE_SUPPORT
field in MULTI_LANE_CONTROL_OFF so that the controller advertises 1 in the Upconfigure Capability bit of the TS2 OS. Default
for this field comes from DEFAULT_UPCONFIGURE_SUPPORT parameter.
Table 63. Link resizing options
Remote Partner Initiates Software Initiates Locally
Link Remains Up Link Remains Up
L0 -> Recovery -> Configuration L0 -> Recovery -> Configuration
Upsizing1 Yes Yes
Downsizing Yes2 Yes
1. Called UpConfigure in the PCI Express Specification.

2. If the lanes are reversed, your application must manually flip the lanes to achieve downsizing for some configurations.
The following steps show how you can initiate link resizing:
1. Ensure the link is in the L0 LTSSM state.
2. Program the TARGET_LINK_WIDTH[5:0] field of the MULTI_LANE_CONTROL_OFF register.
3. Program the DIRECT_LINK_WIDTH_CHANGE[24] field of the MULTI_LANE_CONTROL_OFF register.

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It is assumed that the PCIE_CAP_HW_AUTO_WIDTH_DISABLE field in the LINK_CONTROL_LINK_STATUS_REG register is 0.

If your system has reversed lanes in Gen3 or Gen4 mode, then you should perform upsizing at Gen1 or Gen2 speed only.
Otherwise, there is a risk of link-down caused by LFSR mismatching.
3.9.15.2 Lane reversal and flipping†

The controller supports lane reversal and lane flipping. Depending on the configuration of the link partners and the topology of the
link between them, the controller will attempt to reverse and/or flip lanes to form a link in any of the following scenarios:
• The lanes are reversed by the physical layout of the PCIe link or chip package pinning.
• When connecting a narrower link partner into upper lanes of a wider controller.
• A lane is non-operational (broken).
A lane is said to be non-operational if it cannot be detected in Detect LTSSM state or it cannot receive in Polling LTSSM state.
This might be caused by any of (i) break on PCB (ii) electrical fault in transmitter (iii) electrical fault in receiver.
Lane auto flip occurs in Detect and is useful to connect physical lane 1 to logical Lane0 of the controller to form a link when physical
Lane0 cannot be detected.
Lane auto reverse occurs in Configuration and is useful to form a link when logical Lane0 receives TS Ordered Sets from the link
partner with the Lane Number field different from 0.
To enable lane auto flip and reverse support, you must set GEN2_CTRL_OFF register fields AUTO_LANE_FLIP_CTRL_EN =1 and
PRE_DET_LANE =0.
Figure 37 shows the muxing logic implemented in the controller.
[24] The controller clears the contents of this register after it has accepted the request.

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GEN2_CTRL_OFF Register fields

AUTO_LANE_FLIP_CTRL_EN = 1
PRE_DET_LANE = 0
LTSSM Auto Reverse LTSSM Auto Flip Manual Flip rx_lane_flip_en =1/
(Config) (Detect) tx_lane_flip_en =1
Reversal Flip Mux

7 Mux 7
3
6 6
2
5 5
1
4 4 Logical Lane 0
0
Remote Link
3 3 Partner
2 2
1 1
Logical Lane 0 0 0 Physical Lane 0
Figure 37. Muxing logic
3.10 Initialization/application information

After you complete the steps in the order presented below, the ports can start to send traffic.
3.10.1 Power on and link training
Step Action
1 Finish the functional reset of the chip. See the chip-specific SerDes information in the chip reference manual for the
exact steps to do this.
2 Finish the reset of the SerDes subsystem. See the chip-specific SerDes information in the chip reference manual for
3 If your application requires programming of the CDM registers, program these registers.

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Step Action
4 If you want to change to the Gen2 speed rate (5.0 Gbps) after linkup, write a 1 to
GEN2_CTRL_OFF[DIRECT_SPEED_CHANGE].
5 Write a 1 to PE0_GEN_CTRL_3[LTSSM_EN] to start link training.
6 Wait until the following fields in PE0_LINK_DBG_2 are both 1:

• RDLH_LINK_UP
• SMLH_LINK_UP
3.10.2 BAR configuration
Step Action
1 Wait until the following fields in PE0_LINK_DBG_2 are both 1:

• RDLH_LINK_UP
• SMLH_LINK_UP
2 Use a Configuration Write 0 (CfgWr0) transaction to write 1 to every bit in BAR0.
3 Use a Configuration Read 0 (CfgRd0) transaction to read every bit in BAR0.
4 Determine the BAR0 size based on the bits that are still zero.
For example, if you read back BAR0=FFF0_0000h, it means that the size of the BAR is F_FFFFh, or 1 MB.
5 Repeat steps 2–5 for the other BARs.
6 Program each BAR based on your application's needs.
3.10.3 Enabling bus masters
Step Action
1 Write a 1 to COMMAND[BUS_MASTER_EN].
2 Write a 1 to COMMAND[MEM_SPACE_EN].
3.10.4 Secure and nonsecure accesses

As an AXI master, the PCIe controller always issues non-secure accesses. If you require secure accesses, you must program
other peripherals on your chip to convert non-secure accesses to secure accesses. See the chip-specific SerDes information in
the chip RM for information on how to do this.
3.11 Embedded direct-memory access (DMA) controller

The PCIe controller includes an embedded multichannel DMA controller. This section refers to this controller as "the DMA"
for brevity.

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3.11.1 DMA overview†

The RC system CPU, or the EP application CPU, can offload the transferring of large blocks of data to the embedded DMA
controller, leaving the CPU free to perform other tasks. You can configure the DMA to have one to eight read channels and one
to eight write channels. It can simultaneously perform the following types of memory transactions (as shown in Figure 38):
• DMA write: Transfer (copy) of a block of data from local (application) memory to remote (link partner) memory
• DMA read: Transfer (copy) of a block of data from remote (link partner) memory to local (application) memory
The DMA therefore supports full-duplex operation. It processes read and write transfers at the same time and in parallel with
normal (non-DMA) traffic. Upon completion of a DMA transfer or an error, the DMA optionally interrupts the local CPU or sends
an interrupt MWr (IMWr) to the remote CPU. The DMA is highly configurable and you can program it using the local DBI or over
the PCIe wire.
NOTE
RC can program the EP DMA using CfgWr or MWr (when ENABLE_MEM_MAP_PL_REG=1), but the EP cannot
program the RC DMA over the wire.
In linked-list mode, the DMA fetches the transfer control information (called channel context) for each transfer (block) from a list
of DMA elements that you have constructed in local memory.
You can use the DMA with the AXI bridge, in which case the DMA is located between the native PCIe controller and the AXI
bridge module.
3.11.2 Feature list†

The DMA supports the following features:
Table 64. Features of the DMA
Feature Supported
Number of read channels 4
Number of write channels 4
Linked list mode Yes
Scatter gather support (by using linked lists) Yes
Full-duplex read/write channel operation Yes
Separate tag pool for DMA traffic Yes
SAR/DAR address alignment Byte
Transfer size 1 byte - 4 GB
Multifunction support Yes
ARI Yes
SR-IOV Yes
Latency tolerance reporting (LTR) Yes
OBFF Yes

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Table 64. Features of the DMA (continued)
Feature Supported
Address translation services (ATS) Yes
Atomic ops No
TLP processing hints (TPH) Yes
Programmable interrupt generation Yes
Reordering of DMA read transfer completions Yes
ID-based ordering (IDO) signaling1 Yes
Datapath and RAM protection (for limitations, see RAS data protection (DP)†) Yes
RAM read enable for low-power optimization Yes
Automatic flushing/reset of bridge (AXI configurations) when link goes down Yes
Automatic flushing of slave (AXI configurations) when link is not up Yes
1. The DMA identifies and decodes IDO bit from the TLP bit stream and passes on the information to the application through the
AXI bridge. However, the DMA cannot explicitly set the IDO bit of the TLP header.
3.11.3 Limitations†
The following table identifies the limitations when using the DMA.
Table 65. DMA limitations
Limitation Note
Memory DMA traffic only I/O and Type 0 or Type 1 configuration DMA transfers are
not supported.
3.11.4 DMA architecture
3.11.4.1 Architecture overview†
A DMA write and read channel operate independently to maximize the performance of the DMA read and write data transfers over
the PCIe link. When you configure the DMA with multiple read channels, then it uses a weighted round robin (WRR) arbitration
scheme to select the next read channel to be serviced. The same applies when you have multiple write channels.

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DMA Write
Local
Source 1
Memory
re
ad
DMA
re
sp
2 Write
Channel
3
write
Remote
Destination
Memory
DMA Read
Local
Indicates TLP type
Destination
conversion by the
Memory 3
DMA Channel
wr
ite
DMA
Read
Channel
1
read
Remote
cpl Source
Memory
2
Figure 38. System-level view of DMA
3.11.4.1.1 DMA write transfer†

The DMA injects multiple MRd requests of size less than or equal to Max_Payload_Size into the inbound request path, directed
toward the local application. The DMA converts the read responses into MWr TLPs, that it then transmits to the remote link partner.
When the DMA data transfer is complete, the CPU is notified. For more details, see Interrupts and error handling†. For a write
transfer, the SAR is the address of the local memory, and the DAR is the address of the remote memory.
3.11.4.1.2 DMA read transfer†

The DMA injects multiple MRd requests of size less than or equal to the minimum of {Max_Read_Request_Size,
Max_Payload_Size[25]} into the outbound request path, directed toward the remote link partner. The DMA converts the read
responses into write requests that it then transmits to the local application. When the DMA data transfer is complete, the CPU is
notified. For more details, see Interrupts and error handling†. For a read transfer, the SAR is the address of the remote memory,
and the DAR is the address of the local memory.
3.11.4.1.3 Registers and context memory†

You program each DMA transfer (channel) using the registers described in PCIE_DMA register descriptions. The registers that are
specific to each channel are called the channel context registers. As the transfer progresses, the DMA updates these registers.
[25] This limit is set by the DMA read buffer segment size. For more details, see Read buffer†.

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PCIe Controller
The design sometimes caches the context to increase performance. Therefore these registers might contain a delayed snapshot
of the actual DMA channel state.
You program the channel context information and other DMA control registers directly with the local CPU through the DBI or
remotely over the PCIe link. Some of the registers are implemented in a high-speed wide interface context RAM.
3.11.4.2 Interrupts and error handling†
3.11.4.2.1 Interrupt handling†

The DMA generates two interrupts per channel:
• Done: The DMA successfully completes the transfer.
• Abort: The DMA fails to complete the transfer, or an error occurs during the transfer.
The interrupts are signalled to the software on your CPU, using one or both of the following mechanisms:
• Locally through the edma_int[CC_NUM_DMA_RD_CHAN+CC_NUM_DMA_WR_CHAN-1:0] bus.
• Remotely using a posted memory write (IMWr), which can be interpreted as an MSI or MSIX when directed toward the RC.
— There are two programmable IMWr addresses per channel, one each for the done and abort interrupts. For MSI, you
must program all IMWRr address registers with the same MSI address, as PCIe only supports a single MSI address
per function.
— A single IMWr data register is used for both types of interrupts, so you must read DMA_READ_INT_STATUS_OFF (or
DMA_WRITE_INT_STATUS_OFF) to identify the interrupt type.
NOTE
◦ The IMWr address and data do not come from the MSI PCIe capability registers but from the PCIE_DMA
register descriptions.
◦ For an upstream port, your software must program these registers with the same information that it is using
to program the MSI/MSI-X capability for the function that is associated by your software with that channel in
a multifunction setup.
◦ You only need to setup these registers at initialization, and not for every DMA transfer.
• The relaxed ordering (RO) bit is automatically set to zero in the TLP header of all IMWr’s so that subsequent MWr TLPs do
not arrive at the remote device before the IMWr.
For more information on interrupt handling, see the descriptions of the DMA interrupt registers and Programming examples†.
The interrupt handling mechanism is different for linked list (LL) mode (than non LL mode), and there are also some differences
between the read and write channels.
3.11.4.2.2 Interrupts and errors in non-linked-list mode†

You enable the local and remote interrupts through the local and remote interrupt enable (LIE and RIE) bits:
DMA_CH_CONTROL1_OFF_WRCH_0.lie and DMA_CH_CONTROL1_OFF_WRCH_0.rie.
In the write channel, there is only one error condition that results in an abort interrupt. For more details, see Linked list mode†. You
mask, clear, and read the status of each of the two interrupts (done and abort) through the DMA interrupt registers as indicated
in Figure 39.
In the read channel, there are five error conditions that results in an abort interrupt. For more details, see Linked list
mode†. You mask and clear each of the two interrupts (done and abort) through the DMA interrupt registers as indicated in
Figure 40. However, you can read the status of each of the five abort errors (that contribute to the abort interrupt) through
DMA_READ_ERR_STATUS_LOW_ OFF and DMA_READ_ERR_STATUS_HIGH_OFF.

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PCIe Controller
DMA Write
Abort Error Abort Interrupt
Write Channel Status and DMA Write Interrupt
Interrupt Status Register
Generation Transfer Done
(DMA_WRITE_INT_STATUS_OFF)
2 2
Write Channel #0 S Q 2 1
Channel Context edma_int[*]
Control Register DMA Write x2
2
(DMA_CH_CONTROL1_OFF_WRCH_0) Done Interrupt R
2
D S(set) takes
precedence *There is one output interrupt bit per channel on
Local Interrupt
over R(reset) edma_int[], upto a maximum of
Enable (LIE)
CC_NUM_DMA_RD_CHAN+CC_NUM_DMA_WR_CHAN
Remote Interrupt
Enable (RIE)
DMA Write Interrupt DMA Write Interrupt

Clear Register Mask Register
(DMA_WRITE_INT_CLEAR_OFF) (DMA_WRITE_INT_MASK_OFF)
D D
LOCAL interrupt
REMOTE interrupt (IMWr)
En
(1) DMA Write Done Write Channel
IMWr Address Register Remote Done Interrupt
IMWr Generator Done
MWr (1)
DMA_WRITE_DONE_IMWR_LOW_OFF
(2) DMA Write Channel #0 PCIe Core Tx DMA_WRITE_DONE_IMWR_HIGH_OFF
IMWr Data Register
MWr (2)
DMA_WRITE_CH01_IMWR_DATA_OFF
Write Channel Abort
DMA Write Abort Remote Abort Interrupt (3)
IMWr Generator DMA_WRITE_ABORT_IMWR_LOW_OFF
(3) IMWr Address Register
DMA_WRITE_ABORT_IMWR_HIGH_OFF
En
Figure 39. Write interrupt generation, non-linked-list mode, shown for write channel #0
If you want a remote interrupt and not a local interrupt then:

• Set LIE and RIE.
• Mask the local interrupt using the mask register.
This will allow you to poll the status register to distinguish a DONE from an ABORT.

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DMA Read Error

Status High/Low Registers
(DMA_READ_ERR_STATUS_LOW_OFF)
(DMA_READ_ERR_STATUS_HIGH_OFF)
5
S Q
1
x5
R
S(set) takes
Abort Errors 5 precedence
Read Channel Status and over R(reset)
Interrupt
DMA Read DMA Read Interrupt

Read Channel #0 Abort Interrupt Status Register
Channel Context (DMA_READ_INT_STATUS_OFF)
Control Register 2 2
DMA Read S Q 2 1
(DMA_CH_CONTROL1_OFF_WRCH_0) edma_int[*]
Done Interrupt
D 2 x2
R
Local Interrupt 2
Enable (LIE) S(set) takes
Remote Interrupt CC_NUM_DMA_RD_CHAN+CC_NUM_DMA_WR_CHAN
Enable (RIE)
DMA Read Interrupt DMA Read Interrupt

Clear Register Mask Register
(DMA_READ_INT_CLEAR_OFF) (DMA_READ_INT_MASK_OFF)
D D
LOCAL interrupt
En
(1) DMA Read Done Read Channel
IMWr Generator Done
MWr (1)
(2) DMA Read Channel #0 PCIe Core Tx DMA_WRITE_DONE_IMWR_HIGH_OFF
IMWr Data Register
MWr (2)
Read Channel Abort
DMA Read Abort Remote Abort Interrupt (3)
5 (3) IMWr Address Register
En
Figure 40. Read interrupt generation, non-linked-list mode, shown for read channel #0
The registers referenced in Figure 39 and Figure 40 that are related to error and interrupt handling are described in PCIE_DMA
register descriptions.
3.11.4.2.3 Interrupts and errors in linked-list mode†

The LIE and RIE bits in the LL element enable the channel done interrupts (local and remote). The LLLAIE and LLRAIE bits
of the DMA_WRITE_LINKED_LIST_ERR_EN_OFF/DMA_READ_LINKED_LIST_ERR_EN_OFF registers enable the channel abort
interrupts (local and remote). In the write channel, there are two error conditions that results in an abort interrupt. For more details,
see Linked list mode†. You mask and clear each of the two interrupts (done and abort) through the DMA interrupt registers as
indicated in Figure 41. You can read the status of each of the two abort errors (that contribute to the abort interrupt) through the
DMA_WRITE_ERR_STATUS_OFF register.

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DMA Write Error

DMA Write Linked List Error Enable Register Status Register
(DMA_WRITE_LINKED_LIST_ERR_EN_OFF) (DMA_WRITE_ERR_STATUS_OFF)
2
S Q 1
D
LL Local Abort
Interrupt Enable R
(LLLAIE)
Linked List Error S(set) takes
Abort Error 2 precedence
Write Channel Status and over R(reset)
Interrupt
DMA Write DMA Write Interrupt

Write Channel #0 Abort Interrupt Status Register
Channel Context (DMA_WRITE_INT_STATUS_OFF)
DMA Write S Q 2 1
Done Interrupt
D 2 x2
R
Local Interrupt 2
Enable (RIE)
DMA Write Interrupt DMA Write Interrupt

Loaded from Clear Register Mask Register
Linked List (DMA_WRITE_INT_CLEAR_OFF) (DMA_WRITE_INT_MASK_OFF)
Element
D D
LOCAL interrupt
En
2 (1) DMA Write Done Write Channel
DMA Write Linked List Error Enable Register IMWr Generator Done
(DMA_WRITE_LINKED_LIST_ERR_EN_OFF)
MWr (1)
D (2) DMA Write Channel #0 PCIe Core Tx DMA_WRITE_DONE_IMWR_HIGH_OFF
LL Remote Abort IMWr Data Register
Interrupt Enable MWr (2)
(LLRAIE) Abort
Write Channel
DMA Write Abort Remote Abort Interrupt (3)
En
Figure 41. Write interrupt generation, linked-list mode, shown for write channel #0
In the read channel, there are six error conditions that results in an abort interrupt. For more details, see Linked list
mode†. You mask and clear each of the two interrupts (done and abort) through the DMA interrupt registers as indicated
in Figure 42. You can read the status of each of the six abort errors (that contribute to the abort interrupt) through the
DMA_READ_ERR_STATUS_LOW_OFF and DMA_READ_ERR_STATUS_HIGH_OFF registers.

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DMA Read Error

Status High/Low Registers
DMA Read Linked List Error Enable Register (DMA_READ_ERR_STATUS_LOW_OFF)
(DMA_READ_LINKED_LIST_ERR_EN_OFF) (DMA_READ_ERR_STATUS_HIGH_OFF)
6
S Q
D 1
LL Local Abort
Interrupt Enable R
(LLLAIE)
Linked List Error S(set) takes
Abort Errors 5 6 precedence
Read Channel Status and over R(reset)
Interrupt
DMA Read DMA Read Interrupt

Read Channel #0 Abort Interrupt Status Register
Channel Context (DMA_READ_INT_STATUS_OFF)
DMA Read S Q 2 1
Done Interrupt
D 2 x2
R
Local Interrupt 2
Enable (RIE)
DMA Read Interrupt DMA Read Interrupt

Loaded from Clear Register Mask Register
Linked List (DMA_READ_INT_CLEAR_OFF) (DMA_READ_INT_MASK_OFF)
Element
D D
LOCAL interrupt
En
6 (1) DMA Read Done Read Channel
DMA Read Linked List Error Enable Register IMWr Generator Done
(DMA_READ_LINKED_LIST_ERR_EN_OFF)
MWr (1)
D (2) DMA Read Channel #0 PCIe Core Tx DMA_WRITE_DONE_IMWR_HIGH_OFF
LL Remote Abort IMWr Data Register
Interrupt Enable MWr (2)
(LLRAIE) Abort
Read Channel
DMA Read Abort Remote Abort Interrupt (3)
En
Figure 42. Read interrupt generation, linked-list mode, shown for read channel #0
For more information on done interrupts in linked list mode, see Using interrupts for linked list producer-
consumer synchronization†.
In non-linked list mode, LIE acts as a global switch. However when in linked list mode, LIE is just local to the current linked list
element and the global switch is LLLAIE.
CAUTION
If the DMA driver is running on the host and the interrupt service routine is reading local interrupts to determine if the
transfer is successful, then you must set LIE and RIE in the same element and you should mask or ignore the local
interrupt pin. Setting RIE and LIE in element A followed by RIE (only) in element B is not a verified usage scenario.
3.11.4.3 Linked list mode†

The DMA provides a linked list (LL) mode to efficiently move data from source to destination with minimal intervention from
the local CPU. This mode provides an alternative to programming the DMA multiple times to transfer multiple blocks of data.
The programming information (address, size, and so on) for each block of memory is pre-programmed by your software
into a LL element (also known as a descriptor) in local memory. Each element (called a data element) in the LL structure
(called a transfer list) can transfer up to 4 GB of data. You enable LL operation for a channel, by setting the LLE field of the
DMA_CH_CONTROL1_OFF_WRCH[26]_0 register to 1. You can enable LL mode independently for each channel. When you enable
[26] Replace WRCH with RDCH for a read channel.

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LL for more than one channel, then you must have a separate LL structure in local memory for each channel. Your application must
produce the LL element structure in local memory as shown in the following figure. Normally, all of the elements are contiguous
(one after the other) in memory, and each element has six DWORDs containing the information about the block of data to be
transferred. You program the channel context registers (DMA_LLP_LOW_REG_WRCH_0 and DMA_LLP_HIGH_OFF_WRCH_0) with
the location of where you have placed the LL element structure in local memory.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LLP
RIE LIE =0 CB
Transfer Size
(data Element)
Element #0
SAR Low Source

Data Buffer
SAR High
DAR Low Destination

Data Buffer
DAR High
LLP
RIE LIE =0 CB
Transfer Size
(data Element)
Element #1
SAR Low Source

Data Buffer
SAR High
DAR Low Destination

Data Buffer
DAR High
LLP
=1 TCB CB
Element #N-1
(link Element)
LL Element Pointer Low to new list
LL Element Pointer High
Figure 43. Linked list element/descriptor structure in local memory with N elements
When you start the DMA transfer (by writing to the DMA Write Doorbell Register DMA_WRITE_DOORBELL_OFF or DMA Read
Doorbell Register DMA_READ_DOORBELL_OFF), the DMA reads (consumes) each element from local memory, and loads the
information (SAR, DAR, size, and so on) from that element into the channel context registers in the DMA. These channel context
registers determine the operation of the channel that the DMA controller is currently servicing. The DMA then proceeds to transfer
the block of data (as defined by the element), and when it is finished, reads the next element from local memory. Normally, all of the
elements are contiguous (one after the other) in memory, with the starting address defined in the channel context DMA Linked List
Pointer Low Register DMA_LLP_LOW_OFF_WRCH_0. When you want to jump in local memory to another element list (or recycle
the consumed elements), then you set the LLP bit in the element (for example, link element #N-1 in the figure above, specify the
location of the next element structure using the LL Element Pointer DWORDs (as indicated in the figure above), and, set TCB to
1 (for recycling) or to 0 (to jump to another list).
3.11.4.3.1 Relationship between element DWORDs and channel context registers†
Notice the similarity between a data element and the DMA Channel Context registers for each channel. Each element has six
DWORDs as in Figure 43. There are eight channel context registers (DWORDs) for a channel. The DMA loads the six element
DWORDs into the following channel context:
• CB, LLP, LIE, and RIE fields of the DMA Channel Control 1 register
• DMA Transfer Size

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• DMA SAR Low and DMA SAR High

• DMA DAR Low and DMA DAR High
The definitions of the element DWORD bit fields are the same as the DMA Channel Context registers described in PCIE_DMA
register descriptions, with the exception of the LIE and RIE bits. The LIE and RIE bits in an LL element only enable the "done"
interrupt. In non-LL mode, the RIE and LIE bits (in the channel context registers) enable the "done" and "abort" interrupts.
When the LLP field of the first DWORD in the element is set to "1", the element is a link element. The DMA only loads the following
information into the channel context registers:
• CB, TCB, and LLP bits of the first DWORD. The LIE and RIE bits are not defined in a link element.
• LL Element Pointer (3rd and 4th DWORDs) into the DMA Linked List Pointer registers (DMA_LLP_LOW_ REG_WRCH_0
and DMA_LLP_HIGH_OFF_WRCH_0).
More detailed information about LL operation is available in Linked-list operation†.
CAUTION
• When you enable linked list operation (DMA_CH_CONTROL1_OFF_WRCH_0.lle =1b1), the DMA overwrites
the following DMA channel context registers with information from linked list data elements:
— The CB, LLP, LIE, and RIE fields of the DMA Channel Control 1 register.
— DMA Transfer Size
— DMA SAR Low & High
— DMA DAR Low & High
• The structure of a link element is different to that of the data element. A data element has no TCB field. A link
element has no LIE or RIE fields. It has no SAR, DAR, or Transfer Size DWORDs, but has LL Element Pointer
DWORDs instead of the SAR DWORDs.
• The LIE and RIE bits in a LL element, only enable the done interrupt. In non-LL mode, the RIE and LIE bits
enable the done and abort interrupts. For more information, see Interrupts and error handling†.
3.11.4.3.2 Descriptor early fetch (AXI bridge configuration)†

In AXI bridge configuration, the DMA serializes the next descriptor fetch with the previous descriptor data fetch. This allows the
next descriptor to be loaded into DMA’s context memory just in time. Early descriptor fetch reduces the number of idle cycles
between subsequent descriptor fetches introduced because of high round-trip read-to-completion latencies in scenarios where
the descriptor’s transfer size is small.
The descriptor is fetched and loaded into AXI Bridge’s master completion buffer. While the previous descriptor’s CPL and MWr
transactions are in progress, DMA back-pressures the descriptor loaded in the master completion buffer. It is recommended to
have the configuration respecting the following relationship to avoid any potential performance issues:
CC_MAX_MSTR_TAGS_AXI > (CC_NUM_DMA_RD_CHAN + CC_NUM_DMA_WR_CHAN)
Figure 44. Configuration relationship
Theearly fetched descriptor completes concurrently with previous descriptor’s data completion. If previous descriptor transfer
aborts due to an error in any data completion, the early-fetched descriptor is flushed.
3.11.4.4 Hardware flow control†

This optional feature is available only for those channels which are configured to operate in linked list (LL) mode. It enables your
application hardware to flow control the DMA controller, that is, your hardware determines when data block transfer starts.

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In normal mode, as soon as the DMA is doorbelled, the DMA reads the LL descriptor, and starts the data block transfer. When
this feature is enabled, the DMA reads the descriptor, but starts the data transfer only when your application logic toggles the
dma_[w|r]dxfer_go_togg[] input.
This feature is helpful in scenarios where the data block generation/consumption is hardware controlled. After your application
software configures the DMA channel in LL mode and enables the handshake feature, your application hardware can directly
notify the DMA of the data block availability or its ability to receive the data block, thereby freeing your application software of
additional overheads of tracking the hardware states, maintaining the memory mapped linked lists, and managing the DMA.
The DMA handshake mechanism can be turned on or off per channel using DMA_[WRITE/READ]_ENGINE_EN_OFF
register. The handshake mechanism cannot be enabled/disabled when the channel status is active, that is, when
DMA_CH_CONTROL1_OFF_[WR|RD]CH_i.CS =01.
3.11.4.4.1 DMA handshake operation†

The handshake between the DMA and your application hardware is done using dma_[w|r]dxfer_go_togg[] and dma_[w|
r]dxfer_done_togg[]. In case of a DMA Write, your application should toggle the dma_wdxfer_go_togg[] signal to
indicate data block availability. In case of a DMA Read, your application should toggle the dma_rdxfer_go_togg[] signal to
indicate that your application hardware is ready to receive a data block.
To keep a track of dma_[w|r]dxfer_go_togg[] signal toggles, the DMA implements a 5-bit handshake counter for each write/
read channel. When your application toggles dma_[w|r]dxfer_go_togg[] signal, the handshake counter is incremented.
The handshake counter value is taken into account by the DMA before performing the data transfer for each descriptor. The
data transfer happens only when the handshake counter value is non-zero. When the data transfer is complete, the DMA
decrements the handshake counter, and toggles dma_[w|r]dxfer_done_togg[] signal to indicate completion of data transfer
to your application.
CAUTION
This feature is not supported for LL elements with zero-byte transfer size.
The signal dma_[w|r]dxfer_done_togg:

• Is asynchronous to the core_clk. The time period between toggle edges must be wider than three core_clk periods.
• Can toggle only when edma_xfer_pending is asserted, after the channel is doorbelled
• Has no CDC handshake to acknowledge the signal's toggle
The DMA handshake counter is 5 bits wide, so the DMA can handle only 32 outstanding dma_[w|r]dxfer_go_togg requests
for each channel. The DMA does not implement an overflow protection or overflow error indication mechanism for the handshake
counter. Your application must keep the number of dma_[w|r]dxfer_go_togg toggles under check.
The DMA handshake counter is read-only. your application must use it only for debug purposes.
The operation of the DMA when the handshake feature is enabled for a write/read channel is as follows:

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DMA DMA
DMA Write Engine DMA Read Engine
Write Handshake Counter Read Handshake Counter

CPU Channel 0 Write Channel 0 CPU Channel 0 Read Channel 0
x x
Doorbell Write Channel 0 Reset Handshake Counter Doorbell Read Channel 0 Reset Handshake Counter
Descriptor Read Descriptor Read

(LL Element 0) (LL Element 0)
If Handshake If Handshake
Descriptor CPL 0 Descriptor CPL 0
Counter = 0, Wait Counter = 0, Wait
dma_wdxfer_go_togg[0] dma_rdxfer_go_togg[0]
wait wait
Data Read, Data Read, ... Data Write, Data Write, ...
1 1
CPLD, CPLD, ... dma_wdxfer_done_togg[0] d_trgt1_wreg_cmplt_dma dma_rdxfer_done_togg[0]
Descriptor Read 0 Descriptor Read 0

dma_wdxfer_go_togg[0] dma_rdxfer_go_togg[0]
Descriptor CPL Descriptor CPL
, ... 1 , ..
. 1
ad ite
Re Wr
Data If Handshake dma_wdxfer_go_togg[0] ata If Handshake dma_rdxfer_go_togg[0]
, ,D
ad Counter > 0, ite Counter > 0,
Re transfer data Wr transfer data
ta ta
Da immediately Da immediately
2 2
CPLD, CPLD, ... dma_wdxfer_done_togg[0] d_trgt1_wreg_cmplt_dma dma_rdxfer_done_togg[0]
1 1
Figure 45. DMA handshake operation (write/read channel 0)
1. The CPU doorbells channel 0.

2. The DMA resets the handshake counter for channel 0.
3. The DMA reads LL element 0 descriptor. After the DMA receives descriptor read completions, the DMA checks the value
of the handshake counter:
• If handshake counter =0, DMA waits until handshake counter >0 before transferring the data block.
• If handshake counter >0, DMA transfers the data block immediately.
Note: The handshake counter is checked every time a new descriptor block is loaded and DMA is ready to start a new
descriptor data transfer.
4. After the data transfer is complete, the DMA:
• Decrements the handshake counter, and
• Toggles dma_[w|r]dxfer_done_togg[0].
5. Steps 3-4 are repeated for all the remaining elements of the linked list.
3.11.5 Using the DMA†

You can configure the DMA to have from one to eight read channels and one to eight write channels. It can simultaneously perform
the following types of memory transactions:
• DMA write: Transfer (copy) of a block of data from local memory to remote memory
• DMA read: Transfer (copy) of a block of data from remote memory to local memory
Therefore the DMA supports full duplex operation, processing read and write transfers at the same time, and in parallel with normal
(non-DMA) traffic. Upon completion of a DMA transfer or an error, the DMA optionally interrupts the local CPU or sends an interrupt
MWr (IMWr) to the remote CPU. The DMA is highly configurable and you can program it using the local DBI or over the PCIe wire.

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The channels are named read channel 7..0 and write channel 7..0. Each channel is programmed using a number of registers. For
more details, see PCIE_DMA register descriptions.
3.11.5.1 Source and Destination Address Registers (SAR, DAR)†

The DMA channel context SAR and DAR registers (DMA_SAR_LOW_OFF_WRCH_0[27] / DMA_SAR_HIGH_OFF_WRCH_0 /
DMA_DAR_LOW_OFF_WRCH_0 / DMA_DAR_HIGH_OFF_WRCH_0) provide support for remote-to-local, and local-to-remote PCIe
address mapping. You program the start of the local and remote data buffers using these registers, and the DMA increments the
SAR and DAR as the DMA transfer progresses. For a write transfer, the SAR is the address of the local memory, and the DAR
is the address of the remote memory, as shown in Figure 46.
DMA
Transfer
Size bytes
SAR
Local Remote
Source Destination
Memory Memory
DMA
Controller
DMA
Transfer
Size bytes
DAR
Figure 46. DMA write transfer
For a read transfer, the SAR is the address of the remote memory, and the DAR is the address of the local memory, as shown in
Figure 47.
DMA
Transfer
Size bytes
DAR
Local Remote
Source Destination
Memory Memory
DMA
Controller
DMA
Transfer
Size bytes
SAR
Figure 47. DMA read transfer
[27] Replace WRCH with RDCH for a read channel.

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The presence of the DMA controller does not affect:

• Normal filtering rules for inbound TLPs (for example, BAR checking in an Endpoint, as described in Internal Address
Translation Unit (iATU)†)
• The operation of any internal or external address translation, as described in Receive filtering†
When you do not want the iATU to translate outbound requests that are generated by the internal DMA module, then you must
implement one of the following approaches:
• Ensure that the combination of DMA channel programming and iATU control register programming, causes no translation of
DMA traffic to be done in the iATU.
• Activate the DMA bypass mode to allow request TLPs which are initiated by the DMA controller to pass through
the iATU untranslated. You can activate DMA bypass mode by setting the DMA Bypass field of the iATU Control 2
Register (IATU_REGION_CTRL_OFF_2_OUTBOUND_0).
3.11.5.2 DMA transfer size registers†

You program the DMA transfer size using the DMA transfer size registers (DMA_TRANSFER_SIZE_OFF_WRCH_i or
DMA_TRANSFER_SIZE_OFF_RDCH_i). The maximum DMA transfer size is 4GB, and the minimum transfer size is one byte (0x1).
The DMA decrements the value in these registers as the DMA transfer progresses. When all bytes are successfully transferred,
the value in these registers is zero. In LL mode, the DMA overwrites these registers with the corresponding dword of the LL
element. You can read these registers to monitor the transfer progress. However, in some scenarios there is a delay before the
controller updates these registers. For example, when less than three channels are doorbelled, these registers are only updated
after a descriptor finishes (LL mode), or the transfer ends (non-LL mode).
3.11.5.3 Starting the DMA transfer†

After you program the DMA controller registers (including writing to the DMA Read Engine Enable or DMA Write Engine Enable
register), you start a DMA transfer by writing the channel number to the Doorbell Number field of the DMA Write Doorbell Register
(DMA_WRITE_DOORBELL_OFF) or DMA Read Doorbell Register (DMA_READ_DOORBELL_OFF). You can program and start both
a read and a write transfer at the same time. The DMA supports full duplex operation, processing read and write transfers at the
same time and in parallel with normal (non-DMA) traffic. You can program and start any number of channels in the DMA controller
sequentially or simultaneously.
• Sequentially: configure and start a channel, and then configure and start another channel
• Simultaneously: configure multiple channels, and then start multiple channels
CAUTION
You must not write to any of the context registers for a particular channel after you start the channel
by writing the channel number to the Doorbell Number field of the DMA Write Doorbell Register
(DMA_WRITE_DOORBELL_OFF) or DMA Read Doorbell Register (DMA_READ_DOORBELL_OFF).
3.11.5.4 Detecting the end of the DMA transfer†

If a DMA transfer proceeds without any errors, it stops automatically when finished.
3.11.5.4.1 Detecting the end of the transfer without errors†

The normal end of a DMA transfer is detected by any of the following methods:
• Done local interrupt (pin) asserted.
• Done remote interrupt (IMWr) received.
• Channel status field of the Channel Control 1 register is Stopped, and the DMA Transfer Size register is 0x0.
• Polling of the DMA Write Interrupt Status Register (DMA_WRITE_INT_STATUS_OFF) or DMA Read Interrupt Status
Register (DMA_READ_INT_STATUS_OFF).

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3.11.5.4.2 Detecting the end of the transfer with errors†

The abnormal end of a DMA transfer is detected by any of the following methods:
• Abort local interrupt (pin) asserted.
• Abort remote interrupt (IMWr) received.
• Polling of the DMA Write Interrupt Status Register (DMA_WRITE_INT_STATUS_OFF) or DMA Read Interrupt Status
Register (DMA_READ_INT_STATUS_OFF).
• Channel Status field of the Channel Control 1 register is Halted. When the DMA controller detects an error, it forces the DMA to
stop issuing requests for the channel. It also sets the channel status field of the Channel Control 1 register to Halted, generates
an abort interrupt (if enabled), and sends an abort IMWr (if enabled). The DMA Transfer Size register indicates the remaining
number bytes to be transferred, except when there is an AXI write error during a DMA read transfer. For more details, see
Table 72.
• Channel Status field of the Channel Control 1 register is Stopped, and the DMA Transfer Size register is not 0x0. You have
prematurely stopped this channel as described in Stopping the DMA transfer (software stop)†.
3.11.5.5 Stopping the DMA transfer (software stop)†

You can manually abort (stop) the DMA transfer by writing the channel number to the Doorbell Number field and writing 1 to the
Stop field in DMA_WRITE_DOORBELL_OFF. This causes the DMA to:
• Place the channel in a Stopped state.
The channel Status field in DMA_CH_CONTROL1_OFF_WRCH_0 is Stopped and the value in
DMA_TRANSFER_SIZE_OFF_WRCH_0 will not be 0x0.
• Wait for all outstanding pending transactions.
• Assert the abort interrupt (if it is enabled) in DMA_WRITE_INT_STATUS_OFF.
You might do this as part of error handling which is described in Error handling assistance by remote software†, which is only
necessary during software development if you incorrectly program the DMA write channel DAR. You might also do this as part of
a function level reset (FLR). FLR does not directly affect the DMA transfer so you must manually stop the DMA transfer before
initiating an FLR.
CAUTION
Use this Feature with caution in linked-list mode.
You should not use the STOP feature in operational mode. It is only a debug feature and has associated hazards.
• Before setting the Stop bit, you must read the channel status field (CS) of the DMA Channel Control 1 register
to ensure that the corresponding channel is Running (transferring data). To eliminate the possibility of a
race condition between these two actions (read and write), you should confirm the presence of the abort
bit in the DMA Write Interrupt Status Register (DMA_WRITE_INT_STATUS_OFF) or DMA Read Interrupt
Status Register (DMA_READ_INT_STATUS_OFF) and check the status of any fatal error if some other event
has occurred.
• After a Stop event, you cannot seamlessly resume the transfer again because the DMA will not carry on
exactly from the point that it was stopped at. Therefore you must setup and start the complete channel context
again, including the
— linked list pointer
— linked list structure in memory
— related PCS and CCS values

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3.11.5.6 TLP generator header control†

You must program bits [31:12] of the DMA Channel Control 1 Register (DMA_CH_CONTROL1_REG_ WRCH_0/
DMA_CH_CONTROL1_OFF_RDCH_0), so that the DMA TLP generator correctly sets the TC, RO, NS, AT, and
FN TLP header fields for any TLPs that it generates. When SRIOV is enabled, then you must also program
DMA_CH_CONTROL2_OFF_WRCH_0/DMA_CH_CONTROL2_OFF_RDCH_0.
3.11.6 Programming examples†

This section provides a programming and operation flow for several scenarios.
The order in which the registers in the following examples are programmed is not important, except for the Doorbell register, which
initiates the DMA transfer. Therefore, to start both a 1 MB write transfer on write channel #0 initiated by local CPU (non LL mode)†
and a 1 MB read transfer on read channel #0 initiated by local CPU (non LL mode)†, just execute the commands in Table 66
and then execute the commands in Table 67. If, as mentioned in Starting the DMA transfer†, you want both channels to start at
(approximately) the same time, then do not execute the last command (at 0x280) in Table 66 until after you have executed all the
commands in Table 67.
You must enable the DMA before you start a DMA channel. Therefore you must write "1" to DMA Read Engine Enable or DMA
Write Engine Enable register before you write "1" to the DMA Read Doorbell or DMA Write Doorbell register.
3.11.6.1 1 MB write transfer on write channel #0 initiated by local CPU (non LL mode)†
In this example, the IMWr generation is disabled, as the local CPU initiates the DMA transfer. The local CPU is interrupted using
the edma_int bus. The SAR is the address of the local memory, and the DAR is the address of the remote memory, as shown in
Figure 46. The following table provides the programming details for this example transfer.
Table 66. Register setup for a 1-MB write DMA transfer from 0xBEEF_BEE0 to 0xCAFE_CAF0
Address offset Name Value
0x00C DMA Write Engine Enable 0x1

You must not write 0 to this register. Even temporarily writing 0 to this
register resets the DMA logic. For more details, see DMA Write Engine Enable
Register (DMA_WRITE_ENGINE_EN_OFF).
0x054 DMA Write Interrupt Mask 0x0
0x200 DMA Channel Control 1 register 0x04000008

• Local Interrupt Enable (LIE) =1
• Remote Interrupt Enable (RIE) =0
• AT, RO, NS, TC, Function Number =0
0x208 DMA Transfer Size 0x00100000
0x20C DMA SAR Low 0xBEEF_BEE0
0x210 DMA SAR High 0x0000_0000
0x214 DMA DAR Low 0xCAFE_CAF0
0x218 DMA DAR High 0x0000_0000
0x010 DMA Write Doorbell 0x0

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3.11.6.2 1 MB read transfer on read channel #0 initiated by local CPU (non LL mode)†
In this example, the IMWr generation is disabled, as the local CPU initiates the DMA transfer. The local CPU is interrupted using
the edma_int bus. The SAR is the address of the remote memory, and the DAR is the address of the local memory, as shown in
Figure 47. The following table provides the programming details for this example transfer.
Table 67. Register setup for a 1-MB read DMA transfer from 0xBEEF_BEE0 to 0xCAFE_CAF0
0x02C DMA Read Engine Enable 0x1

register resets the DMA logic. For more details, see DMA Read Engine Enable
Register (DMA_READ_ENGINE_EN_OFF).
0x0A8 DMA Read Interrupt Mask 0x0

0x308 DMA Transfer Size 0x00100000
0x30C DMA SAR Low 0xBEEF_BEE0
0x310 DMA SAR High 0x0000_0000
0x314 DMA DAR Low 0xCAFE_CAF0
0x318 DMA DAR High 0x0000_0000
0x030 DMA Read Doorbell 0x0
3.11.6.3 1 MB write transfer on write channel #5 initiated by remote CPU (non LL mode)†
In this example, the local interrupt generation is disabled, as the remote CPU initiates the DMA transfer. The remote CPU is
interrupted using an IMWr. The SAR is the address of the local memory, and the DAR is the address of the remote memory, as
shown in Figure 46. The following table provides the programming details for this example transfer.
Table 68. Register setup for a 1-MB write DMA transfer from 0xBEEF_BEE0 to 0xCAFE_CAF0
0x00C DMA Write Engine Enable 0x1

register resets the DMA logic. For more details, see DMA Write Engine
Enable Register (DMA_WRITE_ENGINE_EN_OFF).
0x060 / 0x064 DMA Write Done IMWr Address Low and High your IMWr Address #1
0x068 / 0x06C DMA Write Abort IMWr Address Low and High your IMWr Address #2

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Table 68. Register setup for a 1-MB write DMA transfer from 0xBEEF_BEE0 to 0xCAFE_CAF0 (continued)
0x06C DMA Write Channel 0 IMWr Data your IMWr Data
0xA00 DMA Channel Control 1 register 0x04000010

0xA08 DMA Transfer Size 0x00100000
0xA0C DMA SAR Low 0xBEEF_BEE0
0xA10 DMA SAR High 0x0000_0000
0xA14 DMA DAR Low 0xCAFE_CAF0
0xA18 DMA DAR High 0x0000_0000
3.11.6.4 1 MB read transfer on read channel #5 initiated by remote CPU (non LL mode)†
In this example, the local interrupt generation is disabled, as the remote CPU initiates the DMA transfer. The remote CPU is
interrupted using an IMWr. The SAR is the address of the remote memory, and the DAR is the address of the local memory, as
shown in Figure 47. The following table provides the programming details for this example transfer.
Table 69. Register setup for a 1-MB read DMA transfer from 0xBEEF_BEE0 to 0xCAFE_CAF0
0x02C DMA Read Engine Enable 0x1

register resets the DMA logic. For more details, see DMA Read Engine
Enable Register (DMA_READ_ENGINE_EN_OFF).
0x0CC / 0x0D0 DMA Read Done IMWr Address Low and high your IMWr Address #1
0x0D4 / 0x0D8 DMA Read Abort IMWr Address Low and High your IMWr Address #2
0x0DC DMA Read Channel 0 IMWr Data your IMWr Data
0xB00 DMA Channel Control 1 register 0x04000010

0xB08 DMA Transfer Size 0x00100000
0xB0C DMA SAR Low 0xBEEF_BEE0

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Table 69. Register setup for a 1-MB read DMA transfer from 0xBEEF_BEE0 to 0xCAFE_CAF0 (continued)
0xB10 DMA SAR High 0x0000_0000
0xB14 DMA DAR Low 0xCAFE_CAF0
0xB18 DMA DAR High 0x0000_0000
0x030 DMA Read Doorbell 0x5
3.11.6.5 Linked list mode programming example (write channel #0)†

This write channel example corresponds to Figure 53, with the following features:
• Recycled linked list (LL) of nine data elements[28]and one link element.
• Transfer is initiated by local CPU.
• Each data element corresponds to a 1 MB (0x0010_0000) write transfer.
• The SARs for each element are separated by 2 MB (0x0020_0000). The DAR for each element are separated by 16 MB
(0x0100_0000). The SAR is the address of the local memory, and the DAR is the address of the remote memory, as shown
in the figure below.
• The LL transfer list is located at address 0x0000_0200 in local memory.
• No remote interrupt is generated so the IMWr generation is disabled, as the local CPU initiates the DMA transfer. The local
CPU is interrupted using the edma_int bus.
• There is a Watermark interrupt at element #5, and an Empty interrupt at element #8. Both of these interrupts are done
interrupts (as opposed to abort interrupts).
You should familiarize yourself with the Linked List Flow for Producer and Consumer as shown in Figure 52. These are the main
steps for this process in this example:
Step 1: Create TL in local memory
• Create the 10 elements as per Table 70.
— For elements 0, 1, 2, 3, 4, 6, 7: RIE, LIE, LLP, CB =0,0,0,1
— For element 5: RIE, LIE, LLP, CB =0,1,0,1
— For element 8: RIE, LIE, LLP, CB =0,1,0,1
— For element 9: LLP, TCB, CB =1,1,0
• For more details, see PCS-CCS-CB-TCB producer-consumer synchronization† and Linked list mode†.
Step 2: Program and Start DMA
• Configure and start the DMA registers as per Table 71.
Step 4: Wait for done interrupt and recycle TL
• For more details, see Using interrupts for linked list producer-consumer synchronization†.
• When recycling elements, consider Element recycling†.
If the DMA driver is running on the host and the interrupt service routine is reading local interrupts to determine if the transfer is
successful, then you must set LIE and RIE in the same element and you should mask or ignore the local interrupt pin. Setting RIE
and LIE in element A followed by RIE (only) in element B is not a verified usage scenario.
[28] Also known as descriptors.

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DMA
Transfer
Size bytes
SAR
Local Remote
Source Destination
Memory Memory
DMA Controller
DMA
Transfer
Size bytes
DAR
Figure 48. 1 MB Write DMA Transfer from SAR to DAR
Table 70. Linked list element initial setup
Element # Address Data Label
0 0x0000_0200 0x00000001 Channel Control
0 0x0000_0204 0x00100000 Transfer Size
0 0x0000_0208 0xBEEF_BEE0 SAR Low
0 0x0000_020C 0x0 SAR High
0 0x0000_0210 0xCAFE_CAF0 DAR Low
0 0x0000_0214 0x0 DAR High
1 0x0000_021C 0x00100000 Transfer Size
1 0x0000_0220 0xBF0F_BEE0 SAR Low

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Table 70. Linked list element initial setup (continued)
1 0x0000_0224 0x0 SAR High
1 0x0000_0228 0xCBFE_CAF0 DAR Low
1 0x0000_022C 0x0 DAR High
2 0x0000_0234 0x00100000 Transfer Size
2 0x0000_023C 0x0 SAR High
2 0x0000_0240 0xCCFE_CAF0 DAR Low
2 0x0000_0244 0x0 DAR High
3 0x0000_0254 0x0 SAR High
3 0x0000_0258 0xCDFE_CAF0 DAR Low
3 0x0000_025C 0x0 DAR High
4 0x0000_0264 0x00100000 Transfer Size
4 0x0000_026C 0x0 SAR High
4 0x0000_0270 0xCEFE_CAF0 DAR Low
4 0x0000_0274 0x0 DAR High
5 0x0000_0284 0x0 SAR High
5 0x0000_0288 0xCFFE_CAF0 DAR Low

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Table 70. Linked list element initial setup (continued)
5 0x0000_028C 0x0 DAR High
6 0x0000_0294 0x00100000 Transfer Size
6 0x0000_0298 0xBFAF_BEE0 SAR Low
6 0x0000_029C 0x0 SAR High
6 0x0000_0290 0xD0FE_CAF0 DAR Low
6 0x0000_0294 0x0 DAR High
7 0x0000_02A0 0xBFCF_BEE0 SAR Low
7 0x0000_02A4 0x0 SAR High
7 0x0000_02A8 0xD1FE_CAF0 DAR Low
7 0x0000_02AC 0x0 DAR High
8 0x0000_02B0 0x00000009 Channel Control
8 0x0000_02B4 0x00100000 Transfer Size
8 0x0000_02B8 0xBFEF_BEE0 SAR Low
8 0x0000_02BC 0x0 SAR High
8 0x0000_02C0 0xD2FE_CAF0 DAR Low
8 0x0000_02C4 0x0 DAR High
9 0x0000_02C8 0x00000006 Channel Control
9 0x0000_02CC 0x0 Reserved
9 0x0000_02D0 0x0000_0200 Linked List Element Pointer Low
9 0x0000_02D4 0x0 Linked List Element Pointer High

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Table 71. Register setup
Address Name Value

(0x8_0000+)
0x030 DMA Write Engine Enable 0x1

register resets the DMA logic. For more details, see DMA Write Engine Enable
Register (DMA_WRITE_ENGINE_EN_OFF).
0x054 DMA Write Interrupt Mask 0x0
0x090 DMA Write Linked List Error Enable 0x1

• LLLAIE =1

• Linked List Enable (LLE) =1
• Consumer Cycle Status (CCS) =PCS =1
0x21C DMA Linked List Pointer Low 0x0000_0200
0x220 DMA Linked List Pointer High 0x0000_0000
3.11.7 Advanced DMA information and operation†

This section discusses advanced features and operation of the DMA.
3.11.7.1 Overview†
The DMA write and read channels operate independently to maximize the performance of the DMA read and write data transfers
over the PCIe link.
The DMA can simultaneously perform the following types of memory transactions:
• DMA write: transfer (copy) of a block of data from local memory to remote memory
• DMA read: transfer (copy) of a block of data from remote memory to local memory
After you have programmed and started a DMA transfer (see Using the DMA†), the DMA transfers the data as described in
Architecture overview†.
3.11.7.2 DMA ordering†

The DMA assumes that all DMA read channel data must be written to the local application memory in strict address order. For a
DMA read transfer, each original outgoing request has a unique PCIe tag. The remote link partner or intermediate switch does not
have to preserve the order of CPLs corresponding to such individual requests. When the DMA receives the CPLs out of order, it
reorders that data in the read buffer (see Read buffer†) as described in DMA read transfer†. DMA write transfer data is sourced
from the local application memory and sent to the remote memory in address order.
3.11.7.2.1 AXI ordering (DMA)†

IDs ‘0’ → (CC_MAX_MSTR_TAGS_AXI - 1) are used for non-DMA and DMA non-posted requests (including write channel linked list
element access). The write channel uses an unique AXI ID (per channel) for all DMA non-posted requests sent to the AXI master.
You can observe the DMA master sideband signals *misc_info_dma to distinguish a DMA non-posted request from a non-DMA

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non-posted request with same ID. ID 0 is always used for non-DMA and DMA posted requests. Therefore the order of MWr’s to
local memory is preserved through the AXI fabric.
3.11.7.2.2 AXI master CPL-P ordering impact on performance†

The AXI ordering manager ensures that the rule “CPL must not pass a previously-issued P” is obeyed for each virtual channel
(VC). It does this by halting the unloading of completions from the native controller’s receive queues by the AXI bridge when
there are outstanding posted transactions on the AXI master interface. In a system with a single VC, this means that strongly
ordered non-DMA completions at the head of the completion queue can block weakly ordered non-DMA completions and
impact performance.
DMA outbound read completions are weakly ordered and should be mapped to a different VC (in a multi-VC system), enabling
the controller to send the completions to the DMA read buffer when strong and weakly ordered read completions are interleaved
on the wire. In a single-VC system, the DMA can still share the VC without impact from these enforced ordering rules if the RO
bit (relaxed ordering) is set on DMA read engine transactions.
3.11.7.3 Read buffer†

The DMA read buffer fulfills two functions:
• Reordering of CPLs that are returned out-of-order as described in Example transfer†.
• Buffering between the DMA and the AXI bridge master (or application if bridge not used). This is needed for buffering CPLs
when your application applies back pressure (stalling/halting), as the controller advertises infinite CPL credits.
The DMA read buffer size is automatically configured at build time and is logically arranged as a segmented-buffer, as shown
in Figure 49. It has 16 segments. The size of each segment is 256d. This is the value of the Max_Payload_Size_Supported
field of the Device Capability register in the PCIe Express Capability Structure. At enumeration time, the RC can program the
Max_Payload_Size field in the Device Control register in the PCIe Express Capability Structure with any value less than or equal
to this.
16 segments
Read Buffer Segment
64 holding
Max_Payload_Size_Supported
256 bytes
32
Figure 49. DMA read buffer
The DMA read buffer size is as follows:

• Width: 32 (same as the controller datapath width)
• Depth: 1026
The default segment size is 256 bytes, and the default number of DMA tags is 16. Therefore the default read buffer size is 16 *
256 = 4 KB. When you implement your RAMs external to the PCIe controller, you must connect this RAM through the external
RAM interface.
3.11.7.4 PCIe tags†

The combined number of PCIe tags assigned to the DMA read channel and your application (or AXI bridge) is always equal to
32. Of these tags, 16 are reserved for DMA MRd request TLP generation. The remaining tags are assigned to non-DMA transfers
generated by your application on the AXI bridge slave. The figure below shows the division of PCIe tags between the DMA
controller and the rest of the PCIe controller. It also shows the value range of each pool of tags.

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31
16 DMA tags
16
32 PCIe tags
15
16 non-DMA tags
Figure 50. PCIe Tag Allocation For DMA/Non-DMA MRd Traffic Using 16
3.11.7.4.1 Example transfer†

The DMA never has more than CC_NUM_DMA_RD_TAG simultaneous MRd requests outstanding on the PCIe link. To
demonstrate this, consider a DMA read transfer as follows. The figure below shows a scenario where there are four DMA
tags (CC_NUM_DMA_RD_TAG=4), and the remote link partner is returning out-of-order CPLs. An example of out-of-order CPL
delivery would see the CPL (or CPLs) for the first MRd request arriving after the CPL for the second MRd request.
• There are two MRd requests in transit on the PCIe link.
• There is one out-of-order CplD in the DMA read buffer.
• There is one CplD in transit on the PCIe link.

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DMA Block PCIe core, PCIe wire or Remote Link Partner
1 MRd
DMA Block TLP Generator
Read Channel MRd MRd
return
tag
Read Buffer
3
2
CpID
Application CpID
The DMA TLP Generator attempts to continuously generate identically-sized PCIe MRd request TLPs, until it
1
has requested all of the DMA data. It pauses when there are CC_NUM_DMA_RD_TAG requests issued.
When DMA Read Buffer receives all of the data [one or more CplDs] corresponding to an MRd, the PCIe TAG
2
is released and the DMA TLP Generator resumes generation of MRd TLPs.
If CplDs are received out-of-order, they are retained in the Read Buffer until data corresponding to earlier requests is
3
received. This can delay the return of the PCIe TAG to the DMA TLP Generator, as the TAG is only returned when the
segment data is accepted by the application.
Figure 51. DMA read transfer decomposition into multiple MRd requests with CC_NUM_DMA_RD_TAG =4
The DMA segments the transfer into a number (up to a maximum of CC_NUM_DMA_RD_TAG) of MRd requests. The size of each
request is limited to the minimum of {Max_Read_Request_Size, Max_Payload_Size}.
• When a CplD TLP for an MRd request returns from the PCIe Wire out-of-order:
— The CplD is stored in the DMA read buffer.
— The tag is not released back to the DMA tag pool, and the DMA cannot generate another MRd request with this tag
number.
— When the CplD from all of the previous MRd requests have been received, the DMA completes the next steps:
◦ The CplD is converted to an MWr and forwarded to your application (or AXI bridge master for writing to the AXI
bus).
◦ The tag is released back to the DMA tag pool.
◦ The DMA generates another MRd request with this tag number.
• When a CplD TLP for an MRd request returns from the PCIe Wire in-order:
— The CplD is converted to an MWr and forwarded to your application (or the AXI bridge master for writing to the AXI
bus).
— The TAG is released back to the DMA tag pool.
— The DMA generates another MRd request with this tag number.
3.11.7.5 Error handling†

The DMA supports full AXI and PCIe error handling in conjunction with the PCIe controller. Table 72 and Table 73 list the possible
sources of an error for DMA read and write transfers.

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Table 72. Possible sources of an error during a DMA read transfer
Source Type Description
Application Write Fatal The DMA read channel has received an error response from the AXI bus at the bridge
Error Detected master interface while writing posted data to it. This error is fatal.
• You must restart the transfer from the beginning because the channel context
is corrupted.
• The MWr is not rolled back.
• The AXI bridge master does not report this error to software through error logging
or MSG.
Note: During linked list mode, the Application Write Error only corrupts the current
element in the linked list.
Unsupported Non-fatal The DMA read channel has received a PCIe UR CPL status from the remote device in
Request (UR) response to the MRd request.
Completer Abort (CA) Non-fatal The DMA read channel has received a PCIe CA CPL status from the remote device in
response to the MRd request.
CPL Time Out Non-fatal The DMA read channel has timed-out while waiting for the remote device to respond to
the MRd request, or a malformed CplD has been received.
Data Poisoning Fatal The DMA read channel has detected data poisoning in the CPL from the remote device
in response to the MRd request. The DMA read channel will drop the completion and
then be halted. The CX_FLT_MASK_UR_POIS filter rule does not affect this behavior.
Linked List Element Fetch Fatal The DMA read channel has received an error response from the AXI bus (or TRGT1
Error Detected interface when the AXI bridge is not used) while reading a linked list element from
local memory.
Table 73. Possible sources of an error during a DMA write transfer
Source Type Description
Application Read Fatal The DMA write channel has received an error response from the AXI bus at the bridge
Error Detected master interface while reading data from it.
• The response TLP is discarded by the DMA and is not converted to an outbound
MWr TLP.
• The UR or CA CPL status TLP generated by the bridge is discarded by the DMA.
• The AXI bridge master does not report this error to software through error logging
or MSG.
Linked List Element Fetch Fatal The DMA write channel has received an error response from the AXI bus at the bridge
Error Detected master interface (or TRGT1 interface when the AXI bridge is not used) while reading
a linked list element from local memory.
• The UR or CA CPL status TLP generated by the bridge is discarded by the DMA.
• The AXI bridge master1 does not report this (or for non-DMA traffic) error to
software through error logging or MSG.
When the DMA detects an error, it performs the following actions (for the channel with the error):

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• Stops issuing new requests to the remote link partner.

• Stops issuing new requests to your application.
— All data in the read buffer (see Read buffer†) that was received before the error was detected is valid
and is sent to your application. In the case of a non-fatal error, this is reflected in the DMA Transfer Size
Register DMA_TRANSFER_SIZE_OFF_WRCH_0.
— All data in the read buffer (for that channel), that was received after the error was detected, is discarded.
• Places the DMA channel in a halted state (channel status field of the DMA Channel Control 1 Register is halted).
• Waits for all outstanding requests and CPLs to complete.
• Generates the abort interrupt or IMWr, if enabled, as outlined in Interrupt handling†.
For a DMA read transfer, you can read the DMA Read Error Status High Register (DMA_READ_ERR_ STATUS_HIGH_OFF) and
DMA Read Error Status Low Register (DMA_READ_ERR_STATUS_LOW_OFF) to identify the source of the error. For a DMA write
transfer (in linked list mode only), you can read the DMA Write Error Status Register (DMA_WRITE_ERR_STATUS_OFF) to identify
the source of the error. After your software has finished error and interrupt routine handling for Non-Fatal errors, you can request
the DMA to continue processing (for the channel with the error) by:
1. Reprogramming the SAR based on the number of bytes remaining in the DMA Transfer Size register
2. Writing the channel number to the Doorbell Number field of the DMA Write Doorbell Register
(DMA_WRITE_DOORBELL_OFF) or DMA Read Doorbell Register (DMA_READ_DOORBELL_REG).
CAUTION
You cannot continue after a Fatal Error is detected, as the channel context is corrupted. Any actions that were
in progress are not rolled back. To exit from this condition, you need to Soft Reset the complete DMA controller,
as described in DMA Write Engine Enable Register (DMA_WRITE_ENGINE_EN_OFF) and DMA Read Engine
Enable Register (DMA_READ_ENGINE_EN_OFF).
When an error occurs in linked list mode, DMA Linked List Pointer Low Register (DMA_LLP_LOW_OFF_WRCH_0) is not
incremented by the DMA, but remains pointing to the element that caused the error.
3.11.7.5.1 Error handling assistance by remote software†

During a DMA write transfer, the DMA is not aware of MWr errors that are detected in the remote device, because an MWr is
a posted request and has no corresponding completion TLP. In these cases, your remote CPU must manually abort the DMA
transfer by writing the channel number to the Doorbell Number field, and 1 to the Stop field of the DMA Write Doorbell Register
(DMA_WRITE_DOORBELL_OFF). This causes the DMA to:
• Place the channel in a Stopped state. The channel Status field of the DMA Channel Control 1 Register
(DMA_CH_CONTROL1_OFF_WRCH_0) is Stopped and the DMA Transfer Size register is not 0x0.
• Wait for all outstanding pending transactions.
• Assert the abort interrupt if it is enabled
For more details, see Stopping the DMA transfer (software stop)†. Alternatively, your remote CPU can return an error Msg to the
local CPU. The local CPU can then stop the channel by setting the Stop field. You can re-start the transfer by rolling back the SAR
based on the number of bytes remaining in the DMA Transfer Size Register (DMA_TRANSFER_SIZE_OFF_WRCH_0) subject to the
restrictions outlined in Stopping the DMA transfer (software stop)†.
NOTE
This procedure is only necessary during software development; when you incorrectly program the DMA write
channel DAR. An MWr error is fatal and you must resolve it by fixing your software. In normal operation MWr errors
are not expected to occur.

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3.11.7.6 DMA debug†

To assist you in debugging your hardware, use the following outputs to identify DMA traffic (transfer requests, and linked list
element MRds) and non-DMA traffic.
Table 74. DMA debug outputs
Signal name Where used
armisc_info_dma AXI master
awmisc_info_dma AXI master
3.11.7.6.1 Soft reset†

To assist you in debugging your software, use the DMA write engine enable field of the DMA Write Engine Enable Register
(DMA_WRITE_ENGINE_EN_OFF) to reset the DMA write logic. This might be necessary during software development, if you
incorrectly program and hang the DMA. Similarly, use the DMA read engine enable field of the DMA Read Engine Enable Register
(DMA_READ_ENGINE_EN_OFF) to reset the DMA read logic. This soft reset does not clear the DMA configuration registers.
3.11.7.6.2 Stop bit†

To assist you in debugging your software, use the Stop bit of the DMA Write Doorbell Register (DMA_WRITE_DOORBELL_OFF),
or of the DMA Read Doorbell Register (DMA_READ_DOORBELL_REG), to prematurely stop a DMA transfer. For more information,
see Stopping the DMA transfer (software stop)†.
3.11.7.6.3 Test interrupt†

You can write to the DMA Write Interrupt Status Register (DMA_WRITE_INT_STATUS_OFF), or the DMA Read Interrupt Status
Register (DMA_READ_INT_STATUS_OFF), to emulate interrupt generation, during software or hardware testing. A write to these
registers triggers an interrupt, but the DMA does not set the done or abort bits in these registers. This test interrupt is unaffected
by the mask bits. To clear this interrupt, you must write to either of the DMA Write Interrupt Clear or the DMA Read Interrupt
Clear registers.
3.11.7.7 Linked-list operation†

This section describes the detailed operation of the DMA in linked-list (LL) mode. It also discusses how the software should
produce LL elements (also known as descriptors), and how the DMA and software maintain synchronization.
3.11.7.7.1 LL operation overview†

You should first read Linked list mode† for an overview of LL mode. In this section, a normal LL operation called recycling[29] is
described in detail. The process is described for a write channel, but it is possible to have duplicate processes running in parallel
for other write or read channels. In this process interrupts are used to trigger the producer (software) to recycle elements. Typically
a Watermark interrupt (positioned near the middle of the transfer list (TL)) and an Empty interrupt (in the last data element) are
used by setting LIE in these two elements to ‘1’.
The steps in this process are:
1. Software creates a LL element structure called a TL in local memory consisting of N-1 data elements and one link element.
• The link element s “LL Element Pointer Low/High DWORDs” in Figure 43) are programmed to point back to the
beginning of the first data element.
• One of the data elements (near the middle of the TL) is programmed to generate a “Watermark” interrupt.
[29] With recycling, the same LL structure is used over and over again. Another mode of operation would be to jump to a new
LL element structure when the current one is consumed.

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• The last data element is programmed to generate an “Empty” interrupt.

2. Software programs the DMA with the location of the TL. This is done by writing to the DMA Linked List Pointer Low Register
(DMA_LLP_LOW_OFF_WRCH_0) and DMA Linked List Pointer High Register (DMA_LLP_HIGH_OFF_WRCH_0).
3. Software starts the DMA process by ringing the write channel Doorbell. This is done by writing to the DMA Write Doorbell
Register (DMA_WRITE_DOORBELL_OFF).
The solid purple loop L1 in Figure 52 corresponds to steps 1-3.
4. The DMA reads (consumes) each data element from local memory, and if the CB and CCS bits match, loads the information
(SAR, DAR, size, and so on) from that data element into the channel context registers. These context registers determine
the operation of the channel that the DMA is currently servicing. The DMA executes the check for the CB/CCS match after
it has evaluated TCB and toggled CCS. The DMA always loads link elements into the channel context.
NOTE
If the DMA stops on a link element, then your software must set the DMA Linked List Pointer registers, and restart
the DMA process by ringing the doorbell.

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Software
RESET
(SW)
IDLE Software Produces Linked List Element Structure:
a. PCS = 1
yes b. Create N-1 data Elements with C
edma_int
* CB = PCS = 1
‘Done’ L3 Build Element List
* LIE = 1 (Elements #N/2 and #N-2 only)
Channel Status Interrupt
c. Create 1 link Element (#N-1) with
L1
= STOPPED * LLP = 1
no * IF (!TCB) {CB = PCS = 1} ELSE {CB=~PCS=0}
Program and
Ring Channel * TCB = 1 (Recycle Mode only)
no Recycle doorbell * LL Element Pointer set to next LL Element list.
Mode d. PCS = ~PCS, when TCB = 1 [Recycle mode]
“Producer Cycle Status” (PCS) is a local variable in your Software
yes
Initial DMA Controller Condition
Read current value * Linked List enabled through LLE bit.
of Channel Context * CCS = 1
LL Pointer (say x)
DMA
D Controller
Recycle Element
List up to x Using Read Element
Process in 1 Current DMA activity for this
channel finished
yes
edma_int = 1
L5 Clear LIEP
Channel Status
= STOPPED yes
L2
LLP = 1
E yes II no Set Channel Status no
LIEP = 1
CB = CCS Transfer list = STOPPED yes
Ring Channel empty
doorbell no
yes
CB = CCS
Load Element
into Channel Context
CCS = CCS =
L4
CCS ~CCS
yes yes
LLP = 1 TCB = 1
Software Recycles Linked List Element Structure: 1 yes edma_int = 1

LIEP = 1
b. Create N-1 data Elements with Clear LIEP
* CB = PCS
* LIE = 1 (Elements #N/2 and #N-2 only) no
c. Create 1 link Element (#N-1) with
* LLP = 1 Transfer
* CB = ~PCS Block of Data
* TCB = 1
* LL Element Pointer set to Element #0
A
d. PCS = ~PCS LIEP = 1
yes
LIE = 1 Set interrupt
pending flag
no
Element Pointer
++6
Figure 52. Linked-list flow for producer and consumer
5. The DMA then proceeds to transfer the block of data (as defined by the element), and when it is finished, reads the next
element from local memory.
The solid green loop L2 in Figure 52 corresponds to steps 4-5.
6. The last element in the list (called a link element, and indicated by having its LLP field set to 1) is not used to transfer a block
of data.
• It causes the DMA to effectively repeat the task in step 4.
• Its TCB is typically set to 1. This causes the DMA to toggle its CCS bit, and the software to toggle its PCS bit. The
software and DMA use the “PCS-CCS-CB-TCB” producer-consumer synchronization mechanism to ensure that:

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— Software does not recycle elements that have not yet being consumed by the DMA
— DMA correctly recognizes and consumes recycled elements.
The solid red loop L4 in Figure 52 corresponds to step 6.
7. Upon reception of the interrupt (mentioned in step 1), the software starts to recycle the TL.
• Software reprograms each data element with new DMA transfer information.
• The software and DMA use the “PCS-CCS-CB-TCB” producer-consumer synchronization mechanism described later
in this section.
The dashed purple loop L3 in Figure 52 corresponds to step 7.
8. As some point, the software wants to terminate the complete DMA process, by not recycling any more elements. The DMA
recognizes this condition when CB !=CCS, and sets the channel status to stopped
The dashed red loop L5 in Figure 52 corresponds to step 8.
3.11.7.7.2 Using interrupts for linked list producer-consumer synchronization†

When the DMA is finished with an element, the DMA checks the LIE bit, before reading the next LL element. For more details,
see circled step A in Figure 52. When the LIE is set, then the DMA does not assert the “done” interrupt immediately, but sets an
internal interrupt pending flag (LIEP). It asserts the actual done interrupt after the next data element has been read from system
memory. For more details, see circled step B in Figure 52. This automatic internal process of delaying the interrupt avoids a race
condition between the DMA and software when the LIE bit is set in an element.
Your software should set the “Watermark” interrupt early to schedule the recycling of the consumed elements. Placing the
Watermark interrupt too far down in the list, combined with a slow element recycling process in your application; ensures that the
DMA returns to the start of the LL before your software has recycled it. The DMA channel STOPs, and you have to restart it by
writing to its Doorbell. Typically a “Watermark interrupt” (positioned near the middle of the TL) and an Empty interrupt (in the last
data element) are used by setting LIE in these two elements to 1b1. Upon reception of the interrupt, the software starts to recycle
the TL.
Operational interrupts are always “done” interrupts. For more details, see Interrupts and error handling†.
The DMA processes the remote interrupt enable (RIE) bit in the LL element in the same way as the LIE. Therefore, everywhere
that LIE and edma_int are mentioned in this section can be interpreted to mean LIE and edma_int, or RIE and IMWr.
3.11.7.7.3 PCS-CCS-CB-TCB producer-consumer synchronization†

The software and DMA use the “PCS-CCS-CB-TCB” producer-consumer synchronization mechanism to ensure that software
does not recycle elements that have not yet being consumed by the DMA, and that the DMA correctly recognizes and consumes
recycled elements. This process, which is shared between the DMA and the software, is illustrated through an example
producer-consumer flow in the following figure.

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Channel Context LL
Pointer Phase 1 Phase 2
DMA LLP CB TCB LIE LLP CB TCB LIE Software

CCS = 1 0 0 1 - 0 0 0 1 - 0
1 0 1 - 0 1 0 1 - 0
2 0 1 - 0 2 0 1 - 0
3 0 1 - 0 3 0 1 - 0
4 0 1 - 0 4 0 1 - 0 Watermark
lnterrupt
5 0 1 - 1 DMA 5 0 1 - 1 to trigger
... .. .. .. .. CB = PCS = 1 ... .. .. .. .. Producer
Recycling
N-3 0 1 - 0 N-3 0 1 - 0
N-2 0 1 - 1 N-2 0 1 - 1
Software
N-1 1 0 1 - N-1 1 0 1 -
PCS -> 0
LL Element Pointer
Bold = owner is DMA (Consumer)
Phase 3 Phase 4
LLP CB TCB LIE LLP CB TCB LIE

0 0 0 - 0 0 0 0 - 0
1 0 0 - 0 1 0 0 - 0
2 0 0 - 0 2 0 0 - 0
CB = PCS = 0
3 0 0 - 0 3 0 0 - 0
4 0 0 - 0 4 0 0 - 0
5 0 0 - 1 Software 5 0 0 - 1 Software
... .. .. .. .. ... .. .. .. ..
DMA
N-3 0 1 - 0 N-3 0 1 - 0
N-2 0 1 - 1 N-2 0 1 - 1
DMA
N-1 1 0 1 - N-1 1 0 1 -
Empty
CCS -> 0
Interrupt
to re-trigger
Producer
Phase 5 Phase 6 Recycling
LLP CB TCB LIE LLP CB TCB LIE CB = PCS = 1

0 0 0 - 0 0 0 1 - 0
Software
1 0 0 - 0 1 0 0 - 0
2 0 0 - 0 2 0 0 - 0
DMA 3 0 0 - 0 3 0 0 - 0
4 0 0 - 0 4 0 0 - 0
DMA
5 0 0 - 1 5 0 0 - 1
... .. .. .. .. CB = PCS = 0 ... .. .. .. ..
N-3 0 0 - 0 N-3 0 0 - 0
N-2 0 0 - 1 N-2 0 0 - 1
Software
N-1 1 1 1 - N-1 1 1 1 -
PCS -> 1
Figure 53. Example producer (software) - consumer (DMA) synchronization flow
Before looking at the example in detail, it is useful to note that the DMA performs the following two tests as part of this process:
• Consumer-Owned Element, or Transfer List (TL) Empty Test
The solid red loop L4 in Figure 52 corresponds to this test. The Cycle Bit (CB) of DMA Channel Control 1 Register
(DMA_CH_CONTROL1_OFF_WRCH_0) (which was loaded from the LL element) is tested against the DMA Consumer Cycle
State (CCS) bit of the same register. When CB =CCS, the element is owned by the consumer (DMA) and the data transfer
is executed. When CB !=CCS, the TL is empty and the DMA sets channel Status (CS) in DMA Channel Control 1 Register
(DMA_CH_CONTROL1_OFF_WRCH_0) to “Stopped”.

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• Toggle Cycle Bit (TCB) Test

The dashed red loop mMarked L5 in Figure 52 corresponds to this test. When the Toggle Cycle Bit (TCB) of the DMA Channel
Control 1 Register (DMA_CH_CONTROL1_OFF_WRCH_0) (which was loaded from the LL element) is set to 1, the DMA toggles
the CCS bit of the DMA Channel Control 1 Register (DMA_CH_CONTROL1_OFF_WRCH_0) to be ~CB. The producer (software)
also performs a similar action on its local variable “Producer Cycle Status” (PCS), as it sets PCS =~PCS. The TCB field is only
valid in the last LL element (the link element). Toggling the PCS and CCS flags in this manner synchronizes the consumer
to the producer.
The example in Figure 53 has the following six phases:
1. The software builds the transfer list for the write (or read) channel, according to the steps outlined in the circled step C in
Figure 52. For each element, CB =PCS =CCS =1. The exception to this is the link element where CB is set to the next
iteration value because the link element is always loaded into the channel context.
a. The link element points to the start of the TL and its TCB bit is 1. Software toggles its PCS variable.
b. Software writes the location of the TL into the channel context LL Pointer register.
c. Software rings the write channel Doorbell.
2. The DMA starts processing elements. After processing element 5 (and fetching the next element), the DMA asserts a
Watermark “done” interrupt to signal the software to start recycling elements.
3. The software is recycling elements. It reads the channel context DMA Linked List Pointer Low Register
(DMA_LLP_LOW_OFF_WRCH_0) and DMA Linked List Pointer High Register (DMA_LLP_HIGH_OFF_WRCH_0), and recycles
elements up to this location[30]in the TL. It sets CB for each element to be PCS. The dashed purple loop marked L3 in Figure
52 corresponds to this activity.
The DMA continues processing (consuming) elements as before.
4. The DMA then asserts an Empty “done” interrupt (from the LIE bit in the last data element at the end of TL that was set in
the previous phase) to indicate to the software, to start recycling elements again. The DMA reaches the end of the TL, and
as the TCB is set to 1, it toggles its CCS bit to 0 (~CB). For more details, see circled step D in Figure 52.
5. The software reads the channel context DMA Linked List Pointer Low Register (DMA_LLP_LOW_REG _WRCH_0) and DMA
Linked List Pointer High Register (DMA_LLP_HIGH_OFF_WRCH_0), and recycles elements up to this location in the TL. It
sets CB for each element to be PCS. As it recycles the link element, it detects that TCB is set to 1. It toggles its internal
variable PCS to 0, and the initial TL has been fully recycled.
The DMA starts processing the recycled elements.
6. The DMA continues processing (consuming) elements as before. Software did not have to ring the Doorbell, as the first
element was already recycled before the DMA started processing it.
The software might continue recycling from the top of the list, if the DMA had already returned to the top of the list when
the software read the channel context DMA Linked List Pointer Low Register (DMA_LLP_LOW_OFF_WRCH_0) and DMA
Linked List Pointer High Register (DMA_LLP_HIGH_OFF_WRCH_0), in step 5. If not, it starts recycling again when the DMA
processes element 4 and the DMA asserts a Watermark “done” interrupt.
3.11.7.7.4 Element recycling†

When your software is recycling elements, it should program the first DWORD (control bits) in Figure 43 only after the other
DWORDs have been programmed. In addition, it should set the CB bit (to ~PCS) within this DWORD only after the other bits
in this DWORD have been set. This programming sequence avoids the DMA incorrectly fetching an element that software is
currently recycling.
When the software is finished recycling it must check the channel context status (CS). When CS is “Stopped”, the software must
ring the channel Doorbell again. For more details, see circled step E in Figure 52. If your element recycling process was fast
enough, then the DMA will seamlessly move from processing the last old element to the first new element, without the need
[30] If the consumer has moved on to another element, this is not a problem. These newly consumed elements are recycled in
the next recycling phase.

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for the software to ring the channel Doorbell again. To eliminate the possibility of a race condition between these two actions
(read and write), you should first confirm the presence of the “done” interrupt bit in the DMA Write Interrupt Status Register
(DMA_WRITE_INT_STATUS_OFF) or DMA Read Interrupt Status Register (DMA_READ_INT_ STATUS_OFF) and also check the
DMA Linked List Pointer Low Register (DMA_LLP_LOW_REG_WRCH_0) to confirm that it is pointing to the correct location.
3.11.7.7.5 Link down recovery†

During normal operation when the link goes down, the controller generates a “link reset“ request. A high-to-low transition on
link_req_rst_not indicates that the PCIe controller is requesting external logic to reset the PCIe controller because the PHY
link is down. To determine the progress of the linked list operation when the link went down, you can read the contents of
the channel context DMA Linked List Pointer Low Register (DMA_LLP_LOW_OFF_WRCH_0) and DMA Linked List Pointer High
Register (DMA_LLP_HIGH_OFF_WRCH_0).
3.11.7.8 Multichannel arbitration†

A DMA write and read channel operate independently in full duplex mode. This maximizes the performance of the DMA read
and write data transfers over the PCIe link. When you configure the DMA with multiple read channels, then it uses a weighted
round robin (WRR) arbitration scheme to select the next read channel to be serviced. The same applies when you have multiple
write channels. The DMA handles the multiple channels in a time-multiplexed way. From a software point of view every channel
operates independently, so each one has its own instance of linked list and context. The bandwidth for all channels is shared in
time and is controlled by a weighted round-robin arbiter.
You can set the arbitration weight for each channel using the DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF,
DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF), DMA_READ_CHANNEL_ARB_WEIGHT_LOW_REG, and
DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF registers. Each register has a 5-bit field (representing a weight from 1 to
32) for up to four channels. You must set the weights before “ringing” the doorbell.
The channel weight specifies the number of TLP requests that the DMA can issue for that channel before it must return to the
arbitration routine. When the channel weight count is reached, the WWR arbiter selects the next channel to be processed. For
example, consider two DMA write channels (write channel #0 and write channel #1) where you want to assign the bandwidth for
write channel #1 to be two times that of write channel #3. Therefore set:
• write channel #0 weight to 32
• write channel #1 weight to 16
Depending on the transfer size and the max_payload_size, the DMA will issue 32 MRd requests for write channel #0, followed by
16 MRd requests for write channel #1, followed by 32 MRd requests for write channel #0 and so on, until the current transfer (or
element when using LL mode) is finished. Therefore in this example, the weights reserve 33% bandwidth for write channel #1 and
67% bandwidth for write channel #0.
The maximum number of outstanding DMA write engine MRd requests to the application is 16, so the sum of weights should not
exceed this value.
For the DMA read engine, the sum of all weights should not exceed 16.
If these limits are exceeded, then the respective DMA engine requester thread is back-pressured, defeating purpose of the
round-robin bandwidth sharing mechanism.
When the ratio (transfer-size / TLP-size) is smaller than the round-robin arbiter setting (say,
DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF), the DMA issues less requests than the value in
DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF. The TLP size is determined by the DMA using each
function's Max_Payload_Size and Max_Read_Request_Size rules. This means that the arbitration value in
DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF determines the number of TLPs send and not the absolute data bandwidth.
3.11.7.8.1 Request, response, and descriptor-fetch threading in LL mode for a read channel†
For each read channel there are two threads (1) the request thread and (2) the response thread which are running in opposite
directions. The DMA processes these threads independently. The request thread does not wait for the individual responses to
arrive before issuing the next request. The request thread for the current channel i continues to issue requests until one of the
following is true:

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• The DMA exhausts its pool of available tags and the logic in the read buffer (see Read buffer†) back-pressures the DMA read
engine controller.
• The DMA completes its current DMA transfer block for the current channel. It has requested all of the data specified by the
currently-loaded LL element (also known as a descriptor).
• The current channel has issued Wi MRd requests, where Wi is the round robin weight associated with that channel.
A channel arbitration event now occurs and the DMA loads the context for the winning channel j. When the DMA is loading the new
context, the response path for the previous channel i will be still utilizing the wire because the response thread lags the request
thread. As soon as the DMA has loaded the context (and LL element if in LL mode) for the current channel j, it starts to issue
requests. Therefore, in multichannel operation, when the block for channel i completes and a new LL element is been fetched,
the DMA can be issuing requests belonging to other DMA channels. The currently inactive requester thread for channel i needs
to synchronize with the response thread (that is, wait for all completions) before fetching its next LL element from local memory.
3.11.8 PCIE_DMA register descriptions

This section presents the DMA controller registers.†
The channel context registers are stored in RAM whose contents are automatically initialized after power-on.
You must not write to any of the context registers for a particular channel after you start the channel by writing the channel number
to the Doorbell Number field of the DMA Write Doorbell Register (DMA_WRITE_DOORBELL_OFF) or DMA Read Doorbell
Register (DMA_READ_DOORBELL_OFF).
When you enable linked list operation (Linked List Enable field of DMA Channel Control 1 Register
(DMA_CH_CONTROL1_OFF_WRCH_0) t o 1b1), the DMA overwrites the following DMA channel context registers with the
following information from linked list data elements:
• The CB, LLP, LIE, and RIE fields of the DMA Channel Control 1 register
• DMA Transfer Size
• DMA SAR Low
• DMA SAR High
• DMA DAR Low
• DMA DAR High
The structure of a link element is different to that of the data element. A data element has no TCB field. A link element has no LIE or
RIE fields. It has no SAR, DAR, or Transfer Size DWORDs, but has LL Element Pointer DWORDs instead of the SAR DWORDs.
For more details, see Relationship Between Element DWORDs and Channel Context Registers.
The LIE and RIE bits in a LL element, only enable the Done interrupt. In non-LL mode, the RIE and LIE bits enable the Done and
Abort interrupts. For more information, see Interrupts and Error Handling.
3.11.8.1 DMA memory map

PCIE_DMA relative offset: 7_0000h
(In bits)
0h DMA arbitration scheme for TRGT1 interface 32 RW 0000_0688h

(DMA_CTRL_DATA_ARB_PRIOR_OFF)
8h DMA number of channels (DMA_CTRL_OFF) 32 RW 0004_0004h
Ch DMA Write Engine Enable (DMA_WRITE_ENGINE_EN_OFF) 32 RW 0000_0000h

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(In bits)
10h DMA Write Doorbell (DMA_WRITE_DOORBELL_OFF) 32 RW 0000_0000h
18h DMA write engine channel arbitration weight low 32 RW 0000_8421h

(DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF)
2Ch DMA Read Engine Enable (DMA_READ_ENGINE_EN_OFF) 32 RW 0000_0000h
30h DMA Read Doorbell (DMA_READ_DOORBELL_OFF) 32 RW 0000_0000h
38h DMA read engine channel arbitration weight low 32 RW 0000_8421h

(DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF)
4Ch DMA Write Interrupt Status (DMA_WRITE_INT_STATUS_OFF) 32 RW 0000_0000h
54h DMA write interrupt mask (DMA_WRITE_INT_MASK_OFF) 32 RW See

description
58h DMA write interrupt clear (DMA_WRITE_INT_CLEAR_OFF) 32 W1C See

description
5Ch DMA Write Error Status (DMA_WRITE_ERR_STATUS_OFF) 32 RO 0000_0000h
60h DMA write done IMWr address low 32 RW 0000_0000h

(DMA_WRITE_DONE_IMWR_LOW_OFF)
64h DMA write done IMWr interrupt address high 32 RW 0000_0000h

(DMA_WRITE_DONE_IMWR_HIGH_OFF)
68h DMA write abort IMWr address low 32 RW 0000_0000h

(DMA_WRITE_ABORT_IMWR_LOW_OFF)
6Ch DMA write abort IMWr address high 32 RW 0000_0000h

(DMA_WRITE_ABORT_IMWR_HIGH_OFF)
70h DMA write channel 0 and 1 IMWr data 32 RW 0000_0000h

(DMA_WRITE_CH01_IMWR_DATA_OFF)
74h DMA write channel 2 and 3 IMWr data 32 RW 0000_0000h

(DMA_WRITE_CH23_IMWR_DATA_OFF)
90h DMA write linked list error enable 32 RW See

(DMA_WRITE_LINKED_LIST_ERR_EN_OFF) description
A0h DMA Read Interrupt Status (DMA_READ_INT_STATUS_OFF) 32 RW 0000_0000h
A8h DMA read interrupt mask (DMA_READ_INT_MASK_OFF) 32 RW See

description
ACh DMA Read Interrupt Clear (DMA_READ_INT_CLEAR_OFF) 32 WO 0000_0000h
B4h DMA Read Error Status Low 32 RO 0000_0000h

(DMA_READ_ERR_STATUS_LOW_OFF)
B8h DMA Read Error Status High 32 RO 0000_0000h

(DMA_READ_ERR_STATUS_HIGH_OFF)

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(In bits)
C4h DMA read linked list error enable 32 RW See

(DMA_READ_LINKED_LIST_ERR_EN_OFF) description
CCh DMA read done IMWr address low 32 RW 0000_0000h

(DMA_READ_DONE_IMWR_LOW_OFF)
D0h DMA read done IMWr address high 32 RW 0000_0000h

(DMA_READ_DONE_IMWR_HIGH_OFF)
D4h DMA Read Abort IMWr Address Low 32 RW 0000_0000h

(DMA_READ_ABORT_IMWR_LOW_OFF)
D8h DMA Read Abort IMWr Address High 32 RW 0000_0000h

(DMA_READ_ABORT_IMWR_HIGH_OFF)
DCh DMA Read Channel 0 And 1 IMWr Data 32 RW 0000_0000h

(DMA_READ_CH01_IMWR_DATA_OFF)
E0h DMA Read Channel 2 And 3 IMWr Data 32 RW 0000_0000h

(DMA_READ_CH23_IMWR_DATA_OFF)
108h DMA write engine handshake counter channel 0/1/2/3 32 RO 0000_0000h

(DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF)
118h DMA read engine handshake counter channel 0/1/2/3 32 RO 0000_0000h

(DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF)
200h DMA Write Channel Control (DMA_CH_CONTROL1_OFF_WRCH_0) 32 RW 0000_0000h
208h DMA write transfer size (DMA_TRANSFER_SIZE_OFF_WRCH_0) 32 RW 0000_0000h
20Ch DMA Write SAR Low (DMA_SAR_LOW_OFF_WRCH_0) 32 RW 0000_0000h
210h DMA write SAR high (DMA_SAR_HIGH_OFF_WRCH_0) 32 RW 0000_0000h
214h DMA Write DAR Low (DMA_DAR_LOW_OFF_WRCH_0) 32 RW 0000_0000h
218h DMA write DAR high (DMA_DAR_HIGH_OFF_WRCH_0) 32 RW 0000_0000h
21Ch DMA write linked list pointer low (DMA_LLP_LOW_OFF_WRCH_0) 32 RW 0000_0000h
220h DMA write linked list pointer high (DMA_LLP_HIGH_OFF_WRCH_0) 32 RW 0000_0000h
300h DMA Read Channel Control (DMA_CH_CONTROL1_OFF_RDCH_0) 32 RW 0000_0000h
308h DMA read transfer size (DMA_TRANSFER_SIZE_OFF_RDCH_0) 32 RW 0000_0000h
30Ch DMA Read SAR Low (DMA_SAR_LOW_OFF_RDCH_0) 32 RW 0000_0000h
310h DMA read SAR high (DMA_SAR_HIGH_OFF_RDCH_0) 32 RW 0000_0000h
314h DMA Read DAR Low (DMA_DAR_LOW_OFF_RDCH_0) 32 RW 0000_0000h
318h DMA read DAR high (DMA_DAR_HIGH_OFF_RDCH_0) 32 RW 0000_0000h
31Ch DMA Read Linked List Pointer Low 32 RW 0000_0000h

(DMA_LLP_LOW_OFF_RDCH_0)

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(In bits)
320h DMA Read Linked List Pointer High 32 RW 0000_0000h

(DMA_LLP_HIGH_OFF_RDCH_0)



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(In bits)




3.11.8.2 DMA arbitration scheme for TRGT1 interface (DMA_CTRL_DATA_ARB_PRIOR_OFF)
Offset
Register Offset
DMA_CTRL_DATA_ARB 0h
_PRIOR_OFF
Function
This register is used to control traffic priorities among various sources that are delivered to your application through TRGT1
where 0x0 represents the highest priority. - Non-DMA Rx Requests - DMA Write Channel MRd Requests (DMA data requests

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and LL element/descriptor access) - DMA Read Channel MRd Requests (LL element/descriptor access) - DMA Read Channel
MWr Requests Concurrent traffic from channels with same priority are sorted according to Round-Robin arbitration rules. The
arbitration priority defaults to Non-DMA requests (highest), Write Channel MRd, Read Channel MRd, Read Channel MWr.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 RDBUFF_TRGT_WEIGH RD_CTRL_TRGT_WEIG WR_CTRL_TRGT_WEIG

RTRGT1_WEIGHT
W T HT HT
Reset 0 0 0 0 0 1 1 0 1 0 0 0 1 0 0 0
Fields
Field Function
31-12 Reserved
11-9 DMA Read Channel MWr Requests. Note: The access attributes of this field are as follows: - Wire: R/W
RDBUFF_TRG
T_WEIGHT
8-6 DMA Read Channel MRd Requests. For LL element/descriptor access. Note: The access attributes of
this field are as follows: - Wire: R/W
RD_CTRL_TRG
T_WEIGHT
5-3 DMA Write Channel MRd Requests. For DMA data requests and LL element/descriptor access. Note:
The access attributes of this field are as follows: - Wire: R/W
WR_CTRL_TR
GT_WEIGHT
2-0 Non-DMA Rx Requests. Note: The access attributes of this field are as follows: - Wire: R/W
RTRGT1_WEIG
HT
3.11.8.3 DMA number of channels (DMA_CTRL_OFF)
Offset
Register Offset
DMA_CTRL_OFF 8h

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Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 DIS_C DIS_C 0 NUM_DMA_RD_CHAN
W 2W... 2W...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 NUM_DMA_WR_CHAN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
Fields
Field Function
31-26 Reserved
25 Disable DMA Read Channels "completion to memory write" context cache pre-fetch function. Note: For
internal debugging only. Note: The access attributes of this field are as follows: - Wire: R/W
DIS_C2W_CAC
HE_RD
24 Disable DMA Write Channels "completion to memory write" context cache pre-fetch function. Note: For
internal debugging only. Note: The access attributes of this field are as follows: - Wire: R/W
DIS_C2W_CAC
HE_WR
23-20 Reserved
19-16 Number of Read Channels. You can read this register to determine the number of read channels the
DMA controller has been configured to support.
NUM_DMA_RD
_CHAN
15-4 Reserved
3-0 Number of Write Channels. You can read this register to determine the number of write channels the
DMA controller has been configured to support.
NUM_DMA_WR
_CHAN

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3.11.8.4 DMA Write Engine Enable (DMA_WRITE_ENGINE_EN_OFF)
Offset
Register Offset
DMA_WRITE_ENGINE_ Ch
EN_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R 0 DMA_ DMA_ DMA_ DMA_
ed ed ed ed
WRI... WRI... WRI... WRI...
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 DMA_
W WRI...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-24 Reserved
23 Reserved
22 Reserved
21 Reserved
20 Reserved
19 Enable Handshake for DMA Write Engine Channel 3. Note: The access attributes of this field are as
follows: - Wire: R/W
DMA_WRITE_E
NGINE_EN_HS
HAKE_CH3

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Field Function
DMA_WRITE_E
NGINE_EN_HS
HAKE_CH2
DMA_WRITE_E
NGINE_EN_HS
HAKE_CH1
DMA_WRITE_E
NGINE_EN_HS
HAKE_CH0
15-1 Reserved
0 DMA Write Engine Enable. - 1: Enable - 0: Disable (Soft Reset) For normal operation, you must
initially set this bit to "1", before any other software setup actions. You do not need to toggle or
DMA_WRITE_E rewrite to this bit during normal operation. You should set this bit to "0" when you want to "Soft
NGINE Reset" the DMA controller write logic. There are three possible reasons for resetting the DMA
controller write logic: - The "Abort Interrupt Status" bit is set (in the "DMA Write Interrupt Status
Register" DMA_WRITE_INT_STATUS_OFF), and any of the bits is in the "DMA Write Error Status
Register" (DMA_WRITE_ERR_STATUS_OFF) are set. Resetting the DMA controller write logic re-
initializes the control logic, ensuring that the next DMA write transfer is executed successfully. -
You have executed the procedure outlined in "Stop Bit" , after which, the "Abort Interrupt Status"
bit is set and the Channel Status field (CS) of the DMA write "DMA Channel Control 1 Register
" (DMA_CH_CONTROL1_OFF_WRCH_0) is set to "Stopped." Resetting the DMA controller write logic
re-initializes the control logic ensuring that the next DMA write transfer is executed successfully. - During
software development, when you incorrectly program the DMA write engine. To "Soft Reset" the DMA
controller write logic, you must: - De-assert the DMA write engine enable bit. - Wait for the DMA to
complete any in-progress TLP transfer, by waiting until a read on the DMA write engine enable bit
returns a "0". - Assert the DMA write engine enable bit. This "Soft Reset" does not clear the DMA
configuration registers. The DMA write transfer does not start until you write to the "DMA Write Doorbell
Register" (DMA_WRITE_DOORBELL_OFF). Note: The access attributes of this field are as follows: -
Wire: R/W
3.11.8.5 DMA Write Doorbell (DMA_WRITE_DOORBELL_OFF)
Offset
Register Offset
DMA_WRITE_DOORBE 10h
LL_OFF

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Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R WR_ 0
W STOP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
WR_DOORBELL_NUM
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31 Stop. Set in conjunction with the Doorbell Number field. The DMA write channel stops issuing requests,
sets the channel status to "Stopped", and asserts the "Abort" interrupt if it is enabled. Before setting
WR_STOP the Stop bit, you must read the channel Status field (CS) of the "DMA Channel Control 1 Register
" (DMA_CH_CONTROL1_OFF_WRCH_0) to ensure that the write channel is "Running" (transferring
data). For more information, see "Stopping the DMA Transfer (Software Stop)." Note: The access
attributes of this field are as follows: - Wire: R/W
30-3 Reserved
2-0 Doorbell Number

WR_DOORBEL You must write the channel number to this field to start the DMA write transfer for that channel. The DMA
L_NUM detects a write to this register field even if the value of this field does not change. You do not need to
toggle or write any other value to this register to start a new transfer. The range of this field is 0–7h, and 0h
corresponds to channel 0.
A write to this field triggers the controller to exit L1 substates.
- Wire: R/W
3.11.8.6 DMA write engine channel arbitration weight low (DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF)
Offset
Register Offset
DMA_WRITE_CHANNEL 18h
_ARB_WEIGHT_LOW_O
FF
Function
The 5-bit channel weight (for write channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for
that channel before it must return to the arbitration routine. When the channel weight count is reached or DMA channel request

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transfer size reaches zero, the WWR arbiter selects the next channel to be processed. Your software must initialize this
register before ringing the doorbell. For more details, see "Multichannel Arbitration". Value range is (0-0x1F) corresponding to
(1-32) transaction requests.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
WRITE_CHANNEL3_WEIGHT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R WRITE
WRITE_CHANNEL2_WEIGHT WRITE_CHANNEL1_WEIGHT WRITE_CHANNEL0_WEIGHT
W _C...
Reset 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1
Fields
Field Function
31-20 Reserved
Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by
19-15
the channel weighted round robin arbiter to select the next channel read request. A value of '0' means
WRITE_CHAN that one TLP is issued before moving to the next channel. Note: The access attributes of this field are as
NEL3_WEIGHT follows: - Wire: R/W
14-10
9-5
4-0
3.11.8.7 DMA Read Engine Enable (DMA_READ_ENGINE_EN_OFF)
Offset
Register Offset
DMA_READ_ENGINE_E 2Ch
N_OFF

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Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R 0 DMA_ DMA_ DMA_ DMA_
ed ed ed ed
REA... REA... REA... REA...
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 DMA_
W REA...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-24 Reserved
23 Reserved
22 Reserved
21 Reserved
20 Reserved
19 Enable Handshake for DMA Read Engine Channel 3. Note: The access attributes of this field are as
DMA_READ_E
NGINE_EN_HS
HAKE_CH3
DMA_READ_E
NGINE_EN_HS
HAKE_CH2
DMA_READ_E
NGINE_EN_HS
HAKE_CH1

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Field Function
DMA_READ_E
NGINE_EN_HS
HAKE_CH0
15-1 Reserved
0 DMA Read Engine Enable. - 1: Enable - 0: Disable (Soft Reset) For normal operation, you must
initially set this bit to "1", before any other software setup actions. You do not need to toggle or
DMA_READ_E rewrite to this bit during normal operation. You should set this field to "0" when you want to "Soft
NGINE Reset" the DMA controller read logic. There are three possible reasons for resetting the DMA controller
read logic: - The "Abort Interrupt Status" bit is set (in the "DMA Read Interrupt Status Register"
(DMA_READ_INT_STATUS_OFF), and any of the bits in the "DMA Read Error Status Low Register"
(DMA_READ_ERR_STATUS_LOW_OFF) is set. Resetting the DMA controller read logic re-initializes the
control logic, ensuring that the next DMA read transfer is executed successfully. - You have executed the
procedure outlined in "Stop Bit", after which, the "Abort Interrupt Status" bit is set and the channel Status
field (CS) of the DMA read "DMA Channel Control 1 Register " (DMA_CH_CONTROL1_OFF_WRCH_0)
is set to "Stopped". Resetting the DMA controller read logic re-initializes the control logic ensuring
that the next DMA read transfer is executed successfully. - During software development, when you
incorrectly program the DMA read engine. To "Soft Reset" the DMA controller read logic, you must: -
De-assert the DMA read engine enable bit. - Wait for the DMA to complete any in-progress TLP transfer,
by waiting until a read on the DMA read engine enable bit returns a "0". - Assert the DMA read engine
enable bit. This "Soft Reset" does not clear the DMA configuration registers. The DMA read transfer does
not start until you write to the "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF). Note:
3.11.8.8 DMA Read Doorbell (DMA_READ_DOORBELL_OFF)
Offset
Register Offset
DMA_READ_DOORBEL 30h
L_OFF

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PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RD_ 0
W STOP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
RD_DOORBELL_NUM
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31 Stop. Set in conjunction with the Doorbell Number field. The DMA read channel stops issuing requests,
sets the channel status to "Stopped", and asserts the "Abort" interrupt if it is enabled. Before setting
RD_STOP the Stop bit, you must read the channel Status field (CS) of the "DMA Channel Control 1 Register
" (DMA_CH_CONTROL1_OFF_RDCH_0) to ensure that the read channel is "Running" (transferring
data). For more information, see "Stopping the DMA Transfer (Software Stop)". Note: The access
attributes of this field are as follows: - Wire: R/W
30-3 Reserved
2-0 Doorbell Number

RD_DOORBEL You must write the channel number to this field to start the DMA read transfer for that channel. The DMA
L_NUM detects a write to this register field even if the value of this field does not change. The range of this field is
0–7h, and 0h corresponds to channel 0.
A write to this field triggers the controller to exit L1 substates.
- Wire: R/W
3.11.8.9 DMA read engine channel arbitration weight low (DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF)
Offset
Register Offset
DMA_READ_CHANNEL 38h
_ARB_WEIGHT_LOW_O
FF
Function
The 5-bit channel weight (for read channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for
that channel before it must return to the arbitration routine. When the channel weight count is reached or DMA channel request
transfer size reaches zero, the WWR arbiter selects the next channel to be processed. Your software must initialize this

NXP Semiconductors
PCIe Controller
register before ringing the doorbell. For more details, see "Multichannel Arbitration". Value range is (0-0x1F) corresponding to
(1-32) transaction requests.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
READ_CHANNEL3_WEIGHT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R READ_
READ_CHANNEL2_WEIGHT READ_CHANNEL1_WEIGHT READ_CHANNEL0_WEIGHT
W CH...
Reset 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1
Fields
Field Function
31-20 Reserved
Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used
19-15
by the channel weighted round robin arbiter to select the next channel read request. Note: The access
READ_CHANN attributes of this field are as follows: - Wire: R/W
EL3_WEIGHT
14-10
EL2_WEIGHT
9-5
EL1_WEIGHT
4-0
EL0_WEIGHT
3.11.8.10 DMA Write Interrupt Status (DMA_WRITE_INT_STATUS_OFF)
Offset
Register Offset
DMA_WRITE_INT_STAT 4Ch
US_OFF

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 Reserved
WR_ABORT_INT_STATUS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 Reserved
WR_DONE_INT_STATUS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-24 Reserved
23-20 Reserved
19-16 Abort Interrupt Status

WR_ABORT_IN The DMA write channel has detected an error, or you manually stopped the transfer as described
T_STATUS in "Error Handling Assistance by Remote Software". Each bit corresponds to a DMA channel. Bit [0]
corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The
DMA write interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the
corresponding channel bit in the DMA write interrupt Clear register to clear this interrupt bit. Note: You
can write to this register to emulate interrupt generation, during software or hardware testing. A write to
the address triggers an interrupt, but the DMA does not set the Done or Abort bits in this register. Note:
15-8 Reserved
7-4 Reserved
3-0 Done Interrupt Status

WR_DONE_INT The DMA write channel has successfully completed the DMA transfer. For more details, see "Interrupts
_STATUS and Error Handling". Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. -
Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA write interrupt Mask
register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel
bit in the DMA write interrupt Clear register to clear this interrupt bit. Note: You can write to this register
to emulate interrupt generation, during software or hardware testing. A write to the address triggers an
interrupt, but the DMA does not set the Done or Abort bits in this register. Note: The access attributes of
this field are as follows: - Wire: R/W

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PCIe Controller
3.11.8.11 DMA write interrupt mask (DMA_WRITE_INT_MASK_OFF)
Offset
Register Offset
DMA_WRITE_INT_MAS 54h
K_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reserved WR_ABORT_INT_MASK
W
Reset 0 0 0 0 0 0 0 0 u u u u 1 1 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
Reserved WR_DONE_INT_MASK
W
Reset 0 0 0 0 0 0 0 0 u u u u 1 1 1 1
Fields
Field Function
31-24 Reserved
23-20 Reserved
Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA write interrupt status register
19-16
from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to
WR_ABORT_IN channel 0. Note: The access attributes of this field are as follows: - Wire: R/W
T_MASK
15-8 Reserved
7-4 Reserved
Done Interrupt Mask. Prevents the Done interrupt status field in the DMA write interrupt status register
3-0
WR_DONE_INT channel 0. Note: The access attributes of this field are as follows: - Wire: R/W
_MASK

NXP Semiconductors
PCIe Controller
3.11.8.12 DMA write interrupt clear (DMA_WRITE_INT_CLEAR_OFF)
Offset
Register Offset
DMA_WRITE_INT_CLEA 58h
R_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 WR_ABORT_INT_CLEAR
Reserved
W W1C
Reset 0 0 0 0 0 0 0 0 u u u u 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 WR_DONE_INT_CLEAR
Reserved
W W1C
Reset 0 0 0 0 0 0 0 0 u u u u 0 0 0 0
Fields
Field Function
31-24 Reserved
23-20 Reserved
Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt
19-16
status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0]
WR_ABORT_IN corresponds to channel 0. Note: Reading from this self-clearing register field always returns a "0".
T_CLEAR
15-8 Reserved
7-4 Reserved
Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt
3-0
status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0]
WR_DONE_INT corresponds to channel 0. Note: Reading from this self-clearing register field always returns a "0".
_CLEAR

NXP Semiconductors
PCIe Controller
3.11.8.13 DMA Write Error Status (DMA_WRITE_ERR_STATUS_OFF)
Offset
Register Offset
DMA_WRITE_ERR_STA 5Ch
TUS_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LINKLIST_ELEMENT_FETCH_ER
R 0 0
R_DETE...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 APP_READ_ERR_DETECT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-24 Reserved
23-20 Reserved
19-16 Linked List Element Fetch Error Detected

LINKLIST_ELE The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when
MENT_FETCH_ the AXI Bridge is not used) while reading a linked list element from local memory. Each bit corresponds
ERR_DETECT to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error
Handling". - Masking: The DMA write interrupt Mask register has no effect on this register. - Clearing:
You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Write
Interrupt Clear Register" (DMA_WRITE_INT_CLEAR_OFF) to clear this error bit.
15-8 Reserved
7-4 Reserved
3-0 Application Read Error Detected

NXP Semiconductors
PCIe Controller
Field Function
APP_READ_ER . The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when
R_DETECT the AXI Bridge is not used) while reading data from it. Each bit corresponds to a DMA channel. Bit [0]
corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The
DMA write interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to
the corresponding channel bit in the Abort interrupt field of the "DMA Write Interrupt Clear Register"
(DMA_WRITE_INT_CLEAR_OFF) to clear this error bit.
3.11.8.14 DMA write done IMWr address low (DMA_WRITE_DONE_IMWR_LOW_OFF)
Offset
Register Offset
DMA_WRITE_DONE_IM 60h
WR_LOW_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DMA_WRITE_DONE_LOW_REG
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DMA_WRITE_DONE_LOW_REG
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0]
31-0
must be "00" as this address must be dword aligned. Note: The access attributes of this field are as
DMA_WRITE_D follows: - Wire: R/W
ONE_LOW_RE
G

NXP Semiconductors
PCIe Controller
3.11.8.15 DMA write done IMWr interrupt address high (DMA_WRITE_DONE_IMWR_HIGH_OFF)
Offset
Register Offset
DMA_WRITE_DONE_IM 64h
WR_HIGH_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DMA_WRITE_DONE_HIGH_REG
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DMA_WRITE_DONE_HIGH_REG
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0 The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP. Note: The
access attributes of this field are as follows: - Wire: R/W
DMA_WRITE_D
ONE_HIGH_RE
G
3.11.8.16 DMA write abort IMWr address low (DMA_WRITE_ABORT_IMWR_LOW_OFF)
Offset
Register Offset
DMA_WRITE_ABORT_I 68h
MWR_LOW_OFF

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PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DMA_WRITE_ABORT_LOW_REG
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DMA_WRITE_ABORT_LOW_REG
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP it generates.
31-0
Bits [1:0] must be "00" as this address must be dword aligned. Note: The access attributes of this field
DMA_WRITE_A are as follows: - Wire: R/W
BORT_LOW_R
EG
3.11.8.17 DMA write abort IMWr address high (DMA_WRITE_ABORT_IMWR_HIGH_OFF)
Offset
Register Offset
DMA_WRITE_ABORT_I 6Ch
MWR_HIGH_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DMA_WRITE_ABORT_HIGH_REG
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DMA_WRITE_ABORT_HIGH_REG
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-0 The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP. Note: The
DMA_WRITE_A
BORT_HIGH_R
EG
3.11.8.18 DMA write channel 0 and 1 IMWr data (DMA_WRITE_CH01_IMWR_DATA_OFF)
Offset
Register Offset
DMA_WRITE_CH01_IM 70h
WR_DATA_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
WR_CHANNEL_1_DATA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
WR_CHANNEL_0_DATA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-16 The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write
channel 1. Note: The access attributes of this field are as follows: - Wire: R/W
WR_CHANNEL
_1_DATA
WR_CHANNEL
_0_DATA

NXP Semiconductors
PCIe Controller
3.11.8.19 DMA write channel 2 and 3 IMWr data (DMA_WRITE_CH23_IMWR_DATA_OFF)
Offset
Register Offset
DMA_WRITE_CH23_IM 74h
WR_DATA_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
WR_CHANNEL_3_DATA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
WR_CHANNEL_2_DATA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
WR_CHANNEL
_3_DATA
WR_CHANNEL
_2_DATA
3.11.8.20 DMA write linked list error enable (DMA_WRITE_LINKED_LIST_ERR_EN_OFF)
Offset
Register Offset
DMA_WRITE_LINKED_L 90h
IST_ERR_EN_OFF
Function
The LIE and RIE bits in the LL element enable the channel "done" interrupts (local and remote). The LLLAIE and LLRAIE bits
enable the channel "abort" interrupts (local and remote).

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reserved WR_CHANNEL_LLLAIE
W
Reset 0 0 0 0 0 0 0 0 u u u u 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
Reserved WR_CHANNEL_LLRAIE
W
Reset 0 0 0 0 0 0 0 0 u u u u 0 0 0 0
Fields
Field Function
31-24 Reserved
23-20 Reserved
Write Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the write channel local abort
19-16
interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done
WR_CHANNEL interrupts. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Used in linked
_LLLAIE list mode only. For more details, see "Interrupt Handling". Note: The access attributes of this field are as
15-8 Reserved
7-4 Reserved
Write Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the write channel remote abort
3-0
interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done
WR_CHANNEL interrupts. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Used in linked
_LLRAIE list mode only. For more details, see "Interrupt Handling". Note: The access attributes of this field are as
3.11.8.21 DMA Read Interrupt Status (DMA_READ_INT_STATUS_OFF)
Offset
Register Offset
DMA_READ_INT_STAT A0h
US_OFF

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PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reserved RD_ABORT_INT_STATUS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
Reserved RD_DONE_INT_STATUS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-24 Reserved
23-20 Reserved
19-16 Abort Interrupt Status

RD_ABORT_IN The DMA read channel has detected an error, or you manually stopped the transfer as
T_STATUS described in "Stopping the DMA Transfer (Software Stop)". Each bit corresponds to a DMA
channel. Bit [0] corresponds to channel 0. You can read the "DMA Read Error Status Low
Register" (DMA_READ_ERR_STATUS_LOW_OFF) and "DMA Read Error Status High Register"
(DMA_READ_ERR_STATUS_HIGH_OFF) to determine the source of the error. - Enabling: For details,
see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask register has no effect
on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the DMA read
interrupt Clear register to clear this interrupt bit. Note: You can write to this register to emulate interrupt
generation, during software or hardware testing. A write to the address triggers an interrupt, but the DMA
does not set the Done or Abort bits in this register. Note: The access attributes of this field are as follows:
- Wire: R/W
15-8 Reserved
7-4 Reserved
3-0 Done Interrupt Status

RD_DONE_INT The DMA read channel has successfully completed the DMA read transfer. Each bit corresponds to
_STATUS a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error
Handling". - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing:
You must write a 1'b1 to the corresponding channel bit in the DMA read interrupt Clear register to clear
this interrupt bit. Note: You can write to this register to emulate interrupt generation, during software or
hardware testing. A write to the address triggers an interrupt, but the DMA does not set the Done or
Abort bits in this register. Note: The access attributes of this field are as follows: - Wire: R/W

NXP Semiconductors
PCIe Controller
3.11.8.22 DMA read interrupt mask (DMA_READ_INT_MASK_OFF)
Offset
Register Offset
DMA_READ_INT_MASK A8h
_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reserved RD_ABORT_INT_MASK
W
Reset 0 0 0 0 0 0 0 0 u u u u 1 1 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
Reserved RD_DONE_INT_MASK
W
Reset 0 0 0 0 0 0 0 0 u u u u 1 1 1 1
Fields
Field Function
31-24 Reserved
23-20 Reserved
Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA read interrupt status register
19-16
RD_ABORT_IN channel 0. Note: The access attributes of this field are as follows: - Wire: R/W
T_MASK
15-8 Reserved
7-4 Reserved
Done Interrupt Mask. Prevents the Done interrupt status field in the DMA read interrupt status register
3-0
RD_DONE_INT channel 0. Note: The access attributes of this field are as follows: - Wire: R/W
_MASK

NXP Semiconductors
PCIe Controller
3.11.8.23 DMA Read Interrupt Clear (DMA_READ_INT_CLEAR_OFF)
Offset
Register Offset
DMA_READ_INT_CLEA ACh
R_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W Reserved RD_ABORT_INT_CLEAR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
W Reserved RD_DONE_INT_CLEAR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-24 Reserved
23-20 Reserved
19-16 Abort Interrupt Clear

RD_ABORT_IN You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA read
T_CLEAR interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:
Reading from this self-clearing register field always returns a "0".
15-8 Reserved
7-4 Reserved
3-0 Done Interrupt Clear

RD_DONE_INT You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA read
_CLEAR interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:
Reading from this self-clearing register field always returns a "0".

NXP Semiconductors
PCIe Controller
3.11.8.24 DMA Read Error Status Low (DMA_READ_ERR_STATUS_LOW_OFF)
Offset
Register Offset
DMA_READ_ERR_STAT B4h
US_LOW_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LINK_LIST_ELEMENT_FETCH_E
R 0 Reserved
RR_DET...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 Reserved APP_WR_ERR_DETECT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-24 Reserved
23-20 Reserved
19-16 Linked List Element Fetch Error Detected

LINK_LIST_ELE - The DMA read channel has received an error response from the AXI bus while reading a linked list
MENT_FETCH_ element from local memory. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0.
ERR_DETECT - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask
register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit
in the Abort interrupt field of the "DMA Read Interrupt Clear Register" (DMA_READ_INT_CLEAR_OFF)
to clear this error bit. Note, this clears all bits in this register, and also the DMA Read Error Status High
register (DMA_READ_ERR_STATUS_HIGH_OFF).
15-8 Reserved
7-4 Reserved

NXP Semiconductors
PCIe Controller
Field Function
3-0 Application Write Error Detected

APP_WR_ERR The DMA read channel has received an error response from the AXI bus (or TRGT1 interface when the
_DETECT AXI Bridge is not used) while writing data to it. This error is fatal. You must restart the transfer from the
beginning, as the channel context is corrupted, and the transfer is not rolled back. For more details, see
"Linked List Mode". Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling:
For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask register has
no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort
interrupt field of the "DMA Read Interrupt Clear Register" (DMA_READ_INT_CLEAR_OFF) to clear this
error bit. Note, this clears all bits in this register, and also the DMA Read Error Status High register
(DMA_READ_ERR_STATUS_HIGH_OFF).
3.11.8.25 DMA Read Error Status High (DMA_READ_ERR_STATUS_HIGH_OFF)
Offset
Register Offset
DMA_READ_ERR_STAT B8h
US_HIGH_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R Reserved DATA_POISIONING Reserved CPL_TIMEOUT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserved CPL_ABORT Reserved UNSUPPORTED_REQ
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-28 Reserved
27-24 Data Poisoning

DATA_POISIO The DMA read channel has detected data poisoning in the completion from the remote device (in
NING response to the MRd request). The DMA read channel will drop the completion and then be halted.

NXP Semiconductors
PCIe Controller
Field Function
The CX_FLT_MASK_UR_POIS filter rule does not affect this behavior. Each bit corresponds to a DMA
channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling".
- Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must
write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear
Register" (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this also clears the other error bits
for the same channel in this register and in the DMA Read Error Status Low register.
23-20 Reserved
19-16 Completion Time Out

CPL_TIMEOUT The DMA read channel has timed-out while waiting for the remote device to respond to the MRd request,
or a malformed CplD has been received. For more details, see "Linked List Mode". Each bit corresponds
to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error
Handling" . - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing:
You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Read
Interrupt Clear Register" (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this also clears the
other error bits for the same channel in this register and in the DMA Read Error Status Low register.
15-12 Reserved
11-8 Completer Abort

CPL_ABORT The DMA read channel has received a PCIe completer abort completion status from the remote device in
response to the MRd request. For more details, see "Linked List Mode". Each bit corresponds to a DMA
channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error Handling".
- Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing: You must
write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear
Register" (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this also clears the other error bits
for the same channel in this register and in the DMA Read Error Status Low register.
7-4 Reserved
3-0 Unsupported Request

UNSUPPORTE The DMA read channel has received a PCIe unsupported request completion status from the remote
D_REQ device in response to the MRd request. For more details, see "Linked List Mode". Each bit corresponds
to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and Error
Handling". - Masking: The DMA read interrupt Mask register has no effect on this register. - Clearing:
You must write a 1'b1 to the corresponding channel bit in the Abort interrupt field of the "DMA Read
Interrupt Clear Register" (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this also clears the
other error bits for the same channel in this register and in the DMA Read Error Status Low register.

NXP Semiconductors
PCIe Controller
3.11.8.26 DMA read linked list error enable (DMA_READ_LINKED_LIST_ERR_EN_OFF)
Offset
Register Offset
DMA_READ_LINKED_LI C4h
ST_ERR_EN_OFF
Function
The LIE and RIE bits in the LL element enable the channel "done" interrupts (local and remote). The LLLAIE and LLRAIE bits
enable the channel "abort" interrupts (local and remote).
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reserved RD_CHANNEL_LLLAIE
W
Reset 0 0 0 0 0 0 0 0 u u u u 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
Reserved RD_CHANNEL_LLRAIE
W
Reset 0 0 0 0 0 0 0 0 u u u u 0 0 0 0
Fields
Field Function
31-24 Reserved
23-20 Reserved
Read Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the read channel Local Abort
19-16
interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done
RD_CHANNEL_ interrupts. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Used in linked
LLLAIE list mode only. For more details, see "Interrupt Handling". Note: The access attributes of this field are as
15-8 Reserved
7-4 Reserved

NXP Semiconductors
PCIe Controller
Field Function
Read Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the read channel Remote
3-0
Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done
RD_CHANNEL_ interrupts. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Used in linked list
LLRAIE mode only. For more details, see "Interrupt Handling". Note: The access attributes of this field are as
3.11.8.27 DMA read done IMWr address low (DMA_READ_DONE_IMWR_LOW_OFF)
Offset
Register Offset
DMA_READ_DONE_IM CCh
WR_LOW_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DMA_READ_DONE_LOW_REG
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DMA_READ_DONE_LOW_REG
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0]
31-0
must be "00" as this address must be dword aligned. Note: The access attributes of this field are as
DMA_READ_D follows: - Wire: R/W
ONE_LOW_RE
G
3.11.8.28 DMA read done IMWr address high (DMA_READ_DONE_IMWR_HIGH_OFF)
Offset
Register Offset
DMA_READ_DONE_IM D0h
WR_HIGH_OFF

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DMA_READ_DONE_HIGH_REG
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DMA_READ_DONE_HIGH_REG
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0 The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP. Note: The
DMA_READ_D
ONE_HIGH_RE
G
3.11.8.29 DMA Read Abort IMWr Address Low (DMA_READ_ABORT_IMWR_LOW_OFF)
Offset
Register Offset
DMA_READ_ABORT_IM D4h
WR_LOW_OFF
Function
Helps the DMA generate the address field for the Abort IMWr TLP.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DMA_READ_ABORT_LOW_REG
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DMA_READ_ABORT_LOW_REG
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NXP Semiconductors
PCIe Controller
Fields
Field Function
31-0 DMA Read Abort Low

DMA_READ_A The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP. Bits [1:0] must
BORT_LOW_R be "00" as this address must be dword aligned.
EG
- Wire: R/W
3.11.8.30 DMA Read Abort IMWr Address High (DMA_READ_ABORT_IMWR_HIGH_OFF)
Offset
Register Offset
DMA_READ_ABORT_IM D8h
WR_HIGH_OFF
Function
Helps the DMA generate the address field for the Abort IMWr TLP.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DMA_READ_ABORT_HIGH_REG
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DMA_READ_ABORT_HIGH_REG
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0 DMA Read Abort High

DMA_READ_A The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP.
BORT_HIGH_R
EG
- Wire: R/W

NXP Semiconductors
PCIe Controller
3.11.8.31 DMA Read Channel 0 And 1 IMWr Data (DMA_READ_CH01_IMWR_DATA_OFF)
Offset
Register Offset
DMA_READ_CH01_IMW DCh
R_DATA_OFF
Function
Helps the DMA generate the data field for the Done or Abort IMWr TLPs on read channels 0 and 1.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
RD_CHANNEL_1_DATA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
RD_CHANNEL_0_DATA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-16 Read Channel 1 Data

RD_CHANNEL_ The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read
1_DATA channel 1.
- Wire: R/W

0_DATA channel 0.
- Wire: R/W

NXP Semiconductors
PCIe Controller
3.11.8.32 DMA Read Channel 2 And 3 IMWr Data (DMA_READ_CH23_IMWR_DATA_OFF)
Offset
Register Offset
DMA_READ_CH23_IMW E0h
R_DATA_OFF
Function
Helps the DMA generate the data field for the Done or Abort IMWr TLPs on read channels 2 and 3.
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
RD_CHANNEL_3_DATA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
RD_CHANNEL_2_DATA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function

3_DATA channel 3.
- Wire: R/W

2_DATA channel 2.
- Wire: R/W

NXP Semiconductors
PCIe Controller
3.11.8.33 DMA write engine handshake counter channel 0/1/2/3

(DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF)
Offset
Register Offset
DMA_WRITE_ENGINE_ 108h
HSHAKE_CNT_LOW_O
FF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMA_WRITE_ENGINE_HSHAKE_CNT_CH DMA_WRITE_ENGINE_HSHAKE_CNT_CH
R 0 0
3 2
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMA_WRITE_ENGINE_HSHAKE_CNT_CH DMA_WRITE_ENGINE_HSHAKE_CNT_CH
R 0 0
1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-29 Reserved
28-24 DMA handshake counter for DMA Write Engine Channel 3. If CC_DMA_HSHAKE =1, the data transfer in
Linked List mode starts only when the counter is non-zero.
DMA_WRITE_E
NGINE_HSHAK
E_CNT_CH3
23-21 Reserved
DMA_WRITE_E
NGINE_HSHAK
E_CNT_CH2
15-13 Reserved

NXP Semiconductors
PCIe Controller
Field Function
DMA_WRITE_E
NGINE_HSHAK
E_CNT_CH1
7-5 Reserved
DMA_WRITE_E
NGINE_HSHAK
E_CNT_CH0
3.11.8.34 DMA read engine handshake counter channel 0/1/2/3

(DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF)
Offset
Register Offset
DMA_READ_ENGINE_H 118h
SHAKE_CNT_LOW_OFF
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 DMA_READ_ENGINE_HSHAKE_CNT_CH3 0 DMA_READ_ENGINE_HSHAKE_CNT_CH2
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 DMA_READ_ENGINE_HSHAKE_CNT_CH1 0 DMA_READ_ENGINE_HSHAKE_CNT_CH0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-29 Reserved

NXP Semiconductors
PCIe Controller
Field Function
28-24 DMA handshake counter for DMA Read Engine Channel 3. If CC_DMA_HSHAKE =1, the data transfer in
DMA_READ_E
NGINE_HSHAK
E_CNT_CH3
23-21 Reserved
DMA_READ_E
NGINE_HSHAK
E_CNT_CH2
15-13 Reserved
DMA_READ_E
NGINE_HSHAK
E_CNT_CH1
7-5 Reserved
DMA_READ_E
NGINE_HSHAK
E_CNT_CH0
3.11.8.35 DMA Write Channel Control (DMA_CH_CONTROL1_OFF_WRCH_0 -

DMA_CH_CONTROL1_OFF_WRCH_3)
Offset
Register Offset
DMA_CH_CONTROL1_ 200h
OFF_WRCH_0
OFF_WRCH_1
OFF_WRCH_2
OFF_WRCH_3

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R DMA_ DMA_ DMA_ DMA_ DMA_

DMA_AT DMA_TC DMA_RESERVED2
W RES... RO NS_... NS_... FUN...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DMA_RESERV DMA_ CS
DMA_FUNC_NUM LLE CCS RIE LIE LLP TCB CB
W ED1 RES...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-30 Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating
MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W
DMA_AT
29-27 Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not
IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W
DMA_TC
26 Reserved Note: The access attributes of this field are as follows: - Wire: R/W
DMA_RESERV
ED5
25 Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr
(not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W
DMA_RO
Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when
24
generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field
DMA_NS_SRC are as follows: - Wire: R/W
23 Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when
generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are
DMA_NS_DST as follows: - Wire: R/W
22-17 Reserved Note: The access attributes of this field are as follows: - Wire: R/W
DMA_RESERV
ED2
Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr
16-12
DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in
DMA_FUNC_N the "DMA Write Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_WRCH_0). Note: The access
UM attributes of this field are as follows: - Wire: R/W
DMA_RESERV
ED1

NXP Semiconductors
PCIe Controller
Field Function
9 Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The
LLE
8 Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer
(software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer
CCS Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation. Note:
DMA_RESERV
ED0
6-5 Channel Status (CS). The channel status bits identify the current operational state of the DMA channel.
The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This
CS channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA
has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you
have prematurely stopped this channel by writing to the Stop field of the "DMA Write Doorbell Register"
(DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).
4 Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort
Remote interrupts. For more details, see "Interrupts and Error Handling". In LL mode, the DMA
RIE overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done
interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts. This field is not defined in a
link LL element. Note: The access attributes of this field are as follows: - Wire: R/W
3 Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local
interrupts. For more details, see "Interrupts and Error Handling". In LL mode, the DMA overwrites this
LIE with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL
mode, the LIE bit enables the Done and Abort interrupts. This field is not defined in a link LL element.
Note: The access attributes of this field are as follows: - Wire: R/W
2 Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link
element, and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA
LLP loads this field with the LLP of the linked list element. Note: The access attributes of this field are as
1 Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list
mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details,
TCB see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". The DMA loads this field with the TCB of
the linked list element. this field is not defined in a data LL element. Note: The access attributes of this
0 Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the
consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". The
CB DMA loads this field with the CB of the linked list element. Note: The access attributes of this field are as

NXP Semiconductors
PCIe Controller
3.11.8.36 DMA write transfer size (DMA_TRANSFER_SIZE_OFF_WRCH_0 -

DMA_TRANSFER_SIZE_OFF_WRCH_3)
Offset
Register Offset
DMA_TRANSFER_SIZE 208h
_OFF_WRCH_0
_OFF_WRCH_1
_OFF_WRCH_2
_OFF_WRCH_3
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DMA_TRANSFER_SIZE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DMA_TRANSFER_SIZE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA
31-0
transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically
DMA_TRANSF decremented by the DMA as the DMA write channel transfer progresses. This field indicates the number
ER_SIZE bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size
is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.
You can read this register to monitor the transfer progress, however in some scenarios this register is
updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated
only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode). Note: The

NXP Semiconductors
PCIe Controller
3.11.8.37 DMA Write SAR Low (DMA_SAR_LOW_OFF_WRCH_0 - DMA_SAR_LOW_OFF_WRCH_3)
Offset
Register Offset
DMA_SAR_LOW_OFF_ 20Ch
WRCH_0
WRCH_1
WRCH_2
WRCH_3
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
SRC_ADDR_REG_LOW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
SRC_ADDR_REG_LOW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0 Source Address (Lower 32 Bits)

SRC_ADDR_R Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses.
EG_LOW In LL mode, the DMA overwrites this with the corresponding dword of the LL element.
DMA Write: The SAR is the address of the local memory.
- Wire: R/W

NXP Semiconductors
PCIe Controller
3.11.8.38 DMA write SAR high (DMA_SAR_HIGH_OFF_WRCH_0 - DMA_SAR_HIGH_OFF_WRCH_3)
Offset
Register Offset
DMA_SAR_HIGH_OFF_ 210h
WRCH_0
WRCH_1
WRCH_2
WRCH_3
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
SRC_ADDR_REG_HIGH
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
SRC_ADDR_REG_HIGH
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0 Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding
dword of the LL element. Note: The access attributes of this field are as follows: - Wire: R/W
SRC_ADDR_R
EG_HIGH
3.11.8.39 DMA Write DAR Low (DMA_DAR_LOW_OFF_WRCH_0 - DMA_DAR_LOW_OFF_WRCH_3)
Offset
Register Offset
DMA_DAR_LOW_OFF_ 214h
WRCH_0
WRCH_1

NXP Semiconductors
PCIe Controller
Register Offset
WRCH_2
WRCH_3
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DST_ADDR_REG_LOW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DST_ADDR_REG_LOW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0 Destination Address (Lower 32 bits)

DST_ADDR_RE Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses.
G_LOW In LL mode, the DMA overwrites this with the corresponding dword of the LL element.
DMA Write: The DAR is the address of the remote memory.
- Wire: R/W
3.11.8.40 DMA write DAR high (DMA_DAR_HIGH_OFF_WRCH_0 - DMA_DAR_HIGH_OFF_WRCH_3)
Offset
Register Offset
DMA_DAR_HIGH_OFF_ 218h
WRCH_0
WRCH_1
WRCH_2

NXP Semiconductors
PCIe Controller
Register Offset
WRCH_3
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DST_ADDR_REG_HIGH
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DST_ADDR_REG_HIGH
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the
31-0
corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire:
DST_ADDR_RE R/W
G_HIGH
3.11.8.41 DMA write linked list pointer low (DMA_LLP_LOW_OFF_WRCH_0 - DMA_LLP_LOW_OFF_WRCH_3)
Offset
Register Offset
DMA_LLP_LOW_OFF_W 21Ch
RCH_0
RCH_1
RCH_2
RCH_3

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
LLP_LOW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
LLP_LOW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0 Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only.
Updated by the DMA to point to the next element in the transfer list after the previous element is
LLP_LOW consumed. - When the current element is a data element; this field is incremented by 6. - When the
current element is a link element; this field is overwritten by the LL Element Pointer of the element. Note:
3.11.8.42 DMA write linked list pointer high (DMA_LLP_HIGH_OFF_WRCH_0 -

DMA_LLP_HIGH_OFF_WRCH_3)
Offset
Register Offset
DMA_LLP_HIGH_OFF_ 220h
WRCH_0
WRCH_1
WRCH_2
WRCH_3

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
LLP_HIGH
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
LLP_HIGH
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0 Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only.
Updated by the DMA to point to the next element in the transfer list as elements are consumed. Note:
LLP_HIGH The access attributes of this field are as follows: - Wire: R/W
3.11.8.43 DMA Read Channel Control (DMA_CH_CONTROL1_OFF_RDCH_0 -

DMA_CH_CONTROL1_OFF_RDCH_3)
Offset
Register Offset
OFF_RDCH_0
OFF_RDCH_1
OFF_RDCH_2
OFF_RDCH_3

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R DMA_ DMA_ DMA_ DMA_ DMA_

DMA_AT DMA_TC DMA_RESERVED2
W RES... RO NS_... NS_... FUN...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DMA_RESERV DMA_ CS
DMA_FUNC_NUM LLE CCS RIE LIE LLP TCB CB
W ED1 RES...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-30 Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating
MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W
DMA_AT
29-27 Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not
IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W
DMA_TC
DMA_RESERV
ED5
25 Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr
(not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: R/W
DMA_RO
Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when
24
generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field
DMA_NS_SRC are as follows: - Wire: R/W
23 Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when
generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are
DMA_NS_DST as follows: - Wire: R/W
DMA_RESERV
ED2
Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr
16-12
DMA TLP. When you have enabled SR-IOV, then this field is ignored if you have set the VFE field in
DMA_FUNC_N the "DMA Read Channel Control 2 Register" (DMA_CH_CONTROL2_OFF_RDCH_0). Note: The access
UM attributes of this field are as follows: - Wire: R/W
DMA_RESERV
ED1

NXP Semiconductors
PCIe Controller
Field Function
9 Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The
LLE
8 Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer
(software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer
CCS Synchronization". You must initialize this bit. The DMA updates this bit during linked list operation. Note:
DMA_RESERV
ED0
6-5 Channel Status (CS). The channel status bits identify the current operational state of the DMA channel.
The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This
CS channel is active and transferring data. - 10: Halted. An error condition has been detected, and the DMA
has stopped this channel. - 11: Stopped. The DMA has transferred all data for this channel, or you
have prematurely stopped this channel by writing to the Stop field of the "DMA Read Doorbell Register"
(DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell Register" (DMA_READ_DOORBELL_OFF).
4 Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort
Remote interrupts. For more details, see "Interrupts and Error Handling". In LL mode, the DMA
RIE overwrites this with the RIE of the LL element. The RIE bit in a LL element only enables the Done
interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts. This field is not defined in a
link LL element. Note: The access attributes of this field are as follows: - Wire: R/W
3 Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local
interrupts. For more details, see "Interrupts and Error Handling". In LL mode, the DMA overwrites this
LIE with the LIE of the LL element. The LIE bit in a LL element only enables the Done interrupt. In non-LL
mode, the LIE bit enables the Done and Abort interrupts. This field is not defined in a link LL element.
Note: The access attributes of this field are as follows: - Wire: R/W
2 Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link
element, and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA
LLP loads this field with the LLP of the linked list element. Note: The access attributes of this field are as
1 Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list
mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details,
TCB see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". The DMA loads this field with the TCB of
the linked list element. this field is not defined in a data LL element. Note: The access attributes of this
0 Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the
consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". The
CB DMA loads this field with the CB of the linked list element. Note: The access attributes of this field are as

NXP Semiconductors
PCIe Controller
3.11.8.44 DMA read transfer size (DMA_TRANSFER_SIZE_OFF_RDCH_0 -

DMA_TRANSFER_SIZE_OFF_RDCH_3)
Offset
Register Offset
_OFF_RDCH_0
_OFF_RDCH_1
_OFF_RDCH_2
_OFF_RDCH_3
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DMA_TRANSFER_SIZE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DMA_TRANSFER_SIZE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA
31-0
transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically
DMA_TRANSF decremented by the DMA as the DMA read channel transfer progresses. This field indicates the number
ER_SIZE bytes remaining to be transferred. When all bytes are successfully transferred the current transfer size
is zero. In LL mode, the DMA overwrites this register with the corresponding dword of the LL element.
You can read this register to monitor the transfer progress, however in some scenarios this register is
updated after a delay. For example, when less than 3 channels are doorbelled, this register is updated
only after a descriptor finishes(linked list mode), or the transfer ends (non-linked list mode). Note: The

NXP Semiconductors
PCIe Controller
3.11.8.45 DMA Read SAR Low (DMA_SAR_LOW_OFF_RDCH_0 - DMA_SAR_LOW_OFF_RDCH_3)
Offset
Register Offset
RDCH_0
RDCH_1
RDCH_2
RDCH_3
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
SRC_ADDR_REG_LOW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
SRC_ADDR_REG_LOW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0 Source Address Register (Lower 32 Bits)

SRC_ADDR_R Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses.
EG_LOW In LL mode, the DMA overwrites this with the corresponding dword of the LL element.
For DMA reads, the SAR is the address of the remote memory.
- Wire: R/W

NXP Semiconductors
PCIe Controller
3.11.8.46 DMA read SAR high (DMA_SAR_HIGH_OFF_RDCH_0 - DMA_SAR_HIGH_OFF_RDCH_3)
Offset
Register Offset
RDCH_0
RDCH_1
RDCH_2
RDCH_3
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
SRC_ADDR_REG_HIGH
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
SRC_ADDR_REG_HIGH
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0 Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the corresponding
dword of the LL element. Note: The access attributes of this field are as follows: - Wire: R/W
SRC_ADDR_R
EG_HIGH
3.11.8.47 DMA Read DAR Low (DMA_DAR_LOW_OFF_RDCH_0 - DMA_DAR_LOW_OFF_RDCH_3)
Offset
Register Offset
RDCH_0
RDCH_1

NXP Semiconductors
PCIe Controller
Register Offset
RDCH_2
RDCH_3
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DST_ADDR_REG_LOW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DST_ADDR_REG_LOW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0 Destination Address (Lower 32 Bits)

DST_ADDR_RE Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses.
G_LOW In LL mode, the DMA overwrites this with the corresponding dword of the LL element.
For DMA reads, the DAR is the address of the local memory.
- Wire: R/W
3.11.8.48 DMA read DAR high (DMA_DAR_HIGH_OFF_RDCH_0 - DMA_DAR_HIGH_OFF_RDCH_3)
Offset
Register Offset
RDCH_0
RDCH_1
RDCH_2

NXP Semiconductors
PCIe Controller
Register Offset
RDCH_3
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DST_ADDR_REG_HIGH
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DST_ADDR_REG_HIGH
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
Destination Address Register (Higher 32 bits). In LL mode, the DMA overwrites this with the
31-0
corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire:
DST_ADDR_RE R/W
G_HIGH
3.11.8.49 DMA Read Linked List Pointer Low (DMA_LLP_LOW_OFF_RDCH_0 -

DMA_LLP_LOW_OFF_RDCH_3)
Offset
Register Offset
DMA_LLP_LOW_OFF_R 31Ch
DCH_0
DCH_1
DCH_2
DCH_3

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
LLP_LOW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
LLP_LOW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0 Lower Bits

LLP_LOW Contains the lower bits of the address of the linked list transfer list in local memory. Used in linked list
mode only. Updated by the DMA to point to the next element in the transfer list after the previous element
is consumed.
When the current element is a data element, this field increments by 6.
When the current element is a link element, this field is overwritten by the LL Element Pointer of the element.
- Wire: R/W
3.11.8.50 DMA Read Linked List Pointer High (DMA_LLP_HIGH_OFF_RDCH_0 -

DMA_LLP_HIGH_OFF_RDCH_3)
Offset
Register Offset
DMA_LLP_HIGH_OFF_R 320h
DCH_0
DCH_1
DCH_2
DCH_3

NXP Semiconductors
PCIe Controller
Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
LLP_HIGH
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
LLP_HIGH
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
31-0 Upper Bits

LLP_HIGH Contains the upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list
mode only. Updated by the DMA to point to the next element in the transfer list as elements are consumed.
- Wire: R/W

NXP Semiconductors
Chapter 4
PHY
PHY provides SerDes lanes to support both the PCIe and Ethernet-related functionality described in Introduction to
the Subsystem.
4.1 PHY features

• Register-based control of all PCS-to-PMA signals
• Adaptive and configurable RX continuous time linear equalizer (CTLE) and decision feedback equalizer (DFE)
• Programmable TX equalization
• Supports PCIe power gating to further reduce L1-substate power consumption
• IEEE 1149.1 and 1149.6 (AC JTAG) boundary scan
• Built-in Self-Test (BIST) features for production
• Advanced, built-in diagnostics including on-chip sampling scope
• Two PLL modules (MPLLA and MPLLB)
• Configurable PCS with extensive debug options:
— Independent TX and RX control per lane
— Configurable TX and RX power modes
— Pseudo-random bit sequence (PRBS) generation and checker (PRBS31, PRBS23, PRBS16, PRBS15, PRBS11,
PRBS9, PRBS7)
— Programmable 10-bit pattern generation with error injection capability
• Meets the following specifications:
— PCI Express Base Specification, Revision 3.1, November 2013
— Serial Gigabit Media Independent Interface (SGMII) Specification, ENG-46158, Revision 1.8, November 2005
4.2 Interfaces
The PHY can connect to low-voltage differential signaling (LVDS) and current-mode logic (CML) interfaces. If you need these, your
interface must support AC coupling.
4.3 Approximating low-swing operation

The SerDes PHY only supports transmitter full-swing operation as allowed by version 4.3 of the PHY Interface For the PCI
Express, SATA, and USB 3.0 Architectures (PIPE) specification. Because the SerDes PHY supports all the required transmitter
margin settings defined in that specification, you can approximate PHY transmitter low-swing operation by writing 3h to the
PCIE_CAP_TX_MARGIN field in the following registers:
• Link Control 2 And Status 2 (LINK_CONTROL2_LINK_STATUS2_REG) for EP mode
• Link Control 2 and Status 2 (LINK_CONTROL2_LINK_STATUS2_REG) for RC mode
Here is a code example for low-swing operation:
PCIE_RC.GEN2_CTRL_OFF.B.CONFIG_PHY_TX_CHANGE = 1;
PCIE_RC.LINK_CONTROL2_LINK_STATUS2_REG.B.PCIE_CAP_TX_MARGIN = 0x3;

NXP Semiconductors
PHY
4.4 Code examples
4.4.1 PLL bandwidth updates for PCIe applications (PCIe_0 use case)
The PHY PLL bandwidth settings require the following update to optimize performance for PCIe applications.
SERDES_SS.SS_RW_REG_0.B.PHY0_CR_PARA_SEL = 0x1; //Enable CR access to PHY register

SERDES_SS.PHY_REG_ADDR.B.PHY_REG_EN = 0x1; //Enable PHY register write
SERDES_SS.PHY_REG_ADDR.B.ADDR = 0x2005; // MPLLB Overrides
SERDES_SS.PHY_REG_DATA.B.DATA = 0xDA; // 218
SERDES_SS.PHY_REG_ADDR.B.ADDR = 0x2004;
SERDES_SS.PHY_REG_DATA.B.DATA = 0x0400; //override enable
SERDES_SS.PHY_REG_ADDR.B.ADDR = 0x2002; // MPLLA Overrides
SERDES_SS.PHY_REG_DATA.B.DATA = 0xC5; // 197 -
SERDES_SS.PHY_REG_ADDR.B.ADDR = 0x2001;
SERDES_SS.PHY_REG_DATA.B.DATA = 0x0400; //override enable
4.4.2 PHY receiver fixed equalization IQ tuning for PCIe Gen3 long and short channel cases
This code example applies only to chips that include two instances of the SerDes subsystem and therefore have PCIe_1.

//DELTA_IQ_OVRD_IN enable and overrides
SERDES_SS_PCIE_1.PHY_REG_ADDR.B.ADDR = 0x3119;
delay(100);
SERDES_SS_PCIE_1.PHY_REG_DATA.B.DATA = 0x03;
delay(100);
SERDES_SS_PCIE_1.PHY_REG_ADDR.B.ADDR = 0x3119;
delay(100);
SERDES_SS_PCIE_1.PHY_REG_DATA.B.DATA = 0x13;
delay(100);
4.4.3 Refining PHY transmitter settings

This section outlines optional steps to refine PHY transmitter settings if the default settings aren’t ideal for your hardware board.
The examples are for PCIe_0.
The following code example is for TERM_CTRL = 4. It shows how you can adjust termination control and restart
termination calibration.

SERDES_SS.PHY_REG_ADDR.B.ADDR = 0x61; //SUP_DIG_RTUNE_CONFIG
SERDES_SS.PHY_REG_DATA.B.DATA = 0x24; // Enable TX_CAL_EN and set TERM_CTRL = 4
delay(10000);
SERDES_SS.PHY_REG_ADDR.B.ADDR = 0x200a; //RAWCMN_DIG_CMN_CTL_1
SERDES_SS.PHY_REG_DATA.B.DATA = 0x20; // Enable RTUNE_REQ_OVRD
delay(10000);
SERDES_SS.PHY_REG_DATA.B.DATA = 0x30; // RTUNE_REQ_OVRD value

NXP Semiconductors
PHY
delay(10000);
SERDES_SS.PHY_REG_ADDR.B.ADDR = 0x19; //SUP_DIG_ASIC_IN
while(SERDES_SS.PHY_REG_DATA.B.DATA == 0x201a); // wait RTUNE_ACK = 1
delay(10000);
SERDES_SS.PHY_REG_DATA.B.DATA = 0x20; // RTUNE_REQ_OVRD value
The following code example is for VBOOST_CTRL = 5. It shows how you can adjust the transmitter VBOOST level.

SERDES_SS.PHY_REG_ADDR.B.ADDR = 0xf; //SUP_DIG_LVL_OVRD_IN register
SERDES_SS.PHY_REG_DATA.B.DATA = 0x2F1; //Enable override value for tx_vboost_lvl
SERDES_SS.PHY_REG_ADDR.B.ADDR = 0xf; //SUP_DIG_LVL_OVRD_IN register
SERDES_SS.PHY_REG_DATA.B.DATA = 0x371; //set tx_vboost_lvl to 5; 371 = 5
4.5 Accessing PHY registers

The PHY registers are not memory-mapped. Use the following procedure to access them.
Table 75. Procedure for accessing PHY registers
Step Action
1 Write 1 to SS_RW_REG_0[PHY0_CR_PARA_SEL].
2 Write 1 to PHY_REG_ADDR[PHY_REG_EN].
3 Use this chapter to locate the index of the PHY register you wish to access.
4 Write this index to PHY_REG_ADDR[ADDR].
5 Read or write PHY_REG_DATA[DATA] to obtain the result of the PHY register access.
For example, to access SUP_DIG_LVL_OVRD_IN, you would:

1. Write 1 to SS_RW_REG_0[PHY0_CR_PARA_SEL]
2. Write 1 to PHY_REG_ADDR[PHY_REG_EN]
3. Use this chapter to determine that the index of SUP_DIG_LVL_OVRD_IN is Fh
4. Write Fh to PHY_REG_ADDR[ADDR]
5. Read or write PHY_REG_DATA[DATA] for the results of accessing SUP_DIG_LVL_OVRD_IN
4.6 SerDes_PHY register descriptions

This section presents the PHY registers.†
These registers are not memory-mapped, and require a special procedure to access them. See Accessing PHY registers for
this procedure.

NXP Semiconductors
PHY
4.6.1 PHY Indices
Index Register Width Access Reset value
(In bits)
Fh Override Values For Level Settings (SUP_DIG_LVL_OVRD_IN) 16 RW See

description
19h Current values for incoming SUP control signals from ASIC 16 RO See
(SUP_DIG_ASIC_IN) description
61h Configure Rtune Operation (SUP_DIG_RTUNE_CONFIG) 16 RW See

description
67h TX-DN Resistor Tuning Register Status 16 RO See

(SUP_DIG_RTUNE_TXDN_STAT) description
68h TX-UP Resistor Tuning Register Status 16 RO See

(SUP_DIG_RTUNE_TXUP_STAT) description
2001h Override values for incoming MPLLA signals 16 RW See

(RAWCMN_DIG_MPLLA_OVRD_IN) description
2002h Override values for incoming MPLLA bandwidth 16 RW 0043h

(RAWCMN_DIG_MPLLA_BW_OVRD_IN)
2004h Override values for incoming MPLLB signals 16 RW See

(RAWCMN_DIG_MPLLB_OVRD_IN) description
2005h Override values for incoming MPLLB bandwidth 16 RW 0043h

(RAWCMN_DIG_MPLLB_BW_OVRD_IN)
200Ah Common Control 1 (RAWCMN_DIG_CMN_CTL_1) 16 RW See

description
3019h Override incoming values for rx_eq_delta_iq 16 RW See

(RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN) description
3119h Override Incoming Values For rx_eq_delta_iq 16 RW See

(RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN) description
4.6.2 Override Values For Level Settings (SUP_DIG_LVL_OVRD_IN)
Index
Register Index
SUP_DIG_LVL_OVRD_I Fh
N

NXP Semiconductors
PHY
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserved TX_VB RX_VR

TX_VBOOST_LVL RX_VREF_CTRL
W OO... EF...
Reset u u u u u u 0 1 1 1 0 1 0 0 0 0
Fields
Field Function
15-10 Reserved
9 Enable Override Value For tx_vboost_lvl
TX_VBOOST_L
VL_EN
8-6 Override Value For tx_vboost_lvl
TX_VBOOST_L
VL
5 Enable Override Value For rx_vref_ctrl
RX_VREF_CTR
L_EN
4-0 Override Value For rx_vref_ctrl
RX_VREF_CTR
L
4.6.3 Current values for incoming SUP control signals from ASIC (SUP_DIG_ASIC_IN)
Index
Register Index
SUP_DIG_ASIC_IN 19h

NXP Semiconductors
PHY
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEST_ MPLL MPLL RES_ RES_ RES_ RES_ RTUN RTUN TEST_ TEST_ REF_ REF_ REF_ REF_ PHY_
R
TX... B_S... A_S... ACK... ACK... REQ... REQ... E_A... E_R... PO... BU... USE... REP... CLK... CLK... RES...
Fields
Field Function
15 Value From ASIC For test_tx_refclk_en
TEST_TX_REF
_CLK_EN
14 Value To ASIC For mpllb_state_i
MPLLB_STATE
13 Value To ASIC For mplla_state_i
MPLLA_STATE
12 Value To ASIC For res_ack_out_i
RES_ACK_OUT
11 Value From ASIC For res_req_in
RES_ACK_IN
10 Value To ASIC For res_ack_out_i
RES_REQ_OU
T
9 Value From ASIC For res_req_in
RES_REQ_IN
8 Value To ASIC For rtune_ack_i
RTUNE_ACK
7 Value From ASIC For rtune_req
RTUNE_REQ
6 Value From ASIC For test_powerdown
TEST_POWER
DOWN
5 Value From ASIC For test_burnin
TEST_BURNIN

NXP Semiconductors
PHY
Field Function
4 Value From ASIC For ref_use_pad
REF_USE_PAD
3 Value From ASIC For ref_repeat_clk_en
REF_REPEAT_
CLK_EN
2 Value From ASIC For ref_clk_div2_en
REF_CLK_DIV2
_EN
1 Value From ASIC For ref_clk_en
REF_CLK_EN
0 Value From ASIC For phy_reset
PHY_RESET
4.6.4 Configure Rtune Operation (SUP_DIG_RTUNE_CONFIG)
Index
Register Index
SUP_DIG_RTUNE_CON 61h
FIG
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserved TX_CA FAST_ RX_C

SUP_ANA_TERM_CTRL
W L_... RT... AL_...
Reset u u u u u u u u u u 0 1 0 1 0 1
Fields
Field Function
15-6 Reserved
5-3 Set The Reference Resistor In The Analog

Configures the impedance (in ohms).

NXP Semiconductors
PHY
Field Function
SUP_ANA_TER 000b - 54 Ω
M_CTRL
001b - 52 Ω
010b - 50 Ω (default)
011b - 48 Ω
100b - 46 Ω
101b - 44 Ω
110b - 42 Ω
111b - 40 Ω
2 Enable Calibration Of TX Resistor
TX_CAL_EN
1 Enable Fast Resitor Tuning (Simulation Only)
FAST_RTUNE
0 Enable Calibration Of RX Resistor
RX_CAL_EN
4.6.5 TX-DN Resistor Tuning Register Status (SUP_DIG_RTUNE_TXDN_STAT)
Index
Register Index
SUP_DIG_RTUNE_TXD 67h
N_STAT
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserved TXDN_STAT
Fields
Field Function
15-10 Reserved

NXP Semiconductors
PHY
Field Function
9-0 Current Value Of The TX-DN Resistor Tuning Register
TXDN_STAT
4.6.6 TX-UP Resistor Tuning Register Status (SUP_DIG_RTUNE_TXUP_STAT)
Index
Register Index
SUP_DIG_RTUNE_TXU 68h
P_STAT
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserved TXUP_STAT
Fields
Field Function
15-10 Reserved
9-0 Current Value Of The TX-UP Resistor Tuning Register
TXUP_STAT
4.6.7 Override values for incoming MPLLA signals (RAWCMN_DIG_MPLLA_OVRD_IN)
Index
Register Index
RAWCMN_DIG_MPLLA_ 2001h
OVRD_IN

NXP Semiconductors
PHY
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserved MPLL MPLL MPLL MPLL MPLL MPLL MPLLA_TX_CLK_DIV_O MPLL MPLL
W A_B... A_D... A_D... A_D... A_D... A_T... VRD_V... A_W... A_W...
Reset u u u u u 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
15-11 Reserved
10 Override enable for mplla_bandwidth[15:0]
MPLLA_BW_O
VRD_EN
9 Override enable for mplla_div8_clk_en
MPLLA_DIV8_C
LK_EN_OVRD_
EN
8 Override value for mplla_div8_clk_en
MPLLA_DIV8_C
LK_EN_OVRD_
VAL
7 Override enable for mplla_div10_clk_en
MPLLA_DIV10_
CLK_EN_OVRD
_EN
6 Override value for mplla_div10_clk_en
MPLLA_DIV10_
CLK_EN_OVRD
_VAL
5 Override enable for mplla_tx_clk_div[2:0]
MPLLA_TX_CL
K_DIV_OVRD_
EN
4-2 Override value for mplla_tx_clk_div[2:0]
MPLLA_TX_CL
K_DIV_OVRD_
VAL

NXP Semiconductors
PHY
Field Function
1 Override enable for mplla_word_div2_en
MPLLA_WORD
_DIV2_EN_OV
RD_EN
0 Override value for mplla_word_div2_en
MPLLA_WORD
_DIV2_EN_OV
RD_VAL
4.6.8 Override values for incoming MPLLA bandwidth (RAWCMN_DIG_MPLLA_BW_OVRD_IN)
Index
Register Index
RAWCMN_DIG_MPLLA_ 2002h
BW_OVRD_IN
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MPLLA_BW_OVRD_VAL
W
Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1
Fields
Field Function
15-0 Override value for mplla_bandwidth[15:0]
MPLLA_BW_O
VRD_VAL
4.6.9 Override values for incoming MPLLB signals (RAWCMN_DIG_MPLLB_OVRD_IN)
Index
Register Index
RAWCMN_DIG_MPLLB_ 2004h
OVRD_IN

NXP Semiconductors
PHY
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserved MPLL MPLL MPLL MPLL MPLL MPLL MPLLB_TX_CLK_DIV_O MPLL MPLL
W B_B... B_D... B_D... B_D... B_D... B_T... VRD_V... B_W... B_W...
Reset u u u u u 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
15-11 Reserved
10 Override enable for mpllb_bandwidth[15:0]
MPLLB_BW_O
VRD_EN
9 Override enable for mpllb_div8_clk_en
MPLLB_DIV8_C
LK_EN_OVRD_
EN
8 Override value for mpllb_div8_clk_en
MPLLB_DIV8_C
LK_EN_OVRD_
VAL
7 Override enable for mpllb_div10_clk_en
MPLLB_DIV10_
CLK_EN_OVRD
_EN
6 Override value for mpllb_div10_clk_en
MPLLB_DIV10_
CLK_EN_OVRD
_VAL
5 Override enable for mpllb_tx_clk_div[2:0]
MPLLB_TX_CL
K_DIV_OVRD_
EN
4-2 Override value for mpllb_tx_clk_div[2:0]
MPLLB_TX_CL
K_DIV_OVRD_
VAL

NXP Semiconductors
PHY
Field Function
1 Override enable for mpllb_word_div2_en
MPLLB_WORD
_DIV2_EN_OV
RD_EN
0 Override value for mpllb_word_div2_en
MPLLB_WORD
_DIV2_EN_OV
RD_VAL
4.6.10 Override values for incoming MPLLB bandwidth (RAWCMN_DIG_MPLLB_BW_OVRD_IN)
Index
Register Index
RAWCMN_DIG_MPLLB_ 2005h
BW_OVRD_IN
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MPLLB_BW_OVRD_VAL
W
Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1
Fields
Field Function
15-0 Override value for mpllb_bandwidth[15:0]
MPLLB_BW_O
VRD_VAL
4.6.11 Common Control 1 (RAWCMN_DIG_CMN_CTL_1)
Index
Register Index
RAWCMN_DIG_CMN_C 200Ah
TL_1

NXP Semiconductors
PHY
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserved RTUN RTUN MPLL MPLL MPLL MPLL
W E_R... E_R... B_I... B_I... A_I... A_I...
Reset u u u u u u u u u u 0 0 0 0 0 0
Fields
Field Function
15-6 Reserved
5 Override enable for rtune_req
RTUNE_REQ_
OVRD_EN
4 Override value for rtune_req
RTUNE_REQ_
OVRD_VAL
3 Override enable for mpllb_init_cal_disable
MPLLB_INIT_C
AL_DISABLE_O
VRD_EN
2 Override value for mpllb_init_cal_disable
MPLLB_INIT_C
AL_DISABLE_O
VRD_VAL
1 Override enable for mplla_init_cal_disable
MPLLA_INIT_C
AL_DISABLE_O
VRD_EN
0 Override value for mplla_init_cal_disable
MPLLA_INIT_C
AL_DISABLE_O
VRD_VAL

NXP Semiconductors
PHY
4.6.12 Override incoming values for rx_eq_delta_iq

(RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN)
Index
Register Index
RAWLANE0_DIG_PCS_ 3019h
XF_RX_EQ_DELTA_IQ_
OVRD_IN
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserved RX_E
RX_EQ_DELTA_IQ_OVRD_VAL
W Q_D...
Reset u u u u u u u u u u u 0 0 0 0 0
Fields
Field Function
15-5 Reserved
4 Enable override value for rx_eq_delta_iq
RX_EQ_DELTA
_IQ_OVRD_EN
3-0 Override value for rx_eq_delta_iq
RX_EQ_DELTA
_IQ_OVRD_VA
L
4.6.13 Override Incoming Values For rx_eq_delta_iq

(RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN)
Index
Register Index
RAWLANE1_DIG_PCS_ 3119h
XF_RX_EQ_DELTA_IQ_
OVRD_IN

NXP Semiconductors
PHY
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserved RX_E
RX_EQ_DELTA_IQ_OVRD_VAL
W Q_D...
Reset u u u u u u u u u u u 0 0 0 0 0
Fields
Field Function
15-5 Reserved
4 Enable override value for rx_eq_delta_iq
RX_EQ_DELTA
_IQ_OVRD_EN
3-0 Override value for rx_eq_delta_iq
RX_EQ_DELTA
_IQ_OVRD_VA
L

NXP Semiconductors
Chapter 5
XPCS
XPCS implements a Physical Coding Sublayer (PCS) that provides an interface between the Media Access Control (MAC) and
Physical Medium Attachment Sublayer (PMA) through a GMII interface. This interface is defined for a single lane that operates
at 125 MHz to support 1000BASE-X PMA.
XPCS supports 1000BASE-X and SGMII with Clause 37 auto-negotiation support.
5.1 XPCS features

• System-level features
— 1000BASEX-Only PCS
◦ Vendor-specific MII MMD support (also referred as VS MII B1G MMD in this document)
◦ Clause 37 auto-negotiation support
◦ Optional SGMII support
— Configurable MDIO management interface (as defined in IEEE Std 802.3, Clause 45)
• Energy Efficient Ethernet Support
• Monitoring, test, and debugging support
— Provides the following MDIO Manageable Devices (MMD):
◦ Debug PCS
◦ Auto-negotiation
— Loopback control from the PHY Transmit to the PHY Receive lane
— Various error status signals and statistics for monitoring and debugging
5.2 Accessing XPCS registers

You cannot access XPCS registers directly. Instead, you must use the indirect-addressing method described in this section.
You will need the variables in Table 76 for the procedure in Table 77.
Table 76. Variables required for the indirect-access procedure
Variable Value Example
OFS The offset of the register as shown in the memory VR_MII_DIG_STS of XPCS_0 is at offset 1F_8010h,
map so OFS=1F_8010h.
OFSLEFT The leftmost 4 digits of OFS If OFS=1F_8010h, OFSLEFT=1F80h.
OFSRIGHT The righmost 2 digits of OFS If OFS=1F_8010h, OFSRIGHT=10h.
ADDR1 8_23FCh for XPCS_0 —
8_2BFCh for XPCS_1
DATA1 OFSLEFT —
ADDR2 8_2000h + OFSRIGHT×4h for XPCS_0 VR_MII_DIG_STS of XPCS_1 is at offset 1F_8010h,

so ADDR2 is 8_2840h.
8_2800h + OFSRIGHT×4h for XPCS_1

NXP Semiconductors
XPCS
Table 77. Indirect-access procedure and example
Step Action Example for VR_MII_TC of XPCS_0
1 Calculate all the variables in Table 76. OFS=1F_8003h

OFSLEFT=1F80h
OFSRIGHT=03h
ADDR1=8_23FCh
DATA1=1F80h
ADDR2=8_200Ch
2 Write DATA1 to the address in ADDR1. Write 1F80h to address 8_23FCh.
3 Read or write the desired register data at address ADDR2. Read to, or write from, 8_200Ch.
You may repeat this step if you have multiple reads or writes
from the same register.
5.3 Switching the PHY to 1G speed†

Before beginning the procedure in the following table, ensure that one of the following has occurred:
• You have applied internal or external loopback.
• You have connected an active link partner to the SGMII interface.
Table 78. Switching the PHY to 1G speed
Step Action for 100 MHz reference clock Action for 125 MHz reference clock
2 Write Ch to VR_MII_Gen5_12G_16G_TX_EQ_CTRL0[TX_EQ_MAIN].
3 Write 4h to VR_MII_Consumer_10G_TX_TERM_CTRL[TX0_TERM].

7 In VR MII SPHY Reference In VR MII SPHY Reference

Control (VR_MII_Gen5_12G_16G_REF_CLK_CTRL): Control (VR_MII_Gen5_12G_16G_REF_CLK_CTRL):
• Write 0 to REF_MPLLA_DIV2. • Write 1 to REF_MPLLA_DIV2.
• To use the internal reference clock, write 0 to • To use the internal reference clock, write 0 to
REF_USE_PAD. REF_USE_PAD.
• To use the external reference clock, write 1 to • To use the external reference clock, write 1 to
• Write 011b to REF_RANGE. • Write 010b to REF_RANGE.
• Write 0 to REF_CLK_DIV2. • Write 1 to REF_CLK_DIV2.

NXP Semiconductors
XPCS
Table 78. Switching the PHY to 1G speed (continued)
8 In VR MII PHY MPLLA Control In VR MII PHY MPLLA Control

0 (VR_MII_Gen5_12G_16G_MPLLA_CTRL0): 0 (VR_MII_Gen5_12G_16G_MPLLA_CTRL0):
• Write 0 to MPLLA_CAL_DISABLE. • Write 0 to MPLLA_CAL_DISABLE.
• Write 25d to MLLA_MULTIPLIER. • Write 80d to MLLA_MULTIPLIER.
9 Write 0 to VR_MII_Gen5_12G_MPLLA_CTRL1[MPLLA_FRACN_CTRL].
10 In VR MII PHY MPLLA Control 2 (VR_MII_Gen5_12G_16G_MPLLA_CTRL2):

• Write 1 to MPLLA_TX_CLK_DIV.
• Write 1 to MPLLA_DIV10_CLK_EN.
11 Write 357d to Write 43d to

VR_MII_Gen5_12G_MPLLA_CTRL3[MPLLA_BANDWI VR_MII_Gen5_12G_MPLLA_CTRL3[MPLLA_BANDWI
DTH]. DTH].

VR_MII_Gen5_12G_16G_VCO_CAL_LD0[VCO_LD_VA VR_MII_Gen5_12G_16G_VCO_CAL_LD0[VCO_LD_VA
L_0]. L_0].

VR_MII_Gen5_12G_VCO_CAL_REF0[VCO_REF_LD_0 VR_MII_Gen5_12G_VCO_CAL_REF0[VCO_REF_LD_0
]. ].
14 Write 010b to VR_MII_Gen5_12G_16G_TX_RATE_CTRL[TX0_RATE].
15 Write 11b to VR_MII_Gen5_12G_16G_RX_RATE_CTRL[RX0_RATE].
16 Write 0 to VR_MII_Gen5_12G_16G_RX_CDR_CTRL[VCO_LOW_FREQ_0].
17 Write 1 to VR_MII_Gen5_12G_16G_MPLLB_CTRL0[MPLLB_CAL_DISABLE].
19 Write 1 to VR_MII_DIG_CTRL1[VR_RST] to initiate a vendor-specific software reset.
20 Wait until VR_MII_DIG_CTRL1[VR_RST] = 0.
21 Write 1 to VR_MII_Gen5_12G_16G_RX_GENCTRL1[RX_RST_0].
23 Wait until SR_MII_STS[LINK_STS] = 1.
5.4 Switching the PHY to 2.5G speed†

Before beginning the procedure in the following table, ensure that one of the following has occurred:
• You have applied internal or external loopback.
• You have connected an active link partner to the SGMII interface.
Table 79. Switching the PHY to 2.5G speed

NXP Semiconductors
XPCS
Table 79. Switching the PHY to 2.5G speed (continued)
2 Write Ch to VR_MII_Gen5_12G_16G_TX_EQ_CTRL0[TX_EQ_MAIN].
3 Write 4h to VR_MII_Consumer_10G_TX_TERM_CTRL[TX0_TERM].

7 In VR MII SPHY Reference In VR MII SPHY Reference

Control (VR_MII_Gen5_12G_16G_REF_CLK_CTRL): Control (VR_MII_Gen5_12G_16G_REF_CLK_CTRL):
• Write 1 to REF_MPLLB_DIV2. • Write 1 to REF_MPLLB_DIV2.
• To use the internal reference clock, write 0 to • To use the internal reference clock, write 0 to
• To use the external reference clock, write 1 to • To use the external reference clock, write 1 to
• Write 001b to REF_RANGE. • Write 010b to REF_RANGE.
• Write 1 to REF_CLK_DIV2. • Write 1 to REF_CLK_DIV2.
8 In VR MII PHY MPLLB Control In VR MII PHY MPLLB Control

0 (VR_MII_Gen5_12G_16G_MPLLB_CTRL0): 0 (VR_MII_Gen5_12G_16G_MPLLB_CTRL0):
• Write 0 to MPLLB_CAL_DISABLE. • Write 0 to MPLLB_CAL_DISABLE.
• Write 156d to MLLB_MULTIPLIER. • Write 125d to MLLB_MULTIPLIER.

VR_MII_Gen5_12G_MPLLB_CTRL1[MPLLB_FRACN_ VR_MII_Gen5_12G_MPLLB_CTRL1[MPLLB_FRACN_
CTRL]. CTRL].
10 In VR MII PHY MPLLB Control 2 (VR_MII_Gen5_12G_16G_MPLLB_CTRL2):

• Write 5d to MPLLB_TX_CLK_DIV.
• Write 1 to MPLLB_DIV10_CLK_EN.
11 Write 68d to VR_MII_Gen5_12G_MPLLB_CTRL3[MPLLB_BANDWIDTH].

VR_MII_Gen5_12G_16G_VCO_CAL_LD0[VCO_LD_VA VR_MII_Gen5_12G_16G_VCO_CAL_LD0[VCO_LD_VA
L_0]. L_0].

VR_MII_Gen5_12G_VCO_CAL_REF0[VCO_REF_LD_0 VR_MII_Gen5_12G_VCO_CAL_REF0[VCO_REF_LD_0
]. ].
14 Write 000b to VR_MII_Gen5_12G_16G_TX_RATE_CTRL[TX0_RATE].
15 Write 01b to VR_MII_Gen5_12G_16G_RX_RATE_CTRL[RX0_RATE].
16 Write 1 to VR_MII_Gen5_12G_16G_RX_CDR_CTRL[VCO_LOW_FREQ_0].

NXP Semiconductors
XPCS
Table 79. Switching the PHY to 2.5G speed (continued)
17 Write 1 to VR_MII_Gen5_12G_16G_MPLLA_CTRL0[MPLLA_CAL_DISABLE].
19 Write 1 to VR_MII_DIG_CTRL1[VR_RST] to initiate a vendor-specific software reset.
20 Wait until VR_MII_DIG_CTRL1[VR_RST] = 0.
23 Wait until SR_MII_STS[LINK_STS] = 1.
5.5 Switching the SGMII speed

To switch the SGMII speed, you must choose one of these options:
• Changing the speed manually
• Autonegotiation
NOTE
The SGMII speed is not the same as the PHY speed. To change the PHY speed, see Switching the PHY to 1G
speed† and Switching the PHY to 2.5G speed†.
5.5.1 Changing the speed manually

Before beginning the procedure in the following table, ensure that:
• Both sides run at the same SerDes speed—either 2.5G or 1G.
• Both sides have performed either of the following:
— Disabled the autonegotiation state machine
— Enabled autonegotiation and disabled automatic speed change (see Decoding the autonegotiation result)
Table 80. Changing the speed manually
Step Action
1 Write 0 to SR_MII_CTRL[AN_ENABLE].
2 Write 0 to VR_MII_AN_CTRL[MII_CTRL].
3 Write to the following fields in SR MII MMD Control (SR_MII_CTRL) to select the speed:
• For 1G or 2.5G speed, write 1 to MII_CTRL_SS6 and 0 to MII_CTRL_SS13.
• For 100M speed, write 0 to MII_CTRL_SS6 and 1 to MII_CTRL_SS13.
• For 10M speed, write 0 to MII_CTRL_SS6 and 0 to MII_CTRL_SS13.
5.5.2 Autonegotiation
The SerDes subsystem supports autonegotiation in the following scenarios:
• At 1G speed, autonegotiation to 10M, 100M, or 1G speed
• At 2.5G speed, autonegotiation only to 2.5G speed

NXP Semiconductors
XPCS
Autonegotiation changes the duplex type and link speed only in XPCS, not the MAC. You must provide the duplex type and link
speed to the MAC.
5.5.2.1 Enabling autonegotiation

Before beginning the procedure in the following table, ensure that:
• Both sides run at the same SerDes speed—either 2.5G or 1G.
• The other side has enabled the autonegotiation state machine.
Table 81. Enabling autonegotiation
Step Action
2 Write 10b to VR_MII_AN_CTRL[PCS_MODE].
3 In SR MII MMD Control (SR_MII_CTRL), write 1 to MII_CTRL_SS6 and 0 to MII_CTRL_SS13.
4 Write 0 to VR_MII_AN_CTRL[MII_CTRL].
5 Write one of the following values to VR_MII_LINK_TIMER_CTRL[CL37_LINK_TIME]:

• 2FAFh for 1G SerDes speed
• 7A1h for 2.5G SerDes speed
6 Write 1 to VR_MII_DIG_CTRL1[CL37_TMR_OVR_RIDE].
7 Write 1 to VR_MII_AN_CTRL[MII_AN_INTR_EN] to enable the "clause 37 autonegotiation complete" interrupt.
8 Optionally write 1 to VR_MII_DIG_CTRL1[MAC_AUTO_SW] to enable automatic speed changing.
10 Decode the autonegotiation result (see Decoding the autonegotiation result).
5.5.2.2 Decoding the autonegotiation result
Table 82. Decoding the autonegotiation result
Step Action
1 Poll VR_MII_AN_INTR_STS[CL37_ANCMPLT_INTR] until it becomes 1.
2 Read VR_MII_AN_INTR_STS[CL37_ANSGM_STS] to determine the duplex type, link speed, and link status.
3 Write 0 to VR_MII_AN_INTR_STS[CL37_ANCMPLT_INTR].
5.6 XPCS reset priority

In certain working modes, the SerDes subsystem determines which XPCS controller instance has priority control of the PHY. In
the modes where SGMII is enabled, you must configure the specific XPCS controller instance used to program PHY settings and
initiate the vendor-specific software reset (step 19 of Switching the PHY to 1G speed† and Switching the PHY to 2.5G speed†).
The following table explains which XPCS controller instance controls PHY operation and the XPCS controller reset sequence that
you must apply. If you enabled both PHY lanes in the subsystem working modes mentioned in this table, you must configure and
reset the XPCS instances in the following order:
1. The instance without PHY control
2. The instance with PHY control

NXP Semiconductors
XPCS
Table 83. XPCS reset priority
Subsystem working mode Instance with PHY control First vendor-specific Next vendor-specific
(SS_RW_REG_0[SUBSYS_MODE]) software reset software reset
001b PCIe controller XPCS_0 PCIe controller
010b XPCS_1
011b XPCS_0 XPCS_1 XPCS_0
100b XPCS_1 XPCS_0 XPCS_1
5.7 SerDes_XPCS register descriptions

This section presents the XPCS registers.†
These registers require a special procedure to access them. See Accessing XPCS registers.
5.7.1 XPCS memory map

Vendor Specific MII MMD Standard (SR) and Vendor Specific (VR) Registers address block.
SerDes_XPCS_0 relative offset: 8_2000h
SerDes_XPCS_1 relative offset: 8_2800h
(In bits)
1F_0000h SR MII MMD Control (SR_MII_CTRL) 16 RW 1140h
1F_0001h SR MII MMD Status (SR_MII_STS) 16 RO 0189h
1F_0002h SR MII MMD Device Identifier 1 (SR_MII_DEV_ID1) 16 RO 7996h
1F_0003h SR MII MMD Device Identifier 2 (SR_MII_DEV_ID2) 16 RO CED0h
1F_0004h SR MII MMD AN Advertisement (SR_MII_AN_ADV) 16 RW 0020h
1F_0005h SR MII MMD AN Link Partner Base Ability (SR_MII_LP_BABL) 16 RO 0000h
1F_0006h SR MII MMD AN Expansion (SR_MII_EXPN) 16 RO 0000h
1F_000Fh SR MII MMD Extended Status (SR_MII_EXT_STS) 16 RO C000h
1F_0708h SR MII MMD Time Sync Capability (SR_MII_TIME_SYNC_ABL) 16 RO 0003h
1F_0709h SR MII MMD Time Sync Tx Max Delay Lower 16 RO 0038h

(SR_MII_TIME_SYNC_TX_MAX_DLY_LWR)
1F_070Ah SR MII MMD Time Sync Tx Max Delay Upper 16 RO 0000h

(SR_MII_TIME_SYNC_TX_MAX_DLY_UPR)
1F_070Bh SR MII MMD Time Sync Tx Min Delay Lower 16 RO 0038h

(SR_MII_TIME_SYNC_TX_MIN_DLY_LWR)
1F_070Ch SR MII MMD Time Sync Tx Min Delay Upper 16 RO 0000h

(SR_MII_TIME_SYNC_TX_MIN_DLY_UPR)
1F_070Dh SR MII MMD Time Sync Rx Max Delay Lower 16 RO 0058h

(SR_MII_TIME_SYNC_RX_MAX_DLY_LWR)

NXP Semiconductors
XPCS
(In bits)
1F_070Eh SR MII MMD Time Sync Rx Max Delay Upper 16 RO 0000h

(SR_MII_TIME_SYNC_RX_MAX_DLY_UPR)
1F_070Fh SR MII MMD Time Sync Rx Min Delay Lower 16 RO 0050h

(SR_MII_TIME_SYNC_RX_MIN_DLY_LWR)
1F_0710h SR MII MMD Time Sync Rx Min Delay Upper 16 RO 0000h

(SR_MII_TIME_SYNC_RX_MIN_DLY_UPR)
1F_8000h VR MII MMD Digital Control 1 (VR_MII_DIG_CTRL1) 16 RW 2000h
1F_8001h VR MII MMD AN Control (VR_MII_AN_CTRL) 16 RW 0000h
1F_8002h VR MII MMD AN Interrupt And Status (VR_MII_AN_INTR_STS) 16 RW 000Ah
1F_8003h VR MII MMD Test Control (VR_MII_TC) 16 RW 0000h
1F_8005h VR MII MMD Debug Control (VR_MII_DBG_CTRL) 16 RW See

description
1F_800Ah VR MII MMD Link Timer Control (VR_MII_LINK_TIMER_CTRL) 16 RW 0000h
1F_8010h VR MII MMD Digital Status (VR_MII_DIG_STS) 16 RO 0010h
1F_8011h VR MII MMD Invalid Code Group Error Count 1 16 RO 0000h

(VR_MII_ICG_ERRCNT1)
1F_8012h VR MII MMD Digital Error Count Select 16 RW 0000h

(VR_MII_DIG_ERRCNT_SEL)
1F_8015h VR MII MMD GPIO (VR_MII_GPIO) 16 RW 0000h
1F_8018h VR MII MMD Miscellaneous Status (VR_MII_MISC_STS) 16 RO 0000h
1F_8020h VR MII PHY Rx Lane Status (VR_MII_RX_LSTS) 16 RO 0000h
1F_8030h VR MII PHY Tx General Control 0 16 RW 1000h

(VR_MII_Gen5_12G_16G_TX_GENCTRL0)


1F_8033h VR MII PHY Tx Boost Control 16 RW 000Fh

(VR_MII_Gen5_12G_16G_TX_BOOST_CTRL)
1F_8034h VR MII PHY Tx Rate Control 16 RW 0002h

(VR_MII_Gen5_12G_16G_TX_RATE_CTRL)
1F_8035h VR MII PHY Tx Power State 16 RW 0000h

(VR_MII_Gen5_12G_16G_TX_POWER_STATE_CTRL)
1F_8036h VR MII PHY Tx Equalization Control 0 16 RW 1800h

(VR_MII_Gen5_12G_16G_TX_EQ_CTRL0)

NXP Semiconductors
XPCS
(In bits)
1F_8037h VR MII PHY Tx Equalization Control 1 16 RW 0000h

1F_803Ch VR MII PHY Transmit Termination Control 16 RW 0002h

(VR_MII_Consumer_10G_TX_TERM_CTRL)
1F_8040h VR MII PHY Tx Status (VR_MII_Gen5_12G_16G_TX_STS) 16 RO 0000h
1F_8050h VR MII PHY Rx General Control 0 16 RW 0101h

(VR_MII_Gen5_12G_16G_RX_GENCTRL0)



1F_8054h VR MII PHY Rx Rate Control 16 RW 0003h

(VR_MII_Gen5_12G_16G_RX_RATE_CTRL)
1F_8055h VR MII PHY Rx Power State 16 RW 0000h

(VR_MII_Gen5_12G_16G_RX_POWER_STATE_CTRL)
1F_8056h VR MII PHY Rx CDR Control 16 RW 0001h

(VR_MII_Gen5_12G_16G_RX_CDR_CTRL)
1F_8057h VR MII PHY Rx Attenuation Control 16 RW 0000h

(VR_MII_Gen5_12G_16G_RX_ATTN_CTRL)
1F_8058h VR MII PHY Rx Equalization Control 0 16 RW 0007h

(VR_MII_Gen5_12G_RX_EQ_CTRL0)
1F_805Ch VR MII PHY Rx Equalization Control 4 16 RW 0010h

(VR_MII_Gen5_12G_16G_RX_EQ_CTRL4)
1F_805Dh VR MII PHY AFE-DFE Enable 16 RW 0000h

(VR_MII_Gen5_12G_AFE_DFE_EN_CTRL)
1F_805Eh VR MII PHY DFE Tap Control 0 16 RW 0000h

(VR_MII_Gen5_12G_16G_DFE_TAP_CTRL0)
1F_8060h VR MII PHY Rx Status (VR_MII_Gen5_12G_16G_RX_STS) 16 RO 0000h
1F_8064h VR MII PHY Receive Termination Control 16 RW 0002h

(VR_MII_Consumer_10G_RX_TERM_CTRL)
1F_806Bh VR MII PHY RX IQ Control 0 16 RW 0000h

(VR_MII_Consumer_10G_RX_IQ_CTRL0)
1F_8070h VR MII PHY MPLL Common Control 16 RW 0001h

(VR_MII_Gen5_12G_16G_MPLL_CMN_CTRL)

NXP Semiconductors
XPCS
(In bits)
1F_8071h VR MII PHY MPLLA Control 0 16 RW 0050h

(VR_MII_Gen5_12G_16G_MPLLA_CTRL0)
1F_8072h VR MII PHY MPLLA Control 1 (VR_MII_Gen5_12G_MPLLA_CTRL1) 16 RW 0000h
1F_8073h VR MII PHY MPLLA Control 2 16 RW 0A00h

(VR_MII_Gen5_12G_16G_MPLLA_CTRL2)
1F_8074h VR MII PHY MPLLB Control 0 16 RW 807Dh

(VR_MII_Gen5_12G_16G_MPLLB_CTRL0)
1F_8075h VR MII PHY MPLLB Control 1 (VR_MII_Gen5_12G_MPLLB_CTRL1) 16 RW See

description
1F_8076h VR MII PHY MPLLB Control 2 16 RW 1000h

(VR_MII_Gen5_12G_16G_MPLLB_CTRL2)
1F_8077h VR MII PHY MPLLA Control 3 (VR_MII_Gen5_12G_MPLLA_CTRL3) 16 RW 002Bh
1F_8078h VR MII PHY MPLLB Control 3 (VR_MII_Gen5_12G_MPLLB_CTRL3) 16 RW 0044h
1F_8090h VR MII PHY Miscellaneous Control 0 16 RW 5100h

(VR_MII_Gen5_12G_16G_MISC_CTRL0)
1F_8091h VR MII SPHY Reference Control 16 RW 0057h

(VR_MII_Gen5_12G_16G_REF_CLK_CTRL)
1F_8092h VR MII PHY VCO Calibration Load 0 16 RW 0550h

(VR_MII_Gen5_12G_16G_VCO_CAL_LD0)
1F_8096h VR MII PHY VCO Calibration Reference 0 16 RW 0011h

(VR_MII_Gen5_12G_VCO_CAL_REF0)
1F_8098h VR MII PHY Miscellaneous Status 16 RO 0200h

(VR_MII_Gen5_12G_16G_MISC_STS)
1F_8099h VR MII PHY Miscellaneous Control 1 16 RW FFFFh

(VR_MII_Gen5_12G_16G_MISC_CTRL1)
1F_80A0h VR MII PHY CR Control (VR_MII_SNPS_CR_CTRL) 16 RW 0000h
1F_80A1h VR MII PHY CR Address (VR_MII_SNPS_CR_ADDR) 16 RW 0000h
1F_80A2h VR MII CR Data (VR_MII_SNPS_CR_DATA) 16 RW 0000h
1F_80E1h VR MII MMD Digital Control 2 (VR_MII_DIG_CTRL2) 16 RW 0000h
5.7.2 SR MII MMD Control (SR_MII_CTRL)
Offset
Register Offset
SR_MII_CTRL 1F_0000h

NXP Semiconductors
XPCS
Function
The host can use this register to control (enable or disable) some of the features supported by the XPCS with 1G (1000BASE-
X) support and Clause 37 auto-negotiation support.
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R AN_E Reserv REST DUPL Reserv SS5

RST LBE SS13 LPM SS6 Reserved
W NAB... ed ART... EX_... ed
Reset 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0
Fields
Field Function
15 Soft reset (RW, SC type)

RST When the host sets this field, the CSR block triggers the software reset process in which all internal blocks
are reset, except the Management Interface block. The registers are reset to their default values. When this
field is set, it also resets the PHY. This field is self-cleared when PSEQ_STATE in VR XS or PCS or MII MMD
Digital Status Register is equal to 100b, that is, Tx/Rx clocks are stable and in Power_Good state.
Do not access other registers while the reset is in progress.
14 Loopback enable
LBE When LBE=1, the PHY Tx lanes loop back to the PHY Rx lanes.
13 Speed selection (LSB)

SS13 This field, together with the SS6 field of this register, indicates the speed.
For SGMII configurations:
• When SS6=1 and SS13=0, speed is 1000 Mbps.
12 Enable auto-negotiation
AN_ENABLE When you program AN_ENABLE=1, you enable the Clause 37 auto-negotiation process.
11 Power-down mode
LPM This field controls the Power-down mode of the XPCS.
When the host clears this field, the XPCS resumes the normal operation. After clearing this field, the host
must wait until Bits[4:2] of VR XS or PCS MMD Digital Status Register indicate that the XPCS is in the
normal state.
Do not access any other registers when the XPCS is in Power-down mode.
1b - The XPCS and the PHY enter Power-down mode. To trigger Power-down mode, the XPCS
turns off the PHY receiver and transmitter, then switches off all the clocks.

NXP Semiconductors
XPCS
Field Function
10 Reserved
9 Restart auto-negotiation (RW, SC type)

RESTART_AN When the host writes this field, the XPCS initiates the auto-negotiation process. This field is used to
restart the auto-negotiation which is already initiated by setting Bit 12. The XPCS clears this field after
restarting the autonegotiation.
8 Duplex mode
DUPLEX_MOD This bit specifies the duplex mode of the XPCS.
E
If Bit 12 is set to 0, this bit determines the PHY link duplex mode. If Bit 12 is set to 1, then the PHY link duplex
mode is independent of this bit (although the host can write any value) and is determined by the outcome
of the Clause 37 auto-negotiation process.
0b - Half duplex
1b - Full duplex
7 Reserved
6 Speed selection
SS6 This field, along with SS13, indicates the speed. For more information, see the SS13 field description.
5 Reserved
SS5
4-0 Reserved
5.7.3 SR MII MMD Status (SR_MII_STS)
Offset
Register Offset
SR_MII_STS 1F_0001h
Function
The host uses this register to know the features supported by the XPCS in the 1000BASE-X mode.

NXP Semiconductors
XPCS
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABL10 FD100 HD100 FD10A HD10 FD100 HD100 EXT_S UN_DI MF_P AN_ AN_ LINK_ EXT_R
R RF Reserv
0T4 ABL ABL BL ABL T T TS... R_... RE_... CMPL ABL STS EG...
ed
W
Reset 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1
Fields
Field Function
15 100BASE-T4 ability
ABL100T4 The XPCS always returns 0 because it does not support this functionality.
14 100BASE-X full-duplex ability

FD100ABL The XPCS always returns 0 because it does not support this functionality.
13 100BASE-X half-duplex ability

HD100ABL The XPCS always returns 0 because it does not support this functionality.
12 10 Mbps full-duplex ability

FD10ABL The XPCS always returns 0 because it does not support this functionality.
11 10 Mbps half-duplex ability

HD10ABL The XPCS always returns 0 because it does not support this functionality.
10 100BASE-T2 full-duplex ability

FD100T The XPCS always returns 0 because it does not support this functionality.
9 100BASE-T2 half-duplex ability

HD100T The XPCS always returns 0 because it does not support this functionality.
8 Extended status information

EXT_STS_ABL On this chip, EXT_STS_ABL is always 1.
0b - No extended status information is present at register address Fh of this MMD device.
1b - Extended Status information is present at register address Fh of this MMD device.
7 Unidirectional ability
UN_DIR_ABL On this chip, UN_DIR_ABL is always 1.
0b - The XPCS is able to transmit GMII only when the device has determined the valid link.
1b - The XPCS is able to transmit GMII irrespective of whether the device has determined the
valid link or not.
6 MF preamble suppression
On this chip, MF_PRE_SUP is always 0.

NXP Semiconductors
XPCS
Field Function
MF_PRE_SUP 0b - The XPCS does not accept the MDIO frames with preamble suppressed.
1b - The XPCS accepts the MDIO frames with preamble suppressed.
5 Auto-negotiation complete
AN_CMPL When this field is set to 1, the contents of the AN MMD Advertizement, AN MMD Link partner Ability, and
AN MMD Expansion registers are valid. This field returns 0 if AN_ENABLE is set to 0.
0b - The AN process is not complete.
1b - The AN process is complete.
4 Remote fault (RO, LH type)

RF When RF=1, it indicates that the receive link of the link partner is down. This field is set based on the
auto-negotiated (1000BASE-X auto-negotiation) information from the link partner.
0b - The XPCS did not detect a remote fault.
1b - The XPCS detected a remote fault.
3 Auto-negotiation ability
AN_ABL On this chip, AN_ABL is always 1.
0b - The XPCS is unable to perform auto-negotiation.
1b - The XPCS is able to perform auto-negotiation.
2 Link status (RO, LL type)

LINK_STS When XPCS programs LINK_STS=1, it indicates that the Rx link is up. If the link goes down, it is latched until
the host reads SR_MII_STS.
0b - Link down
1b - Link up
1 Reserved
0 Extended register capability

EXT_REG_CAP On this chip, EXT_REG_CAP is always 1.
0b - Extended register capability does not exist
1b - Extended Register capability exists
5.7.4 SR MII MMD Device Identifier 1 (SR_MII_DEV_ID1)
Offset
Register Offset
SR_MII_DEV_ID1 1F_0002h

NXP Semiconductors
XPCS
Function
This register returns the configurable Organizationally Unique Identifier (OUI) to the host.
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VS_MII_DEV_OUI_3_18
Reset 0 1 1 1 1 0 0 1 1 0 0 1 0 1 1 0
Fields
Field Function
15-0 Organizationally Unique Identifier[3:18]

VS_MII_DEV_O This field contains Bits [18:3] of 24-bit OUI of device manufacturer. The XPCS offers 24 configurable
UI_3_18 Bits[24:1] for identifying the device manufacturer. The default value of this register is similar to the value
of SR XS or PCS MMD Device Identifier Register 1. If IEEE_REG_WR_SUPPORT = Enabled, writing to
Bits[15:0] of SR XS or PCS MMD Device Identifier Register 1 modifies the content of this register.
5.7.5 SR MII MMD Device Identifier 2 (SR_MII_DEV_ID2)
Offset
Register Offset
SR_MII_DEV_ID2 1F_0003h
Function
This register returns the configurable Organizationally Unique Identifier (OUI), model number, and revision number of the
device to the host.
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VS_MMD_DEV_OUI_19_24 VS_MMD_DEV_MMN_5_0 VS_MMD_DEV_RN_3_0
Reset 1 1 0 0 1 1 1 0 1 1 0 1 0 0 0 0
Fields
Field Function
15-10 Organizationally unique identifier [19:24]

VS_MMD_DEV This field contains bits [24:19] of 24-bit OUI of device manufacturer. The XPCS offers 24 configurable
_OUI_19_24 Bits [24:1] for identifying the device manufacturer. The default value of this register is similar to the value

NXP Semiconductors
XPCS
Field Function
of SR XS or PCS MMD Device Identifier Register 2. If IEEE_REG_WR_SUPPORT = Enabled, writing to

Bits[15:10] of SR XS or PCS MMD Device Identifier Register 2 modifies the content of this register.
9-4 Model number

VS_MMD_DEV This field contains the 5-bit Model Number of the device. The default value of this register is similar to
_MMN_5_0 the value of SR XS or PCS MMD Device Identifier Register 2. If IEEE_REG_WR_SUPPORT = Enabled,
writing to Bits[9:4] of SR XS or PCS MMD Device Identifier Register 2 modifies the content of this
register.
3-0 Revision number

VS_MMD_DEV This field contains the 4-bit revision number of the device. The default value of this register is similar to
_RN_3_0 the value of SR XS or PCS MMD Device Identifier Register 2. If IEEE_REG_WR_SUPPORT = Enabled,
writing to Bits[3:0] of SR XS or PCS MMD Device Identifier Register 2 modifies the content of this
register.
5.7.6 SR MII MMD AN Advertisement (SR_MII_AN_ADV)
Offset
Register Offset
SR_MII_AN_ADV 1F_0004h
Function
The host uses this register to advertise the abilities and status of the local device to its link partner through the Clause 37
auto-negotiation protocol.
NOTE
This register is present only for configurations with 1G/KX support.
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R NP Reserv
RF Reserved PAUSE HD FD Reserved
W ed
Reset 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
Fields
Field Function
15 Next page
NP The XPCS always returns this field as 0 because it does not support the next-page feature.

NXP Semiconductors
XPCS
Field Function
14 Reserved
13-12 Remote fault

RF This field indicates the fault signaling of the local device to be communicated to the link partner.
00b - No error
01b - Offline
10b - Link failure
11b - Auto-negotiation error
11-9 Reserved
8-7 Pause ability

PAUSE This field indicates the pause ability of the device. Your software can program suitable values based on
the capability of the MAC.
00b - No pause
01b - Asymmetric pause towards the link partner
10b - Symmetric pause
11b - Symmetric pause and asymmetric pause towards the local device
6 Half duplex
HD HD=1 indicates that the device can operate in half-duplex mode.
5 Full duplex
FD FD=1 indicates that the device can operate in full-duplex mode.
4-0 Reserved
5.7.7 SR MII MMD AN Link Partner Base Ability (SR_MII_LP_BABL)
Offset
Register Offset
SR_MII_LP_BABL 1F_0005h
Function
The host uses this page to know the link partner's ability when the base page is received through Clause 37 auto-negotiation.
The content of this register is valid only for 1000BASE-X autonegotiation. It is not valid in SGMII auto-negotiation.

NXP Semiconductors
XPCS
NOTE
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LP_
R LP_NP LP_RF LP_PAUSE LP_HD LP_FD
ACK Reserved Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
15 Next page
LP_NP This field indicates that the link partner can handle the next-page feature.
NOTE
To exchange information through the next-page feature, both devices (local and remote)
should have the capability to handle this feature. The XPCS does not support the next-page
feature. Therefore, the next-page exchange does not happen.
14 ACK bit from the link partner

LP_ACK This field indicates that the link partner has successfully received the page that the local device sent.
13-12 Remote fault

LP_RF This field indicates the fault signaling of the link partner.
00b - No error
01b - Offline
10b - Link failure
11b - Auto-negotiation error
11-9 Reserved
8-7 Pause ability

LP_PAUSE This field indicates the Pause ability of the link partner.
00b - No pause
01b - Asymmetric pause towards the link partner
10b - Symmetric pause
11b - Both symmetric pause and asymmetric pause towards the local device
6 Half duplex

NXP Semiconductors
XPCS
Field Function
LP_HD LP_HD=1 indicates that the link partner is capable of operating in half-duplex mode.
5 Full duplex
LP_FD LP_FD=1 indicates that the link partner is capable of operating in full-duplex mode.
4-0 Reserved
5.7.8 SR MII MMD AN Expansion (SR_MII_EXPN)
Offset
Register Offset
SR_MII_EXPN 1F_0006h
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LD_NP PG_
R Reserv
Reserved _A... RCVD
ed
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
15-3 Reserved
2 Local device next page able

LD_NP_ABL On this chip, LD_NP_ABL is always 0 because the XPCS does not support the next-page feature.
0b - The local device does not have the next-page ability
1b - The local device has the next-page ability
1 Page received (RO, LH type)

PG_RCVD This field indicates that the local device received a page from the link partner.
0b - The local device did not receive a new page
1b - The local device received a new page

NXP Semiconductors
XPCS
Field Function
0 Reserved
5.7.9 SR MII MMD Extended Status (SR_MII_EXT_STS)
Offset
Register Offset
SR_MII_EXT_STS 1F_000Fh
Function
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAP_1 CAP_1 CAP_1 CAP_1

R
G_... G_... G_... G_... Reserved
W
Reset 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
15 1000BASE-X full-duplex capable

CAP_1G_X_FD On this chip, CAP_1G_X_FD is always 1.
0b - Not capable of 1000BASE-X full-duplex
1b - Capable of 1000BASE-X full-duplex
14 1000BASE-X half-duplex capable

CAP_1G_X_HD On this chip, CAP_1G_X_HD is always 1.
0b - Not capable of 1000BASE-X half-duplex
1b - Capable of 1000BASE-X half-duplex
13 1000BASE-T full-duplex capable

CAP_1G_T_FD On this chip, CAP_1G_T_FD is always 0.
0b - Not capable of 1000BASE-T full-duplex
1b - Capable of 1000BASE-T full-duplex

NXP Semiconductors
XPCS
Field Function
12 1000BASE-T half-duplex capable

CAP_1G_T_HD On this chip, CAP_1G_T_HD is always 0.
0b - Not capable of 1000BASE-T half-duplex
1b - Capable of 1000BASE-T half-duplex
11-0 Reserved
5.7.10 SR MII MMD Time Sync Capability (SR_MII_TIME_SYNC_ABL)
Offset
Register Offset
SR_MII_TIME_SYNC_A 1F_0708h
BL
Function
This register is present only in 1000BaseX-Only PCS configurations.
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MII_TX MII_RX
R
Reserved _... _...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Fields
Field Function
15-2 Reserved
1 XPCS transmit path data delay information available

MII_TX_DLY_A MII_TX_DLY_ABL=1 indicates that the information regarding the maximum and minimum transmit data
BL delay of XPCS is available in MII MMD Tx Time Delay Registers.
0 XPCS receive path data delay information available

MII_RX_DLY_A MII_RX_DLY_ABL=1 indicates that the information regarding the maximum and minimum receive data
BL delay of XPCS is available in MII MMD Rx Time Delay Registers.

NXP Semiconductors
XPCS
5.7.11 SR MII MMD Time Sync Tx Max Delay Lower (SR_MII_TIME_SYNC_TX_MAX_DLY_LWR)
Offset
Register Offset
SR_MII_TIME_SYNC_TX 1F_0709h
_MAX_DLY_LWR
Function
SThis register is present only in 1000BaseX-Only PCS configurations.
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R MII_TX_MAX_DLY_LWR
Reset 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0
Fields
Field Function
15-0 Indicates the lower 16 bits of the 32-bit value that indicates the maximum data delay (in ns) in the XPCS
transmit path.
MII_TX_MAX_D
LY_LWR
5.7.12 SR MII MMD Time Sync Tx Max Delay Upper (SR_MII_TIME_SYNC_TX_MAX_DLY_UPR)
Offset
Register Offset
SR_MII_TIME_SYNC_TX 1F_070Ah
_MAX_DLY_UPR
Function

NXP Semiconductors
XPCS
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R MII_TX_MAX_DLY_UPR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
15-0 Indicates the upper 16 bits of the 32-bit value that indicates the maximum data delay (in ns) in the XPCS
transmit path.
MII_TX_MAX_D
LY_UPR
5.7.13 SR MII MMD Time Sync Tx Min Delay Lower (SR_MII_TIME_SYNC_TX_MIN_DLY_LWR)
Offset
Register Offset
SR_MII_TIME_SYNC_TX 1F_070Bh
_MIN_DLY_LWR
Function
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R MII_TX_MIN_DLY_LWR
Reset 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0
Fields
Field Function
15-0 Indicates the lower 16 bits of the 32-bit value that indicates the minimum data delay (in ns) in the XPCS
transmit path.
MII_TX_MIN_D
LY_LWR

NXP Semiconductors
XPCS
5.7.14 SR MII MMD Time Sync Tx Min Delay Upper (SR_MII_TIME_SYNC_TX_MIN_DLY_UPR)
Offset
Register Offset
SR_MII_TIME_SYNC_TX 1F_070Ch
_MIN_DLY_UPR
Function
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R MII_TX_MIN_DLY_UPR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
15-0 Indicates the upper 16 bits of the 32-bit value that indicates the minimum data delay (in ns) in the XPCS
transmit path.
MII_TX_MIN_D
LY_UPR
5.7.15 SR MII MMD Time Sync Rx Max Delay Lower (SR_MII_TIME_SYNC_RX_MAX_DLY_LWR)
Offset
Register Offset
SR_MII_TIME_SYNC_R 1F_070Dh
X_MAX_DLY_LWR
Function

NXP Semiconductors
XPCS
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R MII_RX_MAX_DLY_LWR
Reset 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0
Fields
Field Function
15-0 Indicates the lower 16 bits of the 32-bit value that indicates the maximum data delay (in ns) in the XPCS
receive path.
MII_RX_MAX_D
LY_LWR
5.7.16 SR MII MMD Time Sync Rx Max Delay Upper (SR_MII_TIME_SYNC_RX_MAX_DLY_UPR)
Offset
Register Offset
SR_MII_TIME_SYNC_R 1F_070Eh
X_MAX_DLY_UPR
Function
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R MII_RX_MAX_DLY_UPR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
15-0 Indicates the upper 16 bits of the 32-bit value that indicates the maximum data delay (in ns) in the XPCS
receive path.
MII_RX_MAX_D
LY_UPR

NXP Semiconductors
XPCS
5.7.17 SR MII MMD Time Sync Rx Min Delay Lower (SR_MII_TIME_SYNC_RX_MIN_DLY_LWR)
Offset
Register Offset
SR_MII_TIME_SYNC_R 1F_070Fh
X_MIN_DLY_LWR
Function
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R MII_RX_MIN_DLY_LWR
Reset 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0
Fields
Field Function
15-0 Indicates the lower 16 bits of the 32-bit value that indicates the minimum data delay (in ns) in the XPCS
receive path.
MII_RX_MIN_D
LY_LWR
5.7.18 SR MII MMD Time Sync Rx Min Delay Upper (SR_MII_TIME_SYNC_RX_MIN_DLY_UPR)
Offset
Register Offset
SR_MII_TIME_SYNC_R 1F_0710h
X_MIN_DLY_UPR
Function

NXP Semiconductors
XPCS
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R MII_RX_MIN_DLY_UPR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
15-0 Indicates the upper 16 bits of the 32-bit value that indicates the minimum data delay (in ns) in the XPCS
receive path.
MII_RX_MIN_D
LY_UPR
5.7.19 VR MII MMD Digital Control 1 (VR_MII_DIG_CTRL1)
Offset
Register Offset
VR_MII_DIG_CTRL1 1F_8000h
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EN_V CS_ MSK_ PHY_

R VR_ R2TLB SMM... 0 PWRS MAC_ PRE_ Reserv DTXL CL37_ EN_2_ BYP_P MOD...
EN INIT RD_...
RST E V AUT... EMP ed ANE... TM... 5G... WR...
W
Reset 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
15 Vendor-specific soft reset (RW, SC type)

VR_RST When the host sets this field, the CSR block triggers the vendor-specific software reset process in which all
internal blocks except the Management Interface block and CSR block are reset. When this field is set, it
also resets the PHY. This bit is self cleared under the following conditions:
• For Synopsys PHY: This field is self cleared when Bits[4:2] in VR XS or PCS MMD Digital Status
Register are equal to 3'b100, that is, Tx/Rx clocks are stable and in Power_Good state.
• For Non-Synopsys PHY: This field is self cleared after the following:
— 32 clk_csr_i clocks for the MCI interface

NXP Semiconductors
XPCS
Field Function
— 1 MDC clock period for the MDIO interface
NOTE
For information about the read or write access for any register during the reset process, see
"Special Case Register Access" section.
14 Rx to Tx loopback enable
R2TLBE This bit controls the loopback path from the GMII Rx to the GMII Tx at the GMII interface. It reflects the value
programmed to R2TLBE bit of VR XS or PCS MMD Digital Control 1 Register , as it is a shared bit.
0b - Loopback path is disabled
1b - Loopback path is enabled
13 Enable vendor-specific MMD1

EN_VSMMD1 When this bit is set to 1, the vendor-specific MMD1 (VSMMD1) is enabled. When this bit is set to zero,
VSMMD1 is disabled. It reflects the value programmed to R2TLBE bit of VR XS or PCS MMD Digital
Control 1 Register , as it is a shared bit.
12 Reserved
11 Power save
PWRSV When this field is 1, XPCS triggers the power-down mode by turning off the PHY Receiver and Transmitter,
and without turning off MPLL.
When the host writes 0 to this field, XPCS resumes normal operation.
After writing 0 to this field, the host must wait until VR_MII_DIG_STS[PSEQ_STATE] indicates that XPCS
is in a normal state.
1b - XPCS and the PHY enter the power-save mode
10 Reserved
CS_EN
9 Automatic Speed Mode Change after CL37 AN

MAC_AUTO_S It this field is set to 1, XPCS automatically switches to the negotiated SGMII/USXGMII/QSGMII(port0)
W speed, after the completion of Clause 37 auto-negotiation. This mode is valid only when XPCS is
configured as MAC-side SGMII/USXGMII/QSGMII and should be set only when Auto-negotiation is
enabled (AN_ENABLE bit is set to 1). If this bit is set to 0, XPCS will operate at the speed/duplex mode
as per the values programmed to SR MII MMD Control Register. In that case, after the completion of
CL37 AN, application has to read the negotiated Speed/Duplex Mode from VR MII MMD AN Interrupt
and Status Register and then program SR MII MMD Control Register appropriately. If this bit is set to
1 in SGMII mode, xpcs_sgmii_link_sts_o, xpcs_link_speed_o and xpcs_sgmii_full_duplex_o outputs will
reflect the auto-negotiated values i.e., values from CL37_ANSGM_STS field of VR MII MMD AN Interrupt
and Status Register. For USXGMII mode, if clk_xgmii_tx_i and clk_xgmii_rx_i do not stabilize at the new
operating frequency (based on the selected speed) immediately after the completion of auto-negotiation,

NXP Semiconductors
XPCS
Field Function
then software might need to program 'USRA_RST' bit prior to starting packet transfer in the new speed
mode. Note: This bit should be set only when XPCS is configured as SGMII/USXGMII/QSGMII MAC i.e.,
TX_CONFIG=0 For other configurations: This is a read-only reserved field and returns 0.
8 Datapath initialization control

INIT This field can be set to flush/initialize the various FIFOs implemented inside XPCS. This is Self-Clear bit.
After writing 1 to this bit, software should poll this bit continuously. Software should proceed to any other
operation only after reading this bit as 0. When this bit is programmed to 1, RXFIFO_OVF/RXFIFO_UNF
bits of VR MII MMD Digital Status Register might get set incorrectly. Hence,read these register bits
(RXFIFO_OVF and RXFIFO_UNF) so that they get cleared. Thereafter, RXFIOF_UNF and RXFIFO_UNF
bits would be reliable.
7 Mask running disparity error

MSK_RD_ERR In QSGMII mode of operation, an error in data received from a particular port of a far-end device can
result in unprecedent running disparity errors for other ports (even if data is received correctly). In order
to resolve this issue, XPCS provides an option to mask the running disparity errors. If this register bit
is set, then running disparity errors are ignored by XPCS receiver in evaluating the validity of received
code-groups.
6 Pre-emption packet enable

PRE_EMP This field should be set to 1 to allow the XPCS to properly receive/transmit pre-emption packets in SGMII
10M/100M Modes.
5 Reserved
4 Tx lane 0 disable
DTXLANED_0 When this field is set, the XPCS disables the Tx Lane 0 of the PHY.
When reset, the XPCS enables the Tx Lane 0 of the PHY.
This field is Read-Write only when MAIN_MODE= 1000BASEX-Only PCS.
This bit is shared with the following:
• Bit 4 of VR XS or PCS MMD Digital Control1 Register and VR MII MMD Digital Control1 Register
• Bit 1 of SR PMA MMD Transmit Disable Register
• Bit 0 of SR PMA or PMD KX Control Register
3 Override control for CL37 link timer

CL37_TMR_OV This field can be set to override the default value of Clause 37 link_timer used by the XPCS for
R_RIDE auto-negotiation. If this field is set, the value programmed to VR MII MMD Link Timer Control Register
will be used to compute the duration of Link Timer. This bit should be set, only after programming the
appropriate value to VR MII MMD Link Timer Control Register.
2 Enable 2.5G GMII mode

EN_2_5G_MOD This field should be set to 1 to enable 2.5G GMII Mode of operation. This field drives the output port
E 'xpcs_2pt5g_mode_o'. This field is shared with bit[2] of VR XS or PCS MMD Digital Control 1 Register.

NXP Semiconductors
XPCS
Field Function
1 Bypass power-up sequence

BYP_PWRUP Access type: If SNPS_XAUI_PHY= Enabled, this bit is RW. Otherwise, this bit is RO.
This field is shared with Bit 1 of following registers:
• VR XS or PCS MMD Digital Control1 Register
• VR AN MMD Digital Control1 Register
• VR PMA MMD Digital Control1 Register
When this field is 1, XPCS bypasses the normal flow of the power-up sequence and reaches the
Power_Good state to enable transmission or reception. The XPCS does not wait for the MPLL and Transmit
or Receive PLL status from the Synopsys PHY. You can use this feature when the XPCS is configured to
interface with a specific Synopsys PHY and when the data path needs to interface with some other PHY.
0b - The XPCS waits for the MPLL, Tx, or Rx PLL status from the Synopsys PHY before resuming
the normal transmission and reception.
1b - The XPCS bypasses the normal flow of the power-up sequence as described earlier.
0 When SGMII_PHY_AN_AUTO_RESTART=Enabled or QSGMII_PHY_AN_AUTO_RESTART=Enabled:

PHY mode control
PHY_MODE_C
TRL This field controls the CL37_AN when operating in SGMII/QSGMII (Port 0) PHY mode.
This field should be set only when XPCS is configured as SGMII/QSGMII PHY i.e., TX_CONFIG=1. In other
configurations, this field is reserved and read-only.
0b - SGMII/QSGMII(Port0) autonegotiation advertises the values programmed
to VR_MII_AN_CTRL[SGMII_LINK_STS], SR_MII_CTRL[SS6], SR_MII_CTRL[SS13], and
SR_MII_AN_ADV[FD].
1b - XPCS advertises the values of input ports xpcs_sgmii_link_sts_i, xpcs_sgmii_link_speed_i
and xpcs_sgmii_full_duplex_i during SGMII/(Port0)QSGMII autonegotiation.
5.7.20 VR MII MMD AN Control (VR_MII_AN_CTRL)
Offset
Register Offset
VR_MII_AN_CTRL 1F_8001h

NXP Semiconductors
XPCS
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R MII_ SGMII TX_C MII_A

Reserved Reserved PCS_MODE
W CTRL _L... ONF... N_...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
15-9 Reserved
8 MII Control This bit controls the width of the MAC interface when operating at SGMII/QSGMII/USXGMII
speed modes of 10 Mbps or 100 Mbps - 0: 4-bit MII - 1: 8-bit MII This bit also controls the xpcs_mii_ctrl_o
MII_CTRL signal which is used for external clock multiplexing of the clk_mii_tx_i and clk_mii_rx_i signals.
7-5 Reserved
4 SGMII Link Status/ USXGMII Link Status /QSGMII Port0 Link Status
SGMII_LINK_S This bit is used in Bit 15 of the Config_Reg during Clause 37 auto-negotiation when the TX_CONFIG bit
TS of this register is set to 1 in the SGMII/QSGMII/USXGMII mode and when PHY_MODE_CTRL bit of VR
MII MMD Digital Control 1 Register is 0 . - 0: Link Down - 1: Link Up
3 Transmit configuration
TX_CONFIG This field controls the Config_Reg value to be used during the Clause 37 auto-negotiation in the SGMII/
QSGMII/USXGMII mode.
0b - Configures the XPCS as the MAC side SGMII/QSGMII/USXGMII
1b - Configures the XPCS as the PHY side SGMII/QSGMII/USXGMII
2-1 PCS mode
PCS_MODE 00b - 1000BASE-X mode (clause 37 auto-negotiation is as per 1000BaseX)

01b - Reserved
10b - SGMII mode (clause 37 auto-negotiation is as per SGMII)
11b - QSGMII mode (clause 37 auto-negotiation conforms to QSGMII)
0 Clause 37 AN complete interrupt enable
MII_AN_INTR_ 0b - The Clause 37 auto-negotiation complete interrupt is disabled.

EN 1b - The Clause 37 auto-negotiation complete interrupt is enabled.

NXP Semiconductors
XPCS
5.7.21 VR MII MMD AN Interrupt And Status (VR_MII_AN_INTR_STS)
Offset
Register Offset
VR_MII_AN_INTR_STS 1F_8002h
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LP_CK LP_EE
R Reserv USXG_AN_STS Reserv CL37_ANSGM_STS CL37_
_S... E_...
ed ed AN...
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0
Fields
Field Function
15 Reserved
14-8 Reserved
USXG_AN_STS
7 Reserved
6 Link Partner EEE Clock Stop Capability This field indicates the EEE clock stop capability (or clock-stop
enabe - in case far-end is acting as QSGMII MAC) advertised by the far-end device. This field is valid
LP_CK_STP only when PCS_MODE[1:0] is set to the QSGMII mode and the auto-negotiation is complete along port
0. Note:This field is present only in configurations with QSGMII_EN=Enabled
5 Link Partner EEE Capability This field indicates the EEE capability advertised by the far-end device
(Port 0 QSGMII PHY). This field is valid only when PCS_MODE[1:0] is set to the QSGMII mode and
LP_EEE_CAP the auto-negotiation is complete along port 0. Note:This field is present only in configurations with
QSGMII_EN=Enabled
Clause 37 AN SGMII Status/QSGMII Port 0 Status This field is valid only when the PCS_MODE[1:0]
4-1
is set to the SGMII/QSGMII mode and the auto-negotiation is complete. It indicates the status received
CL37_ANSGM_ from remote link after the SGMII/QSGMII (Port 0) autonegotiation is complete. CL37_ANSGM_STS[0] -
STS 0: Half Duplex - 1: Full Duplex CL37_ANSGM_STS[2:1] - 00: 10 Mbps speed link - 01: 100 Mbps speed
link - 10: 1000 Mbps speed link CL37_ANSGM_STS[3] - 0: Link is Down - 1: Link is Up
0 Clause 37 AN Complete Interrupt (SS,WC Type) The XPCS sets this bit when Clause 37 auto-
negotiation is complete. The host must clear this bit by writing 0 to it.
CL37_ANCMPL
T_INTR

NXP Semiconductors
XPCS
5.7.22 VR MII MMD Test Control (VR_MII_TC)
Offset
Register Offset
VR_MII_TC 1F_8003h
Function
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved TPE TP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
15-3 Reserved
2 Test Pattern Enable Lanes

TPE This bit indicates that a test pattern can be enabled in the Tx path after the current normal frame
transmission is complete. - 0: Test pattern disabled - 1: Test pattern enabled Dependencies: The specific
test pattern that is generated is based on Bits[1:0] of this register.
1-0 Test Pattern Select

TP This field indicates the pattern type that is enabled with Bit 2 of this register. The following are the
supported test patterns: - 2'b00: High Frequency Test Pattern - 2'b01: Low Frequency Test Pattern -
2'b10: Mixed Frequency Test Pattern - 2'b11: Reserved The definition of these test patterns is specified
in IEEE Std 802.3ae, Annex 48A.
5.7.23 VR MII MMD Debug Control (VR_MII_DBG_CTRL)
Offset
Register Offset
VR_MII_DBG_CTRL 1F_8005h
Function

NXP Semiconductors
XPCS
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUPR
R RX_DT SUPR REST
Reserved ESS... Reserved
_E... ESS... AR_...
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 u u u 0
Fields
Field Function
15-7 Reserved
6 Rx Data Enable Control

RX_DT_EN_CT Controls the behavior of xpcs_rx_data_en_o[0] output from XPCS. During normal operation XPCS
L deasserts xpcs_rx_data_en_o[0] on detecting of Loss-of-Signal. However, if this field is 1, XPCS
does not deassert xpcs_rx_data_en_o[0] on detection of Loss-of-Signal. Instead, the value of
VR_MII_Gen5_12G_16G_RX_GENCTRL0[RX_DT_EN_0] will be driven on xpcs_rx_data_en_o[0] output
port.
5 Reserved
SUPRESS_EE
E_LOS_DET
4 Suppress Loss of Signal Detection

SUPRESS_LO When this field is 1, Loss of Signal indicated by the PHY (based on input port xpcs_los_i) is ignored by
S_DET XPCS while evaluating the Receive link.Receive link will be purely evaluated based the Rx data received
on the 'xgxs_rx_data{lane}_i' port of XPCS. When this field is set to 0, Loss of signal indicated by the
PHY will be considered by the XPCS while evaluating the Receive link status. Note: This register bit has
an impact on the EEE Rx behaviour of XPCS when operating in QSGMII mode. if this register bit is set
to 1, then entry to RX_QUIET state is based on 'code_sync_status' (genereated by PCS Synchronization
State Diagram) instead of 'signal_detect'.
3-1 Reserved
0 Restart Synchronization
RESTAR_SYN When set to 1, this bit restarts the Rx Synchronization State machine on Lane 0. The host must clear this
C_0 bit to 0 before setting it to 1 next time.

NXP Semiconductors
XPCS
5.7.24 VR MII MMD Link Timer Control (VR_MII_LINK_TIMER_CTRL)
Offset
Register Offset
VR_MII_LINK_TIMER_C 1F_800Ah
TRL
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CL37_LINK_TIME
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
15-0 Programmable Link Timer Value for Clause 37 autonegotiation. This field can be programmed to any
desired value if application wishes to over-ride the standard specified values for Link Timer used during
CL37_LINK_TI Clause 37 Auto negotiation. Link timer is implemented in XPCS using a 24-bit timer.When operating
ME in USXGMII mode, link timer runs at 156.25 MHz. When operating in 1000BaseX/SGMII mode, this
timer operates at 125 MHz. For USXGMII configurations: This field forms the upper 16-bit of the
24-bit value that gets loaded to the link timer.The lower 8-bits are hard-coded as zero. For example,
if CL37_LINK_TIME = 1, the value that is loaded to the timer is 24'h100, which corresponds to a
duration of 1638 ns (256*6.4ns) in USXGMII mode or 2048 ns (256*8ns) in 1000BaseX/SGMII mode.
For configurations without USXGMII: This field forms the upper 16-bit of the 24-bit value that gets loaded
to the link timer.The lower 8-bits are hardcoded as 8'h7D. For example, if CL37_LINK_TIME = 1, the
value that is loaded to the timer is 24'h17D, which corresponds to a duration of 3048 ns (381*8ns).
After programming this register, application should perform either of the following steps, so that the new
values takes effect: - Set CL37_TMR_OVR_RIDE bit (bit[3]) of VR MII MMD Digital Control 1 Register to
1 - FAST_SIM bit of SR Control MMD Control Register should be cleared (if already set) and then set
back to 1.
5.7.25 VR MII MMD Digital Status (VR_MII_DIG_STS)
Offset
Register Offset
VR_MII_DIG_STS 1F_8010h
Function

NXP Semiconductors
XPCS
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXFIF RXFIF LB_AC

R LTX_STATE LRX_STATE PSEQ_STATE Reserv
Reserved O_... O_... TI...
ed
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Fields
Field Function
15-13 Reserved
LTX_STATE
12-10 Reserved
LRX_STATE
9-7 Reserved
6 Rx FIFO Overflow (RO,LH Type) This bit indicates the clock rate compensation FIFO overflow. - 0:
Normal operation - 1: FIFO overflow
RXFIFO_OVF
5 Rx FIFO Underflow (RO,LH Type) This bit indicates the clock rate compensation FIFO underflow. - 0:
Normal operation - 1: FIFO underflow
RXFIFO_UNDF
4-2 Power Up Sequence State

PSEQ_STATE Indicates the state variable value of the power-up sequence module.
000b - Wait for ACK High 0
001b - Wait for ACK Low 0
010b - Wait for ACK High 1
011b - Wait for ACK Low 1
100b - Tx/Rx stable (Power_Good state)
101b - Power Save state
110b - Power Down state
1 Reserved
LB_ACTIVE
0 Reserved

NXP Semiconductors
XPCS
5.7.26 VR MII MMD Invalid Code Group Error Count 1 (VR_MII_ICG_ERRCNT1)
Offset
Register Offset
VR_MII_ICG_ERRCNT1 1F_8011h
Function
This register is present only for 1000BaseX-Only PCS configurations
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R EC0
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
15-8 Reserved
7-0 Invalid Code Group Count Lane 0 (RO,LH Type) This field gives the invalid code group count in Lane 0
when Bit 4 of VR MII MMD Digital Error Count Select Register is set to 1.
EC0
5.7.27 VR MII MMD Digital Error Count Select (VR_MII_DIG_ERRCNT_SEL)
Offset
Register Offset
VR_MII_DIG_ERRCNT_ 1F_8012h
SEL
Function
This register is present only when the XPCS is configured in 1000BASEX-Only PCS mode.

NXP Semiconductors
XPCS
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R INV_E
Reserved Reserved COR
W C_...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
15-5 Reserved
4 Invalid Code Group Error Counter Enable

INV_EC_EN Enables the counting of invalid code group errors.
For information about the fields containing the number of errors counted, see VR MII MMD Invalid Code
Group Error Count1 Register.
0b - Disabled
1b - Enabled
3-1 Reserved
0 Clear on Read
COR When this field is 1 and the host reads any error counter, that counter is cleared after the read cycle.
1b - Clear any error counter that is read
5.7.28 VR MII MMD GPIO (VR_MII_GPIO)
Offset
Register Offset
VR_MII_GPIO 1F_8015h
Function
This register is present only if the XPCS is configured to have the GPIO interface. Note:This register is not present if
USXGMII_EN=Enabled

NXP Semiconductors
XPCS
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R GPIO_IN
GPIO_OUT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
15-8 GPIO Output The content written on this field is driven to the xpcs_gpo_o[7:0] output port. Dependency:
This field is valid only when GPIO_EN = Enabled.
GPIO_OUT
7-0 GPIO Input This field indicates the content of the xpcs_gpo_i[7:0] port. Dependency: This field is valid
only when GPIO_EN = Enabled.
GPIO_IN
5.7.29 VR MII MMD Miscellaneous Status (VR_MII_MISC_STS)
Offset
Register Offset
VR_MII_MISC_STS 1F_8018h
Function
This register is present only when the XPCS is configured in 1000BASEX-Only PCS mode.
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R BIT_SFT
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
15-4 Reserved
3-0 Bit Shift This field indicates the number of bit-shifts carried-out by comma-detect logic so as to align the
incoming 10-bit XGXS Rx data Default Value: The default value of this field can be any value, depending
BIT_SFT on the status of comma-detect logic.

NXP Semiconductors
XPCS
5.7.30 VR MII PHY Rx Lane Status (VR_MII_RX_LSTS)
Offset
Register Offset
VR_MII_RX_LSTS 1F_8020h
Function
In KX_Only, KR_Only, KR_KX, 10GBASE-R PCS, and 1000BASEX-Only PCS configurations, only Lane 0 control and status
information is present. In configurations with both 1G (KX) and 10G (XGXS PCS, 10GBASE-X PCS, or KX4) modes, only
Lane 0 control and status information is used when the XPCS is operating in the 1G mode.
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX_VA RX_PL SIG_D

R RX_VALID_3_1 RX_PLL_STATE_3_1 SIG_DET_3_1
LI... L_... ET... Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
15-13 DPLL Lock Status for Lanes[3:1]

RX_VALID_3_1 This field indicates that the DPLL in the PHY is locked on the serial data in the corresponding lane. -
3'b**1: Lane 1 DPLL bit locked - 3'b*1*: Lane 2 DPLL bit locked - 3'b1**: Lane 3 DPLL bit locked
12 DPLL Lock Status for Lane 0

RX_VALID_0 This field indicates that the DPLL in the PHY is locked on the serial data in Lane 0. The value 1'b1
indicates that Lane 0 DPLL bit is locked.
11-9 Reserved
RX_PLL_STAT
E_3_1
8 Reserved
RX_PLL_STAT
E_0
7-5 Reserved
SIG_DET_3_1
4 Rx Signal Detect for Lane 0

SIG_DET_0 This bit indicates that the Rx detected the signal on Lane 0. This bit is the complement value of the
signals input from PHY (xgxs_los_i[0]) on Lane 0. The value 1'b1 indicates that Lane 0 signal is detected.

NXP Semiconductors
XPCS
Field Function
3-0 Reserved
5.7.31 VR MII PHY Tx General Control 0 (VR_MII_Gen5_12G_16G_TX_GENCTRL0)
Offset
Register Offset
VR_MII_Gen5_12G_16G 1F_8030h
_TX_GENCTRL0
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R TX_DT_EN_3_1 TX_DT TX_RST_3_1 TX_RS TX_INV_3_1 TX_IN TXBCN_EN_3_1 TXBC
W _E... T_0 V_0 N_E...
Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
15-13 Reserved
TX_DT_EN_3_1
12 Tx Data Enable on PHY lane 0

TX_DT_EN_0 When this bit is set, Transmit Output Driver in the PHY is enabled. This bit controls the output port
'xgxs_tx_data_en_o[0]'. This field should be cleared when PHY Tx is not in P0 power state
11-9 Reserved
TX_RST_3_1
8 Tx Reset on PHY lane 0

TX_RST_0 When this bit is set, PHY transmitter is reset, including common-mode adjustment and receiver detection
state machines. This signal drives the output port 'xgxs_tx_reset_o[0]' when XPCS is in POWER_GOOD
state.
7-5 Reserved
TX_INV_3_1
4 Tx Invert on PHY lane 0

NXP Semiconductors
XPCS
Field Function
TX_INV_0 When this bit is set, the data on PHY Tx serial lines are logically inverted. This signal drives the output
port 'xgxs_tx_invert_o[0]'.
3-1 Reserved
TXBCN_EN_3_
1
0 Tx Beaconing Enable on PHY lane 0

TXBCN_EN_0 When this bit is set, PHY enables transmitter beaconing (LFPS). The period for transmit pulses is
between 20-50ns. This field drives the output port 'xgxs_tx_beacon_en_o[0]'.
Offset
Register Offset
_TX_GENCTRL1
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R TX_CLK_RDY_3_1 TX_CL Reserv VBOOST_EN_3_1 VBOO DET_RX_REQ_3_1 DET_R

VBOOST_LVL
W K_... ed ST_... X_...
Reset 0 0 0 1 0 0 1 1 0 0 0 1 0 0 0 0
Fields
Field Function
15-13 Reserved
TX_CLK_RDY_
3_1
12 Transmitter Input clock ready on lane 0

TX_CLK_RDY_ This field drives the output xpcs_tx_clk_rdy_o[0]. This field should remain high, as long as PHY Tx Clock
0 is active
11 Reserved
10-8 Tx Voltage Boost Maximum Level

NXP Semiconductors
XPCS
Field Function
VBOOST_LVL This field controls the maximum achievable Tx swing in the PHY This field drives the output port
'xpcs_tx_vboost_lvl_o[2:0]'.
7-5 Reserved
VBOOST_EN_3
_1
4 Tx voltage Boost Enable on PHY lane 0

VBOOST_EN_0 When this bit is set, the current mode Tx Swing boost in the PHY is enabled. This bit drives the output
port 'xpcs_tx_vboost_en_o[0]'.
3-1 Reserved
DET_RX_REQ_
3_1
0 Transmitter Rx-Detection request on PHY lane 0.

DET_RX_REQ_ This field drives the output port 'xpcs_tx_detrx_req_o[0]'. Whenever this bit is set, a receiver detection
0 request is made towards the PHY on lane 0. Once this bit is set, it should remain high till 'TX_ACK_0' bit
is read as high. When 'TX_ACK_0' is read as high, the result of the Rx Detection operation is available at
field 'DETRX_RSLT_0'. After obtaining the result of 'Rx-Detect operation', this bit should be cleared. Rx
Detection operation is valid only when transmitter is in P1 power state
Offset
Register Offset
_TX_GENCTRL2
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R TX3_WIDTH TX2_WIDTH TX1_WIDTH TX_LPD_3_1 TX_LP TX_REQ_3_1 TX_RE

TX0_WIDTH
W D_0 Q_0
Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
Fields
Field Function
15-14 Reserved

NXP Semiconductors
XPCS
Field Function
TX3_WIDTH
13-12 Reserved
TX2_WIDTH
11-10 Reserved
TX1_WIDTH
9-8 Tx Datapath Width on lane 0 of the PHY This field controls the width of input transmit data on lane 0. The
encoding of the width is as follows : - 2'b00 : 8-bit - 2'b01: 10-bit - 2'b10: 16-bit - 2'b11: 20-bit This field
TX0_WIDTH drives the output port xpcs_tx0_width_o[1:0].
7-5 Reserved
TX_LPD_3_1
4 Transmitter Lane Power Down on PHY lane 0. This field drives the output 'xpcs_tx_lpd_o[3:1]'. This field
can be asserted to put the phy transmitter to a power state equivalent to that of P1.
TX_LPD_0
3-1 Reserved
TX_REQ_3_1
0 Transmitter operation request on PHY lane 0 (RW,SC Type)

TX_REQ_0 This bit drives the output port 'xpcs_tx_req_o[0]. This bit can be set to initiate a new transmitter setting
request. This bit should be set only if TX_ACK_0 field is low. Once this bit is set, application should
monitor TX_ACK_0 field till it becomes 1'b1. This implies that the transmitter request operation has
been successfully completed. Then application should clear this bit. This bit should be asserted to make
sure that the PHY accepts any change to the following signals: - xpcs_tx0_pstate_o - xpcs_tx0_lpd_o -
xpcs_tx0_rate_o - xpcs_tx0_width_o - xpcs_tx0_mplllb_sel.
5.7.34 VR MII PHY Tx Boost Control (VR_MII_Gen5_12G_16G_TX_BOOST_CTRL)
Offset
Register Offset
_TX_BOOST_CTRL

NXP Semiconductors
XPCS
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R TX3_IBOOST TX2_IBOOST TX1_IBOOST

TX0_IBOOST
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
Fields
Field Function
15-12 Reserved
TX3_IBOOST
11-8 Reserved
TX2_IBOOST
7-4 Reserved
TX1_IBOOST
3-0 Tx current boost level on lane 0 of the PHY. This bit drives the output port xpcs_tx0_iboost_lvl_o[3:0].
TX0_IBOOST
5.7.35 VR MII PHY Tx Rate Control (VR_MII_Gen5_12G_16G_TX_RATE_CTRL)
Offset
Register Offset
_TX_RATE_CTRL
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserv TX3_RATE Reserv TX2_RATE Reserv TX1_RATE Reserv

TX0_RATE
W ed ed ed ed
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Fields
Field Function
15 Reserved

NXP Semiconductors
XPCS
Field Function
14-12 Reserved
TX3_RATE
11 Reserved
10-8 Reserved
TX2_RATE
7 Reserved
6-4 Reserved
TX1_RATE
3 Reserved
2-0 Tx date rate on PHY lane 0.

TX0_RATE Data rate encoding is as follows : - 3'b000 : baud - 3'b001 : baud/2 - 3'b010 : baud/4 - 3'b011 : baud/8 -
3'b111 : baud/10 - 3'b100-3'b110 : Not supported
5.7.36 VR MII PHY Tx Power State (VR_MII_Gen5_12G_16G_TX_POWER_STATE_CTRL)
Offset
Register Offset
_TX_POWER_STATE_C
TRL

NXP Semiconductors
XPCS
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R TX_DISABLE_3_1 TX_DI TX3_PSTATE TX2_PSTATE TX1_PSTATE

Reserved TX0_PSTATE
W SA...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
15-12 Reserved
11-9 Reserved
TX_DISABLE_3
_1
8 Transmitter Disable on lane 0 This field drives the output port 'xpcs_tx_disable_o[0]'.
TX_DISABLE_0
7-6 Reserved
TX3_PSTATE
5-4 Reserved
TX2_PSTATE
3-2 Reserved
TX1_PSTATE
1-0 Tx power state control for PHY lane 0.

TX0_PSTATE Power state encoding is as follows: - 2'b00: P0 - 2'b01: P0s - 2'b10: P1 - 2'b11: P2
5.7.37 VR MII PHY Tx Equalization Control 0 (VR_MII_Gen5_12G_16G_TX_EQ_CTRL0)
Offset
Register Offset
_TX_EQ_CTRL0

NXP Semiconductors
XPCS
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved TX_EQ_MAIN Reserved TX_EQ_PRE
W
Reset 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
15-14 Reserved
13-8 Control for setting Tx driver output amplitude

TX_EQ_MAIN This field drives the output port 'rpcs_ktx_main_o' if
VR_MII_Gen5_12G_16G_TX_EQ_CTRL1[TX_EQ_OVR_RIDE] = 1.
7-6 Reserved
5-0 Tx Pre-Emphasis level adjustment Control

TX_EQ_PRE This field controls the transmitter driver output pre-emphasis (pre-shoot coefficient). This field drives the
output port 'rpcs_ktx_pre_o' if VR_MII_Gen5_12G_16G_TX_EQ_CTRL1[TX_EQ_OVR_RIDE] = 1.
5.7.38 VR MII PHY Tx Equalization Control 1 (VR_MII_Gen5_12G_16G_TX_EQ_CTRL1)
Offset
Register Offset
_TX_EQ_CTRL1

NXP Semiconductors
XPCS
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CA_TX TX_EQ TX_EQ

R
Reserved _EQ _D... _O... TX_EQ_POST
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
15-9 Reserved
8 Reserved
CA_TX_EQ
7 Reserved
TX_EQ_DEF_C
TRL
6 Reserved
TX_EQ_OVR_R
IDE
5-0 Tx Post-Emphasis level adjustment Control This field controls the transmitter driver output pre-emphasis
(pre-shoot coefficient). This field drives the output port 'rpcs_ktx_post_o' if 'TX_EQ_OVR_RIDE' bit is set
TX_EQ_POST or in configurations with CL72_EN=Disabled.
5.7.39 VR MII PHY Transmit Termination Control (VR_MII_Consumer_10G_TX_TERM_CTRL)
Offset
Register Offset
VR_MII_Consumer_10G 1F_803Ch
_TX_TERM_CTRL

NXP Semiconductors
XPCS
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved TX0_TERM
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Fields
Field Function
15-3 Reserved
2-0 Transmit Termination Control for lane 0
TX0_TERM
5.7.40 VR MII PHY Tx Status (VR_MII_Gen5_12G_16G_TX_STS)
Offset
Register Offset
_TX_STS
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DETR TX_AC
R DETRX_RSLT_3_1 TX_ACK_3_1
Reserved X_R... K_0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
15-8 Reserved
7-5 Reserved
DETRX_RSLT_
3_1

NXP Semiconductors
XPCS
Field Function
Receiver Detection Result on PHY lane 0. This field captures the value of the input port
4
'xpcs_tx_detrx_result_o[0]'. The value of this field is valid when 'TX_ACK_0' is high. - 1'b0: Receiver
DETRX_RSLT_ not detected - 1'b1: Receiver detected
0
3-1 Reserved
TX_ACK_3_1
0 Tx Acknowledge on PHY lane 0. This bit captures the value of the input port 'xpcs_tx_ack_i[0]'.
Whenever this bit is read as high, it indicates that the requested transmitter setting is complete or
TX_ACK_0 the requested RX-detection operation is complete. Once this bit is read high, it will remain high till bit
TX_REQ_0 or DET_RX_REQ_0 is cleared
5.7.41 VR MII PHY Rx General Control 0 (VR_MII_Gen5_12G_16G_RX_GENCTRL0)
Offset
Register Offset
_RX_GENCTRL0
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RX_CLKSFT_3_1 RX_CL RX_DT_EN_3_1 RX_DT RX_ALIGN_EN_3_1 RX_AL RX_TERM_EN_3_1 RX_TE
W KS... _E... IG... RM...
Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1
Fields
Field Function
15-13 Reserved
RX_CLKSFT_3
_1
Rx clock shift on PHY lane 0. When this bit is set, a 1-bit shift of receive data happens relate to
12
receive clock. This operation works only if alignment enable is disabled. This bit drives the output port
RX_CLKSFT_0 'xpcs_rx_clk_shift_o[0]'.
11-9 Reserved
RX_DT_EN_3_1

NXP Semiconductors
XPCS
Field Function
8 Rx Data Enable on PHY lane 0. This bit should be set to enable the PHY receiver data output on lane 0.
This bit drives the output port 'xgxs_rx_data_en_o[0]'.
RX_DT_EN_0
7-5 Reserved
RX_ALIGN_EN
_3_1
4 Rx Data Alignment Enable on PHY lane 0. This bit can be set to enable word alignment (based on k28.5
character) in the PHY. This field drives the output port 'xgxs_rx_align_en_o[0]'.
RX_ALIGN_EN
_0
3-1 Reserved
RX_TERM_EN_
3_1
0Rx Termination Enable on PHY lane 0. When this bit is set, PHY Rx is terminated with a nominal
50 ohm resistance. Otherwise, the termination is in high impedance. This field drives the output port
RX_TERM_EN_ 'xpcs_rx_term_en_o[0]'.
0
Offset
Register Offset
_RX_GENCTRL1
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RX_TERM_ACDC_3_1 RX_TE RX_RST_3_1 RX_RS RX_INV_3_1 RX_IN

Reserved
W RM... T_0 V_0
Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
Fields
Field Function
15-12 Reserved

NXP Semiconductors
XPCS
Field Function
11-9 Reserved
RX_TERM_AC
DC_3_1
8 Rx Termination control on PHY lane 0. - 0: DC Termination (Floating Rx) - 1: AC Termination (Grounded

Rx) This field drives the output port xpcs_rx_term_acdc_o[0].
RX_TERM_AC
DC_0
7-5 Reserved
RX_RST_3_1
4 Rx reset on PHY lane 0. When this bit is set, RX data path, all the receiver settings and state
machines of the PHY are reset This field drives the output port xgxs_rx_reset_o[0] when XPCS is in
RX_RST_0 POWER_GOOD state.
3-1 Reserved
RX_INV_3_1
0 Rx Data Invert on PHY lane 0. When this bit is set, the data on PHY Rx serial lines are logically inverted.
This signal drives the output port xgxs_rx_invert_o[0].
RX_INV_0
Offset
Register Offset
_RX_GENCTRL2
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RX3_WIDTH RX2_WIDTH RX1_WIDTH RX_LPD_3_1 RX_LP RX_REQ_3_1 RX_RE

RX0_WIDTH
W D_0 Q_0
Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
Fields
Field Function
15-14 Reserved

NXP Semiconductors
XPCS
Field Function
RX3_WIDTH
13-12 Reserved
RX2_WIDTH
11-10 Reserved
RX1_WIDTH
9-8 Rx Datapath Width on lane 0 of the PHY This field controls the width of output receive data from PHY on
lane 3. The encoding of the width is as follows : - 2'b00: 8-bit - 2'b01: 10-bit - 2'b10: 16-bit - 2'b11: 20-bit
RX0_WIDTH This field drives the output port xpcs_rx0_width[1:0].
7-5 Reserved
RX_LPD_3_1
4 Receiver Lane Power Down on PHY lane 0. This bit can be set to power down the receiver to a power
state equivalent to that of P1. This bit drives the output port 'xpcs_rx_lpd_o[0]'.
RX_LPD_0
3-1 Reserved
RX_REQ_3_1
0 Receiver operation request on PHY lane 0 (RW,SC Type). This bit can be set to 1 by application.This
bit is self-cleared when 'xpcs_tx_ack_i[0]' is asserted. When this bit is set, a new receiver setting request
RX_REQ_0 is made towards the PHY.This bit drives the output port xpcs_rx_req_o[0]. Whenever this bit is set,
PHY captures its following input signals: - rx0_pstate[1:0] - rx0_lpd - rx0_rate[1:0] - rx0_width[1:0]
- rx0_data_en - rx0_adapt_afe_en - rx0_adapt_dfe_en - rx0_eq_att_lvl[2:0] - rx0_eq_vga1_gain[3:0]
- rx0_eq_vga2_gain[3:0] - rx0_eq_ctle_pole[2:0] - rx0_eq_ctle_boost[4:0] - rx0_eq_dfe_tap1[7:0] A
successful completion of receiver request operation on lane 0 is indicated by bit RX_ACK_0.
Offset
Register Offset
_RX_GENCTRL3

NXP Semiconductors
XPCS
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R LOS_LFPS_EN_3_1 LOS_L LOS_TRSHLD_3 LOS_TRSHLD_2 LOS_TRSHLD_1

LOS_TRSHLD_0
W FP...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Fields
Field Function
15-13 Reserved
LOS_LFPS_EN
_3_1
12 Rx LOS LFPS Enable on lane 0 of the PHY This field drives the output port xpcs_rx_los_lfps_en_o[0] to
enable the LFPS filter on lane 0 of the PHY.
LOS_LFPS_EN
_0
11-9 Reserved
LOS_TRSHLD_
3
8-6 Reserved
LOS_TRSHLD_
2
5-3 Reserved
LOS_TRSHLD_
1
Loss of signal threshold on PHY lane 0. This field drives the output port xpcs_rx0_los_threshold_o[2:0].
2-0
Threshold voltages for various values are as follows : - 3'b000: Reserved - 3'b001: 90 mVpp - 3'b010:
LOS_TRSHLD_ 120 mVpp - 3'b011: 150 mVpp - 3'b100: 180 mVpp - 3'b101: 210 mVpp - 3'b110: 240 mVpp - 3'b111:
0 270 mVpp
5.7.45 VR MII PHY Rx Rate Control (VR_MII_Gen5_12G_16G_RX_RATE_CTRL)
Offset
Register Offset
_RX_RATE_CTRL

NXP Semiconductors
XPCS
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RX3_RATE RX2_RATE RX1_RATE

Reserved Reserved Reserved Reserved RX0_RATE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Fields
Field Function
15-14 Reserved
13-12 Reserved
RX3_RATE
11-10 Reserved
9-8 Reserved
RX2_RATE
7-6 Reserved
5-4 Reserved
RX1_RATE
3-2 Reserved
1-0 Rx date rate on lane 0 of the PHY Data Rate Encoding is as follows : - 2'b00: baud - 2'b01: baud/2 -
2'b10: baud/4 - 2'b11: baud/8
RX0_RATE
5.7.46 VR MII PHY Rx Power State (VR_MII_Gen5_12G_16G_RX_POWER_STATE_CTRL)
Offset
Register Offset
_RX_POWER_STATE_C
TRL

NXP Semiconductors
XPCS
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EEE_O
R RX_DISABLE_3_1 RX_DI RX3_PSTATE RX2_PSTATE RX1_PSTATE
Reserved VR... RX0_PSTATE
SA...
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
15-13 Reserved
12 Reserved
EEE_OVR_RID
E
11-9 Reserved
RX_DISABLE_3
_1
8 Receiver Disable on lane 0 This bit can be set in P1 power state to put the receiver in a low power mode.
This field drives the output port 'xpcs_rx_disable_o[0]'.
RX_DISABLE_0
7-6 Reserved
RX3_PSTATE
5-4 Reserved
RX2_PSTATE
3-2 Reserved
RX1_PSTATE
1-0 Rx power state control for PHY lane 0. Power state encoding is as follows : - 2'b00: P0 - 2'b01: P0s -
2'b10: P1 - 2'b11: P2
RX0_PSTATE
5.7.47 VR MII PHY Rx CDR Control (VR_MII_Gen5_12G_16G_RX_CDR_CTRL)
Offset
Register Offset
_RX_CDR_CTRL

NXP Semiconductors
XPCS
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VCO_LOW_FREQ_3_1 VCO_L CDR_SSC_EN_3_1 CDR_ CDR_TRACK_EN_3_1 CDR_T

Reserved
W OW... SSC... RA...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Fields
Field Function
15-12 Reserved
11-9 Reserved
VCO_LOW_FR
EQ_3_1
Rx VCO lower frequency band mode on lane 0 of the PHY This field controls the frequency
8
of the Rx VCO to a lower-frequency operating band. This field drives the output port
VCO_LOW_FR xpcs_rx_cdr_vco_lowfreq_o[0].
EQ_0
7-5 Reserved
CDR_SSC_EN_
3_1
4Rx CDR SSC Mode Enable on lane 0 of the PHY This field controls the CDR tracking gains and duration.
This bit should be set to 1 when receive data has a spread spectrum clock and should be cleared if
CDR_SSC_EN_ receive data does not have SSC. This bit drives the output port 'xpcs_rx_cdr_ssc_en_o[0]'.
0
3-1 Reserved
CDR_TRACK_E
N_3_1
0 Rx CDR Tracking Enable on lane 0 of the PHY This bit should be set to enable CDR tracking of receive
data on lane 0 of the PHY. This bit drives the output port 'xpcs_rx_cdr_track_en_o[0]'.
CDR_TRACK_E
N_0
5.7.48 VR MII PHY Rx Attenuation Control (VR_MII_Gen5_12G_16G_RX_ATTN_CTRL)
Offset
Register Offset
_RX_ATTN_CTRL

NXP Semiconductors
XPCS
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserv RX3_EQ_ATT_LVL Reserv RX2_EQ_ATT_LVL Reserv RX1_EQ_ATT_LVL Reserv

RX0_EQ_ATT_LVL
W ed ed ed ed
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
15 Reserved
14-12 Reserved
RX3_EQ_ATT_
LVL
11 Reserved
10-8 Reserved
RX2_EQ_ATT_
LVL
7 Reserved
6-4 Reserved
RX1_EQ_ATT_
LVL
3 Reserved
2-0 Rx Equalization Attenuation level for lane 0 of the PHY This field drives the output port
xpcs_rx0_eq_att_lvl_o[2:0]. This field controls the AFE attenuation level of the PHY.
RX0_EQ_ATT_
LVL
5.7.49 VR MII PHY Rx Equalization Control 0 (VR_MII_Gen5_12G_RX_EQ_CTRL0)
Offset
Register Offset
VR_MII_Gen5_12G_RX_ 1F_8058h
EQ_CTRL0

NXP Semiconductors
XPCS
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
AFE_GAIN_0 Reserved CTLE_BOOST_0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
Fields
Field Function
15-12 Rx Equalization AFE Gain on lane 0 of the PHY This field drives the output port
xpcs_rx0_eq_afe_gain_o[3:0].
AFE_GAIN_0
11-5 Reserved
4-0 Rx Equalization CTLE Boost value on lane 0 of the PHY This field drives the output port
xpcs_rx0_eq_ctle_boost_o[4:0].This field controls the CTLE boost level.
CTLE_BOOST_
0
5.7.50 VR MII PHY Rx Equalization Control 4 (VR_MII_Gen5_12G_16G_RX_EQ_CTRL4)
Offset
Register Offset
VR_MII_Gen5_12G_16G 1F_805Ch
_RX_EQ_CTRL4
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX_A RX_E SELF_ PING_ SEQ_

R CONT_OFF_CAN_3_1 CONT CONT_ADAPT_3_1 CONT
Reserved D_R... Q_S... MA... PO... EQ_...
_OF... _AD...
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Fields
Field Function
15-13 Reserved
12 Reserved

NXP Semiconductors
XPCS
Field Function
RX_AD_REQ
11 Reserved
RX_EQ_STRT_
CTRL
10 Reserved
SELF_MAIN_E
N
9 Reserved
PING_PONG_E
N
8 Reserved
SEQ_EQ_EN
7-5 Reserved
CONT_OFF_CA
N_3_1
4 Receiver offset cancellation continuous operation on lane 0 This bit can be set if continuous receiver
offset cancellation is required. If this bit is 0, offset cancellation runs when receiver exits P2 power state.
CONT_OFF_CA This bit drives the output port 'xpcs_rx_offcan_cont_o[0]'.
N_0
3-1 Reserved
CONT_ADAPT_
3_1
0 Receiver Adaptation Continuous Operation on lane 0 This bit can be set to enable continuous receiver
adaptation in the PHY. This bit drives the output port 'xpcs_rx_offcan_cont_o'.
CONT_ADAPT_
0
5.7.51 VR MII PHY AFE-DFE Enable (VR_MII_Gen5_12G_AFE_DFE_EN_CTRL)
Offset
Register Offset
VR_MII_Gen5_12G_AFE 1F_805Dh
_DFE_EN_CTRL

NXP Semiconductors
XPCS
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DFE_EN_3_1 DFE_ AFE_EN_3_1 AFE_

Reserved
W EN_0 EN_0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
15-8 Reserved
7-5 Reserved
DFE_EN_3_1
4 Rx DFE Enable on lane 0 of the PHY This bit drives the output port xpcs_rx_adapt_dfe_en_o[0]. This
bit can be set to enable Rx adaption and decision feedback equalization (DFE) circuitry and applies
DFE_EN_0 the input setting of DFE Tap1: -rx0_eq_dfe_tap1[7:0]. If this bit is not set, the change on the input DFE
settings can be applied using a 'RX_REQ_0/RX_ACK_0' handshake. If this bit is set, DFE settings are
initialized to the inputs and RX DFE adaption routines are executed to achieve optimal DFE settings.
3-1 Reserved
AFE_EN_3_1
0 Rx Adaptation AFE Enable on lane 0 of the PHY This bit drives the output port
xpcs_rx_adapt_afe_en_o[0]. This bit can be set to enable Rx adaption circuitry and applies the
AFE_EN_0 following input receiver equalization settings to the PHY: - rx0_eq_att_lvl[2:0] - rx0_eq_vga1_gain[3:0]
- rx0_eq_vga2_gain[3:0] - rx0_eq_ctle_pole[2:0] - rx0_eq_ctle_boost[4:0] If this bit is not set, change
on input AFE settings can be applied using RX_REQ_0/RX_ACK_0 handshake. If this bit is set, AFE
equalization settings are initialized to the PHY inputs, but any further change on these inputs are ignored
by PHY and RX AFE adaption routines are executed to achieve optimal AFE settings
5.7.52 VR MII PHY DFE Tap Control 0 (VR_MII_Gen5_12G_16G_DFE_TAP_CTRL0)
Offset
Register Offset
VR_MII_Gen5_12G_16G 1F_805Eh
_DFE_TAP_CTRL0

NXP Semiconductors
XPCS
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DFE_TAP1_1
DFE_TAP1_0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
15-8 Reserved
DFE_TAP1_1
7-0 Rx Equalization DFE Tap1 value on lane 0 of the PHY This field drives the output port
xpcs_rx0_eq_dfe_tap1_o[7:0]
DFE_TAP1_0
5.7.53 VR MII PHY Rx Status (VR_MII_Gen5_12G_16G_RX_STS)
Offset
Register Offset
_RX_STS
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX_AC
R RX_ACK_3_1
Reserved K_0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
15-4 Reserved
3-1 Reserved
RX_ACK_3_1
0 Rx Acknowledge on PHY lane 0. This bit captures the value of the input port xpcs_rx_ack_i[0]. If this
bit is set, it indicates that the requested receiver setting is complete. This bit forms a hand-shake with
RX_ACK_0 'RX_REQ_0' bit. Once this bit is set, RX_REQ_0 bit is self-cleared.

NXP Semiconductors
XPCS
5.7.54 VR MII PHY Receive Termination Control (VR_MII_Consumer_10G_RX_TERM_CTRL)
Offset
Register Offset
VR_MII_Consumer_10G 1F_8064h
_RX_TERM_CTRL
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved RX0_TERM
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Fields
Field Function
15-3 Reserved
2-0 Receive Termination Control for lane 0
RX0_TERM
5.7.55 VR MII PHY RX IQ Control 0 (VR_MII_Consumer_10G_RX_IQ_CTRL0)
Offset
Register Offset
VR_MII_Consumer_10G 1F_806Bh
_RX_IQ_CTRL0

NXP Semiconductors
XPCS
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved RX0_DELTA_IQ Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
15-12 Reserved
11-8 RX IQ Offset Value for lane0. This field drives the output port xpcs_rx0_delta_iq_o[3:0].
RX0_DELTA_IQ
7-0 Reserved
5.7.56 VR MII PHY MPLL Common Control (VR_MII_Gen5_12G_16G_MPLL_CMN_CTRL)
Offset
Register Offset
_MPLL_CMN_CTRL
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R MPLLB_SEL_3_1 MPLLB MPLL_EN_3_1 MPLL_

Reserved
W _S... EN...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Fields
Field Function
15-8 Reserved
7-5 Reserved

NXP Semiconductors
XPCS
Field Function
MPLLB_SEL_3_
1
4 Tx MPLLB Select-lane 0 When this bit is set, PHY selects MPLLB to generate Tx analog clocks on lane
0
MPLLB_SEL_0
3-1 Reserved
MPLL_EN_3_1
0 Tx MPLL Enable-lane 0 This bit should be set to power-up the MPLL.This bit should be 1, for normal
operation.
MPLL_EN_0
5.7.57 VR MII PHY MPLLA Control 0 (VR_MII_Gen5_12G_16G_MPLLA_CTRL0)
Offset
Register Offset
_MPLLA_CTRL0
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R MPLLA
Reserved Reserved MPLLA_MULTIPLIER
W _C...
Reset 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0
Fields
Field Function
15 MPLLA Calibration Disable This field can be programmed to 1, to disable calibration of MPLLA by PHY
firmware.
MPLLA_CAL_DI
SABLE
14-11 Reserved
10-8 Reserved

NXP Semiconductors
XPCS
Field Function
MPLLA frequency Multiplier Control This field controls the multiplication of reference clock to a frequency
7-0
suitable for operating speed Any change in this field should be followed by a Vendor-specific Soft Reset
MPLLA_MULTI to ensure that PHY is properly powered-up in the desired mode.
PLIER
5.7.58 VR MII PHY MPLLA Control 1 (VR_MII_Gen5_12G_MPLLA_CTRL1)
Offset
Register Offset
VR_MII_Gen5_12G_MPL 1F_8072h
LA_CTRL1
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserv
MPLLA_FRACN_CTRL Reserved
W ed
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
15-5 MPLLA Fractional Control This field drives the output port xpcs_mplla_fracn_ctrl_o.
MPLLA_FRACN
_CTRL
4 Reserved
3-0 Reserved
5.7.59 VR MII PHY MPLLA Control 2 (VR_MII_Gen5_12G_16G_MPLLA_CTRL2)
Offset
Register Offset
_MPLLA_CTRL2

NXP Semiconductors
XPCS
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserv Reserv MPLL MPLL MPLL

MPLLA_TX_CLK_DIV MPLLA_DIV_MULT
W ed ed A_D... A_D... A_D...
Reset 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0
Fields
Field Function
15 Reserved
14 Reserved
13-11 MPLLA Tx Clock Divider. This field drives the output port 'xpcs_mplla_tx_clk_div_o[1:0]'.
MPLLA_TX_CL
K_DIV
10 Enable mplla_div_clk from PHY. When asserted, the frequency of mplla_div_clk from PHY is the MPLLA
frequency divided by 'mplla_div_multiplier'
MPLLA_DIV_CL
K_EN
9 MPLLA Divide by 10 Enable When this bit is set, the frequency of the mplla_word_clk output clock from
PHY is MPLLA frequency divided by 10.
MPLLA_DIV10_
CLK_EN
8 MPLLA Divide by 8 Enable When this bit is set, the frequency of the mplla_word_clk output clock from
PHY is MPLLA frequency divided by 8.
MPLLA_DIV8_C
LK_EN
7-0 MPLLA Output Frequency Multiplier Control This field controls the frequency multiplication factor used to
generate MPLLA clock output from the reference clock input as seen by the MPLL.
MPLLA_DIV_M
ULT
5.7.60 VR MII PHY MPLLB Control 0 (VR_MII_Gen5_12G_16G_MPLLB_CTRL0)
Offset
Register Offset
_MPLLB_CTRL0

NXP Semiconductors
XPCS
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R MPLLB
Reserved Reserved MPLLB_MULTIPLIER
W _C...
Reset 1 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1
Fields
Field Function
15 MPLLB Calibration Disable This field can be programmed to 1, to disable calibration of MPLLB by PHY
firmware.
MPLLB_CAL_DI
SABLE
14-11 Reserved
10-8 Reserved
MPLLB frequency Multiplier Control This field controls the multiplication of reference clock to a frequency
7-0
suitable for operating speed Any change in this field should be followed by a Vendor-specific Soft Reset
MPLLB_MULTI to ensure that PHY is properly powered-up in the desired mode.
PLIER
5.7.61 VR MII PHY MPLLB Control 1 (VR_MII_Gen5_12G_MPLLB_CTRL1)
Offset
Register Offset
LB_CTRL1
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserv
MPLLB_FRACN_CTRL Reserved
W ed
Reset 0 0 0 0 0 0 0 0 0 0 0 u 0 0 0 0
Fields
Field Function
15-5 MPLLB Fractional Control This field drives the output port 'xpcs_mpllb_fracn_ctrl_o'.

NXP Semiconductors
XPCS
Field Function
MPLLB_FRACN
_CTRL
4 Reserved
3-0 Reserved
5.7.62 VR MII PHY MPLLB Control 2 (VR_MII_Gen5_12G_16G_MPLLB_CTRL2)
Offset
Register Offset
_MPLLB_CTRL2
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserv Reserv MPLL MPLL MPLL

MPLLB_TX_CLK_DIV MPLLB_DIV_MULT
W ed ed B_D... B_D... B_D...
Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
15 Reserved
14 Reserved
13-11 MPLLB Tx Clock Divider. This field drives the output port 'xpcs_mpllb_tx_clk_div_o[1:0]'.
MPLLB_TX_CL
K_DIV
10 Enable mpllb_div_clk from PHY When asserted, the frequency of mpllb_div_clk output from PHY is
MPLLB frequency divided by 'mpllb_div_multiplier'
MPLLB_DIV_CL
K_EN

NXP Semiconductors
XPCS
Field Function
9 MPLLB Divide by 10 Enable When this bit is set, the frequency of the mpllb_word_clk output clock from
PHY is MPLLB frequency divided by 10.
MPLLB_DIV10_
CLK_EN
8 MPLLB Divide by 8 Enable When this bit is set, the frequency of the mpllb_word_clk output clock from
PHY is MPLLB frequency divided by 8.
MPLLB_DIV8_C
LK_EN
7-0 MPLLB Output Frequency Multiplier Control This field controls the frequency multiplication factor used to
generate MPLLB clock output from the reference clock input as seen by the MPLL.
MPLLB_DIV_M
ULT
5.7.63 VR MII PHY MPLLA Control 3 (VR_MII_Gen5_12G_MPLLA_CTRL3)
Offset
Register Offset
LA_CTRL3
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MPLLA_BANDWIDTH
W
Reset 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 1
Fields
Field Function
15-0 MPLLA Bandwidth Control This field controls the bandwidth of MPLLA present in the PHY. This field
drives the output port 'xpcs_mplla_bandwidth_o'.
MPLLA_BAND
WIDTH

NXP Semiconductors
XPCS
5.7.64 VR MII PHY MPLLB Control 3 (VR_MII_Gen5_12G_MPLLB_CTRL3)
Offset
Register Offset
LB_CTRL3
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MPLLB_BANDWIDTH
W
Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0
Fields
Field Function
15-0 MPLLB Bandwidth Control This field controls the bandwidth of MPLLB present in the PHY. This field
drives the output port 'xpcs_mpllb_bandwidth_o'.
MPLLB_BAND
WIDTH
5.7.65 VR MII PHY Miscellaneous Control 0 (VR_MII_Gen5_12G_16G_MISC_CTRL0)
Offset
Register Offset
_MISC_CTRL0
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R PLL_ CR_P RTUN RX2TX_LB_EN_3_1 RX2TX TX2RX_LB_EN_3_1 TX2RX

RX_VREF_CTRL
W CTRL ARA... E_R... _L... _L...
Reset 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0
Fields
Field Function
15 PLL Reinitialization Control

NXP Semiconductors
XPCS
Field Function
PLL_CTRL If the PHY PLL does not lock for a long time, XPCS would initiate a Rx power-state change from P0
to P1 and then back to P0, if this bit is set. This process is done to re-initialize the PLL. The time
duration to wait before reinitializing the PLL is determined by VR MII PHY Miscellaneous Control 1
(VR_MII_Gen5_12G_16G_MISC_CTRL1).
14 Select CR Para Port This bit select the interface for accessing PHY registers * 0 -JTAG * 1 -CR parallel
port This bit should be changed only after disabling 'jtag_tck'to PHY.
CR_PARA_SEL
13 Resistor Tuning Request This bit can be set to trigger a resistor tune request to the PHY. This bit
controls the 'xgxs_rtune_req_o' output port.
RTUNE_REQ
12-8 Rx Biasing Current Control

RX_VREF_CTR This field drives the output port 'xpcs_rx_vref_ctrl_o[4:0]'. This field sets the Rx biasing current for Rx
L analog front end.
7-5 Reserved
RX2TX_LB_EN
_3_1
4 Enable Parallel Rx-to-Tx Loopback on lane 0 When this bit is set, recovered parallel data from PHY
receiver is looped back to the transmit serializer. This loop-back takes place internal to the PHY (not
RX2TX_LB_EN within XPCS).
_0
3-1 Reserved
TX2RX_LB_EN
_3_1
0 Enable Analog Tx-to-Rx Serial Loopback on lane 0 This bit can be set to enable serial loopback in the
PHY from Tx pre-driver to Rx analog front-end.
TX2RX_LB_EN
_0
5.7.66 VR MII SPHY Reference Control (VR_MII_Gen5_12G_16G_REF_CLK_CTRL)
Offset
Register Offset
_REF_CLK_CTRL

NXP Semiconductors
XPCS
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R REF_R REF_ REF_ REF_C REF_U REF_C

Reserved REF_RANGE
W PT... MPL... MPL... LK... SE... LK...
Reset 0 0 0 0 0 0 0 0 0 1 0 1 0 1 1 1
Fields
Field Function
15-9 Reserved
8 Repeat Reference Clock Enable If this bit is set, ref_repeat_clk_{p,m} clock from PHY is enabled.
REF_RPT_CLK
_EN
7 MPLLB Reference Clock Divider Control

REF_MPLLB_D The reference clock used for MPLLB calibration and locking can be divided by 2 by setting this bit to
IV2 1. This division is applied after ref_clk_div2_en. Hence the total division ratio (from the input reference
clock) can be 1, 2 or 4
6 MPLLA Reference Clock Divider Control

REF_MPLLA_D The reference clock used for MPLLA calibration and locking can be divided by 2 by setting this bit to
IV2 1. This division is applied after ref_clk_div2_en. Hence the total division ratio (from the input reference
clock) can be 1, 2 or 4.
5-3 Input Reference Clock Range

REF_RANGE This field specifies the frequency range of the input reference clock (post ref_clk_div2_en division if any).
This field should be set to appropriate values based on your reference clock frequency.
000b - 20 - 26 MHz
001b - 26.1 - 52 MHz
010b - 52.1 - 78 MHz
011b - 78.1 - 104 MHz
100b - 104.1 - 130 MHz
101b - 130.1 - 156 MHz
110b - 156.1 - 182 MHz
111b - 182.1 - 200 MHz
2 Reference Clock divide by 2

REF_CLK_DIV2 If this bit is set, reference clock provided to PHY gets divided by 2 internally in the PHY.
1 Use Pad Clock As Reference Clock

REF_USE_PAD Selects the reference clock for the PHY.

NXP Semiconductors
XPCS
Field Function
0b - Internal PLL
1b - External clock
0 Reference Clock Enable

REF_CLK_EN This bit should be set to enable reference clock to the PHY.This bit controls the xpcs_ref_clk_en_o output
port. The value programmed to this bit is driven on xpcs_ref_clk_en_o when LPM (power-down) bit is
programmed to 1. When the LPM bit is programmed to 0, xpcs_ref_clk_en_o remains high.
5.7.67 VR MII PHY VCO Calibration Load 0 (VR_MII_Gen5_12G_16G_VCO_CAL_LD0)
Offset
Register Offset
_VCO_CAL_LD0
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved VCO_LD_VAL_0
W
Reset 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 0
Fields
Field Function
15-13 Reserved
12-0 Rx VCO calibration load value on lane 0 of the PHY

VCO_LD_VAL_ This field is used to load internal calibration registers in the PHY to perform Rx VCO calibration on lane
0 0. This field drives the output port 'xpcs_rx0_vco_ld_val_o[5:0]'.
5.7.68 VR MII PHY VCO Calibration Reference 0 (VR_MII_Gen5_12G_VCO_CAL_REF0)
Offset
Register Offset
VR_MII_Gen5_12G_VC 1F_8096h
O_CAL_REF0

NXP Semiconductors
XPCS
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VCO_REF_LD_1
Reserved Reserved VCO_REF_LD_0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1
Fields
Field Function
15-14 Reserved
13-8 Reserved
VCO_REF_LD_
1
7-6 Reserved
5-0 Rx VCO calibration reference load value -lane 0

VCO_REF_LD_ This field controls the PHY's internal calibration registers used to perform Rx VCO calibration on lane 0.
0 This field drives the output port 'xpcs_rx0_ref_ld_val_o[5:0]'.
5.7.69 VR MII PHY Miscellaneous Status (VR_MII_Gen5_12G_16G_MISC_STS)
Offset
Register Offset
_MISC_STS

NXP Semiconductors
XPCS
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REF_C MPLL MPLL RTUN

R FOM
Reserved LK... B_S... A_S... E_A...
Reset 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
Fields
Field Function
15-12 Reserved
11 Reserved
REF_CLKDET_
RESULT
10 Status of MPLLB from PHY This bit denotes the value of xpcs_mpllb_state_i input.
MPLLB_STS
9 Status of MPLLA from PHY. This bit denotes the value of xpcs_mplla_state_i input
MPLLA_STS
8 Acknowledgment for Resistor Tune Request This bit denotes the value of 'xgxs_rtune_ack_i' input.
RTUNE_ACK
7-0 Reserved
FOM
5.7.70 VR MII PHY Miscellaneous Control 1 (VR_MII_Gen5_12G_16G_MISC_CTRL1)
Offset
Register Offset
_MISC_CTRL1

NXP Semiconductors
XPCS
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
RX_LNK_UP_TIME
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Fields
Field Function
15-0 Wait Time before PLL Re-initialization

RX_LNK_UP_TI This field determines the number of 'clk_csr_i' clock cycles that can elapse before the Rx link is
ME established (after XPCS has reached POWER_GOOD state). This field is relevant only if you write 1
to VR_MII_Gen5_12G_16G_MISC_CTRL0[PLL_CTRL]. If the receive link is not up (or if frame lock does
not happen during CL72 Training or if AN page is not received), within this specified interval, XPCS
would program the PHY Rx power state to P1 and would then bring it back to P0 (thus re-initializing the
PHY PLL).
5.7.71 VR MII PHY CR Control (VR_MII_SNPS_CR_CTRL)
Offset
Register Offset
VR_MII_SNPS_CR_CTR 1F_80A0h
L
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R WR_ START
Reserved
W RDN _B...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
15-2 Reserved
1 Write or Read Indicator This bit indicates whether a read or write operation is to be performed to the
Synopsys PHY registers: - 0: Read - 1: Write
WR_RDN
0 Start CR Port Access or Busy Indicator (WS,SC Type)

NXP Semiconductors
XPCS
Field Function
START_BUSY This bit indicates if CR port access is in progress: - 0: CR port not busy - 1: CR port busy The sequence
is: 1. The host sets this bit to start a read or write transfer through the CR port to the Synopsys PHY
registers. 2. This bit remains set during the CR port access. 3. The XPCS clears this bit when the CR
port access is complete. Dependencies: The host must read this bit as 0 before writing to any of the
following registers: - VR MII Synopsys PHY CR Control Register (this register) - VR MII Synopsys PHY
CR Address Register - VR MII Synopsys PHY CR Data Register During read, the data from the CR port
interface is placed into the VR MII Synopsys PHY CR Data Register.
5.7.72 VR MII PHY CR Address (VR_MII_SNPS_CR_ADDR)
Offset
Register Offset
VR_MII_SNPS_CR_ADD 1F_80A1h
R
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ADDRESS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
15-0 CR Port Address

ADDRESS Indicates the address of the register to be accessed through the CR port.
Dependencies:
• The host must not change this field when VR_MII_SNPS_CR_CTRL[START_BUSY] = 1.
• You must write to this field before writing to any of the following registers:
— VR MII PHY CR Control (VR_MII_SNPS_CR_CTRL)
— VR_MII_SNPS_CR_ADDR (this register)
— VR MII CR Data (VR_MII_SNPS_CR_DATA)

NXP Semiconductors
XPCS
5.7.73 VR MII CR Data (VR_MII_SNPS_CR_DATA)
Offset
Register Offset
VR_MII_SNPS_CR_DAT 1F_80A2h
A
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DATA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
15-0 CR Port Data

DATA Contains the data for CR port access.
During a write operation, the data in this register is written to the Synopsys PHY register pointed by the CR
Port Address.
During a read operation, the data read from the Synopsys PHY is written to this register. The content
becomes valid only when XPCS writes 0 to VR_MII_SNPS_CR_CTRL[START_BUSY]. The host must not
change this field when VR_MII_SNPS_CR_CTRL[START_BUSY] = 1.
5.7.74 VR MII MMD Digital Control 2 (VR_MII_DIG_CTRL2)
Offset
Register Offset
VR_MII_DIG_CTRL2 1F_80E1h
Function
This register is present only when XPCS is configured in 1000BASEX-Only PCS mode.

NXP Semiconductors
XPCS
Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R TX_PO RX_P
Reserved Reserved
W L_... OL_...
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fields
Field Function
15-5 Reserved
4 Tx Polarity Invert
TX_POL_INV_0 Controls the polarity inversion of the data on the Tx differential lines.
When this field is 1, the data is inverted on the lane connected to its XPCS instance.
0b - Not inverted
1b - Inverted
3-1 Reserved
0 Rx Polarity Invert
RX_POL_INV_0 Controls the polarity inversion of the data received on the Rx serial line.
When this field is 1, the data is inverted on the lane connected to its XPCS instance. This reverses the
polarity on the data received from the PHY core.
0b - Not inverted
1b - Inverted

NXP Semiconductors
Chapter 6
Revision History
The following table lists the technical changes compared to Rev. 5. The current release also includes editorial changes such as
spelling, punctuation, grammar, voice, style, presentation, and navigation.
Table 84. Revision history
Location Technical changes
PLL usage Moved this section from PHY to Introduction to the Subsystem.
VR MII PHY Tx Equalization Control 0 Changed the reset value of the TX_EQ_MAIN field (was Ch, is 18h).

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NXP Semiconductors Document identifier: S32G2SERDESRM

Reference Manual Rev. 6, 8 Nov 2022

S32G2 SerDes Subsystem Reference Manual

Chapter 2 SerDes_SS register descriptions........................................................ 10

S32G2 SerDes Subsystem Reference Manual , Rev. 6, 8 Nov 2022

2.29 PCIe PHY Calibration Control For Gen2 Speed (PCIE_PHY_EXT_CALI_CTRL_2)............. 44

S32G2 SerDes Subsystem Reference Manual , Rev. 6, 8 Nov 2022

2.84 Reset Control (RST_CTRL).................................................................................................127

Chapter 3 PCIe Controller..................................................................................129

Chapter 5 XPCS................................................................................................ 906

Chapter 6 Revision History................................................................................ 987

S32G2 SerDes Subsystem Reference Manual , Rev. 6, 8 Nov 2022

Table 1. Subsystem components

Component Description See section

One PCIe controller Provides a solution to implement a PCIe PCIe Controller

One PHY Supports various PCIe and Ethernet PHY

1.1 Copyright and permissions

1.2 Block diagram

S32G2 SerDes Subsystem Reference Manual , Rev. 6, 8 Nov 2022

PHY (serves as SerDes)

Figure 1. Subsystem block diagram†

1.3 Subsystem working modes

1.4 Selecting a working mode

Table 2. Selecting a working mode

2 Program SS_RW_REG_0[SUBSYS_MODE] with the desired mode number.

3 If you are using an internal reference clock, write 1 to SS_RW_REG_0[CLKEN].

4 Wait for at least 10 μs.

1.5 Enabling 2.5G SGMII with PCIe on SerDes lane 0

S32G2 SerDes Subsystem Reference Manual , Rev. 6, 8 Nov 2022

Table 3. Enabling 2.5G SGMII with PCIe on SerDes lane 0

1 If you are using the internal reference clock, write 1 to VR_MII_DIG_CTRL1[BYP_PWRUP].

3 In VR MII MMD Debug Control (VR_MII_DBG_CTRL):

4 In PCIe PHY Miscellaneous Control 2 (PCIE_PHY_EXT_MISC_CTRL_2):

6 In PCIe Reference Clock Control (PCIE_PHY_REF_CLK_CTRL):

7 In PCIe PHY MPLLB Control 2 (PCIE_PHY_EXT_MPLLB_CTRL_2):

8 In PCIe PHY MPLLB Control 3 (PCIE_PHY_EXT_MPLLB_CTRL_3):

9 In PCIe PHY MPLLB Control 1 (PCIE_PHY_EXT_MPLLB_CTRL_1):

10 In PCIe PHY XPCS_1 Rx Override Control (PCIE_PHY_XPCS1_RX_OVRD_CTRL):

11 In PCIe PHY Boundary Scan Control (PCIE_PHY_EXT_BS_CTRL):

Table continues on the next page...

S32G2 SerDes Subsystem Reference Manual , Rev. 6, 8 Nov 2022

Table 3. Enabling 2.5G SGMII with PCIe on SerDes lane 0 (continued)

18 In VR MII PHY Rx CDR Control (VR_MII_Gen5_12G_16G_RX_CDR_CTRL):

19 If you are using the internal reference clock, write 0 to VR_MII_DIG_CTRL1[BYP_PWRUP].

20 Write 1, then 0, to RST_CTRL[COLD_RST].

21 Write 1 to VR_MII_Gen5_12G_16G_TX_GENCTRL2[TX_REQ_0], then read this field until it returns to 0.

22 Write 1 to VR_MII_Gen5_12G_16G_RX_GENCTRL2[RX_REQ_0], then read this field until it returns to 0.

24 Write 1 to VR_MII_DIG_CTRL1[INIT], then read this field until it returns to 0.

1.6 Requirements for Split Reference Independent Spread Spectrum (SRIS)

1.7 PLL usage

Table 4. PLL as a function of protocol and speed

Protocol and speed PLL used

PCIe Gen1 MPLLA

PCIe Gen2 MPLLA

PCIe Gen3 MPLLB

SGMII 2.5G MPLLB

S32G2 SerDes Subsystem Reference Manual , Rev. 6, 8 Nov 2022

Table 5. MPLL_STATE transition time

100 MHz Within 3.4 ms