S32G2 MEMORIES

APRIL 2021

PUBLIC
NXP, THE NXP LOGO AND NXP SECURE CONNECTIONS FOR A SMARTER W ORLD ARE TRADEMARKS OF NXP B.V.
ALL OTHER PRODUCT OR SERVICE NAMES ARE THE PROPERTY OF THEIR RES PECTIVE OW NERS. © 2021 NXP B.V.
MEMORY OVERVIEW

Unlike the previous generation gateway family, the S32G2 has no internal flash

S32G2
Internal External
Memories Memory
Interfaces
8 MB SRAM DRAM –
DRAM Supports LPDDR4, DDR3L

32 KB Standby QuadSPI -
RAM QuadSPI Supports Octal, DDR, HyperFlash

BootROM
(~128K) SDHC Supports MMC, eMMC, SDXC

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MEMORY ARCHITECTURE

S32G2 • Load / Execute

SECURE MEMORY / OTP
− NVM: Ext. NOR Flash
Tightly HSE Fuse Bank

Isolated
Core 0 Coupled − Execute: System RAM
RAM Key1
Cortex
Cortex Crypto
M7 Key2
M7 Engine • High performance execution path
I-Cache Key3 − CPU to System RAM
... ENCRYPTED +
HSE RAM SIGNED
L1 I / D-Cache • Security built into architecture
CONTENT − External = Encrypted + Signed
(3) EXECUTE

− On-the-fly Decrypt + Authenticate

HSE f/w Image
▪ Built into ext. flash I/F
Switch Fabric
OEM Key Image ▪ Fast secure boot
− Secure RAM and Secure OTP on-chip
On-the-FLY Primary
Decrypt / Auth (1) LOAD Application
Image OTA • Full OTA support
System RAM QSPI
(ECC) (SDR, DDR, RPC, A-B − A-B Swap, Overwrite method
Hyperflash, Octoflash) Secondary
Application
SWAP − Non-intrusive firmware updates
(2) ON-THE-FLY Image
− Customer only pays for OTA memory
SECURITY External Serial they require
NOR Flash

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INTERNAL MEMORIES: SRAM

• Size: 8 MB – made up of 16 x 512KB Blocks Switch Fabric

• Each block has independent RAM controller with
128-bit data bus
• Implements ECC on contents (initialized by
RAM RAM RAM
hardware as triggered by BootROM) CTRL CTRL CTRL

• Uses an Interleaved architecture

x16

512KB

512KB

512KB
− Interleaved on a 64byte boundary
− Transaction splitting and reordering taken care of
by FlexNOC – entirely transparent to user
SRAM
Advantages of this approach:
• Accesses are shared across all 16 ports – lessening
the amount of bottlenecks on single ports
• No need for customer to manually partition code
between RAM controllers to optimize for multi master
accesses

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I N T E R N A L M E M O R I E S : S TA N D B Y R A M , B O O T R O M

Standby RAM BootROM

• Separate 32 KB block – not part of • ROM contains NXP boot code
main SRAM array. • Executed by HSE core upon boot
• Clocked at 400 MHz − Not executed at any other time
• 39 bits wide: 32-bit + 7-bit ECC • Reads fuses/boot pins and
• Remains powered during standby configures external memory
mode and retains content through • Securely copies software to RAM and
functional reset. begins execution
• Approximately 128 KB

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E X T E R N AL M E M O RY I N T E R FAC E S : D R AM

• Memory map contains up to 4 GB

− Upper 2 GB restricted to A53, PCIe and CAAM
• Supports LPDDR4, DDR3L
• Supports x16 and x32-bit DRAM Modules
− DDR3L @ DDR-1600 (800 MHz): x16
− LPDDR4 @ DDR-3200 x16 and x32
• Support for 2x CS
• Supports self-refresh mode in standby
• 3 ports:
− 2x 128-bit wide optimized for BW over latency
− 1x 64-bit optimized for latency critical traffic (M7/DMA)
• Supports burst length of 16 for LPDDR4
• ASIL D

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 E X T E R N AL M E M O RY I N T E R FAC E S : D R AM

• Supports Inline ECC:

Figure from synopsys: https://www.synopsys.com/designware-ip/technical-bulletin/automotive-ddr-dram.html

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DRAM CONTROLLER: INLINE ECC (WRITE)

• DRAM address space will be split into 8 regions for each DRAM channel
• Each region can separately enable inline ECC
• The 8th region is used for ECC storage and becomes unavailable for application
• Write example to ECC region – 8 data bursts will fill one additional ECC burst
Burst 1 (BL=16) Burst 1 (BL=16) Write data to
Burst 2 (BL=16) Write data w/o ECC into DRAM DRAM address
Transfer 1 Transfer
Burst 1
2 (BL=16)
Transfer region 1-7
Burst28 1(BL=16)
Transfer … 2
Transfer
Transfer 2
… Transfer 1 Generate ECC
Burst 8…(BL=16)
Transfer 2
…
TransferTransfer
16 2 per 64-bit Transfer
Burst 9 (ECC
… 16
Transfer 1
Burst)
Transfer 16 transfer and
… Store in buffer Transfer
ECC Transfer
for 2 (half)
Burst16
1 Write ECC to
… Transfer 16 Write ECC buffer … 1 (half)
ECC for Burst
DRAM address
region 8
to DRAM
WriteWay1:ECC Buffer when buffer is full … 16
Transfer
ECC for Burst 1 (half) ECC for Burst 8 (half)
ECC for Burst 1 (half)
8x ECC buffers for
…
optimized handling of Ideally, 12.5% bandwidth overhead if
ECC for Burst 8 (half)
interleaved write the parallel threads can fill the ECC
threads buffers (linear interleaved traffic). Up
to 100% for random traffic
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 DRAM CONTROLLER: INLINE ECC (READ)

• Read access to ECC enabled region

Adds latency of one
DRAM burst for first read

Initiate Read:
Read ECC first Read data Detect and
Burst 9 (ECC Burst) Burst 1 (BL=16) Corr. Burst 1 (BL=16)
if ECC buffer is bursts correct errors
Burst 2 (BL=16) Corr. Burst 2 (BL=16)
empty ECC for Burst 1 (half) Transfer 1 in data bursts Transfer 1
Transfer
Burst28 1(BL=16) Transfer
Corr. 1
Burst
ECC for Burst 1 (half) Transfer Transfer 2 8 (BL=16)
Transfer 2 Transfer 2
… … Transfer 1 … Transfer 1
… …
ECC for Burst 8 (half) TransferTransfer
16 2 TransferTransfer
16 2
Transfer 16
… Transfer 16
…
Transfer 16 Transfer 16

Store in ECC buffer

ReadWay1:ECC Buffer
ECC for Burst 1 (half) Ideally, 12.5% bandwidth
8x ECC buffers for ECC for Burst 1 (half) overhead if the parallel threads
optimized handling of … fully use the ECC buffers
interleaved read ECC for Burst 8 (half) (linear interleaved traffic). Up to
threads 100% for random traffic

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E X T E R N AL M E M O RY I N T E R FAC E S : Q U AD S P I

• Memory Mapped (512 MBytes)

• Single QSPI module supports A and B interface (dual flash).
QSPI_A QSPI_B
I/O 1.8V (dedicated) 1.8V or 3.3V (shared with SDHC)
Max Speed 200 MHz (400 MB/s) 1.8V: 133 MHz (266MB/s)
3.3V: 66 MHz (66MB/s)

• All AHB accesses to flash devices are directly memory mapped to the chip system memory.
• Flexible sequence engine to support various flash vendor devices.
− Single, dual, quad and octal modes of operation
• There is no set standard for QuadSPI protocol. S32G2 supports:
− Cypress HyperFlash
− Macronix Octa Flash
− Micron Octal Flash
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E X T E R N AL M E M O RY I N T E R FAC E S : Q U AD S P I

Cypress HyperFlash

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E X T E R N AL M E M O RY I N T E R FAC E S : S D H C

• Supports SD and eMMC

− No support for raw NAND
− eMMC has higher max bandwidth
− SD high speeds requires the supply voltage to begin at 3.3V and then switch to 1.8V.
• SD likely to be used for development only – eMMC is main use case.
• Supports latest HS400 and Enhanced HS400
• Supports 1-bit / 4-bit SD and SDIO modes, 1-bit / 4-bit / 8-bit MMC modes
Name Data Rate I/O Voltage CLK Freq Max Data Rate
Legacy SDR 3.3V / 1.8V 26 MHz 26 MB/s
High Speed SDR SDR 3.3V / 1.8V 52 MHz 52 MB/s
High Speed DDR DDR 3.3V / 1.8V 52 MHz 104 MB/s
HS200 SDR 1.8V 200 MHz 200 MB/s
HS400 DDR 1.8V 200 MHz 400 MB/s

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USE CASES: QUADSPI VS EMMC

Feature QuadSPI eMMC

Cost Medium Cheaper
Standby Current (CS Release) 55 uA 150 uA
Deep power down 2 uA 110 uA
Deep power down exit time 30 uS 6.5 mS
Power up time <300 uS 1001 mS!
Compatible with OTC? Yes No

Customers with external DRAM will typically use eMMC and copy full application at
boot.
If A53/DRAM not required, then QuadSPI is preferred due to memory mapping.

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USE CASES

CPU Platform

Cortex®-M7 Cortex-M7 Cortex-M7 Cortex-A53 Cortex-A53

32kB I-cache 32kB D-cache 32kB I-cache 32kB D-cache
32 KB I-cache 32 KB I-cache 32 KB I-cache Cortex-A53 Cortex-A53
32 KB D-cache 32 KB D-cache 32 KB D-cache 32kB TCM 32kB TCM 32kB TCM 32kB TCM 32kB TCM 32kB TCM
32 KB I-cache 32 KB D-cache 32 KB I-cache 32 KB D-cache
64 KB TCM 64 KB TCM 64 KB TCM NEON
NEON NEON
NEON
FPU FPU FPU 512 KB L2 Cache / Cluster 512 KB L2 Cache / Cluster

3x Dual-core Lockstep

Switch Fabric
x16

SDHC QuadSPI DRAM

8 MB SRAM

A53 Linux
A53 Linux M7 flash
image copied
M7 image flash image image
from SDHC
copied from
QuadSPI
+shared data
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NXP, THE NXP LOGO AND NXP SECURE CONNECTIONS FOR A SMARTER WORLD ARE TRADEMARKS OF NXP B.V. ALL OTHER PRODUCT OR SERVICE NAMES ARE THE PROPERTY OF THEIR RESPECTIVE OWNERS. © 2021 NXP B.V.