Floorplanning with Graph Attention

Yiting Liu, Ziyi Ju, Zhengming Mingzhi Dong∗ Hai Zhou

Li School of Computer Science IC Bench, Inc.
School of Computer Science Fudan University Shanghai, China
Fudan University Zhangjiang Fudan International hai@icbench.com
Shanghai, China Innovation Center
{yitingliu20,zyju20,zhengmingli21}@fudan.edu.cn Shanghai, China
mingzhidong@gmail.com

Jia Wang Fan Yang, Xuan Zeng Li Shang

Department of ECE School of Microelectronics School of Computer Science
IIIinois Institute of Technology Fudan University Fudan University
Chicago, USA Shanghai, China Shanghai, China
jwang@ece.iit.edu {yangfan,xzeng}@fudan.edu.cn lishang@fudan.edu.cn

ABSTRACT
Floorplanning has long been a critical physical design task with high
computation complexity. Its key objective is to determine the initial
locations of macros and standard cells with optimized wirelength for
a given area constraint. This paper presents Flora, a graph attention-
based floorplanner to learn an optimized mapping between circuit
connectivity and physical wirelength, and produce a chip floorplan
using efficient model inference. Flora has been integrated with
two state-of-the-art mixed-size placers. Experimental studies using
both academic benchmarks and industrial designs demonstrate
that compared to state-of-the-art mixed-size placers alone, Flora
improves placement runtime by 18%, with 2% wirelength reduction
on average.
KEYWORDS
floorplanning, physical design, electronic design automation, graph
attention network, deep learning
1 INTRODUCTION
Chip floorplanning has been a critical and challenging task in the
physical implementation of VLSI chips. It affects key down-stream
optimization objectives, among which placement wirelength is
the most important one. Different from traditional floorplanning
which only places macros, the modern version inputs a netlist of
mixed macro blocks and standard cells, and places them so as to
optimize physical wirelength for a given area constraint, which
closely correlates with timing and routability[10].
Proven to be NP-hard even in the classical formulation [14], chip
floorplanning is difficult to solve efficiently using algorithmic ap-
proaches. Lack of effective automatic tools, most expert designers
∗ Corresponding author.
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https://doi.org/10.1145/3489517.3530484
have resorted to doing the job manually, usually taking months of
intense efforts [13]. In order to improve the productivity, Google
has developed a floorplanner based on deep reinforcement learn-
ing [13]. Adopting the approach used in the successful AlphaGo
system, it treats the floorplanning as a sequence of moves, each of
which places a macro on the chip. When all the macros are placed,
the down-stream physical implementation stages are conducted
using commercial tools and a final reward is computed. Similar to
AlphaGo, this final reward is back-propagated to each situation
and movement in the sequence, and an evaluation network and a
policy network are trained based on these rewards. It has reported
better than human expert results on TPU designs, generated under
6 hours by the system.
Our work has been greatly inspired by Google’s work, and we
agree that deep learning is a promising way to solve the chip floor-
planning problem. On the other hand, we are rather conservative
on using reinforcement learning on chip floorplanning, because
decomposing the task into a sequence of moves, each only places
one block, complicates the job. Quite different from the Go game,
where a player can only take one move before the opposite’s un-
known next move, chip designers have the complete connectivity
information of the circuit netlist upfront and rarely need to do the
floorplan in a sequential process, one block at a time. In reality,
having a holistic view of the circuit in mind, an expert designer
usually partitions the circuit into finer and finer subcircuits, and
each time simultaneously places all subcircuits at one level onto the
chip, optimizing the data flow among them. It is, in essence, a pro-
cess of establishing a rough floorplan at a time with an optimized
mapping from subcircuit connectivity to physical locations.
In this work, we pursue a Graph Attention Network (GAT)-based
approach for chip floorplanning. By the general rule of thumb that
“Where the human intuition plays, neural networks may triumphs”,
the main idea of our approach is to utilize GAT [16] to gain a
holistic understanding of the subcircuit connectivity, and learn an
optimized mapping between subcircuit connectivity and physical
wirelength, and then decode the physical locations of circuit blocks
with efficient model inference. The resulted floorplan is then used
to drive the downstream mixed-size placement task.
This work aims to answer the following research questions.

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DAC ’22, July 10–14, 2022, San Francisco, CA, USA
(1) How to establish an optimized mapping between circuit con-
nectivity and physical wirelength? We propose to use a GAT-
based approach. The proposed model consists a shared GAT-
based encoder followed by two task-specific autoencoders
to learn an optimized mapping between circuit connectivity
and physical wirelength, and generate the physical locations
of macros and standard cells, i.e., chip floorplan, which then
drives the downstream placement task.
(2) How to train a GAT-based floorplanner without the need of
big real-world dataset? Real-world optimal floorplans are
challenging to obtain. We propose a methodology to gen-
erate a synthetic training dataset to train the GAT model.
In the dataset, the mapping between circuit connectivity
and physical wirelength is guaranteed to be optimal. In ad-
dition, it offers a broad coverage of statistical connectivity
distributions, to ensure the trained model generalizes well
on real-world designs.
The proposed floorplanner, called Flora, has been integrated
with two state-of-the-art mixed-size placers [4, 7], which will be
publicly released along with the synthetic dataset. Experimental
studies using both ISPD2005 benchmarks and real-world industry
designs demonstrate that, compared to state-of-the-art mixed-size
placers alone, Flora consistently improves placement runtime by
18%, with 2% wirelength reduction on average. Using both academic
benchmarks and industrial designs also validates the generalization
capability of the proposed GAT-based approach.
The rest of this paper is organized as follows. Section 2 summa-
rizes the related works. Section 3 describes the problem formulation.
Section 4 presents the proposed approach. Section 5 demonstrates
the experimental results. We conclude the paper in Section 6.
2 RELATED WORK
Floorplanning is an NP-hard problem which determines the loca-
tions of large physical modules (e.g., embedded memories, intel-
lectual property (IP) cores, clusters of standard cells) and enables
early estimation of interconnect wirelength [1]. Researchers have
proposed various representation schemes [14] and optimization
algorithms [9]. Early work on floorplanning focused on macro pack-
ing and left the task of placing standard cells to downstream placers,
which may limit the optimization space of physical design [8]. Re-
cent work tackles the placement problem of macros and standard
cells simultaneously as one mixed-size placement task [12].
The state-of-the-art mixed-size placers include ePlace [11], Re-
PlAce [4] and DREAMPlace [7], which formulate the mixed-size
placement problem as a constrained nonlinear optimization prob-
lem. The objective function consists of a convex wirelength function
and a weighted non-convex density function. Chip placement is an
iterative optimization process driven by wirelength-induced force
and density-induced force. Studies show that these methods yield
high-quality solutions but require a long iteration time.
Recently, Google developed a floorplanner based on deep rein-
forcement learning [13]. It places macros sequentially and calculates
the reward iteratively, which is then back-propagated to train the
policy network. It has reported better and faster than human ex-
pert results on TPU designs. However, with the complete circuit
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Liu, et al.
netlist information upfront, the reinforcement learning based se-
quential optimization process may unnecessarily complicate the job.
Inspired by how circuit experts create and optimize chip floorplan,
we pursue a GAT-based approach to learn a mapping from circuit
connectivity to block physical locations with optimized wirelength.
3 PROBLEM FORMULATION
A floorplan instance can be modeled as a hypergraph 𝐺 = (𝐶, 𝐸)
with a set of objects 𝐶 (i.e., macros and clustered standard cells)
connected by hyperedges 𝐸. The primary objective of chip floor-
planning can be formulated as minimizing the total wirelength
𝑊 (𝑐) while adhering to the density constraint 𝜌 (𝑐).
min 𝑓 (𝑐) = 𝑊 (𝑐) 𝑠.𝑡 . 𝜌 (𝑐) ≤ 𝜌𝑡 . (1)
𝑐
The total wirelength 𝑊 (𝑐) of the floorplan can be estimated
as the sum of wirelength between all connected objects, which is
defined in Eq. 2.
𝑛 𝑛 𝑛 𝑛
1 ∑︁ ∑︁ 1 ∑︁ ∑︁
𝑊 (𝑐) = 𝑤𝑖,𝑗 = 𝑒𝑖,𝑗 𝑑𝑖,𝑗 𝑎𝑖,𝑗 , (2)
2 𝑖=1 𝑗=1 2 𝑖=1 𝑗=1
where 𝑒𝑖,𝑗 and 𝑑𝑖,𝑗 denote the number of connections and distance
between the objects 𝑖 and 𝑗, respectively, and 𝑎𝑖,𝑗 is an adjacency
matrix with 𝑎𝑖,𝑗 = 1 if objects 𝑖 and 𝑗 are connected, 0 otherwise.
For a given circuit netlist, 𝑒 and 𝑎 are known. According to Eq. 2,
the goal of floorplanning is to calculate the optimal distance 𝑑
between connected objects. As such, the essence of floorplanning
is to construct an optimized mapping between interconnections 𝑒
and physical distances 𝑑, which then guides the downstream task
to optimize and produce final chip placement.
4 METHOD OF FLORA
This section presents Flora, the proposed GAT-based floorplanner.
It first describes the overall algorithmic flow, and then presents the
key components of Flora, including clustering, GAT-based model,
and synthetic training dataset generation.
4.1 Solution Overview
Figure 1 depicts the overall algorithmic flow of Flora. Given a cir-
cuit netlist represented as a weighted undirected hypergraph, Flora
partitions the netlist into subcircuit clusters using the proposed
c-spectral clustering algorithm. The partitioned subcircuit hyper-
graph, consisting of macros and clusters of standard cells, is fed
into the GAT-based model to generate chip floorplan, which is then
fed into downstream placer to produce final chip placement. The
GAT model is trained using synthetic dataset without the need of
real-world chip designs. The dataset covers a wide range of circuit
connectivity distributions to ensure generalization of the proposed
GAT-based floorplanner.
4.2 C-Spectral Clustering Algorithm
This section describes the proposed c-spectral clustering algorithm.
Prior work has shown that spectral clustering can effectively min-
imize inter-cluster weighted connectivity, but with long runtime
Floorplanning with Graph Attention
Clustering
Shared
Encoder
Netlist
Feature
graph
vector GAT
Layer
Figure 1: Overview of the proposed method.
for large-scale graphs [15]. The proposed c-spectral clustering algo-
rithm aims to leverage the benefit of spectral clustering yet avoid
its high computation cost via bottom-up hyperedge coarsening.
Algorithm 1 C-Spectral Clustering Algorithm
Input: A circuit netlist modeled by an undirected hypergraph 𝐺 = (𝐶, 𝐸)
Output: Cluster-level netlist
1: Sort hyperedges in a non-increasing order based on edge weights
2: Merge the objects in the same hyperedge to construct a hypergraph 𝑆 with smaller
scale
3: Compute the Laplacian matrix 𝐿 and the eigenvector 𝑞 corresponding to the
second smallest eigenvalue of 𝐿 for 𝑆
4: Sort 𝑞 and cluster to 𝑘 groups by partitioning at the biggest 𝑘 − 1 gaps of 𝑞
5: Extract macros as single clusters
6: return Cluster-level netlist.
The proposed c-spectral clustering algorithm is summarized in
Alg. 1. Line 1-2 describes the bottom-up hyperedge coarsening
process. Since objects with high connectivity weight need to be
placed closely on the chip, the coarsening process performs bottom-
up clustering based on hyperedge weights, thereby reducing the
scale of the graph and alleviating the computation cost of spec-
tral clustering. Specifically, given the circuit netlist described in
an undirected hypergraph 𝐺 = (𝐶, 𝐸), the hyperedge coarsening
process first sorts hyperedges in a non-increasing order based on
edge weights. Following the sorted order, objects connected by the
same hyperedge are merged into a cluster. This process continues
until a predefined bound in terms of the total number of clusters is
reached.
The output of the coarsening process, i.e., a hyper graph 𝑆 with
much smaller scale, is then fed into spectral clustering (Line 3-4). We
adopt the spectral-based clustering approach [15]. We first compute
the Laplacian matrix 𝐿 of graph 𝑆 and calculate the eigenvector 𝑞
corresponding to the second smallest eigenvalue of 𝐿. Then, we sort
the eigenvector 𝑞 and partition the objects to 𝑘 clusters by finding
the biggest 𝑘 − 1 gaps of the sorted eigenvectors. We also apply
the Lanczos algorithm [5] to improve the calculation efficiency of
eigenvalues and eigenvectors. Finally, we extract macros as single
clusters to balance the total areas of cells within each cluster.
4.3 GAT-based Model
This section presents the proposed GAT-based model for floorplan
generation with optimized mapping between circuit connectivity
and physical wirelength.
Architecture. As shown in Figure 1, the model contains three
key components, including a shared encoder, and two task-specific
autoencoders referred as Dtask-model and Ltask-model, respec-
tively. The shared encoder encodes the circuit netlist information
DAC ’22, July 10–14, 2022, San Francisco, CA, USA
GAT-based Model Nonlinear Optimization Solver
Dtask-model
Encoder Decoder
Node distances
Floorplan
Encoder Decoder
Node positions
Ltask-model
into embeddings using GAT [16]. Dtask-model aims to learn embed-
dings to establish an optimized mapping between circuit connectiv-
ity and the physical wirelength between connected objects in the
floorplan. The embeddings of Dtask-model are concatenated with
the embeddings of Ltask-model, and then fed to the Ltask-model
decoder to generate object physical positions, or the chip floorplan.
Shared GAT encoder. The input to the shared GAT encoder
is the cluster-level netlist generated by c-spectral clustering (cf.
Section 4.2), represented as a graph 𝐺 = (𝑉 , 𝐴) defined by the
set of objects 𝑉 and the adjacency matrix 𝐴. Each object has a
𝑁 -dimensional feature vector representing the connectivity dis-
tribution. Let 𝐹 ∈ R𝑁 ×𝑁 be the feature matrix containing feature
vectors of all objects as rows. 𝐴 is an 𝑁 × 𝑁 binary matrix with
𝐴𝑖,𝑗 = 1 if objects indexed by 𝑖 and 𝑗 are connected by edges,
𝐴𝑖,𝑗 = 0 otherwise, and 𝐴𝑖,𝑖 = 1 for all 𝑖.
The shared GAT-based encoder learns a new representation
for each object by aggregating messages from its local neighbors,
referred to as the first-level object embedding 𝑒 𝑓 ∈ R𝑁 ×𝑀 , where 𝑀
is the number of new features in each object. 𝑒 𝑓 is then transferred
to Dtask-model and Ltask-model to complete the following specific
tasks.
Dtask-model. It aims to learn an optimized mapping between
the clustered netlist connectivity and physical wirelength. The
model consists of a GAT layer to compute a 𝐻 -dimensional distance
embedding 𝑒𝑑 ∈ R𝑁 ×𝐻 and a Multi-Layer Perceptron (MLP) [6] to
decode 𝑒𝑑 to the distances of connected objects 𝐷 ∈ R𝑁 ×𝑁 . Since
GAT can assign different attentions to neighbors, it is capable to
learn the correlation between objects and encode the neighbors
with more correlations to be closer to the object in the new fea-
ture space, thus enabling the model to learn the mapping between
interconnections and distances for all connected objects.
Let 𝑍 𝑑 ∈ R𝑁 ×𝑁 be the output matrix of Dtask-model containing
distance information. We define the model computing 𝑍 𝑑 as follows:
𝑍 𝑑 = 𝐴𝑓𝜃𝑑 [𝑡𝜁𝑑 (𝑒 𝑓 )], (3)
where 𝑡𝜁𝑑 : R𝑀 → R𝐻 is a GAT layer with learnable parameters
𝜁𝑑 to compute the distance embedding 𝑒𝑑 , and 𝐴𝑓𝜃𝑑 : R𝐻 → R𝑁 is
a MLP with learnable parameters 𝜃𝑑 multiplied by 𝐴 to decode the
distances of connected objects. The model is trained by minimizing
the mean-squared loss (MSELoss) between the ground truth 𝐷𝐿𝑎𝑏𝑒𝑙
and the predicted value 𝑍 𝑑 as follows:
1 ∑︁ 𝑑
L𝑑 = (𝑍𝑖 − 𝐷𝐿𝑎𝑏𝑒𝑙𝑖 ) 2 . (4)
𝑁
𝑖 ∈𝑉
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DAC ’22, July 10–14, 2022, San Francisco, CA, USA
Ltask-model. It aims to generate the chip floorplan, i.e., the lo-
cations of macros and clusters of standard cells. The architecture of
Ltask-model is similar to that of Dtask-model, a GAT layer followed
by a MLP, defined as follows:
𝑍 𝑙 = 𝑓𝜃𝑙 [𝑡𝜁𝑙 (𝑒 𝑓 ) ⊕ 𝑒𝑑 ],
where 𝑍 𝑙 represents the object locations predicted by Ltask-model,
𝑡𝜁𝑙 : R𝑀 → R𝑇 is a GAT layer with learnable parameters 𝜁𝑙 to
compute the location embedding 𝑒 𝑙 , ⊕ denotes the concatenation
operator and 𝑓𝜃𝑙 : R𝑇 +𝐻 → R2 is a MLP with learnable parameters
𝜃𝑙 to decode the object locations. In particular, to establish the map-
ping between relative distance and absolute coordinates for objects,
we concatenate the location embedding 𝑒 𝑙 and distance embedding
𝑒𝑑 as 𝑒 𝑐 and feed it to the following MLP layer to generate the
object distribution.
The model is trained using MSELoss between the ground truth
𝐿𝐿𝑎𝑏𝑒𝑙 and the predicted value 𝑍 𝑙 as follows:
1 ∑︁ 𝑙
L𝑙 = (𝑍𝑖 − 𝐿𝐿𝑎𝑏𝑒𝑙𝑖 ) 2 . (6)
𝑁
𝑖 ∈𝑉
By combining the loss functions from the Dtask-model and the
Ltask-model, the final loss function for the GAT-based model is
defined as follows:
L = L𝑑 + L𝑙 . (7)
4.4 Synthetic Training Dataset Generation
Real-world optimal floorplans are hard to obtain. Even assuming
their optimal floorplans are known, the limited number of public
benchmarks are far from enough to support the training of a deep
model. We propose a methodology to create a synthetic training
dataset to solve this problem [3].
The creation of synthetic training dataset needs to guarantee
that each created netlist-floorplan pair shall contain the optimal
mapping between circuit connectivity and physical wirelength. As
described in Section 3, the primary optimization goal of a floorplan-
ner is to minimize the total wirelength which can be calculated as
Eq. 2. The key features we can extract from a given clustered netlist
are 𝑒 and 𝑎, which can be transferred to the statistical distribution
of connectivity, more specifically, the distribution of the number of
connections between two neighbors 𝐸 and the distribution of the
number of neighbors for each object 𝐵. To construct the training
dataset, we start with creating an empty chip region and placing all
objects on the region. Then we calculate the probability distribu-
tion of 𝐸 and 𝐵 in various clustered circuits, which can be denoted
as 𝑃 (𝑒) and 𝑃 (𝑏), respectively. Next, we generate the number of
neighbors 𝐵 = (𝑏 1, . . . , 𝑏𝑖 , . . . , 𝑏𝑛 ) ∼ 𝑃 (𝑏) for each objects and the
number of connections 𝐸 = (𝑒 1, . . . , 𝑒𝑖 , . . . , 𝑒𝑛 ), ∀𝑒𝑖 ∼ 𝑃 (𝑒) between
connected objects, where 𝑏𝑖 denotes the number of neighbors for
objects 𝑖 and 𝑒𝑖 denotes the connection distribution between the
object 𝑖 and its neighbors. We sort 𝑒𝑖 ∈ 𝐸 in descending order and
allocate more connections to neighbors with closer distances. The
final number of connections between objects is set to the average
connections of object-pairs. Then the coordinate of each object
𝑂 (𝑥, 𝑦) can be regarded as the location label 𝐿𝐿𝑎𝑏𝑒𝑙 and the physi-
cal distances between each connected object pair are the distance
label 𝐷𝐿𝑎𝑏𝑒𝑙. The construction of the dataset is depicted in Alg. 2.
Liu, et al.
Algorithm 2 Synthetic Training Dataset Generation Algorithm
Input: The number of objects 𝑛 , the distribution of the number of interconnections
𝑃 (𝑒) and neighbors 𝑃 (𝑏)
Output: Synthetic training dataset with optimal netlist-floorplan pair
1: Determine the locations of 𝑛 objects
2: Generate the count number of neighbors 𝑏𝑖 to each object 𝑜𝑖 ∈ 𝐺 and 𝐵 =
(5) (𝑏 1 , . . . , 𝑏𝑖 , . . . , 𝑏𝑛 ) ∼ 𝑃 (𝑏)
3: for 𝑜𝑖 in 𝐺 do
4: 𝑒𝑖 = (𝑒𝑖,1 , . . . , 𝑒𝑖,𝑗 , . . . , 𝑒𝑖,𝑏𝑖 ) ∼ 𝑃 (𝑒) .
5: end for
6: 𝐸 = (𝑒 1 , . . . , 𝑒𝑖 , . . . , 𝑒𝑛 )
7: Sort 𝑒𝑖 ∈ 𝐸 in descending order.
8: Assign connections to neighbors based on the distance
9: return Synthetic training dataset
(a) (b)
Figure 2: The connectivity statistics of ISPD2005 and real-
world industry designs. (a) the distribution of the number of
connections 𝐸. (b) the distribution of the number of neigh-
bors 𝐵. The red dotted line shows the connectivity statistics
of the created synthetic dataset.
As such, we can obtain the synthetic training dataset with opti-
mal floorplan solution (cf. Proof) while ensuring a wide coverage
of the statistical connectivity distribution, thus leading the trained
model to be generalized well on various benchmarks.
Theorem 4.1. The netlist-floorplan pair generated in Alg. 2 is
optimal.
Proof. The total wirelength between object 𝑖 and its neighbors
𝐵 = {𝑏 1, 𝑏 2, . . . , 𝑏𝑛 } can be calculated as
𝑤𝑖 = 𝑒𝑖,𝑏 1 𝑑𝑖,𝑏 1 + 𝑒𝑖,𝑏 1 𝑑𝑖,𝑏 1 + · · · + 𝑒𝑖,𝑏𝑛 𝑑𝑖,𝑏𝑛 , (8)
where 𝑑𝑖,𝑏𝑛 and 𝑒𝑖,𝑏𝑛 denote the distance and the number of connec-
tions between 𝑖 and 𝑏𝑛 . Since 𝑒 is known in advance, to minimize
𝑤𝑖 while without violating the density constraint (i.e. non-overlap
between objects), 𝑑 needs to be inversely proportional to 𝑒, that is,
𝑒𝑖,𝑏 1 > 𝑒𝑖,𝑏 2 > · · · > 𝑒𝑖,𝑏𝑛 ∧ 𝑑𝑖,𝑏 1 < 𝑑𝑖,𝑏 2 < · · · < 𝑑𝑖,𝑏𝑛 , (9)
the mapping of which is guaranteed in the synthetic training dataset.
Swapping any neighbors’ positions will lead 𝑤𝑖 to increase, thus
proving the optimality of the synthetic training dataset [3].
□
In addition, the synthetic dataset shall provide a broad coverage
in terms of circuit connectivity to ensure the generalization of
trained model. As shown in Figure 2, the distributions of the two
key features 𝐸 and 𝐵 vary significantly among different benchmarks
(represented by different colors). In this work, the connectivity
statistics of the synthetic dataset sufficiently covers that of academic
benchmarks, e.g., ISPD2005, and real-world industry designs, which
can be further extended to accommodate new designs with different
connectivity statistics.
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Floorplanning with Graph Attention DAC ’22, July 10–14, 2022, San Francisco, CA, USA

Table 1: Experimental results on ISPD2005 benchmarks

Flora DREAMPlace
Benchmark #cell #net #Movable #Fixed #Fixed/#cell
HPWL (10^7) Iteration Runtime (s) HPWL (10^7) Iteration Runtime (s)
ADAPTEC1 211447 221142 210967 480 0.20% 6.46 460 180 6.55 605 227
ADAPTEC2 255023 266009 254584 407 0.16% 7.77 520 275 10.11 620 300
ADAPTEC3 451650 466758 450985 59 0.12% 15.65 521 374 15.63 726 445
ADAPTEC4 496054 515951 494785 1260 0.25% 14.28 527 427 14.29 742 545
BIGBLUE1 278164 284479 277636 528 0.19% 8.51 424 196 8.52 646 336
BIGBLUE2 557866 577235 535741 22125 3.97% 12.51 471 273 12.52 630 326
BIGBLUE3 1096812 1123170 1095583 1229 0.09% - - - - - -
BIGBLUE4 2177353 2229886 2169382 7970 0.33% 74.76 949 888 75.90 989 906
ratio - - - - - 1 1 1 1.02 1.33 1.18

Table 2: Experimental results on real-world industrial designs

Flora RePlAce
Benchmark #cell #net #Movable #Fixed
HPWL (10^9) Iteration Runtime (s) HPWL (10^9) Iteration Runtime (s)
design1 134990 141016 134265 725 4.83 440 200 4.89 560 231
design2 234106 218056 233382 724 15.80 521 260 16.31 810 388
design3 82185 81737 81578 607 1.17 463 166 1.19 547 205
ratio - - - - 1 1 1 1.03 1.35 1.32

5 EXPERIMENTAL RESULTS
This section evaluates the performance of Flora using academic
benchmarks and real-world industrial designs.
5.1 Experiment Setting
Flora is implemented in Python with PyTorch. The model is trained
on a Linux server with 16-core Inter Xeon Gold 6226R @ 2.9GHz
and NVIDIA 2080 Ti GPU. We integrate Flora with two state-of-
the-art placers, RePlAce [4] and DREAMPlace version 3.0 [7], as
two integrated floorplan-placement physical optimization flows.
We evaluate the performance of Flora by comparing the two
integrated floorplanning-placement flows, i.e., Flora+RePlAce and
Flora+DREAMPlace, with RePlAce and DREAMPlace alone. We use
the widely used ISPD2005 benchmark suite and three real-world
industrial designs provided by IC Bench, Inc. The three industrial
SoC designs contain 135k, 234k, 82k blocks, and 725, 724, 607 IOs
respectively (see Table 2). To evaluate the performance of the pro-
posed floorplanning method, the locations of macros in ISPD2005
benchmarks and industrial designs are set to be movable. ISPD2005
benchmarks are in GSRC Bookshelf placement format [2]. Since the
publicly available version of RePlAce does not support the book-
shelf format, we only consider the three industrial designs using
RePlAce. For consistent comparison, both Flora-DREAMPlace and
DREAMPlace alone are running the CPU version. The following
experiments are performed on a workstation with Intel i7-7700
3.6GHz CPU and 16GB memory.
5.2 Performance
5.2.1 Comparison to the state-of-the-art mixed-size placers. Table 1
and Table 2 present the performance comparison results using
ISPD2005 benchmarks and three industrial designs, respectively. As
shown in Table 1, on ISPD2005 benchmarks, Flora+DREAMPlace
delivers 33%, 18% and 2% improvement on average, in terms of
the number of placement iterations, total runtime, and HPWL,
compared against DREAMPlace alone. As shown in Table 2, on
three industrial designs, Flora+RePlAce delivers 35%, 32%, and 3%
improvement on average, in terms of the number of placement iter-
ations, total runtime, and HPWL, compared against RePlAce alone.
These results demonstrate that Flora can efficiently produce high-
quality chip floorplan, which when used by downstream placers as
the initial solution, can effectively reduces required optimization
iterations of placers. Figure 3 shows the floorplanning and place-
ment results of ADAPTEC2. Figure 3 (a) is the floorplan generated
by Flora, which is then used by DREAMPlace as the initial chip
placement to produce the final placement (Figure 3 (b)). For com-
parison purpose, Figure 3 (c) shows the placement result produced
by DREAMPlace alone.
(a) (b) (c)
Figure 3: (a) floorplan by Flora. (b) placement by
Flora+DREAMPlace. (c) placement by DREAMPlace.
To further investigate the efficacy of Flora, Figure 4 shows the
HPWL and density metrics during the iterative placement opti-
mization process of Flora+DREAMPlace and DREAMPlace alone
using ADAPTEC1 benchmark. As pointed out by ePlace-MS [11],
for modern mixed-size placers, the initial solution is of vital impor-
tance toward the quality of the final placement results. To this end,
RePlAce and DREAMPlace both consist of an initial phase by first
gathering blocks to the center of the chip, and then adjusting the
initial locations of the blocks around the center region of the chip
by applying large weight to HPWL and small weight to density.
This process indeed improves the final placement quality, which
however significantly slows down the overall placement process.
As shown in Figure 4, for ADAPTEC1, such initial phase accounts
for approximately 25% of the total iterative placement process. On
the other hand, Flora produces an optimized floorplan using highly
efficient model inference. Using Flora, downstream placers can
bypass such time-consuming initialization phase, and effectively
reduce the overall iterations and runtime with high-quality results.

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DAC ’22, July 10–14, 2022, San Francisco, CA, USA Liu, et al.

6 CONCLUSION
This paper presents Flora, a GAT-based floorplanner. Flora is equipped
with an efficient graph clustering algorithm and a graph attention
network to learn an optimized mapping between circuit connectiv-
ity and physical wirelength, and produce high-quality chip floorplan
via efficient model inference. Flora is trained using synthetic dataset
without the need of large real-world circuit dataset. Experimental
studies demonstrate that Flora can effectively improve the efficacy
of downstream placement tasks.
Figure 4: HPWL curve (a) and density curve (b) of ADAPTEC1
during the iterative placement process. ACKNOWLEDGMENTS
Table 3: Experimental results with movable IOs This research is supported by National Natural Science Foundation
of China under Grant No. 62090025, National Natural Science Foun-
Flora DREAMPlace dation of China under Grant No. 62141407 and the young scientist
Benchmark
HPWL (10^7) Runtime (s) HPWL (10^7) Runtime (s)
ADAPTEC1 6.90 186.11 8.53 262.33 project of MOE innovation platform. We thank IC Bench, Inc. for
ADAPTEC2 8.93 279.19 13.22 279.45 providing industrial designs for experiments, and their efficient
ADAPTEC3 14.82 354.26 16.14 449.01
ADAPTEC4 14.61 345.76 29.05 516.89 router for supporting our future work to extend the GNN-based
BIGBLUE1 8.43 213.33 12.74 281.43 model to target post-routing design parameters.
BIGBLUE2 10.12 408.90 18.12 762.10
BIGBLUE3 26.65 988.12 28.31 1126.34
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