Name: - Yash Arya

Roll No.: - 19EEAEC078

EXPERIMENT NO.: - 3
OBJECTIVE: Design and simulate half adder and full adder using VHDL (data flow method)/Verilog.

SOFTWARE USED: Xilinx ISE

VHDL CODE: -

HALF-ADDER

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity yasha_exp3 is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

sum : out STD_LOGIC;

carry : out STD_LOGIC);

end yasha_exp3;

architecture Data_Flow of yasha_exp3 is

begin

sum <= a XOR b;

carry <= a AND b;

end Data_Flow;
Name: - Yash Arya
Roll No.: - 19EEAEC078
Name: - Yash Arya
Roll No.: - 19EEAEC078

Full Adder

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;
Name: - Yash Arya
Roll No.: - 19EEAEC078

entity yasha_fulladder is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

cin : in STD_LOGIC;

sum : out STD_LOGIC;

carry : out STD_LOGIC);

end yasha_fulladder;

architecture Data_Flow of yasha_fulladder is

begin

sum <= a XOR b XOR cin ;

carry <= (a AND b) OR (cin AND a) OR (cin AND b) ;

end Data_Flow;
Name: - Yash Arya
Roll No.: - 19EEAEC078