carry= (x & y) | (y & z) | (x & z)

PROCEDURE:

Software part
1. Click on the Xilinx ISE Design Suite 12.1or Xilinx Project navigator icon on the desktop of
PC.
2. Write the Verilog code by choosing HDL as top level source module.
3. Check syntax, view RTL schematic and note the device utilization summary by double
clicking on the synthesis in the process window.
4. Perform the functional simulation using Xilinx ISE simulator.
5. The output can be observed by using model sim.

PROGRAM:

Verilog code for half adder

module halfadder(a, b, sum, carry);

input a;
input b;
output sum;
output carry;
xor(sum,a,b);
and(carry,a,b);
endmodule

SIMULATION REPORT

Page | 1
PROGRAM:

Verilog code for full adder

module fulladder(a,b,c,d,e,f,sum,carry);
input a,b,c;
output sum,carry,d,e,f;
wire d,e;
xor(d,a,b);
xor(sum,d,c);
and(e,d,c);
and(f,a,b);
or(carry,e,f);
endmodule

SIMULATION REPORT

RESULT:
Thus the verilog program for half adder and full adder were written, synthesized and simulated
using Xilinx tool.

Page | 2
 1. Write the Verilog code by choosing HDL as top level source module.
2. Check syntax, view RTL schematic and note the device utilization summary by double
3. clicking on the synthesis in the process window.
4. Perform the functional simulation using Xilinx ISE simulator.
5. The output wave form can be observed in model sim.

PROGRAM:

Verilog code for 4-Bit multiplier

module multiplierm(a, b, out);

input [4:0] a;
input [4:0] b;
output [9:0] out;
assign out=(a*b);
endmodule

SIMULATION REPORT:

RESULT:
Thus the verilog program for 4-Bit multiplier were written, synthesized and simulated using Xilinx
tool.

Page | 3
 always@(posedge clear or posedge clk)
begin
if(clear)
q <=4'b0000;
else if(updown)
q <= q+1'b1;
else
q <= q-1'b1;
end
endmodule

SIMULATION REPORT :

RESULT:
Thus the verilog program for Up-Down Counter were written, synthesized and
simulatedusing Xilinx tool.

Page | 4
EXP: NO: 5
FPGA implementation of 4 bit Serial adder using HDL.
DATE:
assign sum=temp[3:0];
assign carry=temp[4];
endmodule

SIMULATION REPORT :

RESULT:
Thus the verilog program for 4-Bit Adder was written, synthesized and simulated using
Xilinx tool.

Page | 5
 EXP: NO: 9
Design and simulate a CMOS inverter using digital flow and also generate the
DATE:
layout using EDA tool.

AIM:
To design, synthesize, simulate and implement the CMOS inverter in layout form using
Microwind.

TOOLS REQUIRED:

SOFTWARE:
1. MICROWIND V3.1
CIRCUIT DIAGRAM:

Page | 6
 OUTPUT:

RESULT:
Thus the CMOS inverter schematic form was designed and simulated using Microwind.

Page | 7
 EXP: NO: 10 Design and simulate universal gates and also generate the layout

DATE: using EDA tool.

AIM:
To design, synthesize, simulate and implement the CMOS NAND gate in layout form using
Microwind.

TOOLS REQUIRED:

SOFTWARE:
1. MICROWIND V3.1
CIRCUIT DIAGRAM:

Page | 8
OUTPUT:

RESULT:
Thus the CMOS NAND gate schematic form was designed and simulated using Microwind.

Page | 9