Lecture 4 HO 2022

Digital Electronics: EE 304
Programmable Logic: Lecture 4

Design and Analysis Procedures.
Electrical and Electronic Department

Faculty of Engineering and the Built Environment
1 H.21.10.2022
M. Katongera Electrical and Electronic Department
OFFICE CD 37 mkatongera@eng.uz.ac.zw
2 21.10.2022 H. M. Katongera – mkatongera@eng.uz.ac.zw Electrical and Electronic Department
SUMMARY
Introduction
Simple Programmable Logic Devices (SPLDs)
Complex Programmable Logic Devices (CPLDs)
Macrocell Modes
Field-Programmable Gate Arrays (FPGAs)
Programmable Logic software

INTRODUCTION

Introduction: Objectives
Discuss the types of programmable logic, SPLDs

and CPLDs, and explain their basic structure
Describe the basic architecture of two types of
SPLDs—the PAL and the GAL
Discuss the operation of macrocells
Distinguish between CPLDs and FPGAs
Explain the basic operation of a look-up table
(LUT)
Discuss embedded functions

Introduction: Objectives
Show a basic software design flow for a

programmable device
Explain the design flow elements of design entry,
functional simulation, synthesis, implementation,
timing simulation, and downloading

Introduction
Today, new digital circuits are programmed into

hardware using languages like VHDL
The density (number of equivalent gates on a
single chip) has increased dramatically over the
past few years
The maximum number of gates in an FPGA (a
type of PLD known as a field-programmable gate
array) is doubling every 18 months, according to
Moore’s law

Introduction
At the same time, the price for a PLD is

decreasing
Moore's law:
Gordon E. Moore observed that the number of
transistors on a integrate chip was doubling every 18–
24 months.

Introduction
As shown in the
logarithmic graph
of the number of
transistors on
Intel's processors
at the time of their
introduction, his
“law” was being
obeyed

Introduction
PLDs, such as the FPGA, can be used in

conjunction with processors and software in an
embedded system, or the FPGA can be the sole
component programmed with all the logic functions
An embedded system is one that is dedicated to a
single task or a very limited number of tasks
controlled by a computer
A computer, is multipurpose and can be
programmed to perform just about any task
With PLDs, logic is described with software and
then implemented with internal gates of the PLD
Introduction
PAL/GAL General Block Diagram

SIMPLE PROGRAMMABLE LOGIC
DEVICES (SPLDS)

Simple Programmable Logic Devices
(SPLD)
Two major types of simple programmable logic

devices (SPLDs) are the PAL and the GAL
PAL stands for programmable array logic, and
GAL stands for generic array logic
Generally, a PAL is one-time programmable
(OTP), and a GAL is a type of PAL that is
reprogrammable.
The term GAL is a designation originally used by
Lattice Semiconductor and later licensed to other
manufacturers

(SPLD)
The basic structure of both PALs and GALs is a

programmable AND array and a fixed OR array,
which is a basic sum-of-products architecture

(SPLD): The PAL
A PAL (programmable array logic) consists of a

programmable array of AND gates that connects to
a fixed array of OR gates
Generally, PALs are implemented with fuse
process technology and are, therefore, one-time
programmable (OTP)
The PAL structure allows any sum-of-products
(SOP) logic expression with a defined number of
variables to be implemented
Any combinational logic function can be
expressed in SOP form
(SPLD): The PAL
A simple PAL structure is shown below for two

input variables and one output

(SPLD): The PAL
A programmable array is essentially a grid or

matrix of conductors that form rows and columns
with a programmable link at each cross point
Each programmable link, which is a fuse in the
case of a PAL, is called a cell
Each row is connected to the input of an AND
gate, and each column is connected to an input
variable or its complement

(SPLD): The PAL
By programming the presence or absence of a

fuse connection, any combination of input
variables or complements can be applied to an
AND gate to form any desired product term.
The AND gates are connected to an OR gate,
creating a sum-of-products (SOP) output

(SPLD): The PAL
Let us implement: 𝑋 = 𝐴𝐵 + 𝐴𝐵ത + 𝐴ҧ𝐵ത

The fuses are opened where a variable or its
complement is not used in a given product term
The final output from the OR gate is the SOP
expression

(SPLD): Programming a PAL
We need to generate the following outputs

𝑤 = 𝐴𝐵𝐶ҧ + 𝐴ҧ 𝐵𝐶
ത 𝐷 ഥ
𝑥 = 𝐴 + 𝐵𝐶𝐷
𝑦 = 𝐴𝐵ҧ + 𝐶𝐷 + 𝐵ത 𝐷 ഥ
𝑧 = 𝐴𝐵𝐶ҧ + 𝐴ҧ𝐵𝐶 ഥ + 𝐴𝐶ҧ 𝐷
ത 𝐷 ഥ + 𝐴ҧ𝐵ത 𝐶𝐷
ҧ
We rewrite z as follows
𝑧 = 𝑤 + 𝐴𝐶ҧ 𝐷ഥ + 𝐴ҧ𝐵ത 𝐶𝐷
ҧ

Below is the programming table

Types of PAL devices:

PAL 16L8
PAL 16H8
PAL 16P8
PAL 16H8 is identical to PAL 16L8 but does not have
inverted output buffers
PAL 16P8 has a programmable output polarity as it
uses the EX-OR gates on the output side as buffers

PAL numbering:
PAL 16L8, 16 is the number of inputs, L means active
low output, and 8 is the number of outputs
PAL 16H8, 16 equal number of inputs, H active high
output and 8 is the number of outputs
PAL 16P8, the P stands for the programmable output
polarity

(SPLD): The GAL
The GAL is essentially a PAL that can be

reprogrammed.
It has the same type of AND/OR organization that
the PAL does.
The basic difference is that a GAL uses a
reprogrammable process technology, such
EEPROM(E2CMOS), instead of fuses

(SPLD): The GAL
Schematic of an unprogrammed GAL

(SPLD): Simplified Notation for PAL/ GAL
Actual PAL and GAL devices have many AND-

and OR- gates in addition to other elements and
can handle many variables and their complements
Most PAL and GAL diagrams that you may see on
a data sheet use simplified notation
This is to keep the schematic from being too
complicated

A portion of a programmed PAL/ GAL

(SPLD): Simplified Notation for PAL/GAL
PALs and GALs have a large number of

programmable interconnection lines, and each
AND gate has multiple inputs. Typical PAL and
GAL logic diagrams represent a multiple input
AND gate with an AND gate symbol having a
single input line with a slash and a digit
representing the actual number of inputs
Programmable links in an array are indicated in a
diagram by a red X at the cross point for an intact
fuse or other type of link and the absence of an X
for an open fuse or other type of link
In the previously shown diagram which is below,

the 2-variable logic function 𝐴𝐵 + 𝐴𝐵ത + 𝐴ҧ𝐵ത is
programmed

(SPLD): Example 1 Problem
Show how a PAL is programmed for the following

3-variable logic function:
ҧ 𝐶ҧ + 𝐴ҧ𝐵ത + 𝐴𝐶
ത + 𝐴𝐵
𝑋 = 𝐴𝐵𝐶

(SPLD): Example 1 Solution
The programmed array is shown below

An intact fusible is indicated by small red 
The absence of an  means that the fuse is open

MACROCELL MODES

Macrocell Modes
A macrocell generally consists of one OR gate

and some associated output logic
The macrocells vary in complexity, depending on

the particular type of PAL or GAL
A macrocell can be configured for combinational

logic, registered logic, or a combination of both

Macrocell Modes
Registered logic means that there is a flip-flop in

the macrocell to provide for sequential logic
functions

Macrocell Modes
PAL/ GAL macrocells for combinational logic

Macrocell Modes
The output of the tristate inverter can be either

LOW, HIGH, or disconnected. Part (b) is a
macrocell that can be either an input or an output
When it is used as an input, the tristate inverter is
disconnected, and the input goes to the buffer that
is connected to the AND array
Part (c) is a macrocell that can be programmed to
have either an active-HIGH or an active- LOW
output, or it can be used as an input
One input to the exclusive-OR (XOR) gate can be
programmed to be either HIGH or LOW
Macrocell Modes
When the programmable XOR input is HIGH, the

OR gate output is inverted because 01 = 1 and 11
=0
Similarly, when the programmable XOR input is
LOW, the OR gate output is not inverted because
00 = 0 and 10 = 1

COMPLEX PROGRAMMABLE LOGIC
DEVICES (CPLDS)

Complex Programmable Logic Devices
(CPLDs)
The complex programmable logic device (CPLD)

is basically a single device containing multiple
SPLDs and providing more capacity for larger logic
designs
We refer to each SPLD array in a CPLD as a LAB
(logic array block). Other designations are
sometimes used, such as function block, logic
block, or generic block

(CPLDs)
The programmable interconnections are generally

called the PIA (programmable interconnect
array) although some manufacturers, such as
Xilinx, use the term AIM (advanced interconnect
matrix) or a similar designation

(CPLDs)
Power consumption can range from a few

milliwatts to a few hundred milliwatts
DC supply voltages are typically from 2.5 V to 5 V,
depending on the specific device
Several manufacturers, (for example, Altera,
Xilinx, Lattice, and Atmel) produce CPLDs
CPLDs and other programmable logic devices are
really a combination of hardware and software

(CPLDs):
Basic block diagram of a typical CPLD

(CPLDs): Specific CPLD Devices
Several manufacturers produce CPLDs
Table in next slide (slide 44) lists device families from
selected companies
As time passes, a series may become obsolete, or a new
series may be added
You can check the websites for the most current
information
CPLDs vary greatly in terms of complexity. Table in slide
45 lists some of the parameter ranges that are available
Keep in mind that these numbers are subject to change as
technology advances

List of device families from selected companies

List of some of the parameter ranges that are

available

(CPLDs): Macrocell Modes
The Combinational Mode:

When a macrocell is programmed to produce an SOP
combinational logic function, the logic elements in the
data path are as shown in red in Figure on slide 47.
As you can see, only one multiplexing unit (mux) is

used and the register (flip-flop) is bypassed

(CPLDs): Macrocell Modes
A macrocell configured for generation of an SOP

logic function. Red indicates data path

(CPLDs): Parallel Expanders
When a macrocell is programmed for the

registered mode with the SOP combinational logic
output providing the data input to the register and
clocked by the global clock, the elements in the
data path are as shown in red in Figure following in
slide 49
As you can see, four multiplexers (mux) are used
and the register (flip-flop) is active

(CPLDs): The Registered Mode
Below, a macrocell configured for generation of a

registered logic function. Red indicates data path

(CPLDs): Shared Expanders
A complemented product term that can be used to

increase the number of product terms in an SOP
expression is available from each macrocell in a
LAB.
The Figure in slide 51 illustrates how a shared
expander term from another macrocell can be
used to create additional product terms.
In this case, each of the five AND gates in a
macrocell array is limited to four inputs

(CPLDs): Shared Expanders
Left Hand Side of diagram: A 4-input AND array

gate can produce one 4-variable product term
Right Hand Side of diagram: AND gate is
expanded to produce two product terms

Another way to increase the number of product

terms for a macrocell is by using parallel
expanders
In this case additional product terms are ORed
with the terms generated by a macrocell instead of
being combined in the AND array, as in the shared
expander
A given macrocell can borrow unused product
terms from neighboring macrocells

The basic concept is illustrated in the Figure that

follows where a simplified circuit that can produce
two product terms borrows three additional product
terms
Below is basic concept of the parallel expander

FIELD-PROGRAMMABLE GATE
ARRAYS (FPGA)

Field-Programmable Gate Arrays (FPGA):
Introduction
FPGA (field-programmable gate array) differs in

architecture, from PAL/PLA array) architecture
It does not use PAL/PLA type arrays, and has
much greater densities than CPLDs
A typical FPGA has many times more equivalent
gates than a typical CPLD
The logic-producing elements in FPGAs are
generally much smaller than in CPLDs, and there
are many more of them

Introduction
Also, the programmable interconnections are

generally organized in a row and column
arrangement in FPGAs type arrays, and has much
greater densities than CPLDs
The three basic elements in an FPGA are the
configurable logic block (CLB), the
interconnections, and the input/ output (I/O)
blocks.
The CLBs in an FPGA are not as complex as the
LABs or function blocks (FBs) in a CPLD, but
generally there are many more of them
Introduction
When the CLBs are relatively simple, the FPGA

architecture is called fine grained.
When the CLBs are larger and more complex, the
architecture is called coarse grained

Introduction
Basic structure of an FPGA. CLB is configurable

logic block, also known as logic array block (LAB)

Introduction
The I/O blocks around the perimeter of the

structure provide individually selectable input,
output, or bidirectional access to the outside world.
Large FPGAs can have tens of thousands of
CLBs in addition to memory and other resources.
FPGAs are reprogrammable and use SRAM or
antifuse process technology for the programmable
links.
Densities can range from hundreds of logic
modules to hundreds of thousands of logic
modules in packages with up to over 1,000 pins
Introduction
DC supply voltages are typically 1.8 V to 5 V,

depending on the specific device

Configurable Logic Blocks
Typically, an FPGA logic block consists of several

smaller logic modules that are the basic building
units, somewhat analogous to macrocells in a
CPLD.
Each CLB (somewhat similar to logic array block,
LAB) is made up of multiple smaller logic modules
and a local programmable interconnect that is
used to connect logic modules within the CLB

Configurable Logic Blocks
Basic Configurable Logic Blocks (CLBs) within

the global row/ column programmable
interconnects

Logic Modules
A logic module in an FPGA logic block can be

configured for combinational logic, registered logic,
or a combination of both
A flip-flop is part of the associated logic and is
used for registered logic
An LUT (look-up table) is a type of memory
programmable
It is used to generate SOP combinational logic
functions

Logic Modules
The LUT essentially does the same job as the

PAL or PLA does
Basic block diagram of a logic module in an FPGA

Logic Modules
Generally, the organization of an LUT consists of

a number of memory cells equal to 2n, where n is
the number of input variables
For example, three inputs can select up to eight
memory cells, so an LUT with three input variables
can produce an SOP expression with up to eight
product terms
A pattern of 1s and 0s can be programmed into
the LUT memory cells, as illustrated in Slide 67 for
a specified SOP function

Logic Modules
Each 1 means the associated product term

appears in the SOP output, and each 0 means that
the associated product term does not appear in the
SOP output

Logic Modules
The basic concept of an LUT programmed for a

particular SOP output

Logic Modules Example
Problem
Show a basic 3-variable LUT programmed to produce
the following SOP function:
𝐴2 𝐴1 𝐴0 + 𝐴2 𝐴1 𝐴0 + 𝐴2 𝐴1 𝐴0 + 𝐴2 𝐴1 𝐴0 + 𝐴2 𝐴1 𝐴0

Logic Modules Example
Solution:
𝐴2 𝐴1 𝐴0 + 𝐴2 𝐴1 𝐴0 + 𝐴2 𝐴1 𝐴0 + 𝐴2 𝐴1 𝐴0 + 𝐴2 𝐴1 𝐴0

Specific FPGA Devices
Selected FPGA manufacturers and Features

PROGRAMMABLE LOGIC SOFTWARE

Programmable Logic software:
In order to be useful, programmable logic must

have both hardware and software components
combined into a functional unit.
All manufacturers of SPLDs, CPLDs, and FPGAs
provide software support for each hardware
device.
These software packages are in a category of
software known as computer-aided design (CAD).
Tutorials for two types of software, Altera Quartus
II and Xilinx ISE, are provided on the website

The programming process is generally referred to

as design flow.
A basic design flow diagram for implementing a
logic design in a programmable device is shown in
slide 74
Most specific software packages incorporate
these elements in one form or another and
process them automatically.
The device being programmed is usually referred
to as the target device

General design flow diagram for programming a

SPLD, CPLD, or FPGA

You must have four things to get started

programming a device:
a computer,
development software,
a programmable logic device (SPLD, CPLD, or FPGA),
a way to connect the device to the computer.
After the software has been installed on your
computer, you must become familiar with the
particular software tools before attempting to
connect and program a device

Essential elements for programming an SPLD,

CPLD, or FPGA. (d) photo courtesy of Digilent, Inc

Programmable Logic software: Design
Entry
You can enter the design on your computer in

either of two basic ways: schematic entry or text
entry.
In order to use text entry, you must be familiar
with an HDL such as VHDL, Verilog, or AHDL.
Altera Hardware Description Language (AHDL) is
a proprietary hardware description language (HDL)
developed by Altera Corporation.
Its feature set is comparable to the synthesizable
portions of the Verilog and VHDL hardware
description languages
Entry
VHDL stands for very high-speed integrated

circuit hardware description language
It is a programming language used to model a
digital system by dataflow, behavioral and
structural style of modeling
This language was first introduced in 1981 for the
US Department of Defense (DoD)
ABEL stands for Advanced Boolean
Expression Language (ABEL).
It was created in 1983 by Data I/O Corporation

Entry
ABEL includes both concurrent equation and truth

table logic formats as well as a sequential state
machine description format
Most programmable logic manufacturers provide
software packages that support VHDL and Verilog
because they are standard HDLs.
Some also support AHDL, ABEL, or other
proprietary HDLs

Entry
Schematic entry allows you to place symbols of

logic gates and other logic functions from a library
on the screen and connect them as required by
your design
A knowledge of an HDL is not required for
schematic entry

Programmable Logic software: Building a
Logic Design
In addition to programming languages such as

VHDL and Verilog, schematic capture can also be
used in PLD development
When you enter a complete logic circuit schematic
on the screen, it is called a “flat” schematic
Complex logic circuits may be hard to fit onto the
screen and difficult to read
You can enter logic circuits in segments, save
each segment as a block symbol, and then
connect the block symbols graphically to form a
complex circuit
Logic Design
Block diagram for the traffic signal controller: A

segmentation example

Logic Design
Sequential logic block created using schematic

entry (also known as schematic capture)

Logic Design
Breaking the schematic into separate logic circuits

allows for functional compartmentalization and
easier development
The Boolean expressions are implemented using
separate logic gates with graphical representation
The completed and tested module is reduced to a
simple block symbol, as shown in following, slide
85 and can be inserted as a component
A block symbol can also be created using HDL
code

Logic Design
The sequential logic using schematic entry to

create symbol

SUMMARY
Simple Programmable Logic Devices (SPLDs)

Complex Programmable Logic Devices (CPLDs)
Macrocell Modes
Field-Programmable Gate Arrays (FPGAs)
Programmable Logic softwareTroubleshooting

SUMMARY: Lecture Recap
In this lecture we looked at the following concepts:

1. What a CPLD is
2. We now know what LAB stand for
3. Describe a LAB in a typical CPLD
4. Described the purpose of a shared expander
5. Describe the purpose of a parallel expander
6. Design flow phases for programmable logic
7. The essential elements for programming a SPLD,
CPLD or FPGA


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Digital Electronics: EE 304

Programmable Logic: Lecture 4

Electrical and Electronic Department

3 21.10.2022 H. M. Katongera – mkatongera@eng.uz.ac.zw Electrical and Electronic Department

4 21.10.2022 H. M. Katongera – mkatongera@eng.uz.ac.zw Electrical and Electronic Department

Discuss the types of programmable logic, SPLDs

5 21.10.2022 H. M. Katongera – mkatongera@eng.uz.ac.zw Electrical and Electronic Department

Show a basic software design flow for a

6 21.10.2022 H. M. Katongera – mkatongera@eng.uz.ac.zw Electrical and Electronic Department

Today, new digital circuits are programmed into

7 21.10.2022 H. M. Katongera – mkatongera@eng.uz.ac.zw Electrical and Electronic Department

At the same time, the price for a PLD is

8 21.10.2022 H. M. Katongera – mkatongera@eng.uz.ac.zw Electrical and Electronic Department

9 21.10.2022 H. M. Katongera – mkatongera@eng.uz.ac.zw Electrical and Electronic Department

PLDs, such as the FPGA, can be used in

PAL/GAL General Block Diagram

11 21.10.2022 H. M. Katongera – mkatongera@eng.uz.ac.zw Electrical and Electronic Department

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Two major types of simple programmable logic

13 21.10.2022 H. M. Katongera – mkatongera@eng.uz.ac.zw Electrical and Electronic Department

The basic structure of both PALs and GALs is a

14 21.10.2022 H. M. Katongera – mkatongera@eng.uz.ac.zw Electrical and Electronic Department

A PAL (programmable array logic) consists of a

A simple PAL structure is shown below for two

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A programmable array is essentially a grid or

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By programming the presence or absence of a

18 21.10.2022 H. M. Katongera – mkatongera@eng.uz.ac.zw Electrical and Electronic Department

Let us implement: 𝑋 = 𝐴𝐵 + 𝐴𝐵ത + 𝐴ҧ𝐵ത

19 21.10.2022 H. M. Katongera – mkatongera@eng.uz.ac.zw Electrical and Electronic Department

We need to generate the following outputs

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Below is the programming table

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Types of PAL devices:

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The GAL is essentially a PAL that can be

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Schematic of an unprogrammed GAL

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Actual PAL and GAL devices have many AND-

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A portion of a programmed PAL/ GAL

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PALs and GALs have a large number of

In the previously shown diagram which is below,

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Show how a PAL is programmed for the following

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The programmed array is shown below

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A macrocell generally consists of one OR gate

The macrocells vary in complexity, depending on

A macrocell can be configured for combinational

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Registered logic means that there is a flip-flop in

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PAL/ GAL macrocells for combinational logic

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The output of the tristate inverter can be either