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The external unit (Host Connection), supplies the following to the printer via a parallel port: power
supply voltage, reference clock and data.

Equipment status is updated by the Status Register block that stores all information regarding:
• Paper size, A4 or letter, by means of the Paper Size block
• Start and end of page, by means of the Paper Mark block
• Paper cover open or paper finished, by means of the Paper Out block
• Thermal head malfunction indicators by means of the Thermal Head Alarm block
• Indications from the keyboard by means of the Keyboard block

The Control Register 1 block updates the LED indicator status taking into account equipment status and
transfers power supply voltage to the Power Supply block for printer operation.

The Reference Clock Generator block generates the external time reference for internal equipment
synchronisation.

The DSP block processes the digital signal and the manages equipment by means of the program stored
in the EPROM (non-volatile memory).

The Control Register 0 block controls the drive motor and supplies other controls for general
equipment operation.

The thermal head is managed by the RISC block by means of the program stored in the EPROM (non-
volatile memory) and by means of the Print Head Control block.

The RISC block, and therefore the thermal head, are activated by the DSP only when the print
command is given via the Command Communication Channel block, while data are transferred from
the Data Communication Channel block.

III - 1
$UFKLPHG3URGXFWV6HUYLFH0DQXDO 6HFWLRQ

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The analog signal ECG enters the floating section of the equipment via the patient cable and after pre-
processing (ANALOG PROCESSING), sampling (S/H and MUX) and pre-amplification (GAIN) it is
converted into a digital signal (A/D) and transferred to the DSP block for further processing.

The optoisolator array ensures insulation between the floating and non-floating sections of the
equipment.

The DSP block serves to process the digital signal by means of a program stored in the BOOT EPROM
(non-volatile memory) which at the time of program execution is transferred to the PROGRAM RAM
to obtain a transfer speed suited to the DSP execution speed. The data are saved in the DATA RAM.
Processed data are transferred to the memory shared by the DSP and CPU (SHARED RAM). The
SHARED MEMORY MANAGER block manages the shared memory.

The DSP I/O SELECT block manages digital signal input /output from the DSP.

The DAC block converts the digital/analog signal to enable an analog output.

The CPU block manages the system by means of a program stored in the EPROM. The system
configuration is stored in the FLASH EPROM while data used by the CPU are stored in the RAM
block. The CPU block manages the RS232 serial connection directly.

The CPU DATA bus transfers data to the CPU which then transfers them to the internal peripherals
(Floppy Disk Drive and Display) and external peripherals (Printer) by means of the relative interfaces
(UNIVERSAL PERIPHERAL CONTROLLER, VGA CONTROLLER and PRINTER INTERFACE).
The bus also enables data transfer from the keyboard to the CPU via the KEYBOARD INTERFACE
block. The signal sent from the VGA CONTROLLER is conveyed externally for possible connection to
an external colour monitor.

The POWER SUPPLY block is connected to an external AC line and generates continuous voltage
required to power the system by means of the DC REGULATOR unit. The POWER SUPPLY also
enables battery stack recharging by means of the BATTERY CHARGER block. VCLOCK voltage
supplies the REAL TIME CLOCK block and updates the clock in real time.

III - 2
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The analog signal ECG enters the floating section of the equipment by means of the patient cable and
after pre-processing (ANALOG PROCESSING), sampling (S/H and MUX) and pre-amplification
(GAIN) it is converted into a digital signal (A/D) and transferred to the DSP0 block for further
processing.

The optoisolator array ensures insulation between the floating and non-floating sections of the
equipment.

The DSP block serves to process the digital signal by means of a program stored in the BOOT EPROM
(non-volatile memory) which at the time of program execution is transferred to the PROGRAM RAM
to obtain a transfer speed suited to the DSP execution speed. The data are saved in the DATA RAM.
Processed data are transferred to the memory shared by the DSP0, DSP1 and 486 CPU (486 Board)
(SHARED RAM). The SHARED MEMORY MANAGER block manages the shared memory.

The DSP I/O SELECT block manages digital signal input /output from the DSP.

The DAC block converts the digital/analog signal to enable an analog output.

The DSP1 block carries out further processing of the digital signal and manages the external thermal
printer by means of the PRINTER INTERFACE block. The DSP1 program is stored in the FLASH
EPROM BOOT together with the equipment configuration. The PROGRAM RAM and DATA RAM
blocks are the same as those used by the DSP1.

The POWER SUPPLY block is connected to an external AC line and generates continuous voltage
required to power the system by means of the DC REGULATOR unit. The POWER SUPPLY also
enables battery stack recharging by means of the BATTERY CHARGER block. VCLOCK voltage
supplies the REAL TIME CLOCK block and updates the clock in real time.

III - 3
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The 486 CPU block, with the relative control system, is used for general management of the equipment
and external/internal peripherals excluding the thermal printer.

The system bus transfers the data to the 486 CPU which then transfers them to the internal peripherals
(Floppy Disk Drive, Hard Disk Drive and Display) and external peripherals (RS232 Connections,
ETHERNET network, Laser printer) by means of the relative interfaces (UNIVERSAL PERIPHERAL
CONTROLLER, VGA CONTROLLER, RS232 INTERFACE and ETHERNET CONTROLLER). The
bus also enables the transfer of data from the keyboard to the CPU by means of the KEYBOARD
INTERFACE block. The KEYBOARD INTERFACE and RS232 INTERFACE blocks (with a RS232
connector) and ETHERNET CONTROLLER are located on the Main Board. The signal from the VGA
CONTROLLER is also conveyed externally (the CRT connector is positioned on the Main Board) for
possible connection to an external colour monitor.

&RQQHFWRU%RDUG

The board contains:

• The coaxial connector for the ETHERNET network (managed by the ETHERNET CONTROLLER
block), with relative receiver/transmitter and insulation transformer.
• 3 RS232 serial connectors, 2 managed by the UNIVERSAL PERIPHERAL CONTROLLER block
and 1 by the RS232 INTERFACE block.
• The parallel connector for connection to a possible external laser printer (PRT Conn) managed by
the UNIVERSAL PERIPHERAL CONTROLLER block

III - 4
 1 2 3 4 5 6 7 8
-- NON DISTRUGGERE MAI --
ORIGINALE AUTOGRAFO

Parallel Port
D
Reference
Host Connection Osc. Clock
Generator

Paper Size

Control Reg. 0
Motor Paper
Drive Motor

Status Register
Paper Mark

A TERMINI DI LEGGE E’ VIETATO RIPRODURRE O COMUNICARE A TERZI IL CONTENUTO DEL PRESENTE DISEGNO
C
Paper Out
DSP EPROM RAM

optional

Head Thermal
Alarm

Keyboard

Leds
Control Reg. 1

Indicators

Command Data
Communication Communication EPROM RAM RAM
Channel Channel
optional

B
ARCHIVIO DBTEC
ARCHIVIO CAD

JTAG RS232

Power Supply RISC Print Head

Control
Interf.

optional
Interf.

optional
COPIA CONFORME
ALL’ ORIGINALE

Print Head

FORMATO REVISIONE PREPARATO: CONTROLLATO: APPROVATO: DATA: DENOMINAZIONE:

4240 ECG Printer - Block
A3 Nr. O.V.
Magherini Donnini Cerofolini 16-01-97
Cod. Doc.: Revisione:
by Visula DISEGNATO 970 4240 000 SB A Foglio1/1

Electronic copy (C)1996-2000

 1 2 3 4 5 6 7 8
-- NON DISTRUGGERE MAI --
ORIGINALE AUTOGRAFO

ANALOG PROCESSING S/H OPTOCOUPLERS DSP I/O DAC

& SAMPLE SAMPLE RATE SELECT
MUX PULSE CONTROL ANALOG OUTPUT
ANALOG PROCESSING DSP DATA
GEN.
DSP DATA
D ANALOG PROCESSING

GAIN A/D
ANALOG PROCESSING

ANALOG PROCESSING DSP BOOT EPROM PROGRAM RAM DATA RAM

ANALOG PROCESSING CHAN

SELECT
ANALOG PROCESSING
DSP ADDR
ANALOG PROCESSING SPORT
DSP DATA
PATIENT INPUT
CABLE CONTROL
CONNECTOR
SHARED RAM

A TERMINI DI LEGGE E’ VIETATO RIPRODURRE O COMUNICARE A TERZI IL CONTENUTO DEL PRESENTE DISEGNO
+5V FLOAT SHARED MEMORY
SHARED MEMORY DATA MANAGER
FLOATING SECTION POWERING
C SHARED MEMORY ADDR

CPU CPU DATA

INVERTER CPU ADDR

EPROM FLASH EPROM RAM

EEPROM PIO

RS232
VCC

DC REGULATORS BATTERY CHECK

B
CPU I/O
SELECT

POWER SUPPLY CPU DATA

LINE VIDEO
MEM
ARCHIVIO DBTEC

UNIVERSAL KEYBOARD PRINTER FLAT PANEL/CRT DATA VIDEO MEMORY

ARCHIVIO CAD

REAL TIME CLOCK

PERIPHERAL INTERFACE INTERFACE VGA CONTROLLER
CONTROLLER VIDEO
MEM
VCLOCK ADDR
BATTERY
CHARGER
COPIA CONFORME
ALL’ ORIGINALE

RS232 PRT
A BATTERY CONN. CONN.
VCLOCK

4210 MAIN BOARD

LCD POWER DISPLAY

KEYBOARD CONTROL
FLOPPY DISK DRIVE

FORMATO REVISIONE PREPARATO: CONTROLLATO: APPROVATO: DATA: DENOMINAZIONE:

4210: SCHEMA A BLOCCHI
A3 Nr. O.V.
CHIODAROLI DONNINI CEROFOLINI 15/1/97
Cod. Doc.: Revisione:
by Visula DISEGNATO 970 4210 000 SB A Foglio1/1

Electronic copy (C)1996-2000

 1 2 3 4 5 6 7 8 9 10 11

ANALOG PROCESSING S/H OPTOCOUPLERS DSP I/O DAC

& SAMPLE SAMPLE RATE SELECT
MUX PULSE CONTROL ANALOG OUTPUT
ANALOG PROCESSING DSP DATA
-- NON DISTRUGGERE MAI --

GEN.
F DSP DATA
ANALOG PROCESSING
ORIGINALE AUTOGRAFO

GAIN A/D
ANALOG PROCESSING

ANALOG PROCESSING DSP0 BOOT EPROM PROGRAM RAM DATA RAM DSP1 FLASH EPROM PROGRAM RAM DATA RAM
(BOOT)
ANALOG PROCESSING CHAN
SELECT
ANALOG PROCESSING
DSP0 ADDR DSP1 ADDR
ANALOG PROCESSING SPORT SPORT
DSP0 DATA DSP1 DATA
PATIENT INPUT
CABLE CONTROL
CONNECTOR
SHARED RAM
+5V FLOAT SHARED MEMORY
SHARED MEMORY ADDR DSP I/O
MANAGER DSP1 ADDR SELECT
E FLOATING SECTION POWERING
SHARED MEMORY DATA

PRINTER
INTERFACE
DSP1 DATA PRT
CONN.
INVERTER

PIO KEYBOARD
INTERFACE

VCC MATRIX
EEPROM KEYBOARD

DC REGULATORS BATTERY CHECK

D ETHERNET EEPROM
CONTROLLER ISOL ETHERNET COAX
TRANSCEIVER CONN.

VCC
RS232
CONN.
RS232
INTERFACE

POWER SUPPLY RS232

LINE RS232 CONN.
CONN.

A TERMINI DI LEGGE E’ VIETATO RIPRODURRE O COMUNICARE A TERZI IL CONTENUTO DEL PRESENTE DISEGNO
RS232
CONN.
BATTERY BUFFERS
CHARGER 486 CPU
PRT
C 486 ADDR BUS CONN.
ISA ADDR BUS UNIVERSAL CONNECTORS BOARD
486 DATA BUS PERIPHERAL
BATTERY CONTROLLER
VCLOCK ISA DATA BUS
FLOPPY DISK DRIVE

3.3V

HARD DISK DRIVE

DC/DC
VCC
DRAM MODULE 84031 84035
DRAM ADDR DMA CONTR.
& DRAM CONTROL
ISA BUS CONTR. PIC
CONTROL TIMER
VL BUS CONTR.
RT CLOCK

KEYBOARD & MOUSE

MOUSE CONN.
CONTROLLER
KEYBOARD
ARCHIVIO DBTEC

CONN.
ARCHIVIO CAD

EPROM (BIOS)

VIDEO
COPIA CONFORME
ALL’ ORIGINALE

MEM LCD POWER DISPLAY

DATA FLAT PANEL/CRT CONTROL
VIDEO MEMORY
A VGA CONTROLLER
VIDEO
MEM
CRT ADDR
CONN.

MAIN BOARD 486 BOARD

FORMATO REVISIONE PREPARATO: CONTROLLATO: APPROVATO: DATA: DENOMINAZIONE:

4220: SCHEMA A BLOCCHI
A2 Nr. O.V.
CHIODAROLI DONNINI CEROFOLINI 15/1/97
Cod. Doc.: Revisione:
by Visula DISEGNATO 970 4220 000 SB A Foglio1/1

Electronic copy (C)1996-2000