5-8 Complete Computer Descri flowchart for basic * The final flowchart of the instruction cycle, including the interrupt cycle for computer the basic computer, is shown in Fig. 5-15. The interrupt flip-flop R may be set at any time during the indirect or execute phases. Control retums to timing signal Ty after SCis cleared to 0. ILR = 1, the computer. goes through an inter- rupt cycle. If R = 0, the computer goes through an instruction cycle. If the insthreto i-one Gt the ‘memory-reference instructions, the computer first checks if there is an indirect address and then continues to execute the decoded instruction according to the flowchart of Fig. 5-11. If the instruction is one of the register-reference instructions; it is executed with one of the microoperations listed in Table 5-3. If it is an input-output instruction, it is executed with one of the microoperations listed in Table 5-5. Instead of using a flowchart, we can describe the operation of the com- Puter with a list of register transfer statements. This is done by accumulating all the control functions and micfooperations in oné table. The entries in the table aré taken from Figs. 5-11 and 5-16, and Tables 5-3 and 5-5. ‘The control functions and microoperations for the entire computer are summarized in Table 5-6. The register transfer statements in this table describe in a concise form the internal organization of the basic computer. They also give all the information necessary for the design of the logic cireuits of the computer. The control functions and conditional control statements listed in the table formulate the Boolean functions for the gates in the control unit. The list of microopérations specifies the type of control inputs needed for the reg- isters and memory. A register transfer language is useful not only for describ- ing the internal organization of a digital system but also for specifying the logic circuits needed for its design. Design of Basic Computer 2 The basic computer consists of the following hardware components: jive Jar ERRRE2E /RSRRRREREEE 8 i Scanned with CamScanner164 courrer net Baie Comper Ogaiation and Design Table 56 to find the statement apd Monts eco fom he pa 4 Sn. The ed py Read = RT, + Dyit, + (0, + D, + Dy ‘The output ofthe logic gates that i ‘ust be connected to th ead input ot annoy, Control of Single Flip-flops Soa eters S eeesener ee eS eS etn ma instructions ION and IOF. $B: TENG 7B: TENA where p= DyIT, and B, and By are bits 7 and 6 of IR, respectively. Moreove atthe end ofthe interrupt cycle JEN s cleared to 0. Rty 1ENAO we use a JK flip-ip for ZEN, the control gate logic will be as shown Fig. 518. Control of Common Bus Boolean variable x, through x, corresponding tothe gate structure that may bbe active in order to select the register or memory forthe bus. For examy when x, = 1, the value of $,5,$ must be OO! and the Figure 518 Control input for IEN. iplement the Boolean expression abon r +D)T ‘output of AR wal > => coe} DP secron 5.9 Design o Basic Comper 65 “TABLE 5-7 Encoder fo Bus Selection Circuit selected for the bus. Table 57 is recognized as the truth table of binary . acoder. The placement ofthe encoder tthe inputs ofthe bus selection logic {S shown in ig 519. The Boolean functions for the encoder are S-atatats + Semtataty Saatatyte ‘To determine the logic fr each encoder input, it is necesmy to find the control functions thal place the corresponding register onto the bus. For exam- Pl, to find the loge tal makes =, ~ 1, we sca all register transfer slatements fn Table 56 nd extract those statements Ut have Aas a soures. DT: PC AR DsT: PC AR ‘Therefor, the Boolean function for sis " na DT + DE Figure 5-19 Encoder for bus selection inputs. 2 t+] 5 Muttiperer * Encoder |S, busselect — a Scanned with CamScannersem 5:10 ! 166 curr ve Basic Computer Onpenition and Deon acio-7)- INPR i “The data output from memo Ace cE ‘output from memory ae selected f fer AG, 4C5) S,5,S = I. The gate logic that generates 1 must ue cE | OS UL Tepe ee pee dec aiac 400 ! Sere rly treo peice, pee ces | we RT, + DT + (+ + D+ DT te jee cna lng pron ae aL | Ina similar manner we can determine the gate logic forthe other registers Fm nat we at : : joer ee oecarn i Control of AC Revise 1, nyp, and CLR inputs of AC sh I ‘The gate atzacture that controls the LDP, YT or a2 contol functions in the Pas a The gute configurations dened Fine $21. Gate acre for conaing te LD INE and CLR of AC. From adder 19 4c Tobe ndog Lo check > five [our Do: ACeACADR Dil: 4Ce-AC+ DR Di: AC DR “Transfer from DR Figure 5.20 Circuits associated with AC. 15. be Scanned with CamScannerFigure 5-22 One sage of adder and lope circuit crow 5.40 Design of AccumnorLope 169 Jed, the 16 inpats I, for #= 0, by ‘output AC{). When the LD Dyan 1S ae transferred to cuit consists of seven AND gates, on vom in Fig, 522. The inputs of the gates fates marked with the me ft marked ADD in Fig- 5-21 sand the shift-left operation transfers the Bit from AC(— 1). ‘The complete adder and logic cient consists of 16 sages connected together. Scanned with CamScanner 4a ——_., @ ‘A computer ues « memory wait with 256K words of 32 bits each binary ‘RSSESSETE htcd im euc wed of mencny Te imtrctin oer SES a opera codes oie code pe to pel oe oh Sem and uncles pre T'fovTauny bn re ther in the pero ad, the vepster ode teen pu d 1s Dre tecton word fra and nde he uberis ech pr cw sony bis re there nthe data and adres np of te memory? 52 Whats the dierence between a dcet and an indirect ae instruction? 52, Thefillowing control inputs are active a the bu tem shown in Fig 4 For ‘ch ete ply the rege enfer that wil be exeated using the bet lock ‘ston BS & WDotregner Memory Adder Pe reer Read rear Rane ana ye © 1.0 0., be Wee a0. eet Eee SA. Thefolowing regis tantra to be executed in Tes cated in th rte of Fig 54. For spec (I) the inary vale at mus be tppled to bus ale spe170. comrren vt Bac Compe Orntation sd Design on tions, gv the equlvalent ourdigt hexadecimal ede and explain your ma words whal its tal the naruto 8 ging te petra, ‘& oot co00 0010 0100 & tot coor 0010 0100 OWL 6000 9010 O20 ‘What re he two istrcinn mend in the basic computer nde st he Edip hop ta 1? = ‘Dra aiming diagram ina to Fig $7 assuming hat SCiceared oO ine Tvcamimd Geacwe LDC Adare rR essai) 3. Add regiter reference intron ICSZ: Increment CTR and skip ext insveson if ser, Discs the advantage ofthis change (aires aedren) withthe adress part ofthe instruction csiding in postions through I. Bat when J 0 (fret adres), the addres ofthe isiruction is Scanned with CamScannerpw ot fave Comparer Organization and Design 518. 520, Fancher Ing 99 ees ene Hor ney die Aa output program resides in memory sartig from adden 2200. Ris exected see computer regis an inter when RO me oie ‘2 What instruction must be placed at adres 1? “The operations to be performed wit fipflp F (oot wed inthe basic com otc) are specified by the folowing register transfer satement: wy Felt StFol Yi: FeO CewrFiod de FER Complement F wh; FEG — Tanservaleof Gio F ‘Otherwise, the content of Frat nt change. Draw the logic diagram showing {Be connections of the gates tat form the conto functions and the aps of Hip Mop F Use a JK Dip flop and minnie the numberof gles cron 5.10 Design of Accamubit Lope 173 521 Derive the contol gates associated with the program counter PCin he basic 1. Bel. C.6, J.C. Madge, ad J. E. MeNamara, Computer Engineering. Bedford MA: Diglal Pres, 1980. 2, Booth, TL, tedaton to Computer Engnering Seed. New York John Wiley, 1984 + 3, Gibson, GA, Computer’ Sytoms Compt and Design. Englewood Cis, NJ: Prentice Hal, 1961 4. Gray, NAB, latodaton to Compster Spon. Englewood Cif, NJ: Prentice Hal, 1982 5. Hill FJ, and G, R. Peterson, Dita Sten: Hardware Organica and Des ee [New Yor: Joba Wiley, 1987 6, Lewin, MCF. Lege Doign ond Computer Orgenzton. Reading, MA: Asan Wesley, 1983, 1 MM Ma ptr aging Had De aero Cs Prentice 8, Patenon,D. A. and J. L. Hennessy, Computer Arecure: Quantaive Approach San ‘Mateo, CA: Morgan Kaufinann Publishers, 190. 9, Prower,E-P and D. E. Winkel, The Arto Digital Dag, 2nd ed. Englewood Cis, NJ: Preis Hall, 1987, 10, Shiv SG Design end Archer Dod ed. New York: ms SCout HarperColl Scanned with CamScanner