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    Imp Instruction Formats and Addressing M

    Uploaded by

    yuvrajahuja2003

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    © All Rights Reserved
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    rE SECTION 84 Insttion Ean conversion for the user. Most compilers, irrespective of their CPU oy, tion, convert all arithmetic expressions into Polish notation anyway ENG thar is the most efficient method for translating arithmetic expressions in, machine language instructions. So in essence, a stack-organized CPU may he more efficient in some applications than a-CPU without a stack. \\ Ww 4 Instruction Formats ‘The physical and logical strycture of computers is The phil provided with te sytem. Soch manuals xpi the internal Fading the proceso’ riers avalable and thet consrueion of the CT logical capabilites. They list all hardware-implemented instructions, specify se definition of each instruction. normally described in ref- “heir binary code format, and provide a precise ¢ E {A computer will ‘usually have a variety of instruction code formats. It is the Function of the control unit within the CPU to interpret each instruction code and provide the necess: led to process the instruction. Z ‘The format ctangular box sy - the bits of the instruct y regis e bits of the instruction are divided into The most common fields found in instruction formats are: sa/€ode Iheld that specifies the operation to be formed. thai, designates « memory. address ar @ processor + the effective address ffelds are sometimes employed undet certain circumstances, as field that gives the number of shifts in, a shift-type instruction. a tions of bits that define jous processor operatio tract, complement, and shi A a a rioaradioas ae ¢ "strucions are enumer- an ;¢ most common operations avi er special imple’ tod and discussed in’ Sec. 86, The’ bits that define the mode : justiiétion ‘code specify'a variety. of: 4 7 F he pivei addFéss. The various addressing modes that have been formu- Farrer digital computers are presented in Sec. 8-5. In this section we are con- ; iitstruction format and consider the effect sified By Ir speeitied With'a iti ster iddregs.'A’ that’ defines one of 2! the GPUs " 7 16 processor Scanned with CamScanner == a = 1 Fon Stipes tee ae eee | eee satemne 158 signais regi RS. General regitertype computers employ two of three addeess fields a ey Se Se a eying ni : ‘ fatereancet aml ; a rks 0 j 05K A warp ie word ade Xo the Wp OUT #ae? The stack pointe is va pa Wee icy inno Jono ned on ae edad oma re stecustheopeaton peste) a eau op cee Toe secon Ey pire gdAveze® : natch comput consis ofan operation code oly with 0 are ld Ths poration haste efect of popping the two lop numbers fom Une ack sing ee ug Gaus ie tad Thre no pond ely on dnc al operas re pdt be i the sack aon le ire peso organizations at have bar & ii Be FE 2. Only register addresses for rer et be specie in dis matcions i > 4 R2 ne espe procenor registers te the move into wi i . bs ts ES RTOV to symbolize a tansfersatrytin, Thus the insruction Q cee cof the number of addresses on compute pro- se porns ‘grams, we wil evaluate the asthmatic ateent agen ins R212 depeng on pro : : Sea ome PPB! > leg bean h ee fipmanlna asl pe ane tons ened ‘aiding 2676! one, to, of thied addreds initiutions. We will use the symbols sae ‘ADD, SUB, MUL, and DIV forte fear arithmetic operations; MOV forthe Scanned with CamScanner 260 atarre noi Cenl Procening Unit transfertype operation; and LOAD and STORE for transfers to and from mem ‘ory and AC register. We will assume thatthe operands are in memory address, ‘2B, Gand D, and the result must be stored in memory ataddvess X. ee ‘The MOV inaction moves or antes the operands and om mem, ory and processor fegiaters. The first symbol listed in an instrction cast «ot , . weasgumed be botha. source andthe destination where the result of th ppesation is transferred. yy) yo e i er a a operations are done between the ACregister and a memory operand ‘isthe adress of temporary memory location required for storing the inter- “To evalute arithmetic expressions in «stack cSmputer, iti ann Sepa ee each eet heey ie gen o bis ype of computer because ofthe absence ofan sldrecs Bld the computational instructions. : east HSC Insieyctiong.y. cores zvanages of a. fediced instruction set comptice (RISC) archi Peanedin oc 88 The nsucton of pica ISS eS ae Scanned with CamScanner =F FF 2652. conrnn ocr Cenueal Procesing Unt : to the use of load and store instructions when communicating betw' within ‘of LOAD and STORE instructions that have one memo ‘pes nT UMP TIC age nee that have three addresses witha ree specifying processor registers. The following isa program to evaluate fede aeeeD " So, Torredace the number of bits in tbe ade silat fhe wresing ode es tne expesenced assent | ‘The availability ofthe pressing modes ves the experienced mre Hes lone nd excain Se 2 bFspect te vss addressing modes presented in tise +i tydimperatir tt we anderiand a bade Operation eye oft Scanned with CamScanner saa sere Ciro ARES Ta TESS tre Uranchype Sng moses in Chap. 5. They 0 na the conjunction with Fig. 52. TA fow addressing modes require that the address field of the instruction ‘be added to the content ofa specific register in the CPU. The effective address in these modes is obtained from the following computation: ‘Antolacrement or Autodecrement Mode: This is similar to the rect mode except thatthe segster is incremented or decremented aft its value i, Scanned with CamScanner secrion 65 Addeening Modes 267 <<. a? - 2, 7 cata 7, Tne soogea "Next instruct ction ~~ : i aa b at ae 5 Scanned with CamScanner + next sections 9 ‘Most computer instru secrion 8-6 Data Trarser nd Minin Scanned with CamScanner J 270 carn wou Cenual Processing Unit TABLE 8.6 Eight Addresing Modes for the Load I Insertion Azembly Mode Convention H Direct address LD ADR shitter abet cmtgaieed porte Circuits for their implementation Relaive address LD SADR. Immediate operand LD #NBR ieee ae AcithmeticTastrctions Regu indieet LDR) “The four basic arithmetic operations aze ait Autoincrement Ry) and division. Most computers provide instruct Seme small computers have only addition and possibly subtraction instruc tion fication and division must then be generated by means of, tions. The muliplication Software subroutines The four basic arithmetic operations are suficient for different addressing modes. Table 8-6 shows the recommended assembly formulating solutions to scientific problems when expressed in terms of numer. e ical analysis methods. ‘Stands for an address, NBR is a number or operand, Xis an index register, 2 "A lat of typial arithmetic instructions is given in Table 87 The incre a proce ment instruction add 1 to the value stored in a register or memory word. One bolizes an indirect address. The $ character before an address makes th ‘ommon characters ofthe inerement operations when executed:in proces- Sor registers is that a binary number of all i when inerementedprosaces 2 ‘O's. The decrement instruction subtraets 1 from a value stored in address relative to the program counter PC."The # character precedes ‘operand in an immediate-mode intriction. An indexed mode instruction ise result of all “ognized by a register that is placed in parentheses ater the symbolic addrex I register or memory word. A number with all 0's, when decremented, pro- ‘The register mode is symbolized by giving the name ofa procesor register,

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