Week 2: Course Material

DFT (Contd.)
(C td )
Lecture 6
 Structured
Approach
D Scan design
• Convert the sequential design into a scan design
• Three
Th modes
d off operation
ti
– Normal mode
• All test signals are turned off
• The scan design operates in the original functional configuration
– Shift mode
– Capture mode
• In both shift and capture modes
modes, a test mode signal TM is
often used to turn on all test-related fixes

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 St t d Approach
Structured A h ‐ Scan
S
Design
Assume that a stuck-at
stuck at
X1
X2
Combinational logic Y1 fault f in the combinational
Y2
0 X3 logic requires the primary
f
input X3, flip-flop FF2,
andd flip-flop
fli fl FF3, to t be
b sett
0 FF3 to 0, 1, and 0.
Q D
The main difficulty in
1 FF2
testing
i a sequential i l circuit
i i
Q D stems from the fact that it
FF1
. is difficult to control and
Q D
observe the internal state
CK . of the circuit.

Difficulty in testing a sequential

circuit
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 St t d Approach
Structured A h ‐ Scan
S
Design
Test stimulus application
n
1 1
Test stimulus Shift register composed of n scan cells Test response

n
Test response upload

1. Converting How to detect stuck-at fault f :

selected
l d storage (1)switching
(1) i hi to shift
hif mode
d andd shifting
hif i in
i the
h desired
d i d test
elements in the design stimulus, 1 and 0, to FF2 and FF3, respectively
into scan cells. (2) driving a 0 onto primary input X3
(3)switching to capture mode and applying one clock
1. Stitching them
pulse to capture the fault effect into FF1
together to form scan (4)switching back to shift mode and shifting out the test
chains. response stored in FF1, FF2, and FF3 for comparison with
the expected response.

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 Scan Cell Design
D A scan cell has two inputs: data input
and scan input
• In normal/capture mode, data input is selected to update the
output
• In shift mode, scan input is selected to update the output

D Three widely used scan cell designs

• Muxed-D Scan Cell
• Clocked-Scan Cell
• LSSD Scan Cell

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 Muxed‐D
Muxed D Scan
Cell
This scan cell is composed of a D
DI 0
D Q Q/SO flip-flop and a multiplexer.
SI 1

SE CK
The multiplexer uses an additional
Edge-triggered
Ed ti d scan enable
bl input
i t SE to
t select
l t
muxed-D scan
cell
between the data input DI and the
scan input SI.

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 Muxed‐D
Muxed D Scan
Cell In normal/capture
o /c p u e mode,
ode,
SE is set to 0. The value
CK
present at the data input
SE
DI is captured into the
internal D flip-flop
flip flop when
DI a rising clock edge is
D1 D2 D3 D4
applied.
SI
T1 T2 T3 T4 IIn shift
hift mode,
d SE is i sett to
t
1. The scan input SI is
Q/SO
D1 T3 used to shift in new data
to the D flip-flop, while
the content of the D flip-
Edge-triggered muxed-D scan flop is being shifted out.
cell design and operation

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 Muxed‐D
Muxed D Scan
Cell
This scan cell is composed of a
DI
SI
0
1
D Q . Q
multiplexer, a D latch, and a D
flip-flop.
p p
CK
SE D Q SO In this case, shift operation is
conducted in an edge-triggered
CK . manner while normal operation
manner,
and capture operation is
conducted in a level-sensitive
manner.
Level-sensitive/edge-
g
triggered muxed-D scan
cell design

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 Clocked‐Scan
Clocked Scan
Cell

DI In the clocked-scan
SI
Q/SO
cell,
ll input
i t selection
l ti isi
conducted using two
DCK SCK independent clocks,
DCK and SCK.
Clocked-scan cell

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 Clocked‐Scan
Clocked Scan
Cell
In normal/capture mode,
mode
the data clock DCK is used
to capture the contents
present at the data input DI
i t the
into th clocked-scan
l k d cell.
ll

In shift mode, the shift

clock SCK is used to shift
i new data
in d from
f the
h scan
input SI into the clocked -
scan cell, while the content
of the clocked-scan cell is
Clocked-scan cell design
being shifted out.
and operation

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 LSSD Scan Cell
An LSSD scan cell is
used for level-sensitive
. SRL latch base designs.
D . .
L1
+L1
This scan cell contains
C . two latches, a master 2-
port D latch L1 and a slave
I . .
L2
+L2 D latch L 2. Clocks C,
A and B are used to select
A . . between the data input D
and the scan input I to
B drive +L1 and +L2. In an
LSSD design,g , either +L1
or +L2 can be used to
Polarity-hold SRL drive the combinational
(shift register latch) logic of the design.

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 LSSD Scan Cell
C IIn order
d tot guarantee
t race-free
f
operation, clocks A, B, and C are
A applied in a non-overlapping
B manner.

D D1 D2 D3 D4 The master latch L1 uses the system

clock C to latch system data from the
I T1 T2 T3 T4 data input
p D and to outputp this data
onto +L1. Clock B is used after clock
D1 T3
+L1 A to latch the system data from latch
T3
L1 and to output this data onto +L2.
+L2

Polarity-hold SRL design and

operation

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 Comparing three scan cell
designs
Advantages Disadvantages

Muxed-D
M d D Scan
S Compatibility
C tibilit to
t Add a
modern Cell designs multiplexer
Comprehensive support delay
provided by existing
design automation tools
Clocked-Scan No performance
degradation Cell Require additional
shift clock
routing
LSSD Scan Insert scan into a latch- Increase
based Cell design routing
EE141 Guarantee to be race-free complexity
DFT (Contd
(Contd.))
Lecture 7
 Scan Architectures
D Full-Scan Design
• All or almost all storage element are converted into scan cells
and combinational ATPG is used for test generation
D Partial-Scan Design
g
• A subset of storage elements are converted into scan cells
and sequential ATPG is typically used for test generation
D Random-Access Scan Design
g
• A random addressing mechanism, instead of serial scan
chains, is used to provide direct access to read or write any
scan cell
43
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 Full-Scan Design
D All storage elements are replaced with scan cells
• All inputs can be controlled
• All outputs can be observed
D Advantage:
• Converts sequential ATPG into combinational ATPG
D Almost full-scan
full scan design
• A small percentage of storage elements are not replaced
with scan cells
– For performance reasons
• Storage elements that lie on critical paths
– For functional reasons
• Storage elements driven by a small clock domain that are
deemed too insignificant to be worth the additional scan
insertion effort
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 Muxed‐D Full-Scan
Design
X1 Y1
X2 Combinational logic
X3
Y2 The three D flip
flip-
FF1 FF2 FF3 flops, FF1, FF2 and
D Q D Q D Q FF3, are replaced
CK . . with three
w ee muxed-D
u ed
scan cells, SFF1,
SFF2 and SFF3,
respectively.
p y
Sequential circuit example

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 D Full-Scan
Muxed‐D
Muxed Full Scan
Design
X1 Y1
To form a scan chain,
chain
PI X2 PO the scan input SI of
Combinational logic Y2
X3
SFF2 and SFF 3 are
PPI PPO
connected to the output
Q off the
th previous
i scan
cell, SFF1 and SFF2,
SFF1 SFF2 SFF3
DI DI DI
respectively. In
SI SI Q . SI Q . SI Q . SO addition, the scan input
SE SE SE SI of the first scan cell
SE
CK
. . . . SFF1 is connected to
the primary input SI,
and the output Q of the
last scan cell SFF3 is
(a) Muxed-D full-scan circuit connected to the
primary output SO.

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 D Full-Scan
Muxed‐D
Muxed Full Scan
Design
• Primary inputs (PIs) • Primary outputs (POs)
– the external inputs to the – the external outputs of the
circuit circuit
– can be set to anyy required
q logic
g – can be observed
values – are observed directly in
– set directly in parallel from the – parallel from the external
external inputs outputs
• Pseudo primary inputs • Pseudo primary
(PPIs) outputs (PPOs)
– the scan cell outputs
– the scan cell inputs
– can be set to any required logic
values – can be observed
– are set serially through scan – are observed
b d serially
i ll through
h h
chain inputs scan chain outputs

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 D Full-Scan
Muxed‐D
Muxed Full Scan
Design
PI V1: PI V2: PI
SE
S H C H S H C
CK
SFF1.Q 0 1 1 1 L L 1 0 1 1 L
SFF2.Q X 0 1 1 H H L 1 0 0 L
SFF3.Q X X 0 0 L L H L 1 1 H

V1: PPI V2: PPI

PO PPO
observation observation

S: shift operation / C: capture operation / H: hold cycle

(b) Test operations

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 D Full-Scan
Muxed‐D
Muxed Full Scan
Design
Circuit Sca TM SE
Operatio n
n type cell
mod
e
Normal Normal 0 0

Shift Shift 1 1
Operation

Capture Capture 1 0
Operation
p
Circuit operation type and scan cell
mode

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 Clocked Full-Scan
Full Scan
Design
In a muxed-D full-
X1 Y1 scan circuit, a scan
PI X2 PO enable signal SE is
X3 Combinational logic Y2
PPI PPO used.

In a clocked full-
scan design, two
SFF1 SFF2 SFF3 operations are
DI
SI
DI
SI Q . DI
SI Q . SI Q . SO
distinguished by
DCK SCK DCK SCK DCK SCK properly applying
DCK . . . . the two independent
SCK clocks SCK and
DCK during shift
mode
d andd capture
t
Clocked full-scan circuit mode.

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 LSSD Full-Scan Design
g
D Single-latch design
D Double-latch design

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 LSSD Full-Scan Design
X1 X3 The output port
Combinational logic 1 Combinational logic 2
X2 Y1
Y2
+L1 of the master
latch L1 is used to
SRL1 SRL2 SRL3 drive the
D D D combinational
SI SO
g of the
logic
I +L2 I +L2 I +L2
C C C
A +L1 A +L1 A +L1
B B B design. In this
C1 .. .. case, the slave
A
B
. latch L2 is onlyy
C2
used for scan
Single-latch design testing.

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 IIn normall mode,
d the
h C1
LSSD Full-Scan Design and C2 clocks are used
in a non-overlapping
Manner.
During the shift
X1 Y1 operation, clocks A and
X2 Combinational logic
X3 Y2 B are applied in a non-
overlapping manner,
SRL1 SRL2 SRL3 the scan cells SRL1 ~
D D D
SI I +L2 . I +L2 . I +L2 . SO SRL3 form a single
C C C scan chain from SI to
A +L1 A +L1 A +L1 SO
SO.
B B B
C1 .. .. During the capture
A
. . operation, clocks C 1
C2 or B and C2 are applied to
load the test response
from the combinational
Double-latch design logic into the scan
cells.

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 LSSD Design Rules
D All storage elements must be polarity-hold latches.
D The latches are controlled by two or more
non- overlapping clocks.
D A set of clock primary inputs must follow three
conditions:
• All clock inputs to SRLs must be inactive when clock PIs are
inactive
• The clock input to any SRL must be controlled from one or
more clock primary inputs
• No clock can be ANDed with another clock or its
complement

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 LSSD Design Rules
D Clock primary inputs must not feed the data inputs
to SRLs either directly or through combinational
logic.
g
D Each system latch must be part of an SRL, and
each SRL must be part of a scan chain.
D A scan state exists under certain conditions:
• Each SRL or scan out SO is a function of only the preceding
SRL or scan input SI in its scan chain during the scan
operation
• All clocks except the shift clocks are disabled at the SRL
clock inputs

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DFT (Contd.)
Lecture 8
 Partial-Scan Design
D Was once used in the industry long before
full-scan design became the dominant scan
architecture.
architecture
D Can also be implemented using muxed-D
scan cells, clocked-scan cells, or LSSD scan
cells.
D Either combinational ATPG or sequential
ATPG can be used.
used

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 Partial-Scan Design
A scan chain is onstructed
X1 Y1 with two scan cells SFF1 and
PI X2 PO
X3 Combinational logic Y2 SFF3, while flip-flop FF 2 is
PPI PPO left out.
It is
i possible
ibl to
t reduce
d th test
the t t
generation complexity by
SFF1
. FF2 SFF3
splitting the single clock into
DI DI two separate clocks, one for
SI SI Q DI Q SI Q . SO controlling all scan cells
cells, the
SE SE other for controlling all non-
SE
CK
. . . scan storage elements.
However, this may result in
additional complexity of
routing two separate clock
An example of muxed-D trees during physical
partial- scan design implementation.

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 Partial-Scan Design
D Scan cell selection
• A functional partitioning approach
– A circuit is composed of a data path portion and a control portion
– Storage elements on the data path are left out of the scan cell
replacement process
– Storage elements on the control path can be replaced with scan cells
• A pipelined or feed-forward partial-scan design approach
– Make the sequential circuit feedback-free by selecting the storage
elements to break all sequential feedback loops
– First construct a structure graph for the sequential circuit
• A balanced p
partial-scan design
g approach
pp
– Use a target sequential depth to simply the test generation process for
the pipelined or feed-forward partial-scan design

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 P ti l S
Partial-Scan D i ‐ Structure
Design S
Graph
D A feedback-free sequential circuit
• Use a directed acyclic graph (DAG)
• The maximum level in the structure graph
is referred to as sequential depth
D A sequential circuit containing feedback
loops
• Use a directed cyclic graph (DCG)

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 S
Sequential
i l circuit
i i and d its
i structure
graph
C1 FF3 C3 FF5 1 3 5
FF1

C2
2 4
FF2 FF4

( ) Sequential
(a) S i l Circuit
Ci i (b) Structure
S graphh
Sequential depth is 3
The sequential depth of a circuit is equal to the maximum number of clock
cycles
l that
th t needs
d to
t be
b applied
li d in
i order
d tot control
t l andd observe
b values
l to
t andd
from all non-scan storage elements
• The sequential depth of a full-scan circuit is 0

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 Partial-Scan Design
D Advantage:
• Reduce silicon area overhead
• Reduce performance degradation
D Disadvantage:
• Can result in lower fault coverage
• Longer test generation time
• Offers
Off less
l supportt for
f debug,
d b diagnosis
di i
and failure analysis

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 Random-Access Scan Design
D Advantages of RAS:
• Can control or observe individual scan cells without affecting
others
• Reduce test power dissipation
• Simplify the process of performing delay test
D Disadvantages of traditional RAS:
• High overhead in scan design and routing
• No guarantee to reduce the test application time
D Progressive Random-Access Scan( PRAS )
was proposed to alleviate the disadvantages
in traditional RAS

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 Traditional random‐access
random access
scan architecture
PI Combinational logic PO
All scan cells are
organized into a
SC SC … SC two-dimensional
two dimensional
array. A ┌ log2n ┐ -
Row (X) decoder

CK
SC SC … SC SI bit address shift
SCK register,
g , where n is
…
…

…
SO the total number of
SC SC … SC
scan cells, is used to
specify
p y which scan
Column (Y) decoder
cell to access.
Address shift register AI

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 P
Progressive
i R Random‐Access
d A Scan
S
(PRAS)
Structure is similar to that of a static
SD SD
random access memory (SRAM) cell
or a grid addressable latch.
RE
Ф Ф In normal mode, all horizontal row
D Q enable (RE) signals are set to 0,
Ф Ф Ф Ф forcing each scan cell to act as a
normall D flip-flop.
fli fl

In test mode, to capture the test

response from D, the RE signal is set
PRAS scan cell design to 0 and a pulse is applied on clock
Φ, which causes the value on D to be
loaded into the scan cell.

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 P
Progressive
i R Random‐Access
d A Scan
S
(PRAS)
Sense-amplifiers & MISR PO
… Rows are enabled in a
… fixed order.
Row enable shift reegister

SC SC SC

Combinational llogic
SC SC … SC

It is only necessary to
…
…

…
… SC supply a column address
SC SC
to specify
specif which
hich scan
R

…
TM Test
Column line drivers
…
PI cell in an enabled row to
control
access.
SI/SO
CK logic Column address decoder

CA

PRAS Architecture

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DFT (Contd.)
Lecture 9
 Scan Design Rules
Design Style Scan Design Rule Recommended Solution

Tri-state buses Avoid during shift Fix bus contention during shift

Bi-directional I/O ports Avoid during shift Force to input or output mode
during shift
Gated clocks (muxed-D full-scan) Avoid during shift Enable clocks during shift

Derived clocks (muxed-D full- Avoid Bypass clocks

scan)
Combinational feedback loops Avoid Break the loops
Asynchronous set/reset signals Avoid Use external pin(s)
Clocks driving data Avoid Block clocks to the data portion

Floating buses Avoid Add bus keepers

Floating inputs Not recommended Tie to Vcc or ground
Cross-coupled NAND/NOR gates Not recommended Use standard cells

Non-scan storage elements Not recommended for full-scan Initialize to known states,
Design bypass, or make transparent

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 Tri‐State
Tri State
Buses SFF1
DI
Bus contention occurs when
SI Q
EN1 two bus drivers force opposite
SE … logic values onto a tri-state
D1 bus.
SFF2
Functiona DI
l enable Bus contention is designed not
logic
. SI Q . EN2
to happen during the normal
SE … Bus
operation, and is typically
. D2
avoided
id d during
d i the h capture
SFF3
operation.
DI
SI SI Q . EN3
SE . SE … However, during the shift
CK . D3 operation, no such guarantees
can be made.
Original Circuit

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 Comparison of design flows
• RTL design
g
at RTL and Gate‐level
Gate level
• Logic synthesis
RTL design
g
• Gate‐level design
Testability repair
Testable RTL design
Testability repair
Logic/scan synthesis

Testable
Scan designdesign

Scan synthesis
RTL testability repair Scan
design flow
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 RTL Scan Design Rule
Checking
D Fast synthesis
• Mapped onto combinational primitives and
hi h l
high-level
l models
d l
D Identify testability problems
• Static solutions (without simulation)
• Dynamic solutions (with simulation)

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 RTL Scan Design Repair – An
Example
D original

always
l @(
@(posedge
d clk)lk)
if (q == 4'b1111)
start D
clk_15 <= 1; clk_15
Q Q d
else
begin
clk_15 <= 0; clk
q <= q + 1;
end
always y @(p
@(posedge
g clk_15))
d < = start;

(a) Generated clock (RTL code) (b) Generated clock (Schematic)

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 RTL Scan Design Repair – An
Example
D Atuomatic repair at the RTL using TM
always @(posedge clk)
if (q
( == 4'b1111)
start D
clk_15 <= 1; clk_15
Q Q d
else
begin
clk 15 <= 0;
clk_15 clk . 0
1
clk_test

q <= q + 1;
end TM
assign clk_test = (TM)? clk : clk_15;
always @(posedge clk_test)
d < = start;

(c) Generated clock (RTL code) (d) Generated clock repair (Schematic)

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 RTL Scan Synthesis

D RTL scan synthesis

• The scan equivalent of each storage
element refers to an RTL structure
• The scan chains are inserted into the RTL design
D Pseudo RTL scan synthesis
• Specify pseudo primary inputs and pseudo
primary outputs
• Can cope with many other DFT structures
• Perform one-pass or single-pass synthesis

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 RTL Scan Extraction and
Verification
D Scan extraction
• Rely on performing fast synthesis on the RTL scan design
• Generate a software model for tracing the scan connection

D Scan verification
• Rely on generating a flush testbench to simulate flush tests
• The flush testbench can be used for both RTL and gate-level
designs
• Apply broadside-load test for verifying the scan capture
operation at RTL

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 Concluding Remarks
D DFT has become vital for ensuring
product quality
D Scan design is the most widely used
DFT technique
D New design and test challenges
• Further reduce test power, test data volume
and test application time
• Cope
C with
ith physical
h i l failures
f il off the
th
nanometer design era

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