Week 3: Course Material

Logic
g and Fault Simulation
Lecture 11

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 Logic and Fault Simulation
D IIntroduction
t d ti
D Simulation models
D L i simulation
Logic i l i
D Fault simulation
D Concluding remarks

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 Logic Simulation
D Predict the behavior of a design prior to its physical
realization
Specification
D Design
g verification

Manual design or Testbench

via Synthesis Development

Circuit Expected
Input Stimuli
Description Responses

yes Simulated
Responses
Bug?
no Response
Analysis
Next Design
g
Stage
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 Fault Simulation
D Predicts the behavior of faulty circuits
• As a consequence of inevitable fabrication
process imperfections

D An important tool for test and diagnosis

• Estimate fault coverage
• Fault simulator
• Test compaction
• Fault diagnosis

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 Logic and Fault Simulation
D IIntroduction
t d ti
D Simulation models
D L i simulation
Logic i l i
D Fault simulation
D Concluding remarks

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 Gate-Level Network
D The interconnections of logic gates

A H
G2

G4 K
L

B J
G1 G3
C E F

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 Sequential Circuits
x1 z1
D The outputs depend on x2 z2
both the current and Combinational
past input values Logic
xn zm

y1 Y1
y2 Y2
xi: primary input (PI)

zi: primary output (PO) yl Yl

yi: pseudo primary input (PPI)

Flip--Flops
Yi: pseudo primary output (PPO)

clock
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 A Positive Edge-Triggered D-FF
PresetB

PresetB

Q
D Q
DFF
Clock QB
Clock QB

ClearB

ClearB

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 Logic Symbols
D The mostt commonly
Th l used
d are 0,
0 11, u and
dZ
D 1 and 0
• true
t and
d false
f l off the
th two-value
t l B Boolean
l algebra
l b
D u
• Unknown
U k llogic
i state
t t ((maybe
b 1 or 0)
D Z
• High
High-impedance
impedance state
• Not connected to Vdd or ground

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 Ternary Logic
D Three logic symbols: 0,
0 1,
1 and u

AND 0 1 u OR 0 1 u NOT 0 1 u
0 0 0 0 0 0 1 u 1 0 u
1 0 1 u 1 1 1 1
u 0 u u u u 1 u

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 Information Loss of Ternary Logic
D Simulation based on ternary logic is pessimistic
D A signal may be reported as unknown when its value
can be uniquely
q y determined as 0 or 1
1
A u
G2 u
G4 K
u
B u
G1 G3
C u
0

1
A 0 or 1
G2 0
G4 K
0 or 1
B 1 or 0
G1 G3
C 0 or 1
0
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 High-Impedance State Z
D Tri-state
Tri state gates permit several gates to time-share
time share a
common wire, called bus
D A signal
g is in high-impedance
g p state if it is connected
to neither Vdd nor ground
 xi if ei  1
oi 
Z if ei  0
e1
o1
x1 G1
pull-up
or down
d
e2
o2 y
x2 G2
DFF
Resolution
e3 Function
o3
x3 G3
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 Resolving Bus Conflict
D Bus conflict
B fli t occurs if att least
l t ttwo drivers
di d
drive
i
the bus to opposite binary values
D To simulate tri-state bus behavior, one may
insert a resolution function for each bus wire
• May report only the occurrence of bus conflict
• Mayy utilize multi-valued logic
g to represent
p
intermediate logic states (including logic signal
values and strengths)

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 Logic Element Evaluation Methods
D Choice of evaluation technique depends on
• Considered logic symbols
• Types and models of logic elements

D Commonly used approaches

• Truth table based
• Input scanning
• Input counting
• Parallel gate evaluation

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 Truth Table Based Gate Evaluation
D The most straightforward and easy to
implement
g , 2n entries for n-input
• For binaryy logic, p logic
g
element
• May use the input value as table index
• Table size increases exponentially with the
number of inputs
D Could be inefficient for multi-valued logic
g
• A k-symbol logic system requires a table of 2mn
entries for an n-input logic element
– m = log2k
– Table indexed by mn-bit words

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 Input Scanning
D The gate
Th t output
t t can be
b determined
d t i db by the
th
types of inputs
• If any of the inputs is the controlling value
value, the
gate output is ci
• Otherwise, if any of the inputs is u, the gate output
is u
• Otherwise, the gate output is c'i
Table 3.2: The c (controlling) and
i (inversion) values of basic gates
c i
AND 0 0
OR 1 0
NAND 0 1
NOR 1 1
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 Input Scanning - cont’d
Start

u in  false
u_in

Next no u_in is no
return c’i
input? true?
yes yes

u_in  true v  next input return u

yes
no no yes
v == u? v == c? return ci

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 Input Counting
D Keep the
K th counts
t off controlling
t lli andd unknown
k
inputs
• cc_count:
count: the number of controlling inputs
• u_count: the number of unknown inputs
D Update counts during logic simulation
• Example:
One input of a NAND switches from 0 to u
– c_count --
– u_count ++
D Same rules
S l as input
i t scanning
i used
d to
t
evaluate gate outputs
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 Parallel Gate Evaluation
D Exploit the inherent concurrency in the host computer
• A 32-bit computer can perform 32 logic operations in parallel

1 0 0 1
A 1 0 0 0
G2
H

G4 K
0 1 1 0
1 1 1 0
B E J
G1 G3
C 1 1 1 0 0 0 0 1
0 0 1 0

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Logic and Fault Simulation (contd.)

Lecture 12
 Multi-Valued Parallel Gate Evaluation
D U ternary
Use t logic
l i as example
l
• Assume
–ww-bit
bit wide word
– Symbol encoding: v0 = (00), v1 = (11), vu = (01)
• Associate with each signal X two words, X1 and X2
– X1 stores the first bits and X2 the second bits of thew
copies of the same signal
• AND and OR operations are realized by applying
the same bitwise operations to both words
– C = OR(A,B) ==> C1 = OR(A1,B1) and C2 = OR(A2,B2)
• Complement
C requires inversion
– C = NOT(A) ==> C1 = NOT(A2) and C2 = NOT(A1)
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 Timing Models
D Transportt delay
T d l
D Inertial delay
D Wi delay
Wire d l
D Function element delay model

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 Compiled Code Generation Flow
gate-level
gate level
description

logic optimization

logic levelization

code generation

compiled
code

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 Code Generation
D High-level
Hi hl l programming
i llanguage source
code
• Easier to debug
• Can be ported to any target machine that has the
compiler
• Limited in applications due to long compilation
times
D Native machine code
• Generate the target machine code directly
• Higher
Hi h simulation
i l ti efficiency
ffi i
• Not as portable
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 Code Generation - cont’d
D I t
Interpreted
t d code
d
• The target machine is a software emulator
• The codes are interpreted and executed one at a
time
• Best p
portability
y and maintainability
y
• Reduced performance

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 Compiled-Code vs. Event-Driven Simulation
D C
Compiled-code
il d d
• Cycle-based simulation
• High switching activity circuits
• Parallel simulation
• Limited by compilation times
D Event-driven
• Implementing gate delays and detecting hazards
• Low switching activity circuits
• More complicated memory management

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 Types of Hazards
D Static or dynamic
• A static hazard refers to the transient pulse on a signal line
whose static value does not change
• A dynamic hazard refers to the transient pulse during a 0-to-
1 or 1-to-0 transition
D 1 or 0

Static 1-hazard Static 0-hazard Dynamic 1-hazard Dynamic 0-hazard

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 Logic and Fault Simulation
D IIntroduction
t d ti
D Simulation models
D L i simulation
Logic i l i
D Fault simulation
D Concluding remarks

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Logic and Fault Simulation (contd.)

Lecture 14
 Fault Simulation
D Introduction
D Serial Fault Simulation
D Parallel Fault Simulation
D Deductive Fault Simulation
D Concurrent Fault Simulation
D Differential Fault Simulation
D Fault Detection
D Comparison of Fault Simulation Techniques
D Alternative to Fault Simulation
D Conclusion
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 Introduction
D Wh t is
What i ffaultlt simulation?
i l ti ?
• Given
– A circuit
– A set of test patterns
– A fault model
• Determine
– Faulty outputs
– Undetected faults
– Fault coverage

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 Time Complexity
D Proportional to
• n: Circuit size, number of logic gates
• p: Number of test patterns
• f : Number of modeled faults
D Since f is roughly proportional to n, the overall
time complexity is O(pn2)

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 Serial Fault Simulation
D Fi t perform
First, f fault-free
f lt f logic
l i simulation
i l ti on the
th
original circuit
• Good (fault-free) response
D For each fault
fault, perform fault injection and
logic simulation
• Faulty circuit response

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 start
Algorithm Flow
F  collapsed fault list

fault-free simulation for

all patterns

no next
end
fault?
yes
1. gett nextt fault
1 f lt f from
f F
2. reset pattern counter

next no
pattern?
yes
1 get next pattern p
1.
2. fault simulation for p

no mis- yes
delete f from F
match? 51
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 Exampl
e
A H
f: A stuck-at 1 G2

G4 K
L

B g: J stuck-at 0
G1 G3
C E F J

0 1 0 1 1 1 0 0 1 1
0 0 1 1 1 1 0 0 1 1
1 0 0 0 0 0 1 0 0 0

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 Fault Dropping
D Halting
H lti simulation
i l ti off the
th detected
d t t d fault
f lt
D Example
• S
Suppose we are to t simulate
i l t P1, P2, P3 in
i order
d
• Fault f is detected by P1
• Do not simulate f for P2, P3
D For fault grading
• Most faults are detected after relatively few test
patterns have been applied
D For fault diagnosis
g
• Avoided to obtain the entire fault simulation results

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 Pro and Con
D Advantages
• Easy to implement
• Ability to handle a wide range of fault models
((stuck-at, delay,
y Br, …))

D Disadvantages
• Very slow

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 Parallel Fault Simulation
D Exploit
E l it the
th inherent
i h t parallelism
ll li off bitwise
bit i
operations
D Parallel fault simulation
• Parallel in faults
D Parallel pattern fault simulation
• Parallel in patterns

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 Parallel Fault Simulation
D A
Assumption
ti
• Use binary logic: one bit is enough to store logic
signal
• Use w-bit wide data word
D P ll l simulation
Parallel i l ti
• w-1 bit for faulty circuits
• 1 bit ffor ffault-free
lt f circuit
i it
D Process faulty and fault-free circuit in parallel
using
i bitwise
bit i logic
l i operations
ti

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 Fault Injection
A H
f: A stuck-at 1 G2

G4 K
L

B g: J stuck-at 0
G1 G3
C E F J

A
Gf H
0 1 0 G2

G4 K
L

B J
G1 G3
C E F Gg
0 1 0
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 Example

FF 0 0 1 0 1 1 1 0 0 0 1

f 1 0 1 1 1 0 0

g 0 0 1 0 1 1 1 0 0 0 1

FF 0 0 0 1 1 1 1 0 0 0 1

f 0 0 1 1 1 1 0 0

g 0 0 0 1 1 1 1 0 0 0 1

FF 1 1 0 0 0 0 0 1 1 0 0

f 1 1 0 0 0 0 0 1 1 0 0

g 1 1 0 0 0 0 0 1 0

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 Pro and Con
D Advantages
• A large number of faults are detected by each
pattern when
h simulating
i l i the h bbeginning
i i off test
sequence

D Disadvantages
• Only applicable to the unit or zero delay models
• Faults cannot be dropped unless all (w-1) faults
are detected

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 Parallel Pattern Fault Simulation
D Parallel
P ll l pattern
tt single
i l fault
f lt propagation
ti
(PPSFP)
D Parallel pattern
• With a w-bit data width, w test patterns are packed
i t a word
into d and
d simulated
i l t d ffor th
the ffault-free
lt f or
faulty circuit
D Single fault
• First, fault-free simulation
• Next,
Next for each fault,
fault fault injection and faulty circuit
simulation
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 start
Algorithm Flow
F  collapsed fault list

no new w
end
patterns?
yes
1. apply next w patterns
2. Ogood  good circuit outputs

next no F
fault? empty?
yyes yes
get next fault f from F end
delete f from F
1. remove last fault
1
2. inject fault f
no
yes Of  faulty circuit outputs
Of == Ogood?
off w patterns
tt 61
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Logic and Fault Simulation (contd.)

Lecture 15
 Example
A H
f: A stuck-at 1 G2

G4 K
L

B g: J stuck
stuck-at
at 0
G1 G3
C E F J

0 1 0 1 1 1 0 0 1
0 0 1 1 1 1 0 0 1
1 0 0 0 0 0 1 0 0
1 0 1 1 1 0
0 1 1 1 1 0
1 0 0 0 0 0 1 0 0
0 1 0 1 1 1 0 0 1
0 0 1 1 1 1 0 0 1
1 0 0 0 0 0 0

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 Pro and Con

D Advantages
• Fault is dropped
pp as soon as detected
• Best for simulating test patterns that come later,
where fault dropping rate per pattern is lower

D Disadvantages
• Not suitable for sequential circuits

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 Deductive Fault Simulation
D Based
B d on logic
l i reasoning
i rather
th than
th
simulation
D Fault list attached with signal x denoted as Lx
• Set of faults causing x to differ from its fault-free
value
l
D Fault list propagation
• Derive the fault list of a gate output from those of
the gate inputs based on logic reasoning

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 Fault List Propagation Rules

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 Algorithm Flow
start

F  collapsed fault list

no next
end
pattern?
yes
apply next pattern

1. fault-free simulation
2. propagate fault list
no
delete detected faults yes
F empty? end
from F

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 Example
D P1
LK  LH  LJ  K/ 0 by first Eq.

LA = {A/1} {A/1, H/1}

A H
0 G2
0 1
G4 K
1 L {A/1, H/1, B/0,
{{B/0,, E/0,, L/0}} E/0 F/0,
E/0, F/0 J/1,
J/1 K/0}
LB = {B/0}
1
B 1 1 0
G1 G3
C E F J
0 {B/0, E/0} {B/0, E/0, F/0} {B/0, E/0, F/0, J/1}
LC = {C/1}

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 Example (cont’d)
D P2

0
A H
G2
0 1
G4 K
1 L {C/0}
{C/0}
LB = {B/1}
0
B 1 1 0
G1 G3
C E F J
1 {C/0} {C/0} {C/0}
LC = {C/0}

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 Example (cont’d)
D P3
LK  (LJ  L H )  K /1 by second Eq.

LA = {A/0} {B/1, C/1, E/1, L/1}

A H
1 G2
0 0
G4 K
0 L {F/1, J/0, K/1}
{{B/1,, E/1,, L/1}}
LB = {B/1}
0
B 0 0 1
G1 G3
C E F J
0 {B/1, C/1, E/1} {B/1, C/1, E/1, F/1} {B/1, C/1, E/1, F/0, J/0}
LC = {C/1}

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 Pro and Con
D Advantages
• Very efficient
• Simulate all faults in one pass

D Disadvantages
• Not easy to handle unknowns
• Only
O for
f zero-delay timing model
• Potential memory management problem

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 Concurrent Fault Simulation
D Simulate only differential parts of whole circuit
D Event-driven simulation with fault-free and
faulty circuits simulated altogether
D Concurrent fault list for each gate
• Consist of a set of bad gates
– Fault index & associated gate I/O values
• Initially only contains local faults
• Fault propagate from previous stage

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 Good Event and Bad Event
D Good event
• Events that happen in good circuit
• Affect both good gates and bad gates
D Bad event
• Events that occur in the faulty circuit of
corresponding fault
• Affect only bad gates
D Diverge
• Addition of new bad gates
D Converge
• Removal of bad gates whose I/O signals are the
same as corresponding good gates
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 Algorithm Flow start

F  collapsed fault list

next no
end
pattern?
yes
apply next pattern

1. analyze events at gate inputs

2. execute events
3 compute events at gate outputs
3.

yes more
events?
yes no
no F delete detected faults
end
empty? from F
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 Example
D P1

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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 77
 Example (cont’d)
D P2

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 Example (cont’d)
D P3

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 Pro and Con
D Advantages
• Efficient

D Disadvantages
• Potential memory problem
– Size of the concurrent fault list changes at run time

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 Differential Fault Simulation
D [Cheng 1989]
[Ch
D Combines the merits of two techniques
• Concurrent
C t ffaultlt simulation
i l ti
• PPSFP
D Idea
• Simulate in turn every fault circuit
• Track only difference between faulty circuit and
last simulated one
• Inject differences as events
• Easily implemented by event-driven simulator

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 Simulation Sequence

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 start

Algorithm Flow F  collapsed fault list

no next
end
pattern?
yes
restore good circuit state

1. apply next pattern

2. Oggood  good circuit outputs
no
next no
F empty?
fault?
yes yes
delete f from F get next fault f end

no 1. restore
1 t f lt circuit
faulty i it state
t t
yes 2. remove last fault
Of == Ogood? 3. inject fault f
4. Of  fault circuit outputs
5 store
5. t gate
t difference
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 Pro and Con

D Advantages
• Suitable for sequential
q fault simulation

D Disadvantages
• Order
O d off events
t caused
dbby ffaulty
lt sites
it iis NOT th
the
same as the order of the timing of their occurrence

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Logic and Fault Simulation (contd.)

Lecture 16
 Fault Detection
D Hard detected fault
• Outputs of fault-free and faulty circuit are different
– 1/0 or 0/1
– No unknowns, no Z

D Potentially detected fault

• Whether the fault is detected is unclear
• Example: stuck-at-0 on enable signal of tri-state
buffer

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