4 NEUROMORPHIC HARDWARE

In this section, we delve into the design of neuromorphic hardware [40, 54] that can faithfully
emulate the algorithmic functionalities and leverage the inherent computational efficiency
offered by SNNs.

4.1 Motivation for Neuromorphic Hardware Design

Neuromorphic hardware design originated from the ambition to create electronic systems
mirroring the computational prowess of the human brain [48]. The initial breakthrough by
Mahowald and Douglas in 1991 showcased an analog integrated circuit that emulated silicon
neurons, complemented by a silicon retina geared for stereoscopic vision. This marked the
genesis of a journey that has since seen a surge in interest propelled by the demand for artificial
intelligence and machine learning systems. Contemporary efforts have been directed towards
optimizing the performance of such systems, leveraging domain-specific acceleration methods in
platforms like GPUs and TPUs, owing to the data-intensive nature of these workloads.

A defining characteristic of neuromorphic computing, particularly in the context of Spiking

Neural Networks (SNNs), lies in its intrinsic temporal dynamics. Unlike traditional computing
paradigms, SNNs operate over multiple time steps, evaluating the neural network model's
evolution across these temporal increments. This temporal dependency introduces a unique
challenge as it limits the extent of parallelism that can be harnessed without disrupting the
temporal flow of processing. Consequently, the scope for temporal parallelism is constrained,
and the focus shifts towards exploiting data-level parallelism within individual time steps. This
limitation can be effectively addressed through the acceleration capabilities offered by GPUs or
TPUs, optimizing the processing efficiency within each time step while ensuring seamless
temporal continuity in neuromorphic computing workflows.
Fig. 12. (a) Mesh architecture adopted in Loihi for transmitting spikes across various neurons
[41], (b) Multi core implementation of neuromorphic processors connected to a common router
[50] and {c} a 2-D array of processing elements makes up the near-memory processing
architecture. Each PE has computational elements for synaptic computations and internal storage
for neural functions. [35].

Router is responsible for long-distance communication. The DYNAPs chip, hailed as a

breakthrough in neuromorphic engineering, not only showcases a cutting-edge digital
communication scheme but also excels in emulating neuro-synaptic functionalities through
CMOS analog circuits. This innovative chip architecture facilitates the integration of event-
driven systems via 2-D processing arrays seamlessly connected to a central packet router, a
design approach exemplified by the SpiNNaker Project [50] (depicted in Figure 12(b)). Taking
another stride forward, the Brain Scales system [46] achieves remarkable scalability by
integrating multiple instances of the HICANN ASIC on a wafer scale. The ASIC realizes the
Adaptive Exponential Integrate-and-Fire Model via analog circuitry, complemented by synapses
capable of executing Spike-Timing-Dependent Plasticity (STDP) learning protocols. Meanwhile,
Neurogrid [38] emerges as a prominent mixed-signal system, boasting expansive scalability to
conduct intricate brain simulations and facilitate comprehensive visualization.
 F
ig. 13. (a) RESPARC as a Neuro Cell Pool (b) Macro Processing Engine: The crossbars process
the input spikes that the mPE receives across the bus and switch network to produce the
following output currents: C1, C2, C3, and C4. Crossbar currents are incorporated into the
neurons to generate output spikes, which are subsequently sent throughout the network to the
intended neurons.

Proposing a revolutionary approach, the ROLLS design introduces a reconfigurable mixed-signal

architecture adept at tackling two distinct yet interconnected realms: the emulation of intricate
neuronal and synaptic learning functionalities alongside proficient handling of image
classification tasks [51]. To address the challenges posed by Liebig’s law in neuromorphic
hardware, where performance can be bottlenecked by the scarcest component, researchers have
delved into the realm of large-scale reconfigurable systems [57]. This exploration aims to
circumvent limitations by ensuring a balanced supply across all crucial components. The
effectiveness of such an approach has been validated through a prototype employing a field-
programmable gate array (FPGA)-based design, subsequently transitioning to a robust
implementation on silicon, signaling a promising step forward in neuromorphic computing
methodologies.

4.2 CMOS-based Neuromorphic Compute Primitives

Two design elements comprise the computing primitives for efficient neuromorphic systems: (a)
implementing low power synaptic integration functions and (b) implementing complicated neural
[44] and synaptic learning features [39]. First, we go over how these aspects of the concept are
implemented in
Figure 14. CMOS-based neural circuit illustration. (a) Circuit illustrates the fundamental firing
and comparison patterns of an IF neuron [43]. (b) Circuit demonstrates more intricate IF neuron
functions, including refractory duration, leak, and spike frequency adaptation [55].

A major area of study for neuromorphic circuit design is CMOS technology. We will then
outline how new memory technologies can be applied to speed up computation and compactly
construct the basic processor units.

4.2.1 Neuronal Circuits

The classic approach to representing neuronal circuits on silicon relied on establishing

equivalence between ion transportation in biological neurons and electron transport in transistors.
Researchers have demonstrated that the sub-threshold domain of ionic channel transport in
biological neurons may be mimicked using a relatively small number of transistors [42].
Additionally, utilizing programmable kinetics of gating factors, sub-threshold transistors have
been employed to construct Hodgkin-Huxley-based neuron models [60].

In contrast, Integrate-and-Fire (IF) or Leaky Integrate-and-Fire (LIF), which we extensively

discussed in Section 2, is a more commonly known neuronal functionality. An abstract
representation of such a neuron typically consists of a comparison unit, a thresholding unit, and a
capacitive unit that stores and updates the membrane potential. The most primitive form of the IF
neuron was conceived in the late '80s, featuring a basic feedback circuit capable of generating
voltage pulses of fixed width and height. These pulses' temporal characteristics mirrored the
input current waveform shape, with pulse frequency proportional to the injected current (from
synapses).

Subsequent analog domain IF neuron circuit designs introduced a comparator unit, as illustrated
in Figure 14(a) [49, 55]. In this configuration, the injected current is integrated through
membrane capacitance, and then compared to the threshold voltage Vthr by a comparator circuit.
The capacitive feedback, Cfb, in both circuits ensures that small fluctuations of Vmem around
Vthr do not affect firing activity. The neuron's refractory period is also controlled by the
modified circuit. Initially, after firing, Vmem decreases linearly, but once it falls below Vthr, the
output of the first inverter sets high, leading to the discharge of capacitor Cr at a controlled rate
using Vrfr. This ensures Vmem does not start to increase if the voltage at Cr is above a certain
value.

Analog IF neuron circuits have evolved substantially over time with the addition of
characteristics like reset, leak, spike frequency adaptation, and others. Figure 14(b) shows a
complex and generalized IF neuron circuitry [44], comprising an input differential pair integrator
(DPI) for integration, a membrane capacitor, Cmem, and an inverting amplifier with positive
feedback for spike generation. Transistor M13 is responsible for implementing the reset
behavior, while, in conjunction with transistor M21, it facilitates the implementation of
refractory-period behavior. Transistors M5–M10 produce the current proportional.

This adjustment contributes to the neuron's firing rate, thus initiating a spike frequency
adaptation mechanism. The implemented LIF neuron's altered equation is as follows:

Vmem =Idpi −Iτ −Iahp +Ifb , where Cmem d/dt.

This generalized neuron realizes an adaptable exponential IF neuron. The implementation of

other CMOS-based analog neuron types, such as the log-domain LPF neuron, which implements
a reconfigurable IF circuit, has also been explored. The "Tau-Cell neuron" represents a different
kind of IF neuron circuit utilizing current-mode circuits and representing the membrane potential
as a current [56]. More compact IF neuron circuits have been developed using above-threshold
transistors, including the quadratic IF neuron [58], somewhat inspired by the Izhikevich neuron
model [45], maintaining two state variables across two different capacitors.

4.3 Non-volatile Memory-based Compute Primitives

 While CMOS technology has made notable strides in emulating the logical adjacency of
processing and storage elements within Spiking Neural Networks (SNNs), the exploration of
alternative technologies becomes imperative for two pivotal reasons. Firstly, enhancing the
efficiency of Neuromorphic Processing (NMP) systems necessitates a substantial increase in on-
chip storage density. Secondly, the endeavor to replicate complex neuronal and synaptic
functionalities using CMOS can lead to considerable area consumption.

In response to these challenges, non-volatile memory (NVM) technologies such as Resistive

RAMs (RRAM), Phase Change Memories (PCM), and Spintronics emerge as promising avenues
[39]. Their inherent device properties facilitate a direct, one-to-one emulation of neuronal and
synaptic functionality at a component level. This unique capability, coupled with their high on-
chip storage density and ability to execute massively parallel in-memory computations, positions
NVM technologies as particularly well-suited for neuromorphic systems.

The conceptual groundwork for NVM technologies traces back to L. Chua in 1971, with the
realization of the memristor—the fundamental component—in 2008 by HP Labs [53].
Memristors, functioning as non-volatile programmable analog resistors, fundamentally differ
from standard CMOS transistors (Boolean switches) in their operational essence. This distinction
empowers memristors to directly mimic the computational units of neurons and synapses based
on their resistance states.

Organized in array structures, these NVM devices facilitate highly compact and energy-efficient
"In-Memory" dot-product computing kernels, crucial for neuromorphic computations and
aligned with physical principles. The synaptic weight is encoded within each device's
conductance state, with input spikes applied as voltages along rows in the crossbar array. The dot
product operation is achieved by measuring the currents passing through each device based on its
conductance and aggregating them along each column of the array.

Moreover, the characteristics of neural/synaptic devices—such as bit resolution for

programming, programming energy and speed, dependability, durability, and the range of device
conductance—assume paramount importance in ensuring the efficacy and reliability of
neuromorphic systems [47, 52, 59, 61].

FUTURE SCOPES

The human sense of touch is sensitive enough to feel the difference between surfaces that differ
by just a single layer of molecules, yet most of today’s robots operate solely on visual
processing. Researchers at NUS hope to change this using their recently developed artificial skin,
which according to their research can detect touch more than 1,000 times faster than the human
sensory nervous system and identify the shape, texture and hardness of objects 10 times faster
than the blink of an eye.
Future applications: Imam says the chemical-sensing community for years has looked for smart,
reliable and fast-responding chemosensory processing systems, otherwise called “electronic nose
systems.” He sees the potential of robots equipped with neuromorphic chips for environmental
monitoring and hazardous materials detection, or for quality control chores in factories. They
could be used for medical diagnoses where some diseases emit particular odors. Another
example has neuromorphic-equipped robots better identifying hazardous substances in airport
security lines.

Adding more senses in the future: “My next step,” Imam says, “is to generalize this approach to
a wider range of problems — from sensory scene analysis (understanding the relationships
between objects you observe) to abstract problems like planning and decision-making.
Understanding how the brain’s neural circuits solve these complex computational problems will
provide important clues for designing efficient and robust machine intelligence.”

Challenges to overcome: There are challenges in olfactory sensing, Imam says. When you walk
into a grocery, you might smell a strawberry, but its smell might be similar to that of a blueberry
or a banana, which induce very similar neural activity patterns in the brain. Sometimes it’s even
hard for humans to distinguish between one fruit from a blend of scents. Systems might get
tripped up when they smell a strawberry from Italy and one from California, which might have
different aromas, yet need to be grouped into a common category. “These are challenges in
olfactory signal recognition that we’re working on and that we hope to solve in the next couple
of years before this becomes a product that can solve real-world problems beyond the
experimental ones we have demonstrated in the lab,” Imam says. His work, he contends, is a
“prime example of contemporary research taking place at the crossroads of neuroscience and
artificial intelligence.”

[23:10, 27/04/2024] Abhishek Maurya Jss Ece B7: Once the algorithmic work is complete, the
research team will deploy the new model on Intel’s neuromorphic hardware and test the
capabilities of the arm. After making refinements, the device will undergo clinical testing and
evaluation at ALYN Hospital with patients who rely on electric wheelchairs and have motor
impairment of their upper extremities. The participants will control the arm using a small,
dedicated joystick, and researchers will collect information on the robotic arm’s performance to
assess its usefulness.

“We believe that the development of a robotic arm based on neuromorphic computing can be a
game-changer for people with disabilities. It could make it easier for them to engage with the
community, boost their independence and grant them new employment opportunities,” said Arie
Melamed-Yekel, general manager of ALYNnovation at ALYN. “The expected cost and
performance improvements are potentially disruptive to this market. We are proud to lead this
revolution together with the Open University, Intel and Accenture.”
[23:12, 27/04/2024] Abhishek Maurya Jss Ece B7: What’s Next: If this project is successful, the
research team plans to explore how to produce this assistive robotic arm for patients. In addition,
they plan to investigate applications of adaptive control technology in flexible manufacturing and
industrial automation.

[23:14, 27/04/2024] Abhishek Maurya Jss Ece B7: the biological olfactory system in animals and
measure the electrical activity in their brains as they smell odors

Neuromorphic Computing Helps Robots Keep Learning: In a simulated setup, a robot actively
senses objects by moving its eyes (event-based camera or dynamic vision sensor), generating
"miscrosaccades." The events collected are used to drive a spiking neural network on the Loihi
chip. If the object or the view is new, its SNN representation is learned or updated. If the object
is known, it is recognized by the network and respective feedback is given to the user. (Credit:
Intel Corporation)

Intel Labs, in collaboration with the Italian Institute of Technology and the Technical University
of Munich, has introduced a new approach to neural network-based object learning. It
specifically targets future applications like robotic assistants that interact with unconstrained
environments, including in logistics, healthcare or elderly care. This research is a crucial step in
improving the capabilities of future assistive or manufacturing robots. It uses neuromorphic
computing through new interactive online object learning methods to enable robots to learn new
objects after deployment.

Using these new models, Intel and its collaborators successfully demonstrated continual
interactive learning on Intel’s neuromorphic research chip, Loihi, measuring up to 175x lower
energy to learn a new object instance with similar or better speed and accuracy compared to
conventional methods running on a central processing unit (CPU). To accomplish this,
researchers implemented a spiking neural network architecture on Loihi that localized learning to
a single layer of plastic synapses and accounted for different object views by recruiting new
neurons on demand. This enabled the learning process to unfold autonomously while interacting
with the user

Neuromorphic hardware In this work, we implement the neural network architecture on Intel’s
neuromorphic research chip Loihi [8]. As the other neuromorphic hardware devices, Loihi
harnessed insights from biological neural systems to build electronic devices that realize
biological computing principles efficiently [56]. Loihi has shown orders of magnitude
improvements in terms of low power consumption and fast processing speed on a range of AI
tasks [10]. In addition, the on-chip bio-inspired synaptic plasticity on Loihi supports on-chip
continual learning. Each Loihi chip contains 128 neuronal cores, implementing 128K spiking
leaky integrate-and-fire (LIF) neurons and 128M synaptic connections, characterized by their
weight, 𝑤𝑖𝑗, and delay, 𝑑𝑖𝑗. The on-chip learning engine updates the weights of the learning
layer based on the synaptic plasticity equations that define the learning rule [8]. The learning rule
can update weights based on label signals obtained from an expert (e.g. human) while the system
is in use. Our network uses approximately 18K neurons and 0.5M synapses on a single Loihi
chip. In our experiments we combine Loihi with an event-based camera, the
DynamicVisionSensor(DVS)[2,36],whichinturnachieves low-power, low-latency, and high
dynamic range in visual sensing [17] and matches the event-based nature of the processing in
SNNs. The DVS only produces output if there is a change in the visual field. Since in our
experiments we deal with potentially static objects, we use small camera movements,
“microsaccades” to generate events in our experiments. Different methods can be used to
develop algorithms, or SNN architectures, for neuromorphic hardware. Conversion of the
conventional deep convolutional networks to spiking neural networks (SNNs) [49] and surrogate
gradient methods [59] allow us to use the principles of deep learning to create networks that
solve pattern classification tasks. Several attempts have been made to enable online learning in
such deep networks, e.g., by making the last layer of the network plastic to learn new patterns
using features extracted by the early layers of the pre-trained network [23, 62]. We pursue a
similar route in our work, using the plastic layer to learn object prototypes in an online fashion,
controlled by a neuronal state machine.

Philipp Stratmann is a research scientist at Intel Labs, where he explores new neural network
architectures for Loihi, Intel’s neuromorphic research AI accelerator. Co-author Péter Hága is a
master researcher at Ericsson Research, where he leads research activities focusing on the
applicability of neuromorphic and AI technologies to telecommunication tasks.

Highlights

Using neuromorphic computing technology from Intel Labs, Ericsson Research is developing
custom telecommunications AI models to optimize telecom architecture.

Ericsson Research developed a radio receiver prototype for Intel’s Loihi 2 neuromorphic AI
accelerator based on neuromorphic spiking neural networks, which reduced the data
communication by 75 to 99% for energy efficient radio access networks (RANs).
As a member of Intel’s Neuromorphic Research Community, Ericsson Research is searching for
new AI technologies that provide energy efficiency and low latency inference in telecom
systems.

Using neuromorphic computing technology from Intel Labs, Ericsson Research is developing
custom telecommunications artificial intelligence (AI) models to optimize telecom architecture.
Ericsson currently uses AI-based network performance diagnostics to analyze communications
service providers’ radio access networks (RANs) to resolve network issues efficiently and
provide specific parameter change recommendations. At Mobile World Congress (MWC)
Barcelona 2024, Ericsson Research demoed a radio receiver algorithm prototype targeted for
Intel’s Loihi 2 neuromorphic research AI accelerator, demonstrating a significant reduction in
computational cost to improve signals across the RAN.

In 2021, Ericsson Research joined the Intel Neuromorphic Research Community (INRC), a
collaborative research effort that brings together academic, government, and industry partners to
work with Intel to drive advances in real-world commercial usages of neuromorphic computing.

Ericsson Research is actively searching for new AI technologies that provide low latency
inference and energy efficiency in telecom systems. Telecom networks face many challenges,
including tight latency constraints driven by the need for data to travel quickly over the network,
and energy constraints due to mobile system battery limitations. AI will play a central role in
future networks by optimizing, controlling, and even replacing key components across the
telecom architecture. AI could provide more efficient resource utilization and network
management as well as higher capacity.

Neuromorphic computing draws insights from neuroscience to create chips that function more
like the biological brain instead of conventional computers. It can deliver orders of magnitude
improvements in energy efficiency, speed of computation, and adaptability across a range of
applications, including real-time optimization, planning, and decision-making from edge to data
center systems. Intel's Loihi 2 comes with Lava, an open-source software framework for
developing neuro-inspired applications.
Radio Receiver Algorithm Prototype

Ericsson Research’s working prototype of a radio receiver algorithm was implemented in Lava
for Loihi 2. In the demonstration, the neural network performs a common complex task of
recognizing the effects of reflections and noise on radio signals as they propagate from the
sender (base station) to the receiver (mobile). Then the neural network must reverse these
environmental effects so that the information can be correctly decoded.

During training, researchers rewarded the model based on accuracy and the amount of
communication between neurons. As a result, the neural communication was reduced, or
sparsified, by 75 to 99% depending on the difficulty of the radio environment and the amount of
work needed by the AI to correct the environmental effects on the signal.

Loihi 2 is built to leverage such sparse messaging and computation. With its asynchronous spike-
based communication, neurons do not need to compute or communicate information when there
is no change. Furthermore, Loihi 2 can compute with substantially less power due to its tight
compute-memory integration. This reduces the energy and latency involved in moving data
between the compute unit and the memory.

Like the human brain’s biological neural circuits that can intelligently process, respond to, and
learn from real-world data at microwatt power levels and millisecond response times,
neuromorphic computing can unlock orders of magnitude gains in efficiency and performance.

Neuromorphic computing AI solutions could address the computational power needed for future
intelligent telecom networks. Complex telecom computation results must be produced in tight
deadlines down to the millisecond range. Instead of using GPUs that draw substantial amounts of
power, neuromorphic computing can provide faster processing and improved energy efficiency.