IDEC

Verilog HDL 언어 초급 및
설계 가이드라인

송재훈
 IDEC
Contents

1. What is HDL?
2. A System and Its Verilog Representation
3. Signals
4. A Structural View of a System
5. Specification with Signal Transformations
6. The Behavioral Approach
7. Towards Real Engineering
8. Is It Working?

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 IDEC

What is HDL?

송재훈
The World Before Verilog IDEC

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Logic Synthesis - Principles IDEC

Function, Technology
Area, library
Input-to-output timing

HDL Gate-level
Synthesis
description netlists

Constraints

Area, timing,
power, testability

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 IDEC

A System and Its Verilog

Representation
The Anatomy of a System IDEC

Systems and Circuit/Logic Designs are represented as “module” unit

in Verilog HDL

Verilog HDL로 기술된 시스템은 최소한 한 개 이상의 module로 구성됨

- 각 module은 signal로 연결될 수 있음
module mux_4_to_1;
…..
endmodule

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The Structure of a Module
IDEC

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The Structure of a Module IDEC
Definition of a Module

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The Structure of a Module IDEC
Definition of a Module

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The Structure of a Module IDEC
Definition of a Module

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The Structure of a Module IDEC
Definition of a Module

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The Structure of a Module IDEC

Definition of a Module

module module_name (port_name, port_name, ... );

port_declaration port_name, port_name,...;
port_declaration port_name, port_name,...;
module items
endmodule

module module_name
(port_declaration port_name, port_name,...,
port_declaration port_name, port_name,...);
module items
endmodule

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The Structure of a Module IDEC

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The Structure of a Module IDEC

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The Structure of a Module IDEC

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The Structure of a Module IDEC

The Module Interface

Port declarations (1/2)
Verilog-1995 style
port_direction [signed] [range] port_name, port_name, ... ;
data_type_declarations;
Verilog-2001 style (ANSI C style)
port_direction data_type [signed] [range] port_name, port_name, ... ;

• port_direction is declared as:

- input for scalar or vector input ports.
- output for scalar or vector output ports.
- inout for scalar or vector bidirectional ports.

• range (optional) is a range from [msb :lsb] (most-significant-bit to least-significant-bit).

- If no range is specified, ports are 1-bit wide.
• data_type is typicaly wire or reg.
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- implicitly wire
The Structure of a Module IDEC

The Module Interface

Port declarations (2/2)
Verilog-1995 style

Verilog-2001 style (ANSI C style)

Different Types of Module Body IDEC

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Different Types of Module Body IDEC

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Different Types of Module Body IDEC

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Different Types of Module Body IDEC

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Different Types of Module Body IDEC

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Different Types of Module Body IDEC

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Different Types of Module Body IDEC

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 IDEC

Signals
An Introduction to Signals IDEC

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An Introduction to Signals IDEC

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An Introduction to Signals IDEC

0 1

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An Introduction to Signals IDEC

X (x) Z (z)

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Signals in Verilog IDEC

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Signals in Verilog IDEC

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Signals in Verilog IDEC

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Signals in Verilog IDEC

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Signals in Verilog IDEC

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Signals in Verilog IDEC

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External Signals IDEC

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External Signals IDEC

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External Signals IDEC

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 IDEC

A Structural View of a System

Module Instantiation IDEC

-. A module provides a template from which you can

create actual objects.

-.When a module is invoked, Verilog creates a unique

object from the template.

-.Each object has its own name, variables, parameters,

and I/O interface.

-.The process of creating objects from a module template

is called instantiation, and the objects are called instances.

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Module Instantiation IDEC

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Module Instantiation IDEC

P1 P4
net net S6 S9 net
net
P2
var net S7
P5
P3 S10 var net
net net S8

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Module Instantiation IDEC

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Module Instantiation IDEC

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Module Instantiation IDEC

GoldBox

Ordered port mapping

Named port mapping

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 IDEC

Specification with Signal

Transformations
Expressions IDEC

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Expressions IDEC

Possible Operand Types for Expressions

 Constant
• Literal constant: 23, 2’b01, 0.1
• Named constant: `define A 10, parameter A = 10;
 Signals
• Net type: wire
• Variable type: reg
 Function call: f1(s)

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Expressions IDEC

Integer Constant

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3’b011

• size (optional) is the number of bits in the number. Unsized integers default to
at least 32-bits.

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Expressions IDEC
Integer Constant

• ’base represents the radix and sign property of the value. The base and sign
characters are not case sensitive (e.g. ’b and ’B are equivalent).

(Base)

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Expressions IDEC
Integer Constant

• The ? is another way of representing the Z logic value.

• An underscore is ignored (used to enhance readability). The underscore
cannot be used as the first character of the value.
• When size is fewer bits than value, the upper bits are truncated.
• When size is more bits than value, and the left-most bit of value is 0 or 1,
zeros are left-extended to fill the size.
• When size is more bits than value, and the left-most bit of value is Z or X,
the Z or X is left-extended to fill the size.
• Signed numbers are interpreted as 2’s complement values.

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Expressions IDEC
Integer Constant

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Expressions IDEC

DataBus

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Operators IDEC

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Operators IDEC

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Operators IDEC

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Operators IDEC

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Operators IDEC
Case Equality Operator

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Operators IDEC

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Operators IDEC

• For most operations, the operands may be nets, variables, constants or

function calls. Some operations are not legal on real (floating-point) values.
• Operators which return a true/false result will return a 1-bit value where 1
represents true, 0 represents false, and X represents indeterminate.

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Operators IDEC

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Operators IDEC

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Operators IDEC

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Operators IDEC

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Operators IDEC

Operator Precedence
Compound expressions are evaluated in the order of operator precedence.
Operators within parenthesis have a higher precedence and are evaluated first.

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The Continuous Assignment IDEC

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The Continuous Assignment IDEC

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The Continuous Assignment IDEC

ChipOut

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The Continuous Assignment IDEC

ChipOut

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 IDEC

The Behavioral Approach

송재훈
Variables and Parameters IDEC

Variables

• Variable data types are used for programming storage in procedural

blocks.
- A variable data type must be used when the signal is on the left-hand
side of a procedural assignment.
- Variables were called “registers” in older versions of the Verilog
standard.
- signed와 range 옵션은 reg 타입 variable에만 사용 가능함

[ [

[
[

[
[

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Variables and Parameters IDEC

Variables
• variable_type is one of the following:

• signed (optional) may only be used with reg variables, and indicates that
values are interpreted as 2’s complement signed values. If either a port or the
reg connected to the port is declared as signed, then both are signed. Signed
reg variables were added in Verilog-2001.

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Variables and Parameters IDEC

Variables

• [range] (optional) may only be used with reg variables, and is a range
from [msb :lsb] (most-significant-bit to least-significant-bit).
- If no range is specified, then reg variables are 1-bit wide.
- The msb and lsb must be a literal number, a constant, an expression,
or a call to a constant function.

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Variables and Parameters IDEC

Variables

• [array] is [first_address : last_address][first_address : last_address]...

- Any number of array dimensions may be declared. Variable arrays of more
than one dimension were added in Verilog-2001.
- first_address and last_address must be a literal number, a constant, an
expression, or a call to a constant function.
- Either ascending or descending address order may be used.
- A one-dimensional array of reg variables with is referred to as a memory.

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Variables and Parameters IDEC

Variables

• initial_value (optional) sets the initial value of the variable.

- The value is set in simulation time 0, the same as if the variable had
been assigned a value in an initial procedure.
- If not initialized, the default value for reg, integer and time variables is X,
and the initial value for real and realtime variables is 0.0.
- Specifying the initial value as part of the variable declaration was added
in Verilog-2001

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Variables and Parameters IDEC

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Variables and Parameters IDEC

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Variables and Parameters IDEC

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Behavioral Basics IDEC

Procedure Routines for Behavioral Description

1) initial
2) always

Concurrent Objects in Verilog

1) Instance
- Module instance, Primitive instance
2) Continuous assignment
- assign A = B;
3) Procedure routine
- Initial routine, always routine
Behavioral Basics IDEC

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Behavioral Basics IDEC

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Behavioral Basics IDEC

variable type
signals

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Behavioral Basics IDEC

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Behavioral Basics IDEC

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Behavioral Basics IDEC

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Behavioral Basics IDEC

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Behavioral Basics IDEC

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Behavioral Basics IDEC

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Behavioral Basics IDEC

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Behavioral Basics IDEC

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Behavioral Basics IDEC

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Behavioral Basics IDEC

Possible Behavioral Operation Elements in Procedure Routine (initial,

always)
1) Assignment
- Blocking assignment ( = )
- Non-blocking assignment ( <= )
2) Condition
- If, if else, case, casez, casex, ? :
3) Loop
- for, whie, repeat, forever
4) Subroutine call
- function call, task call
5) Timing control
- #, @, wait()
Complex Statements IDEC

Multi-Way Branching

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Complex Statements IDEC

Multi-Way Branching

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Complex Statements IDEC

Multi-Way Branching

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Complex Statements IDEC

Multi-Way Branching

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Complex Statements IDEC

Multi-Way Branching

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Complex Statements IDEC

Multi-Way Branching

if ( expression ) statement or statement_group

•vExecutes the next statement or statement group if the expression evaluates as

true.

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Complex Statements IDEC

Multi-Way Branching

if ( expression ) statement or statement_group

else statement or statement_group

• Executes the first statement or statement group if the expression evaluates as

true. Executes the second statement or statement group if the expression
evaluates as false or unknown.

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Complex Statements IDEC
Multi-Way Branching

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Complex Statements IDEC

Multi-Way Branching

case ( expression )
case_item: statement or statement_group
case_item, case_item: statement or statement_group
default: statement or statement_group
endcase

• Compares the value of the expression to each case item and executes the
statement or statement group associated with the first matching case.
Executes the default if none of the cases match (the default case is optional).

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Complex Statements IDEC

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Complex Statements IDEC

Loops

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Complex Statements IDEC

Loops

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Complex Statements IDEC

Loops

for ( initial_assignment; expression; step_assignment )

statement or statement group

• Executes initial_assignment once, when the loop starts.

• Executes the statement or statement group as long as expression evaluates
as true.
• Executes step_assignment at the end of each pass through the loop.

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Complex Statements IDEC

Loops
while ( expression ) statement or statement group

• A loop that executes a statement or statement group as long as an expression

evaluates as true. The expression is evaluated at the start of each pass of the
loop.
//--- Example ---//
// Increment count from 0 to 127. Exit at count 128. //Display the count variable.
integer count;
initial
begin
count = 0;
while (count < 128) //Execute loop till count is 127. (exit at count 128)
begin
$display("Count = %d", count);
count = count + 1;
end
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end
Complex Statements IDEC

Loops

repeat ( expression ) statement or statement_group

• A loop that executes the statement or statement group a set number of times.
The number may be an expression (the expression is only evaluated when the
loop is first entered).
//--- example ---//
integer count;
initial
begin
count = 0;
repeat(128)
begin
$display("Count = %d", count);
count = count + 1;
end
end 108
Complex Statements IDEC

Loops

forever statement or statement_group

• An infinite loop that continuously executes the statement or statement group.

• A forever loop is typically used in conjunction with timing control constructs.

//--- example ---//

reg clock;
initial
begin
clock = 1'b0;
forever #10 clock = ~clock; //Clock with period of 20 units
end

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Advanced Control over Behavior IDEC
Timing Control (1/8) - (Delay-based)

#delay

• Delays execution of the next statement for a specific amount of time. The
delay may be a literal number, a variable, or an expression.

//--- example ---//

assign #10 y = 1; // delay control with a number. Delay execution of
// y = 1 by 10 units

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Advanced Control over Behavior IDEC
Timing Control (2/8) - (Event-based)

@([edge] signal or [edge] signal or ... )

@([edge] signal, [edge] signal, ... )
@(*)

• [ ] : option
• Delays execution of the next statement until there is a transition on a signal.
- edge (optional) maybe either posedge or negedge. If no edge is
specified, then any logic transition is used.
• Either a comma or the keyword or may be used to specify events on any
of several signals. The use of commas was added in Verilog-2001.
• signal may be a net type or variable type, and may be any vector size.

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Advanced Control over Behavior IDEC
Timing Control (3/8) - (Event-based)

//--- example ---//

@(clock) q = d; //q = d is executed whenever signal clock changes value

@(posedge clock) q = d; //q = d is executed whenever signal clock does

//a positive transition ( 0 to 1,x or z, // x to 1, z to 1 )

@(negedge clock) q = d; //q = d is executed whenever signal clock does

//a negative transition ( 1 to 0,x or z, //x to 0, z to 0)

q = @(posedge clock) d; //d is evaluated immediately and assigned

//to q at the positive edge of clock

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Advanced Control over Behavior IDEC
Timing Control (4/8) - (Level-sensitive)

wait (expression)

• Delays execution of the next statement until the expression evaluates

as true.

//--- example ---//

always
wait (count_enable) #20 count = count + 1;

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Advanced Control over Behavior IDEC
Timing Control (5/8)

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Advanced Control over Behavior IDEC
Timing Control (6/8)

clock input data input

output

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Advanced Control over Behavior IDEC
Timing Control (8/8)

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Advanced Control over Behavior IDEC

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Advanced Control over Behavior IDEC

Sensitivity List

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Advanced Control over Behavior IDEC

Sensitivity List

The sensitivity list is used at the beginning of an always procedure to infer

combinational logic or sequential logic behavior in simulation.

• always @(signal, signal, ... ) infers combinational logic if the list of

signals contains all signals read within the procedure.
• always @* infers combinational logic. Simulation and synthesis will
automatically be sensitive to all signals read within the procedure. @* was
added in Verilog-2001.
• always @(posedge signal, negedge signal, ... ) infers sequential
logic. Either the positive or negative edge can be specified for each signal
in the list. A specific edge should be specified for each signal in the list.

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Advanced Control over Behavior IDEC

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Advanced Control over Behavior IDEC

Non-Blocking
Assignment

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Advanced Control over Behavior IDEC

Non-Blocking
Assignment

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Advanced Control over Behavior IDEC

Non-Blocking
Assignment

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Advanced Control over Behavior IDEC

Non-Blocking
Assignment

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Advanced Control over Behavior IDEC

Non-Blocking
Assignment

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Advanced Control over Behavior IDEC

Non-Blocking
Assignment

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Advanced Control over Behavior IDEC

Non-Blocking
Assignment

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Advanced Control over Behavior IDEC

Non-Blocking
Assignment

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 IDEC

Towards Real Engineering

송재훈

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Logic Synthesis - Principles IDEC

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Logic Synthesis - Principles IDEC

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Logic Synthesis - Principles IDEC

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 IDEC

Is It Working?

송재훈
An Introduction to Test Benches IDEC

stimuli generator

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An Introduction to Test Benches IDEC

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An Introduction to Test Benches IDEC

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An Introduction to Test Benches IDEC

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The Structure of a Test Bench IDEC

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The Structure of a Test Bench IDEC

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The Structure of a Test Bench IDEC

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The Structure of a Test Bench IDEC

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 IDEC

Thank you!

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