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R09
Code No: D109110509
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
M.Tech I Semester Regular Examinations March 2010
ADVANCED COMPUTER ARCHITECTURE
(COMPUTER SCIENCE)
Time: 3hours Max.Marks:60
Answer any five questions
All questions carry equal marks
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1. a) Explain Amdahl’s Law.

b) Explain various operations in the instruction set.

2. a) Explain the basics of RISC instruction set.

b) Explain the implementation of a RISC instruction set.

3. a) Explain the first miss penalty reduction technique in multilevel caches.

b) Suppose that in 1000 memory references there are 40 misses in the first-level

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cache and 20 misses in the second level cache. What are the various miss rates?
Assume the miss penalty from the L2 cache to memory is 100 clock cycles, the hit
time of the L2 cache is 10 clock cycles, the hit time of L1 is 1 clock cycle, and

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there are 1.5 memory references per instruction, what is the average memory
access time and the average stall cycles per instruction? Ignore the impact of
writes.

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4. Explain Dynamic scheduling using Tomasulo’s approach.

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5. a) Explain hardware versus software speculation mechanisms.
b) Briefly explain loop unrolling and scheduling.

6.

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Explain multiprocessor cache coherence.

7. a)
b)

8. a)
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Explain about Ethernet, the local area network.
Explain the cost and performance of a cluster for transaction processing.

Explain the architecture of Trimedia TM32.

b) Define cluster? Give designing principles of cluster?

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