SRI VENKATESWARA COLLEGE OF

ENGINEERING
(Autonomous)

Karakambadi Road, TIRUPATI – 517507

COMPUTER ORGANIZTION(CA20FPC101)
Unit – 1

1 Explain the Basic Operational concepts of a computer with a block 10M

diagram.

2 Discuss the functional units of a computer with a block diagram. 10M

3 Define bus. Elucidate the bus structure with a neat diagram. 10M

4 Explain the concept of Data Representation? 10M

5 Illustrate Error detection codes with an example. 10M

Unit – 2

1 Explain Bus and Memory transfers using Bus system for four registers 10M

2 What is a Micro operation? Briefly explain the arithmetic micro- 10M

operations with examples?

3 What is register transfer language? Explain the basic symbols used in 10M
register transfer language.

4 I. Explain the concept of computer instruction 10M

ii.Explain the concept of Instruction cycle

5 List out the Memory Reference Instructions with descriptions 10M

Unit – 3

1 Write about Instruction formats 10M

2 Explain the concept of data transfer and manipulation in detail? 10M

3 Explain different types of addressing modes with a numerical example. 10M

4 Write about Program control with relevant examples. 10M

5 Write about Reduced Instruction set computer (RISC) in detail. 10M

6 Explain the concept of Booth Multiplication Algorithm in detail? 10M

7 Explain the concept of Division Algorithms with an example? 10M

 Unit – 4

1 Explain semiconductor RAM Memories? 10M

2 Write about Cache memory, explain the performance and types of 10M
cache

3 Write about performance considerations of a memory. 10M

4 Discuss the concept of Read only Memories in detail 10M

5 Compare and contrast Asynchronous DRAM and Synchronous DRAM. 10M

Unit – 5

1 With a neat diagram, explain instruction pipeline processing in detail. 10M

2 Write about pipeline hazards in detail 10M

3 Write about RISC Pipeline in detail 10M

4 Write about vector processing and array processors in detail 10M

5 Write about Interconnection structures in detail. 10M

6 Write about Inter process Arbitration & Inter Processor 10M

communication.

7 Write about Cache coherence and conditions for Incoherence. 10M