Dicd Spectrum

L ATEST
2022
EDITION
DIGITAL IC DESIGN
[Electronics and Communication Engineering]
B.Tech (R20) (JNTU-Kakinada)
B.Tech : III-Year II-Sem

Prepared by : SIA Team of Experts
Total Pages : 288
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Books for B.Tech (ECE) II-Year II-Sem (R20)(JNTU-K)
- Electronic Circuit Analysis
- Digital IC Design
- Analog Communications
- Linear Control Systems
- Management and Organizational Behaviour
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DIGITAL IC DESIGN
ECE B.Tech. II-Year II-Sem. ( JNTU - Kakinada )
CONTENTS
Introduction to the Subject
Syllabus as per R20 Curriculum

MID-1 & 2 OBJECTIVE TYPE & ESSAY QUESTIONS WITH KEY M.1 - M.19
MODEL QUESTION PAPERS WITH SOLUTIONS (As Per Latest External Exam Pattern)
Model Paper-1 MP.1 - MP.2

GUESS PAPERS WITH SOLUTIONS GP.1 - GP.8
UNIT-WISE QUESTIONS WITH SOLUTIONS
Unit No. Unit Name

Question Nos. Page Nos.
Topic No. Topic Name
UNIT - I HARDWARE DESCRIPTION LANGUAGES Q1 - Q51 1 - 48
1.1 VHDL 2
1.1.1 Introduction to VHDL Q1 - Q3 2
1.1.2 Entity Declaration, Architecture, Configu-ration

Declaration, Package Q4 - Q7 3
1.1.3 Data-Flow, Behavioral and Structural Style of

Modellings Q8 - Q9 7
1.1.4 Data Types, Data Objects, Operators and Identifiers Q10 - Q13 9
1.1.5 Generic, Process, If, Case & Loop Statements Q14 - Q21 13
1.1.6 VHDL Libraries Q22 - Q32 19
1.2 Verilog HDL 28
1.2.1 Introduction to Verilog HDL, Module Statement,

Wire Statement Q33 - Q42 28
1.2.2 Data Types, Data Operators Q43 - Q45 37
1.2.3 If-else Statement, Case-end Case Statement,

Verilog Syntax and Semantics
(Qualitative Approach) Q46 - Q51 42
FREQUENTLY ASKED & IMPORTANT QUESTIONS 47
UNIT - II COMBINATIONAL LOGIC DESIGN Q1 - Q43 49 - 96
2.1 Parallel Binary Adder, Carry Look Ahead Adder, BCD Adder Q1 - Q10 50
2.2 Multiplexers and Demultiplexers and their Use in

Combinational Logic Design Q11 - Q21 60
2.3 ALU Q22 - Q24 68
2.4 Digital Comparators Q25 - Q31 73
2.5 Parity Generators Q32 - Q36 81
2.6 Code Converters and Parity Encoders Q37 - Q43 88
UNIT - III SEQUENTIAL LOGIC DESIGN Q1 - Q84 97 - 180
3.1 Registers, Applications of Shift Registers Q1 - Q25 98
3.2 Ripple of Aysnchronous Counters, Synchronous Counters Q26 - Q49 121
3.3 Synchronous and Aynschronous Sequential Design Q50 - Q82 146
3.3 Hazards in Sequential Circuits Q83 - Q84 176

UNIT - IV COMBINATIONAL MOS LOGIC CIRCUITS Q1 - Q27 181 - 212
4.1 Introduction, MOS Logic Circuits with deplection NMOS

Loads: Two input NOR gate, generalized NOR structure
with multiple inputs, Transient Analysis of NOR gate Q1 - Q6 182
4.2 Two Input NAND Gate, Generalized NAND Structure with

Multiple Inputs, Transient Analysis of NAND Gate Q7 - Q10 189
4.3 CMOS Logic Circuits : CMOS NOR Gate, CMOS NAND Gate Q11 - Q13 194
4.4 Complex Logic Circuits, Complex CMOS Logic Gates,

AOI and OAI Gates, Pseudo - nMOS Gates, CMOS Full
Adder Circuit Q14 - Q21 197
4.5 CMOS Transmission Gates (Pass Gates), Complementary

Pass Transistor Logic Q22 - Q27 205
UNIT - V SEQUENTIAL MOS LOGIC CIRCUITS Q1 - Q25 213 - 240
5.1 Introduction Q1 214
5.2 Behaviour of Bistable Elements Q2 - Q3 214
5.3 SR Latch Circuit Q4 - Q5 217
5.4 Clocked Latch and Flip-Flop Circuits-Clocked SR Latch,

Clocked JK Latch, Master-Slave Flip-Flop Q6 - Q11 219
5.5 CMOS D-Latch and Edge-Triggered Flip-Flop Q12 - Q14 225
5.6 Schmitt Trigger Circuit Q15 - Q19 229
5.7 Basic Principles of Pass Transistor Circuits Q20 - Q25 234
IMPORTANT QUESTIONS 240

INTRODUCTION TO THE SUBJECT
Digital IC Design of B.Tech II-Year II-Sem. (ECE) JNTU-Kakinada, is a core subject in ever-expanding courses of
Electronics and Communication Engineering. It deals with the introduction of digital logic families and inter facing concepts for
digital design, VHDL fundamentals to modeling the digital system design blocks. It also includes design and implementation of
combinational and sequential digital logic circuits.
The table below illustrates the complete idea about the subject, which will be helpful to plan and score good marks in the
end examinations.
S.No. Unit Name Description
1. Hardware Description Lan- In this unit, you will study about HDL based digital design, VHDL hardware
guages description language program structure, types, constants and arrays, functions
and procedures, libraries and packages, structural design elements, dataflow
design elements, behavioural design element and synthesis.
2. Combinational Logic Design In this unit, you will study qualitative approach of designing and modeling
of combinational logic circuits such as adders, multiplexers, ALU, digital
comparators, parity generators, code converters and priority encoders with
relevant digital ICs using HDL.
3. Sequential Logic Design In this unit, you will study qualitative approach of designing and modeling of
sequential logic circuits such as registers and counters with relevant digital ICs
using HDL. It also includes different synchronous and asynchronous sequential
circuit and hazards in sequential circuits.
4. Combinational MOS Logic This unit deals with construction and working of different combinational
Circuits MOS logic circuits, generalized NOR and NAND structures with multiple
inputs along with transient analysis, CMOS logic circuit, AOI and OAI gates,
Pseudo-nMOS gates, CMOS full-adder circuit,CMOS transmission gates and
complementary pass-transistor logic.
5. Sequential MOS Logic This unit explains design of different sequential MOS logic circuits, latch
Circuits circuits, flip-flops, CMOS latches, Schmitt trigger and principles of pass
transistor circuits.
It is sincerely hoped that this material will satisfy the expectations of students and at the same time helps them to
score maximum marks in exams.
Suggestions for improvement of the material from our esteemed readers will be highly appreciated and incorporated
in our forthcoming editions.
Syllabus
UNIT-1
HARDWARE DESCRIPTION LANGUAGES
VHDL: Introduction to VHDL, Entity declaration, Architecture, Data-flow, Behavioral and structural style
ofmodelings, Datatypes, Dataobjects, configurationdeclaration, Package, Generic, Operatorsandidentifiers,
PROCESS,IF, CASE & LOOPstatements, VHDL libraries.
VERILOG HDL: Introduction to Verilog HDL, Data types, Data operators, Module statement, Wire statement,
If-elsestatement, Case-endcasestatement, Verilog syntax and semantics (qualitative approach)
UNIT-2
COMBINATIONAL LOGIC DESIGN: Parallel binary adder, Carry look ahead adder, BCD adder, Multiplexers
anddemultiplexers and their use in combinational logic design, ALU, Digital comparators, Parity generators,
Codeconverters, Priority encoders. (Qualitative approach of designing and modeling the mentioned
combinationallogiccircuits with relevant digital ICs using HDL)
UNIT-3
SEQUENTIAL LOGIC DESIGN: Registers, Applications of shift registers, Ripple or a synchronous counters,
Synchronous counters, Synchronous and a synchronous sequential circuits, Hazards in sequential circuits.
(Qualitative approach of designing and modeling the mentioned sequential logic circuits with relevant digital
ICs using HDL)
UNIT-4
COMBINATIONAL MOS LOGIC CIRCUITS: Introduction, MOS logic circuits with depletion nMOS loads:
Two-inputNOR gate, Generalized NOR structure with multiple inputs, Transient analysis of NOR gate, Two-
input NANDgate, Generalized NAND structure with multiple inputs, Transient analysis of NAND gate, CMOS
logic circuits:CMOS NOR2 gate, CMOS NAND2 gate, Complex logic circuits, Complex CMOS logic gates,
AOI and OAIgates, Pseudo-nMOS gates, CMOS full-adder circuit, CMOS transmission gates (Pass Gates),
Complementarypass-transistorlogic.
UNIT-5
SEQUENTIAL MOS LOGIC CIRCUITS: Introduction, behavior bistable elements, SR latch circuit, Clocked
latch andflip-flop circuits: Clocked SR latch, Clocked JK latch, Master-slave flip-flop, CMOS D-latch and Edge-
triggeredflip-flop, Schmitt trigger circuit, Basic principlesof pass transistor circuits.
MID - 1 & 2 M.1
MID - 1 & 2
OBJECTIVE TYPE &
ESSAY QUESTIONS WITH KEY
SPECTRUM ALL-IN-ONE JOURNAL FOR ENGINEERING STUDENTS

M.2 DIGITAL IC DESIGN [JNTU-KAKINADA]
OBJECTIVE TYPE
UNIT - 1
1. ________ symbol identifies a system task. [ ]
(a) / (b) $
(c) # (d) %
2. The higher level of design description next to circuit level is __________ level. [ ]
(a) Switch level (b) Gate level
(c) Data flow level (d) Behavioural level.
3. Any program written to test a design description is, [ ]
(a) Module (b) Stimulus module
(c) Test bench (d) All of the above
4. Functions are used in all programming languages is known as [ ]
(a) Subroutines (b) Level
(c) Programs (d) Languages
5. In verilog, the system task used for controlling system is [ ]
(a) $ display (b) $ monitor
(c) $ finish (d) All of the above
6. The two groups of data types are, [ ]
(a) Variable and et data type (b) Wire and tri-data type
(c) Integer (d) Real
7. The two types of numbers used in verilog are [ ]
(a) Decimal and real (b) Integer and real
(c) Base form and real (d) None of the above
8. In order to increase readability of a digital design, __________ are written in a verilog code. [ ]
(a) Programs (b) Functions
(c) Operands (d) Comments
9. White space characters are used to separate [ ]
(a) Numbers (b) Keywords
(c) Identifiers (d) Integers
10. When a string of ASCII characters are used as an operand in an expression, it is treated as, [ ]
(a) Real number (b) Octal number
(c) Binary number (d) None of the above
KEY
1. (b) 2. (b) 3. (d) 4. (a) 5. (c)
6. (a) 7. (b) 8. (d) 9. (b) 10. (c)
WARNING: Xerox/Photocopying of this book is a CRIMINAL act. Anyone found guilty is LIABLE to face LEGAL proceedings.
MID - 1 & 2 M.3
UNIT - 2
1. Multiplexers are also known as, [ ]
(a) Data finder (b) Data deselectors
(c) Data selector (d) None of the above
2. The ripple carry adder requires a significant amount of time to complete the addition step,
and the time delay experienced during the process is referred to as _____ (or) _____. [ ]
(a) Carry propagation delay (b) Inter-stage carry delay
(c) Both a & b (d) None
3. To overcome this limitation of ripple carry adder and accelerate the addition process, a new technique
called _________ is implemented. [ ]
(a) Look ahead-carry addition (b) Carry addition
(c) BCD adder (d) Multiplexer
4. The problem of subtraction is changed into a problem of addition by using _____ representations. [ ]
(a) 10’s complement (b) Adder
(c) 9’s complement (d) 1’s and 2’s complement
5. An 8:1 multiplexer is available in the form of _____ & _____ IC’s. [ ]
(a) 74157 & 74158 (b) 74151 & 74152
(c) 74151 & 74157 (d) None
6. IC 74181 is used as _____. [ ]
(a) ALU (b) comparator
(c) Adder (d) Subtractor
7. 74 × 85 IC is a _____ bit MSI comparator and to design a 16-bit comparator _____ number
of 74 × 85 comparators has to be cascaded. [ ]
(a) 4-bit, 5 (b) 16-bit, 1
(c) 4-bit, 4 (d) 8-bit, 4
8. The 74180 has dual functions; it can be used as a _____ as well as a _____. [ ]
(a) Parity generator, Priority encoder (b) Parity checker, Priority encoder
(c) Parity generator, Parity checker (d) None
9. In BCD-to-binary converter using IC 74185A, the _____ of the binary input skips (bypasses)
the converter and appears as the _____of BCD output.
(a) LSB, LSB (b) LSB,MSB
(c) MSB,LSB (d) MSB,MSB
10. An IC 74148 is used as _____ [ ]
(a) Octal-to-Binary Priority Encoder (b) Decimal-to-BCD Priority Encoder
(c) BCD-to-Binary Converter (d) None
11. Which of the following is not an arthmetic circuit? [ ]
(a) 4 - bit comparator (b) 16 - bit BCD adder
(c) Ripple carry adder (d) BCD to 7 segment code converter
KEY
1. (c) 2. (a) 3. (d) 4. (b) 5. (a)
6. (c) 7. (c) 8. (a) 9. (a) 10. (a)
11. (d)

UNIT - 3
1. Parallel access shift register performs, [ ]
(a) Parallel to serial conversion
(b) Serial to parallel conversion
(c) Parallel to parallel conversion
(d) Both (a) and (b)
2. ______ counter counts only in one direction (i.e., either up or down). [ ]
(a) Up-down counter
(b) Single mode counter
(c) Multi mode counter
(d) None of the above
3. A 4-bit ring counter is also known as, [ ]
(a) Universal register
(b) Parallel register
(c) Circular shift register
4. LFSR is also known as [ ]
(a) Maximum length sequence generator
(b) Minimum length sequence generator
(c) Shift circular register
(d) Johnson counter
5. Moebius counter is also called as [ ]
(a) Ring counter
(b) Twisted-ring counter
(c) Johnson counter
(d) Both (b) and (c)
6. The glitch free outputs are present in ____________ counter. [ ]
(a) Johnson
(b) Ring
(c) Twisted-ring
(d) None
7. 74 × 163 is a synchronous 4-bit binary ____________ counter with active-low load and clear inputs [ ]
(a) MSI
(b) Ring
(c) Johnson
(d) None
MID - 1 & 2 M.5
8. Specialized ____________ functions are used for data encryption and decryption. [ ]
(a) Combinational
(b) Arithmatic
(c) Sequential
(d) None
9. In sequential circuits, output depends on, [ ]
(a) Present input and future output
(b) Present input and output
(c) Present input and past output
(d) Present input only
10. Which of the following are true about sequential circuits? [ ]
(a) Input signals can effect memory elements
(b) Circuits are simple to design
(c) Speed of operation is limited
(d) All of the above
11. Asynchronous sequential circuits use , [ ]
(a) Timer delay latches
(b) Gate devices
(c) Memory elements
12. ________ is a pictorial representation of the behavior of a sequential circuit. [ ]
(a) State table
(b) State diagram
(c) State assignment
(d) Flow table
13. _______ is the next portion of state table. [ ]
(a) Tabular
(b) Flow table
(c) Transition
(d) State diagram
14. Which of the following are the major fundamentals for VHDL [ ]
(a) Library support
(b) Timing control
(c) Concurrency

15. _________ provides the interface between the device and other external peripherals. [ ]
(a) Entity declaration
(b) Package body
(c) Architecture
(d) Package declaration
16. _____ is used for a unidirectional ouput signal. [ ]
(a) in
(b) Buffer
(c) Out
(d) inout
17. The common package declarations can be shared by many design units by using [ ]
(a) Library clause
(b) Use clause
(c) Both (a) and (b)
18. Process is used to declare, [ ]

(a) Variables
(b) Constants
(c) Functions
19. In __________ description, the circuits are represented interms of flow of data and elements. [ ]
(a) Behavioral
(b) Structural
(c) Data flow
20. In component declaration, every individual component is declared with unique [ ]
(a) Name-identifier
(b) Number
(c) Type of the input and output ports
21. In _____ type, data elements are represented in a sequential manner [ ]
(a) Scalar
(b) Composite
(c) Access
(d) File
MID - 1 & 2 M.7
22. ______ data type indicates the files that are present in host environment. [ ]
(a) Access
(b) Composite
(c) File
(d) Scalar
23. Which of the following are the example of a signal object? [ ]
(a) Signal CLOCK:BIT;
(b) signal DATABUS:BIT VECTOR (0 to 15);
(d) type BIT_FILE
24. Which of the following is true about basic identifier? [ ]
(a) Character must begin with a letter but, should not end with an underscore
(b) Character cna be both upper case and lower case letter
(c) It should not contain two underscore characters.
25. A library consists of [ ]
(a) Shared Designs
(b) Shared implementations
(c) Shared declarations
26. STD library includes, [ ]
(a) Basic definitions
(b) Type of VHDL language
(c) Utilities for text
(d) Both (a) and (b)
27. In IEEE.STD_LOGIC_1164.ALL ; ALLmeans, [ ]
(a) Use all definitions of file
(b) Use all variables of file
(c) Use all constants of file
(d) All of the abpve.
28. The process of associating a design entity and an architecture to a component instance is known as, [ ]
(a) Binding
(b) Component installation
(c) Component declaration
(d) Package declaration

29. Which of the statements are used to stoop the execution? [ ]
(a) Process
(b) Wait
(c) Variable assignment
(d) Signal assignment
30. Wait for ‘0‘ns indicates the processor to wait for, [ ]
(a) ‘0‘ns
(b) Less than ‘0‘ns
(c) One data cycle
31. In ______ loop, the statements are repeated until a specified condition becomes false. [ ]
(a) While
(b) Simple
(c) For
32. _______ statement is used inside the loop to terminate statements unconditionally. [ ]
(a) Next
(b) Assertion
(c) Terminate
(d) Exit
33. Which of the following is used to eliminate unwanted splices and transients in signals. [ ]
(a) Transport delay
(b) Insertion delay
(c) Delta delay
34. In the syntax, Target_Signal<=transport A after trasnport_delay; represents, [ ]
(a) Input
(b) Output
(c) Transport delay value
(d) Input-Output value
35. The process of automatic transformation of higher level abstraction to a lower level abstraction
is known as. [ ]
(a) Synthesis
(b) Translation
(c) Minimization
(d) Optimization
MID - 1 & 2 M.9
36. Which of the following are the functions of logic synthesizer? [ ]
(a) Translation
(b) Logic minimization and Optimization
(c) Mapping to gates
37. Translation operation is performed using , [ ]
(a) AND, OR gates
(b) Flip flops
(c) Latches
38. Logic optimization uses___ to make the equations of synthesizer network. [ ]
(a) Sequence of factoring
(b) Substitution operation
(c) Elimination operation
KEY
1. (d) 2. (b) 3. (c) 4. (a) 5. (d)
6. (b) 7. (a) 8. (c) 9. (b) 10. (d)
11. (d) 12. (b) 13. (a) 14. (d) 15. (a)
16. (b) 17. (c) 18. (a) 19. (c) 20. (d)
21. (a) 22. (c) 23. (c) 24. (d) 25. (d)
26. (a) 27. (a) 28. (a) 29. (b) 30. (a)
31. (a) 32. (d) 33. (b) 34. (d) 35. (a)
36. (d) 37. (d) 38. (d)

UNIT - 4
1. The _________ is a simplified drawing that encompasses useful information about the relative arrangement [ ]
of transistors and their interconnections.
(a) stick-diagram
(b) Layout
(c) Both a & b
(d) None
2. A straightforward way for determining the best gate ordering is the _________ technique. [ ]
(a) Hamilton path
(b) Euler-path
(c) Fleury’s algorithm
(d) None
3. _______ &________ , are critical voltage points for combinational logic circuits [ ]
(a) VOH, or Vth
(b) VOL, or VOH
c. VOL, or Vth
(d) VOL, or VOH
4. The two-input CMOS NOR gate is composed of [ ]
(a) An nMOS-network and a pMOS-network connected in series
(b) An nMOS-network and a pMOS-network connected in parallel
(c) An nMOS-network and a pMOS-network connected in Jumbling
(d) NONE
5. In two-input CMOS NOR gate, The nMOS-network contains ________ [ ]
(a) pMOS transistors that are connected in parallel
(b) nMOS transistors that are connected in series
(c) pMOS transistors that are connected in series
(d) nMOS transistors that are connected in parallel
6. In two-input CMOS NOR gate, The pMOS-network contains ________ [ ]
MID - 1 & 2 M.11
7. In two-input CMOS NAND gate, The nMOS-network contains ________ [ ]
8. In two-input CMOS NAND gate, The pMOS-network contains ________ [ ]
9. In the Two-input CMOS NAND gate equivalent kn = ______ kp [ ]
(a) 3
(b) 2
(c) 4
(d) NONE
10. Two nMOS transistors linked in series and having the same gate voltage act as if they were one nMOS [ ]
transistor with _________.
(a) keq = 0.5 kdriver
(b) keq = 5 kdriver
(c) keq = 50 kdriver
(d) keq = 5.5 kdriver
11. ______ path is described as an unbroken path that crosses every edge (branch) of the graph exactly once [ ]
(a) The Euler
(b) The Hamilton
(c) Low resistance
(d) NONE
12. In Complex Boolean functions, driver transistors connected in parallel carry-out _____ operations [ ]
(a) NOT
(b) AND
(c) OR
(d) NONE

13. In Complex Boolean functions, driver transistors connected in series carry-out _____ operations [ ]
(a) NOT
(b) AND
(c) OR
(d) NONE
KEY
1. (a) 2. (b) 3. (c) 4. (a) 5. (d)
6. (c) 7. (b) 8. (a) 9. (c) 10. (a)
11. (a) 12. (c) 13. (b)
MID - 1 & 2 M.13
UNIT - 5
1. ____________ is the minimum delay between negative S & R (in S-R latch) for them to be considered
non simultaneous. [ ]
(a) Recovery time
(b) Propagation time
(c) Delay time
(d) Access time
2. The basic bistable element circuit is also referred as [ ]
(a) 1-bit memory cell
(b) 3-bit memory cell
(c) 2-bit memory cell
(d) None
3. Latches and flip flops are ____________ elements [ ]
(a) Mono stable
(b) Bistable
(c) Astable
(d) None
4. _____ is often used to analyse the performance and to define the operation of SR latch. [ ]
(a) State table
(b) Flow table
(c) Primitive table
(d) Transition table
5. _______ describes a synchronous sequential machine. [ ]
(a) FSM
(b) ASM
6. Finite state machines are of ______ types. [ ]
(a) Three
(b) Two
(c) Four
(d) Five
7. In Mealy machine, outputs are functions of present _________ and _________. [ ]
(a) Input, Output
(b) Input state
(c) State, Output
(d) Output, input

8. FSM has ______ number of memory devices. [ ]
(a) Finite
(b) Infinite
(c) Zero
9. In Moore machine, output is a function of ________. [ ]
(a) Present input
(b) Past output
(c) Present state
10. In Mealy machine, _________ number of states are used to implement a function.
(a) More
(b) Less
(c) Zero
KEY

1. (a) 2. (a) 3. (b) 4. (d) 5. (a)

6. (b) 7. (b) 8. (a) 9. (c) 10. (b)
MID - 1 & 2 M.15
ESSAY QUESTIONS WITH KEY
UNIT - 1
Q1. With suitable block diagram explain about the design flow of VHDL. (Refer Unit-1, Q2)
Q2. Explain the VHDL program file structure with the syntax of a VHDL entity declaration and
architecture definition. (Refer Unit-1, Q4)
Q3. Explain the difference in program structure of VHDL and any other procedural language.
Give an example. (Refer Unit-1, Q5)
Q4. Explain in detail about the various abstraction levels in VHDL. (Refer Unit-1, Q8)
Q5. What are the different data objects supported by VHDL? Explain scalar types with
suitableexamples. (Refer Unit-1, Q11)
Q6. Explain various data types supported by VHDL and give necessary examples. (Refer Unit-1, Q10)
Q7. Explain various types of operators used in VHDL. (Refer Unit-1, Q12)
Q8. With suitable example, explain PROCESS statement in VHDL. (Refer Unit-1, Q16)
Q9. Explain about variable assignment statement, signal assignment statement,

wait statement. (Refer Unit-1, Q17)
Q10. List out the differences between variable assignment statement and signal assignment
statement with example. (Refer Unit-1, Q18)
Q11. Explain the following terms in Behavioral Modeling:
(i) Case statement
(ii) Null statement
(iii) Loop statement. (Refer Unit-1, Q20)
Q12. Explain IF, exit, next, assertion, report and null statements. (Refer Unit-1, Q21)
Q13. Explain about the following ,
(i) Packages with syntax
(ii) Libraries with syntax. (Refer Unit-1, Q22)
Q14. Discuss the binding. Discuss the binding between entity and components. (Refer Unit-1, Q24)
Q15. Write a process based VHDL program for the prime-number detector of 4-bit input and
explain the flow using logic circuit. (Refer Unit-1, Q31)
Q16. Write a VHDL program for comparing 8 bit unsigned integers. (Refer Unit-1, Q32)
Q17. Explain different levels of design descriptions in verilog. (Refer Unit-1, Q38)
Q18. Explain identifiers and keywords used in verilog HDL. (Refer Unit-1, Q42)

Q19. Explain different types of operators used in the verilog HDL. (Refer Unit-1, Q45)
Q20. Write the syntax for the following constructs and give one example for each relevant to
behavioral verilog HDL modeling,
(i) initial construct
(ii) always construct
(iii) wait construct. (Refer Unit-1, Q47)
Q21. Write the syntax for the following constructs and give one example for each relevant
to behavioral Verilog HDL modeling,
(i) The case statement
(ii) if and if-else constructs. (Refer Unit-1, Q50)
(i) assign-deassign construct
(ii) repeat construct
(iii) for loop. (Refer Unit-1, Q51)
UNIT - 2
Q1. Explain the implementation of N-bit binary adder using full adders. (Refer Unit-2, Q1)
Q2. Explain the operation of a Look ahead carry generator. (Refer Unit-2, Q3)
Q3. Draw the circuit of a 4-bit ripple carry adder circuit and explain how it is different from
look-a-head carry circuit. Give the equation for C1 to C4 for a look-ahead carry adder
circuit. (Refer Unit-2, Q4)
Q4. Write VHDL code for 4-bit look ahead carry generator along with circuit diagram. (Refer Unit-2, Q5)
Q5. Write a VHDL code to implement binary adder subtractor. (Refer Unit-2, Q7)
Q6. Design full subtractor circuit and write a VHDL code for implementation of full subtractor. (Refer Unit-2, Q8)
Q7. Using a process statement write a VHDL source code for 4 to 1 multiplexer. (Refer Unit-2, Q14)
Q8. What is multiplexer? Draw the logic diagram of 8 to 1 line multiplexer. (Refer Unit-2, Q15)
Q9. With the help of logic diagram explain 74×157 multiplexer. Write the data flow style
VHDL program for this IC. (Refer Unit-2, Q19)
Q10. What is ALU? Draw the block diagram of 74181ALU and Explain. (Refer Unit-2, Q22)
Q11. Discuss about the implementation of comparator using digital IC. (Refer Unit-2, Q26)
Q12. Explain about comparator and design a 16-bit comparator using 74×85 IC’s.
Write VHDL program. (Refer Unit-2, Q28)
MID - 1 & 2 M.17
Q13. Design a 24-bit comparator using 74×682 ICs and explain the functionality of the circuit.
Also implement VHDL source code in data flow style. (Refer Unit-2, Q31)
Q14. Draw the logic diagram of IC 74180 parity generator checker and explain its operation
with the help of a truth table. (Refer Unit-2, Q36)
Q15. Draw the block diagram of IC 74185A binary-to-BCD converter and Explain. (Refer Unit-2, Q39)
Q16. Design a 2 to 4 decoder circuit. Give its entity declaration behavioural model.
Also draw the waveform giving relation between its inputs and outputs. (Refer Unit-2, Q42)
Q17. Design a function F = ABC + (A + B + C) by using 74X138. (Refer Unit-2, Q43)
UNIT - 3
Q1. Discuss the logic circuit of 74×377 register. Write a VHDL program for the same in
structural style. (Refer Unit-3, Q7)
Q2. Explain different types of shift registers. (Refer Unit-3, Q9)
Q3. Give the VHDL programs for different type of shift register. (Refer Unit-3, Q10)
Q4. Draw the circuit of a bidirectional shift register with parallel loading using 2 to 4 line
decoder and D-flip-flops. (Refer Unit-3, Q12)
Q5. Draw and explain the working of shift left register. (Refer Unit-3, Q13)
Q6. Write a VHDL code for an n-bit left-to-right shift register using ‘FOR’ loop. (Refer Unit-3, Q15)
Q7. Draw and explain 4-bit universal shift register. (Refer Unit-3, Q17)
Q8. Write down truth table, VHDL code for the 4 bit register with parallel load.
Also draw the circuit and output waveform. (Refer Unit-3, Q18)
Q9. Design a self-correcting 4-bit, 4-state ring counter with a single circulating 0 using
IC 74LS194. (Refer Unit-3, Q21)
Q10. Write a VHDL program for 16-bit barrel shifter for left circular shift only? (Refer Unit-3, Q23)
Q11. Design a 4 bit synchronous binary even counter and write its behavioural mode. (Refer Unit-3, Q31)
Q12. Discuss about the working of Johnson counter using 74 LS194. (Refer Unit-3, Q33)
Q13. Explain the operation of a 4-bit synchronous binary counter with the required diagram
and waveforms. (Refer Unit-3, Q42)
Q14. Give a VHDL code for a 4-bit up counter with enable and clear inputs. (Refer Unit-3, Q43)
Q15. What are the capabilities and limitations of finite state machines? (Refer Unit-3, Q52)
Q16. Write short notes on the following with suitable examples.
(i) State diagram
(ii) State table
(iii) State assignment. (Refer Unit-3, Q54)

Q17. Explain the state equivalence and machine equivalence with reference to sequential
machines. (Refer Unit-3, Q56)
Q18. Draw the logic diagram of Melay model & explore its operation with examples. (Refer Unit-3, Q58)
Q19. Draw the logic diagram of Moore model & explore its operation with examples. (Refer Unit-3, Q59)
Q20. What are the Moore and Mealy machines? Compare them. (Refer Unit-3, Q60)
Q21. Give the comparison between synchronous sequential and asynchronous sequential
circuits. (Refer Unit-3, Q67)
UNIT - 4
Q1. Draw the two input NOR gate logic circuit with depletion nMOS loads and Explain. (Refer Unit-4, Q2)
Q2. Explain how to calculate VOH and VOL for two input NOR gate Logic Circuits with
Depletion nMOS Loads. (Refer Unit-4, Q3)
Q3. Draw the two input NAND gate logic circuit with depletion nMOS loads and Explain. (Refer Unit-4, Q7)
Q4. Explain how to calculate VOH and VOL for Two input NAND gate Logic Circuits with
Depletion nMOS Loads. Also calculate drain current when the output voltage is VOL. (Refer Unit-4, Q8)
Q5. Draw the two input CMOS NOR gate logic circuits and Explain its operation. (Refer Unit-4, Q11)
Q6. Explain how to calculate switching threshold for two input NOR gate using CMOS
Logic Circuits. (Refer Unit-4, Q12)
Q7. Explain about Implementation of Complex Boolean functions using nMOS Logic Circuits. (Refer Unit-4, Q15)
Q8. Explain about Implementation of Complex Boolean functions using CMOS Logic Circuits. (Refer Unit-4, Q16)
Q9. Explain about problem of constructing a minimum-area layout for the complex CMOS
logic gate. (Refer Unit-4, Q17)
Q10. Write short notes on Pseudo-nMOS gate. (Refer Unit-4, Q19)
Q11. What is CMOS transmission gate? Explain its operation. (Refer Unit-4, Q22)
Q12. Explain the DC analysis of the CMOS transmission gate. (Refer Unit-4, Q23)
Q13. Explain about the equivalent resistances of the three operating regions of the
transmission gate. (Refer Unit-4, Q24)
Q14. Explain about Complementary Pass-Transistor Logic (CPL). (Refer Unit-4, Q27)
UNIT - 5
Q1. Explain bistability principle. (Refer Unit-5, Q2)
Q2. Explain the operation of CMOS bistable element and its transient analysis. (Refer Unit-5, Q3)
Q3. Explain the operation of an SR latch using NOR gates. Implement it with CMOS design. (Refer Unit-5, Q4)
Q4. What is the advantage of JK latch over SR latch. Explain the operation of clocked
JK-latch. (Refer Unit-5, Q8)
MID - 1 & 2 M.19
Q5. Explain master-slave JK latch in detail. (Refer Unit-5, Q10)
Q6. Explain the working of an edge-triggered CMOS master-slave D flip-flop with neat
diagram. (Refer Unit-5, Q13)
Q7. Mention the basic principle of a pass transistor circuit. (Refer Unit-5, Q20)
Q8. Explain the logic 1 transfer in a pass transistor circuit. (Refer Unit-5, Q21)
Q9. Explain the logic 0 transfer in a pass transistor circuit. (Refer Unit-5, Q23)
Q10. Explain charge storage charge leakage at the soft node X during the inactive clock
cycle in an nMOS pass transistor. (Refer Unit-5, Q24)

Model Question Papers with Solutions MP.1
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Jawaharlal Nehru Technological University, Kakinada 1
B.Tech. II Year II Semester Examinations o
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Time: 3 Hours Max. Marks: 75
Answer any five Questions, one Question from Each Unit
All Questions Carry Equal Marks
---
1. (a) Explain the VHDL program file structure with the syntax of a VHDL entity declaration and architecture
definition. (Unit-1 / Q4)
(b) Explain various data types supported by VHDL and give necessary examples. (Unit-1 / Q10)
(or)
2. (a) Discuss the binding. Discuss the binding between entity and components. (Unit-1 / Q24)
(b) Explain different levels of design descriptions in verilog. (Unit-1 / Q38)
3. (a) Explain the operation of a Look ahead carry generator. (Unit-2 / Q3)
(b) What is multiplexer? Draw the logic diagram of 8 to 1 line multiplexer. (Unit-2 / Q15)
(or)
4. (a) What is meant by arithmetic comparison circuits? Design 4 bit comparator circuit using logic gates and
write a VHDL code for implementation of 4-bit comparator. (Unit-2 / Q29)
(b) Explain in brief about the need of code converters. (Unit-2 / Q37)
5. (a) Discuss the logic circuit of 74×377 register. Write a VHDL program for the same in structural style.
(Unit-3 / Q7)
(b) Design a self-correcting 4-bit, 4-state ring counter with a single circulating 0 using IC 74LS194.
(Unit-3 / Q21)
(or)
6. (a) Write short notes on the following with suitable examples.
(i) State diagram
(ii) State table
(iii) State assignment. (Unit-3 / Q54)
(b) Describe gated ‘D’ latch as an asynchronous circuit. (Unit-3 / Q75)
7. Draw the two input NOR gate logic circuit with depletion nMOS loads and Explain. (Unit-4 / Q2)
(or)
8. (a) Explain how to calculate switching threshold for two input NOR gate using CMOS Logic Circuits.
(Unit-4 / Q12)
(b) Write short notes on Pseudo-nMOS gate. (Unit-4 / Q19)

MP.2 DIGITAL IC DESIGN [JNTU-KAKINADA]
9. Explain the operation of CMOS bistable element and its transient analysis. (Unit-5 / Q3)
(or)
10. (a) Explain the logic 1 transfer in a pass transistor circuit. (Unit-5 / Q21)
(b) Consider the monostable multivibrator circuit drawn in figure below. Calculate the output pulse width.
VT(dep) = –2V
VT(enh) = 1 V
k' =20 µA/V2
y = 0.
5V
2/4 2/16 2/4
1nF Vout
Vin 4/2 4/2 4/2
(Unit-5 / Q18)
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1. (a) With suitable block diagram explain about the design flow of VHDL. (Unit-1 / Q2)
(b) Explain various types of operators used in VHDL. (Unit-1 / Q12)
(or)
2. (a) What are the different data objects supported by VHDL? Explain scalar types with suitable
examples. (Unit-1 / Q11)
(b) Explain the port connection rules in a module instantiation? (Unit-1 / Q40)
3. (a) Write VHDL code for 4-bit look ahead carry generator along with circuit diagram. (Unit-2 / Q5)
(b) Explain the operation of a ripple carry adder. (Unit-2 / Q1)
(or)
4. (a) Explain about comparator and design a 16-bit comparator using 74×85 IC’s. Write VHDL program.
(Unit-2 / Q28)
(b) Draw the block diagram of IC 74184 BCD-to-binary converter and explain its use as one and half decade
BCD-to-binary converter. (Unit-2 / Q38)
5. (a) Give the VHDL programs for different type of shift register. (Unit-3 / Q10)
(b) Design a 4 bit synchronous binary even counter and write its behavioural mode. (Unit-3 / Q31)
(or)
6. (a) What are the Moore and Mealy machines? Compare them. (Unit-3 / Q60)
(b) Explain in detail about state reduction in Asynchronous sequential circuits. (Unit-3 / Q79)
7. (a) Explain how to calculate VOH and VOL for two input NOR gate Logic Circuits with Depletion nMOS Loads.
(Unit-4 / Q3)
(b) Consider the depletion load nMOS NOR2 gate shown in figure with the following parameters: mnCox = 25
mA/V2, VT0.driver = 1.0V, VT0.load = – 3.0 V, g = 0.4 V1/2, and |2fF| = 0.6 V. The transistor dimensions are given
as (W/L)A = 2, (W/L)B = 4, and (W/L)load = 1/3. The power supply voltage is VDD = 5V. Calculate the output
voltage levels for all four valid input voltage combinations. (Unit-4 / Q4)

(or)
8. (a) Draw and explain the layout for CMOS NOR and NAND gates. (Unit-4 / Q14)
(b) Explain implementation of full adder using CMOS logic circuits. (Unit-4 / Q21)
9. Explain the operation of an SR latch using NOR gates. Implement it with CMOS design. (Unit-5 / Q4)
(or)
10. (a) Explain the logic 0 transfer in a pass transistor circuit. (Unit-5 / Q23)
(b) Draw the schematic circuit of a D flip-flop with positive edge triggering using NAND gates. Give its timing
diagram and explain its operation. (Unit-5 / Q14)
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1. (a) Explain the difference in program structure of VHDL and any other procedural language.
Give an example. (Unit-1 / Q5)
(b) Explain about variable assignment statement, signal assignment statement, wait statement. (Unit-1 / Q17)
(or)
2. (a) Design the logic circuit and write a structural style VHDL program for the following function.
F(Q) = / (0, 2, 5, 7, 8, 10, 13, 15) + d(11). (Unit-1 / Q27)

A,B,C,D
(b) Explain defparam and localparam keywords. (Unit-1 / Q44)

3. (a) Design a full subtractor with logic gates and write VHDL data flow program for the implementation of the
above subtractor. (Unit-2 / Q8)
(b) With the help of logic diagram explain 74×157 multiplexer. Write the data flow style VHDL program for this
IC. (Unit-2 / Q19)
(or)
4. (a) What is Parity? Draw the Block Diagram of 74180 Parity Generator/Checker and Explain. (Unit-2 / Q32)
(b) What are the drawbacks of ordinary digital encoders? How are they over come using priority encoders?
Explain Decimal-to-BCD Priority Encoder using IC 74147. (Unit-2 / Q40)
5. (a) Write a VHDL code for an n-bit left-to-right shift register using ‘FOR’ loop. (Unit-3 / Q15)
(b) Discuss about the working of Johnson counter using 74 LS194. (Unit-3 / Q33)
(or)
6. (a) Write a VHDL code for the serial adder. (Unit-3 / Q63)
(b) For the machine given in table, find the equivalence partition and a corresponding reduced machine in
standard form and also explain the procedure. (Unit-3 / Q81)
NS, Z
PS
X=0 X=1
A B, 0 E, 0
B E, 0 D, 0
C D, 1 A, 0
D C, 1 E, 0
E B, 0 D, 0

7. Draw the two input NAND gate logic circuit with depletion nMOS loads and Explain. (Unit-4 / Q7)
(or)
8. (a) Explain about Implementation of Complex Boolean functions using nMOS Logic Circuits.
(Unit-4 / Q15)
(b) What is CMOS transmission gate? Explain its operation. (Unit-4 / Q22)
9. Explain master-slave JK latch in detail. (Unit-5 / Q10)
(or)
10. Explain charge storage charge leakage at the soft node X during the inactive clock cycle in an nMOS pass
transistor. (Unit-5 / Q24)
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1. (a) Explain in detail about the various abstraction levels in VHDL. (Unit-1 / Q8)
(b) Explain the following terms in Behavioral Modeling :
(i) Case statement,
(ii) Null statement
(iii) Loop statement. (Unit-1 / Q20)
(or)
2. (a) Write a VHDL program for comparing 8 bit unsigned integers. (Unit-1 / Q32)
(b) Write Verilog code using case statement for any one example. (Unit-1 / Q49)
3. (a) Using a process statement write a VHDL source code for 4 to 1 multiplexer. (Unit-2 / Q14)
(b) Design an 8-bit ALU circuit using 74LS181 IC’s and write its VHDL code. (Unit-2 / Q23)
(or)
4. (a) Draw the logic diagram of IC 74180 parity generator checker and explain its operation with the help of a
truth table. (Unit-2 / Q36)
(b) Explain about IC 74148 and its use as Octal-to-Binary priority encoder. (Unit-2 / Q41)
5. (a) Write down truth table, VHDL code for the 4 bit register with parallel load. Also draw the circuit and output
waveform. (Unit-3 / Q18)
(b) Give a VHDL code for a 4-bit up counter with enable and clear inputs. (Unit-3 / Q43)
(or)
6. (a) Give the comparison between synchronous sequential and asynchronous sequential circuits.
(Unit-3 / Q67)
(b) Discuss the hazards in asynchronous sequential circuits and the methods to eliminate them.
(Unit-3 / Q84)
7. (a) Explain how to calculate VOH and VOL for Two input NAND gate Logic Circuits with Depletion nMOS Loads.
Also calculate drain current when the output voltage is VOL. (Unit-4 / Q8)
(b) Draw the two input CMOS NOR gate logic circuits and Explain its operation. (Unit-4 / Q11)
(or)

8. (a) Explain about Implementation of Complex Boolean functions using CMOS Logic Circuits. (Unit-4 / Q16)
(b) Explain about Complementary Pass-Transistor Logic (CPL). (Unit-4 / Q27)
9. Explain the working of a basic CMOS D-latch with neat diagram. (Unit-5 / Q9)
(or)
10. (a) Illustrate the CMOS implementation of Schmitt trigger. (Unit-5 / Q15)
(b) Explain bistability principle. (Unit-5 / Q2)
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( Electronics and Communication Engineering )

Answer any Five Questions, One Question from Each Unit
---
1. (a) With suitable example, explain PROCESS statement in VHDL.
Refer Unit-1, Q16
(b) Explain about the following,
(ii) Libraries with syntax.
Refer Unit-1, Q22
(or)
2. (a) Compare VHDL and verilog HDL.
Refer Unit-1, Q35
(b) Explain about different data types used in verilog HDL.
Refer Unit-1, Q43
3. (a) Write the disadvantages in implementation of N-bit binary adder using full adders. How it is overcome by
“carry look ahead adder” Explain.
Refer Unit-2, Q3
(b) With the help of logic diagram explain 74×157 multiplexer. Write the data flow style VHDL program for this
IC.
Refer Unit-2, Q19
(or)
4. (a) Draw the logic diagram of IC 74180 parity generator checker and explain its operation with the help of a
truth table.
Refer Unit-2, Q36
(b) Design a function F = ABC + (A + B + C) by using 74X138.
Refer Unit-2, Q43
5. (a) Write a VHDL for an n-bit register with asynchronous clear.
Refer Unit-3, Q4
(b) Write a VHDL program for 16-bit barrel shifter for left circular shift only?
Refer Unit-3, Q23
(or)

GP.2 DIGITAL IC DESIGN [JNTU-KAKINADA]
6. (a) Write short notes on,
(i) Finite state machine
(ii) State transition function
(iii) Finite state model
(iv) Terminal state
(v) Strongly connected machine.
Refer Unit-3, Q51
(b) Design a Mealy model of sequence detector to detect the pattern 1001.
Refer Unit-3, Q66
7. Explain how to calculate VOH and VOL for Two input NAND gate Logic Circuits with Depletion nMOS Loads. Also
calculate drain current when the output voltage is VOL.
Refer Unit-4, Q8
(or)
8. (a) Draw and explain the layout for CMOS NOR and NAND gates.
Refer Unit-4, Q14
(b) Explain the DC analysis of the CMOS transmission gate.
Refer Unit-4, Q23
9. (a) What is a sequential circuit? Give its classification.
Refer Unit-5, Q1
(b) Explain the operation of clocked NAND based SR-latch.
Refer Unit-5, Q7
(or)
10. (a) Draw the schematic circuit of a D flip-flop with positive edge triggering using NAND gates. Give its timing
diagram and explain its operation.
Refer Unit-5, Q14
(b) Explain the impact of node voltage Vx during logic 1 transfer in a pass transistor circuit.
Refer Unit-5, Q22
Guess Papers with Solutions GP.3
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1. (a) Discuss identifiers in VHDL.
Refer Unit-1, Q13
(b) Explain the difference between function and procedure supported by VHDL. Give the necessary examples.
Refer Unit-1, Q25
(or)
2. (a) Explain differences between module and module instances in verilog.
Refer Unit-1, Q37
(b) Write the syntax for the following constructs and give one example for each relevant to behavioral verilog
HDL modeling,
(iii) wait construct.
Refer Unit-1, Q47
3. (a) Draw the circuit of a 4-bit ripple carry adder circuit and explain how it is different from look-a-head carry
circuit. Give the equation for C1 to C4 for a look-ahead carry adder circuit.
Refer Unit-2, Q4
(b) What is ALU? Draw the block diagram of 74181ALU and Explain.
Refer Unit-2, Q22
(or)
4. (a) Design an n-bit input odd parity generator using daisy-chain structure.
Refer Unit-2, Q34
(b) Draw the block diagram of IC 74185A binary-to-BCD converter and Explain.
Refer Unit-2, Q39
5. (a) Explain different types of shift registers.
Refer Unit-3, Q9
(b) Write the VHDL program for 74×163 4-bit counter.
Refer Unit-3, Q35
(or)

6. (a) What are the capabilities and limitations of finite state machines?
Refer Unit-3, Q52
(b) Give a VHDL code for a 4-bit up counter with enable and clear inputs.
Refer Unit-3, Q43
7. (a) Consider the depletion load nMOS NOR2 gate shown in figure with the following parameters: mnCox = 25
voltage levels for all four valid input voltage combinations.
Refer Unit-4, Q4
(b) Explain the transient analysis NOR gate using MOS transistors.
Refer Unit-4, Q6
(or)
8. (a) Explain about problem of constructing a minimum-area layout for the complex CMOS logic gate.
Refer Unit-4, Q17
(b) Explain about the equivalent resistances of the three operating regions of the transmission gate.
Refer Unit-4, Q24
9. (a) Explain bistability principle.
Refer Unit-5, Q2
(b) What is the advantage of JK latch over SR latch. Explain the operation of clocked JK-latch.
Refer Unit-5, Q8
(or)
10. (a) Briefly explain the Schmitt trigger circuit.

Refer Unit-5, Q16
(b) Explain the logic 0 transfer in a pass transistor circuit.

Refer Unit-5, Q23
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1. (a) List out the differences between variable assignment statement and signal assignment statement with
example.
Refer Unit-1, Q18
(b) Design the logic circuit and write a data-flow style of VHDL program for the following function,
F(Y) = ΣA,B,C,D (1, 4, 5, 7, 12, 14, 15) + d (3, 11).
Refer Unit-1, Q27
(or)
2. (a) Explain different number specifications used in verilog HDL.
Refer Unit-1, Q41
(b) Write the syntax for the following constructs and give one example for each relevant to behavioral Verilog
HDL modeling,
(ii) if and if-else constructs.
Refer Unit-1, Q50
3. (a) Write a VHDL code to implement binary adder subtractor.
Refer Unit-2, Q7
(b) Discuss about the implementation of comparator using digital IC.
Refer Unit-2, Q26
(or)
4. Explain about IC 74148 and its use as Octal-to-Binary priority encoder.
Refer Unit-2, Q41
5. (a) Draw and explain 4-bit universal shift register.
Refer Unit-3, Q17
(b) Write a VHDL code for a down-counter.
Refer Unit-3, Q45
(or)

6. (a) Design a serial adder circuit to add two binary numbers using D-flip flops.
Refer Unit-3, Q57
(b) Discuss the design steps of asynchronous sequential circuits.
Refer Unit-3, Q77
7. (a) Explain how to calculate VOH and VOL for two input NOR gate Logic Circuits with Depletion nMOS Loads.
Refer Unit-4, Q3
(b) Explain the generalized NAND structure with multiple inputs.
Refer Unit-4, Q9
(or)
8. (a) Write short notes on Pseudo-nMOS gate.
Refer Unit-4, Q19
(b) What is the advantage of implementing logic circuits using CMOS transmission gates? Implement a Two-
input multiplexor circuit using two CMOS TGs and explain its working.
Refer Unit-4, Q25
9. Explain the operation of CMOS bistable element and its transient analysis. Model Paper-1, Q9
Refer Unit-5, Q3
(or)
10. (a) Consider the monostable multivibrator circuit drawn in figure below. Calculate the output pulse width.
VT(dep) = –2V
VT(enh) = 1 V
k’ =20 µA/V2
y = 0.
5V
2/4 2/16 2/4
1nF Vout
Vin 4/2 4/2 4/2
Refer Unit-5, Q18
(b) Explain charge storage charge leakage at the soft node X during the inactive clock cycle in an nMOS pass
transistor.
Refer Unit-5, Q24
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1. (a) Explain with an example the syntax and the function of if statement.
Refer Unit-1, Q19
(b) Write a process based VHDL program for the prime-number detector of 4-bit input and explain the flow
using logic circuit.
Refer Unit-1, Q31
(or)
2. (a) Explain about identifiers and keywords used in verilog HDL.
Refer Unit-1, Q42
(b) Explain different levels of design descriptions in verilog.
Refer Unit-1, Q38
3. (a) What is BCD? Explain how to perform BCD Addition.
Refer Unit-2, Q9
(b) Design a 24-bit comparator using 74×682 ICs and explain the functionality of the circuit. Also implement
VHDL source code in data flow style.
Refer Unit-2, Q31
(or)
4. Design a 2 to 4 decoder circuit. Give its entity declaration behavioural model. Also draw the waveform giving
relation between its inputs and outputs.
Refer Unit-2, Q42
5. (a) Design a self-correcting 4-bit, 4-state ring counter with a single circulating 0 using IC 74LS194.
Refer Unit-3, Q21
(b) Design a 4-bit binary synchronous counter using 74×74.
Refer Unit-3, Q49
(or)
6. (a) Draw the logic diagram of Moore model & explore its operation with examples.
Refer Unit-3, Q59
(b) Describe master-slave D flip-flop as an asynchronous circuit.
Refer Unit-3, Q76

7. (a) Explain the generalized NOR structure with multiple inputs.
Refer Unit-4, Q5
(b) Draw the two input CMOS NOR gate logic circuits and Explain its operation.
Refer Unit-4, Q11
(or)
8. (a) The simplified layout of a CMOS complex logic circuit is given in figure below. Draw the corresponding
circuit diagram, and find an equivalent CMOS inverter circuit for simultaneous switching of all inputs,
assuming that (W/L)p = 15 for all pMOS transistors and (W/L)n = 10 for all nMOS transistors.
D E A B C Z
VDD
DIFF.
NWELL
P+
POLY
GND MET-1
Refer Unit-4, Q20

(b) Explain the Implementation of the logic XOR function, using two CMOS TGs and two CMOS inverters.
Refer Unit-4, Q26
9. Explain the operation of an SR latch using NOR gates. Implement it with CMOS design.
Refer Unit-5, Q4
(or)
10. (a) Explain the logic 1 transfer in a pass transistor circuit.

Refer Unit-5, Q21
(b) Explain the working of a basic CMOS D-latch with neat diagram.
Refer Unit-5, Q12
UNIT-1 (Hardware Description Languages) 1
UNIT
Hardware Description
1 Languages SI
A GROUP
Syllabus
VHDL : Introduction to VHDL, Entity declaration, Architecture, Data-flow, Behavioral and structural style of modelings,
Data types, Data objects, Configuration declaration, Package, Generic, Operators and identifiers, PROCESS, IF, CASE &
LOOP statements, VHDL libraries.
VERILOG HDL: Introduction to Verilog HDL, Data types, Data operators, Module statement, Wire statement, If-else
statement, Case-end case statement, Verilog syntax and semantics (qualitative approach)
Learning Objectives
C VHDL
 Program structure of VHDL
 Data-Flow, Behavioral and Structural Style of modellings
 Data types, Data objects, Operators and identifiers
 Statements such as, GENERIC, PROCESS, IF, CASE and LOOP
 VHDL Libraries
C Verilog HDL
 Design flow of Verilog HDL
 Comparison between VHDL and Verilog HDL
 Data-Flow, Behavioral and Structural Style of modellings
 Data Types, Data Operators
 Statements such as, MODULE, WIRE, IF-ELSE and CASE.
Introduction
HDL is acronym for hardware description language, which describes the hardware of digital systems in textual form. Digital
systems can be represented in the form of documentation, which can be understood by human and also computers. Logic
diagrams, digital circuits, Boolean expressions can be represented using HDL. The orientation of HDL is specially towards
describing the hardware structures and behavior. To describe hardware for the purpose of simulation, modeling testing,
design and documentation HDLs are used. In this unit we will study the basics of VHDL and Verilog HDL.

2 DIGITAL IC DESIGN [JNTU-KAKINADA]
1.1 VHDL
1.1.1 Introduction to VHDL
Q1. Explain in brief the evolution of VHDL and men- The first step is the “design concept”, where we need to
tion the capabilities of the language. have a complete picture of the device under consideration and
Ans: the specifications required to achieve the device properties.
VHDL is an acronym for very high speed integrated The second step is “initial design”. Where we need
to have a design entry by using the VHDL (language) code.
circuits hardware description language. This language was first
Signals in the circuit are represented as variables in the source
introduced in 1981 for the Department of Defense (DoD) under code and logic functions are expressed by assigning values to
the VHSIC program. In 1983 IBM, Texas instruments and these variables. Hence, VHDL code is a combination of plain
intermetrics started to develop this language. In 1985, VHDL 7.2 text and may utilize any text editor.
version was released. In 1987 IEEE standardized the language. The third step is “simulation/verification”. Here, we check
The language has been through a few revisions, and you will come whether the designed circuit functions are expected or not. The
across this in the VHDL community. Currently, the most widely VHDL code can be simulated by using “test benches” which
used version is the 1987 (std 1076-1987) version, the language automatically apply inputs and compares with the desired outputs.
referred to as VHDL 93. VHDL 93 (Adopted in 1994 of course) If the design is correct then we have to move to the final
is fairly new and is still in the process of replacing VHDL 87. step called “successful design”. But when the design is wrong
we move to an intermediate step called “redesign”.
VHDL was originally designed to serve two major
objectives, Where we modify the old design to achieve the given
objective i.e., desired output and again move to the simulation
(i) It is used for documentation of large digital designs. to verify the outputs. This process is continued until we achieve
(ii) VHDL incorporates features for showing the perfor- the correct design.
mance of a digital circuit. The next step of the process is logic synthesis, which is used
This permits to use VHDL as an input to software pro- to translate the design described in a design-entry method (Usually,
grams, which are used to simulate the circuit operation. Further, a program in VHDL or verilog) into a physically realizable circuit.
it is used in design entry in CAD systems. The CAD tools syn- The same tool is also used to optimize the circuit. When the design-
thesize the VHDL code into a hardware unit that performs the entry progresses through the initial synthesis tools, logic equations,
operation described by the code. In addition to being used for that describe the logic functions needed to realize the circuit, are
each of these purposes, VHDL can be used to take three differ- automatically generated. Usually the logic equations generated
by the initial synthesis tools are not in the optimal form. As these
ent approaches for describing hardware. These three different
expressions mirror the designer’s input to the CAD tools, it is hard
approaches are the structural, data flow and behavioral methods
for a designer to generate optimal results by hand, particularly for
of hardware description. Most of the time a mixture of the three
large circuits. Usage of optimization techniques produces logic
methods is employed. equations that are not only correct functionally but are optimized
Q2. With suitable block diagram explain about the (enhanced/improved) for design goals such as cost, speed, and
design flow of VHDL. technology of implementation. The process of optimization is
performed after functionally correct design is obtained, because
Ans: (Model Paper-2, Q1(a) | Oct./Nov.-19, Set-1, Q3(a) M[7])
optimization performed before the acquisition of functionally
The VHDL design flow consists of basic sequence of steps correct design does not serve any purpose.
that are performed to achieve a successful design as shown in figure. Q3. List and explain the VHDL requirements.
Design Cncept
Ans:
Initial Design Department of Defence (DoD) imposed certain criteria
(which were not met by other HDLs) as basic requirements for
Simulation Re Design
VHDL. The eight major requirements of VHDL are,
(i) Concurrency
Is (ii) Support for design hierarchy
design
Correct?
(iii) Library support
(iv) Sequential statement
Yes No (v) Generic design
Successful Design (vi) Type declarations and usage
(vii) Use of subprograms
Logic Synthesis
(viii) Timing control.
Figure (ix) Structural Specification
(i) Concurrency: Concurrency is defined as the
1.1.2 Entity Declaration, Architecture, Configu-
simultaneous execution of functions such as transfer of
ration Declaration, Package
statements, description of components and component
instantiation. VHDL must be designed in such a way Q4. Explain the VHDL program file structure with
that the large and small units in the system are made the syntax of a VHDL entity declaration and
simultaneously active, in order to perform concurrent architecture definition.
operations. (Model Paper-1, Q1(a) | March-21, Set-1, Q3(a) M[7])
(ii) Support for Design Hierarchy: Generally, a design (or)
involves for interface description and definition of
Explain the VHDL program file structure and
operations of separate system parts. The entire system
explain the same with the syntax of a VHDL
requires number of descriptions for a given interface
entity declaration and architecture definition.
description. To overcome this limitation, VHDL was
developed with design hierarchy, wherein a divide and Oct./Nov.-20, Set-1, Q3(a) M[7]
conquer technology is introduced. The technique divides (or)
a multi level system into subsystems with descriptions With the help of block diagram explain the
being defined using behavioural or structural modelling. program structure for VHDL.
The division is further carried out till the basic unit of
design is obtained. Oct./Nov.-19, Set-2, Q3(b) M[7]
(or)
(iii) Library Support: VHDL must support a standard
library with user and system defined primitives and What is package body? Explain with example.
descriptions. The language must provide an appropriate Oct./Nov.-19, Set-2, Q3(a) M[7]
method to access different libraries of the system. (Refer only Package body)
(iv) Sequential Statements: The language must support a (or)
sequential internal operation carried out after dividing
Write short note on package declaration.
the system into concurrent components. This can be
accomplished by employing various constructs (such Oct./Nov.-19, Set-3, Q1(a) M[7]
as case, if then else, loop). (Refer only Package Declaration)
(v) Generic Design: VHDL must permit a generic Ans:
description such that it is configurable at any size, physical Block diagram of program structure
characteristics, timing, loading and environmental
The program structure of VHDL is as shown in figure.
conditions. In other words, besides input and output
influence of other physical characteristics such as Entity Declaration
ambient temperature, loading of components are also
taken into consideration. For instance, a 7400 logic Architecture
family NAND gate way involves many series such as,
LS, F, ALS which are functionally identical and differ Configuration Declaration
only in their timing and loading characteristics.
Package Declaration
(vi) Type Declarations and Usage: Type declaration and
its usage is another requirement which is imposed on Package Body
VHDL by DoD. The hardware description provided
by the language (besides bit or boolean) must include Figure
integer, floating, point, enumerate types and user-defined The program structure of VHDL contains,
types. The system-defined and user-defined types must
(i) Entity declaration
be included in the library of environment along with
their transparent availability to the users. (ii) Architecture
(vii) Use of Subprograms: Subprograms such as functions (iii) Configuration declaration
and procedures must be included in the VHDL language. (iv) Package declaration
(viii) Timing Control: The language must assign timings at (v) Package body.
all levels of designing. It must be capable of delaying the (i) Entity Declaration: An entity is a basic block of
actual assignment values (for a finite time) by scheduling VHDL code that provides the specification of input
all the signal values. and output signals and modes of a hardware module.
(ix) Structural Specification: The another requirement It also provides the interface between the device and
imposed on VHDL by DoD is of structural specification other external peripherals. Entity is modeled by an
i.e., it should employ constructs for representing entity declaration and a architecture body. The entity
decomposition of structural hardware at every level. declaration demonstrates the external view of the entity.

Syntax
ENTITY entityname IS
PORT (signalnames : mode signaltype;

signalnames : mode signaltype);
END entityname;
An entity declaration must begin with a keyword “ENTITY” and terminate with a keyword “END”. The various elements
in entity declaration are,
(i) Entity Name : Entityname could be anything which is selected by the programmer to name the entity.
(ii) Signal Name : Signalnames are the set of user defined identifiers to give the name to external interface signals.
(iii) Mode : Mode is used to describe the ports. Based on the signal direction, there are four types of ports.
(a) in : It is used for a unidirectional input signal i.e., for a signal which is input to an entity.
(b) out : It is used for a unidirectional output signal i.e., for a signal which is output from an entity.
(c) input : It is used for a bidirectional signal.
(d) buffer : It is used for a unidirectional output signal and its value can be read inside the architecture.
(iv) Signaltype : Signal type is a user defined signal.
Example: The following is an example of an entity declaration for the logic expression Y =
Entity boolean_exp is
Port (A, B, C, D : in STD_LOGIC;
Y : Out STD_LOGIC );
End Boolean_exp;.
(ii) Architecture
Architecture body is an another basic block after entity declaration in VHDL code. It provides the internal detail information
of an entity by using any of the following modelling styles.
(a) Structural style: In structural style, a set of interconnected components are used.
(b) Dataflow style: In dataflow style, a set of concurrent assignment statements are used.
(c) Behavioural style: In behavioural style, a set of sequential assignment statements are used.
Syntax
ARCHITECTURE architecturename of entityname is
Declarations
BEGIN
Statements;
END architecturename;
Architecture body must begin with a keyword ‘ARCHITECTURE’ and terminate with a keyword “END”. The various
elements in the architecture body are,
Architecturename : It is a user_defined name given to architecture body and must be associated with an entity name.
Declarations : In this section different signals, types, constant, functions, variables procedure definitions and
component definitions are declared.
Begin : It is a predefined keyword used to keep the statements within architecture body.
Statements : In this section, based on the style of modelling various statements can be used i.e., either sequential
or concurrent.
(iii) Configuration Declaration
Configuration declaration binds the architecture body to its associated entity and components to other entities. An entity
may possess one or more various configurations.
Syntax
CONFIGURATION configurationname of entityname is block_configuration;
END configurationname;
A configuration declaration must begin with a keyword
CONFIGURATION and terminate with a keyword “END”.
The various elements in the configuration declaration are, Example of Package Body
Configuration name : It is a user defined name that Package body packbd is
specifies the configuration for the entity name function mean (x, y, z: REAL) return REAL is
Block_configuration : In this section, the ports which begin
are to be binded are declared.
return (x + y + z) / 3.0;
(iv) Package Declaration
end mean
Package declaration is a mechanism employed in VHDL
to store some common declarations like types, procedures, end packbd;
functions etc. These common declarations can be shared by Q5. Explain the differences in VHDL program
many design units by using “library” and “use” clauses. structure with any other language with the help
Syntax of an example. March-21, Set-2, Q3(a) M[7]
PACKAGE packagename IS (or)

type declarations Explain the difference in program structure of
subtype declarations VHDL and any other procedural language. Give
an example.
Constant declarations
(Model Paper-3, Q1(a) | Oct./Nov.-18, Set-1, Q3(b) M[7])
signal declarations
Ans:
Variable declarations
The differences between VHDL program structure and
Subprogram declarations
other procedural language are as follows,
File declarations
Alias declarations VHDL Language Other Procedural
Component declarations Language
attribute declarations 1. In VHDL, the program 1. I n o t h e r p r o c e d u r a l
attribute specifications file structure comprises language, the program
disconnection specifications entity declaration and text file comprises
use clauses architecture declaration. documentation, decl-
END packagename; aration, test vectors and
statements.
Example
PACKAGE nand_package IS 2. A semicolon is used 2. A semicolon is used after
COMPONENT nand after every statement. every logic equation.
PORT(A, B : IN STD_LOGIC; 3. V H D L d e f i n e s t h e 3. Other procedural language
Y : OUT STD_LOGIC); interface of a hardware enables the users to
END COMPONENT; module and hides the specify logic functions for
internal information of realization in PLDs.
END nand_package;
same module.
(v) Package Body
A package body possess the details of a package 4. The identifiers used are 4. The identifiers used are
declaration i.e., it stores the definition of functions and procedure not case sensitive. case sensitive.
that are declared in the corresponding package declaration. The Q6. Write the syntax of a VHDL component
name of package body must be same as that of its corresponding declaration and by making use of component
package declaration name. Package body is optional and it is declaration write a VHDL program for a prime-
used only if any subprogram or deferred constants are declared number detector.
in its corresponding package declaration section. Ans: March-21, Set-1, Q3(b) M[7]
Syntax
Syntax of component declaration: Component-name is the
PACKAGE BODY packagename IS name of a previously defined entity that is to be used, or in-
Subprogram bodies stantiated, within the current architecture body. Each instance
Complete constant declarations must be named by a unique label. The port map introduces a
Subprogram declarations list that associates ports of the named entity with signals in the
current architecture. Before being instantiated in architecture’s
type and subtype declarations
definition, a component must be declared in a component dec-
file and alias declarations laration in architecture’s definition. A library of pre-specified
Use clauses components may be utilised in an architecture, or it may em-
END packagename; ploy components that were created as part of a design.

The syntax of component declaration is as follows:
A Component Declaration
component component-name
port (signal-names : mode signal-type;
signal-names : mode signal-type;
…
signal-names : mode signal-type);
end component;
Component statement (a concurrent statement)
label: component-name port map (signal1, signal2, …, signal_n);
label: component-name port map(port1=>signal1, port2=>signal2, …, port_n=>signal_n);
VHDL Program for a Prime Number Detector Using Component Declaration
The minimized circuit which is used to detect prime numbers is as shown in figure (1). For implementation of this circuit
we write the VHDL program using component declaration syntax as follows:
N3' N3' .N0
N3
N2
N'2 N3' .N'2 .N1
F
N1 ' '
N .N
2 1 0 . N
N1'
N'2 .N1'.N0
N0 N0
Figure (1): Minimized Circuit of Prime Number Detector

library IEEE;
use IEEE.std_logic 1164.all;
library unisim;
use unisim.vcomponents.a21;
entity prime is
port ( N: in STD _LOGIC VECTOR (3 downto 0);
E: out STE_LOGIC );
end prime;
architecture primel_arch of prime Is
signal N3_L, N2_L, Nl_L: STD LOGIC;
signal N3L_NO, N3L_N2L_N1, N2L_Nl_NO, N2 N1L_NO: STD LOGIC;
component INV port (I: in STD DOGIC; 0: out STD LOGIC); end component;
component AND2 port (I0, Il: in STD LOGIC; 0: out STD LOGIC): end component;
component AND3 port (I0, Ii, 12: in STD LOGIC; 0: out STD_LOGIC), end component;
component 0R4 port (10, Ii, 12, 13: in STD _LOGIC: 0: out STD LOGIC); end component;
begin
Ul: INV port map (N(3),N3_L);
INV port map (N(2),N2 L);
INV port map (N(1),Nl_L);
04: AND2 port map (N3_L,N(0), N3L_NO);
135: AND3 port map (N3_L,N2_L, N(1), N3L_N2L_N1);
AND3 port map (N2_L,N(1), N(0),N2L_Nl_NO);
AND3 port map (N(2), Nl_L, N(0), N2_1411,_NO);
U8: OR4 port map (N3L_NO, N3L_N2L_N1. N2L_Nl_NO, N2_N1L_NO, F);
end primel arch,
Q7. Explain the use of packages. Give the syntax A package body contains the hidden details of a package
and structure of a package in VHDL. like a function body.
Ans: There may be some declarations in the package body
also. The items declared here are local i.e., their scope
The definitions of different objects that can be used in is restricted within the package body and these items
other programs is stored in a file called package. cannot be made visible in other design units.
A package can be used in any number of other programs The syntax of a package body is as shown below.
and any number of times. The kinds of objects a package can package body package_name is
include are, package_body_item_declarations
(i) Sub-programs subprogram bodies
(ii) Types subprogram declarations
(iii) Subtypes
(iv) Constants
(v) Signals end package body package_name;
(vi) Variables 1.1.3 Data-Flow, Behavioral and Structural
(vii) Files Style of Modellings
(viii) Alias Q8. Explain in detail about the various abstraction
levels in VHDL. Model Paper-4, Q1(a)
(ix) Components
(or)
(x) Attributes
Write the basics in VHDL programming using
(xi) Disconnections structural and data flow modeling.
(xii) Use clauses. Oct./Nov.-20, Set-1, Q3(b) M[7]
A package can have two main parts. (Refer excluding Topic: Behavioural Description)
1. Package declaration (or)
Explain about dataflow design elements of
2. Package body.
VHDL. Oct./Nov.-18, Set-3, Q3(a) M[7]
1. Package Declaration: A package declaration consists of (Refer only Topic: Data Flow Description)
a set of objects declarations to be shared by many design
(or)
units.
Explain data-flow design elements of VHDL.
The objects in a package can be accessed by including Oct./Nov.-16, Set-2, Q3(b)
a “use” clause at the beginning of the program file.
(Refer only topic 2)
Example: Use IEEE.std_logic_1164.all; Ans:
“ieee” is the library which contains the package named There are three basic levels of abstraction (i.e.,
std_logic_1164. The suffix “all” is used to access all the representation or description) in VHDL namely,
definitions contained in the package. 1. Behavioural description
Example of Package Declaration 2. Data flow description
package packs1 is 3. Structural description.
type ARM is (ADD, SUB, MUL, DIV); 1. Behavioural Description
type MVL is (‘X’, ‘0’, ‘3’); Behavioral style of VHDL modelling maps the
relationship between inputs and outputs and uses sequential
Subtype ARM_MVL is ARM range ADD to MUL; statements to execute the code. It describes the behaviour of
component AND2 output with respect to variations in input irrespective of type of
components used. Since the sequential statements are used, the
port(A, B in MVL; C: out MVL)
order in which the statements are written is very important and
end component; hence, this style is also termed as algorithmic style of VHDL
end pack1; modelling. The main behavioral element is “process”.
Process
2. Package Body: A package body is an optional. Until a
package declaration contains subprogram declarations A set of collection of statements that are sequentially
or deferred constant declarations a package body is not executed with other concurrent statements is known as process.
necessary. Process is used to declare “variables” only.

Syntax Syntax
process (sensitivity list) signal_name <= expression;
declarations signal_name <= expression when boolean-expression
begin else expression;
sequential_statements; Concurrent signal-assignment statements are event-
end process; triggered, i.e., they are executed whenever there is an
event on a signal that appears in the expression.
The VHDL process has two states. They are,
(ii) Conditional Signal-assignment Statement: The con-
(i) Running state
ditional signal-assignment statement is used to select
(ii) Suspended state. various values for the target signal based on the specified
Sensitivity list decides whether the process is running (or) possible conditions.
or suspended. Syntax
Example: Consider the following Boolean expression and its signal_name < = expression when condition else;
logic circuit as,
(iii) Selected Signal-assignment Statement: The statement
F = BD + A C + CD is used to evaluate the given expression. It selects differ-
The logic circuit is shown below. ent values for a target signal based on the value of select
B
expression.
D Syntax
A F
F(X) signal_name < = expression when choices.
C
Example: Consider the following boolean expression
and its logic circuit as,
F = (r + s ).( q + s).(p + s )
Figure The logic circuit is shown below.
VHDL Code in Behavioural Style
r
library IEEE; s
use IEEE.STD_LOGIC_1164.all;
F(a)
entity function is
q
port(A, B, C, D: in STD_LOGIC; F : out STD_LOGIC);
end function;
architecture behaviour of function is, p
begin Figure: VHDL Code in Data Flow Style
process(A, B, C, D) library IEEE;
begin use IEEE.STD_LOGIC_1164.all;
F <= (B AND D) OR (NOT A AND C) OR entity logic_function is
(C AND NOT D);
port(p, q, r, s: in STD_LOGIC; F: out STD_LOGIC);
end process;
end logic_function;
end behaviour;
architecture dataflow of logic_function is
2. Data Flow Description
begin
Data flow style of VHDL modeling is the process of
representing a circuit in terms of flow of data and the elements F <= (r OR NOT s) AND(NOT q OR s) AND(p OR NOT s);
used for data flow design are known as data flow design end dataflow;
elements. 3. Structural Description
Concurrent statements provide the details of a circuit in Structural style of VHDL modeling is simple and
terms of the flow of data and operations on it. easy method of coding that represents the circuit in terms of
(i) Concurrent signal-assignment statement interconnected components. However, the designer must be
(ii) Conditional signal-assignment statement familiar or have complete knowledge about the circuit which
(iii) Selected signal-assignment statement. is to be designed and its interconnected components. In this
model, the architecture body comprises of two parts. They are,
(i) Concurrent Signal-assignment Statement: A concur-
rent signal-assignment statement is used to assign a value (i) Component declaration
to a signal in an architecture body. (ii) Component instantiation.
(i) Component Declaration: Component declaration in 2. Composite types
architecture section is same as entity declaration of entity A composite type includes a group of data elements.
section wherein, every individual component is declared This type is divided into two types,
with its unique name_identifier, its number and type of
(i) Array type
input and output ports. This done in the declarative part
of architecture body, here the keyword COMPONENT (ii) Record type
along with name of a component is used. (i) Array type
(ii) Component Instantiation: Component instantiation It is formed by grouping data elements of similar type.
is the next part of architecture body wherein all the Example
declared components are instantiated. In other words, For Array type declaration
component instantiation is the mapping among the type address_word is array (0 to 63) of bit;
actual and formal ports of entity and components. Here,
type data_word is array (7 down to 0) of STD_
the PORT MAP statements are used in the executable
section of architecture body. ULOGIC;
For object declarations
Q9. What is behavioral modeling?
variable ROM_ADDR : ROM;
Ans:
signal ADDRESS_BUS : ADDRESS_WORD;
The most significant style employed by industries (ii) Record Type
to enable the design of huge number of chips is known as
behavioral It is formed by grouping data elements of similar or
different types.
modeling.
Example
The various features of behavioral modeling are, For record type declaration
1. Behavioral modeling analyzes the functionality of a TYPE pin-type is range 0 to 10;
design.
TYPE module is
2. It describes the input-output model of a logic unit. record
3. It conceals the information about its physical size : integer range 20 to 200;
implementation and low-level internal architecture. critical_dly : time
1.1.4 Data Types, Data Objects, Operators and no_inputs : pin_type;
Identifiers no_outputs : pin_type;
Q10. Explain various data types available in VHDL. end record;
March-21, Set-4, Q3(b) M[7]
Assigning data elements to record object using
aggregates
(or)
Example
Explain various data types supported by VHDL Variable nand_comp : module;
and give necessary examples. Model Paper-1, Q1(b) nand_comp : = (50,20 ns, 3,2)
Ans: 3. Access Types
The various data types supported by VHDL are as follows, The data element that belong to access types act as
pointers to dynamically created objects.
1. Scalar types
Examples
2. Composite types
For array declaration
3. Access types (i) type ptr is access MODULE;
4. File types. (ii) type FIFO is array (0 to 63, 0 to 7) of BIT;
1. Scalar Types (iii) type FIFO_ptr is access FIFO;
The data elements of scalar types are represented in a 4. File Types
sequential manner. These are divided into four types File data type indicates the files that are present in host
namely, environment.
Syntax
(i) Enumeration
Type file_type_name is file of type_name;
(ii) Integer
Examples
(iii) Physical (i) type vectors is file of BIT_VECTOR;
(iv) Floating point (ii) type names is file of STRING;

Q11. What are the different data objects supported Examples of signal declaration are,
by VHDL? Explain scalar types with suitable signal CLOCK:BIT;
examples.
signal DATA_BUS:BIT_VECTOR (0 to 7);
(Model Paper-2, Q2(a) | Oct./Nov.-16, Set-1, Q2(a))
4. File
(or) File class object contains a sequence of values. Values
Explain the various scalar data types supported can be read or written to the file using the read and write
by VHDL with suitable examples. procedures respectively. Syntax of a file declaration is
Oct./Nov.-19, Set-1, Q3(b) M[7] file file_names:file_type_name[[open mode] is string_
(Refer only Topic: Scalar Types) expression];
(or) Example
What is the use of library clause and use clause? ---File type declaration
Give examples. Oct./Nov.-19, Set-3, Q3(b) M[7] type STD_LOGIC_FILE is file of STD_LOG-IC_
(Refer only Topic: Data Objects) VECTOR;
type BIT_FILE is file of BIT_VECTOR;
(or)
---file declarations
Explain about data objects in VHDL.
Nov.-15, Set-1, Q2(a) file VECTORS:BIT_FILE IS “Usr/home/james/add.
vec”;
(Refer only Topic: Data Objects)
file PAT1, PAT2:STD_LOGIC_FILE;
Ans:
Scalar Types
Data Objects
There are four different kinds of scalar types. These are,
Data object carries a value of a particular type. It can be
produced with the help of an object declaration. 1. Enumeration
2. Integer
Example
3. Physical
Variable COUNT : INTEGER;
4. Floating point.
Data object called COUNT is created, which holds
integer values. The object COUNT is also declared to be of Integer types, floating point types and physical types are
variable class. classified as numeric types. Enumeration and integer
types are called discrete types because these types have
Every data object belongs to one of the following four
discrete values associated with them.
classes.
1. Enumeration Types
1. Constant
An enumeration type declaration defines a type that has
A constant class object can hold a single value of a a set of user-defined values consisting of identifiers and
given type. This value is assigned to the constant before character literals.
simulation starts and the value cannot be changed during
the simulation process. Example
Example of constant declaration is, type MVL (‘U’, ‘0’, ‘1’, ‘Z’);
type MICRO_OP (LOAD, STORE, ADD, SUB, MUL,
constant RISE_TIME:TIME:= 10 ns;
DIV);
constant BUS_WIDTH:INTEGER:= 8;
subtype ARITH_OP is MICRO_OP range ADD to DIV
2. Variable
MVL is an enumeration type that has the set of ordered
A variable class object can hold a single value of a given values, ‘U’, ‘0’, ‘1’, and ‘Z’. ARITH_OP is a subtype
type. Different values can be assigned to the variable at of the base type MICRO_OP and has a range constraint
different times using a variable assignment statement. specified to be from ADD to DIV. The values ADD, SUB,
Examples of variable declaration are, MUL and DIV belong to the subtype ARITH_OP.
variable CTRL_STATUS : BIT_VECTOR (10 downto 0); 2. Integer Types
variable SUM : INTEGER range 0 to 100:= 10; An integer type defines a type whose set of values fall
with in a specified integer range.
variable FOUND, DONE : Boolean;
Example
3. Signal
type INDEX is range 0 to 15;
The signal class object carries a list of values, that include
current values and set of possible future values, which are type WORD_LENGTH is range 31 downto 0;
to appear on the signal. In this case, signal assignment subtype DATA_WORD is WORD_LENGTH range 15
statement is used to allot future values. downto 0;
type MY_WORD is range 4 to 6; Units
INDEX is an integer type having the values from 0 to nA; --- (base unit) nano-ampere
15. DATA_WORD is a subtype of WORD_LENGTH µA: = 100 nA; --- micro ampere
that includes the integer values ranging from 15 through µA: = 1000 µA; --- milli-ampere
0. The position of each value of an integer type is the
value itself. Amp: = 1000 mA; --- ampere
end units;
Values belonging to an integer type are called Integer
literals. Subtype Filter_CURRENT is CURRENT range 10 µA
to 5 mA;
Example
CURRENT is a physical quantity that contains values
56349 6E2 0 98 – 71 – 28 from 0 nA to 109 nA. Nano-ampere is the base unit and all others
INTEGER is the only pre-defined integer type of the are derived units. The position number of value is the number
language and it must cover the range from –(231 – 1) to of base units represented by that value.
+ (231 – 1). Values of a physical type are called physical literals. This
3. Floating Point Types can be written either as integer or floating point literal followed
by the unit nano for example, “10 nA” is a physical literal.
It has a set of values in a given range of real numbers.
Examples of floating point declarations are, The only predefined physical type is TIME, and range of
its base values must at least be –(231 – 1) to (231 – 1). There is
type ITL_VOLTAGE is range –5.5 to –1.4; a predefined physical subtype, DELAY_LENGTH, represents
type REAL_DATA is range 0.0 to 31.9; non-negative time values. The type TIME and subtype DELAY_
Example of an object declaration is LENGTH declarations appear in package STANDARD.
variable LENGTH : REAL_DATA range 0.0 to 15.9; Q12. Explain various types of operators used in VHDL.
Ans: (Model Paper-2, Q1(b) | March-21, Set-3, Q3(b) M[7])
....
The different operators present in the VHDL are,
variable L1, L2, L3 : REAL_DATA range 0.0 to 15.9;
1. Logical operators
LENGTH is a variable object of type REAL_DATA takes
2. Relational operators
real values in the range 0.0 through 15.9 only. The range
constraint was specified in the variable declaration itself. 3. Arithmetic operators
4. Concatenation operators
The range bounds specified in the floating point
type declaration must be constants or locally static 5. Shift and rotate operators.
expressions. 1. Logical Operators
Floating point literals are values of a floating point type. The logical operators in the VHDL programming are,
Example (a) AND: ‘AND’ operator is used to perform logical
AND operation between two operands.
16.260.0 0.002 3 – 1.4 – 2
Example: C = A AND B;
Floating point literals differ from integer literals by the
(b) OR: ‘OR’ operator is used to perform logical ‘OR’
character dot (.).
operation (i.e., addition) between two operands.
Floating point literals can also be expressed in an
Example: C = A OR B;
exponential form. The exponent represents a power of
10 and exponent value must be integer. (c) NAND: It is used to perform logical NAND
operation between two operands.
Example
Example: C = A NAND B;
62.3E – 2 5.0E+2
(d) NOR: It is used to perform logical NOR (i.e., OR
The only pre-defined floating point type is REAL. It must followed by NOT) between two operands.
at least cover the range −1.0E38 to +1.0E38, and should Example: C = A NOR B;
provide at least six decimal digits of precision.
(e) XOR: It is used to perform logical XOR operation
4. Physical Types between two operands.
A physical type contains values that represent Example: C = A XOR B;
measurement of physical quantity like time, length, (f) XNOR: It is used to perform logical XNOR
voltage or current. Its values are expressed as integer operation between two operands.
multiples of a base unit.
Example: C = A XNOR B;
Example of a physical type declaration. (g) NOT: It is used to logically invert the data.
type CURRENT is range 0 to 1E9 Example: NOT A, NOT B etc.

2. Relational Operators (b) Shift Right Logical: It is used for logical right shift.
Relational operators are used in VHDL to compare the Example: B = A SRL 1;
expressions. The result of the comparison is either TRUE
or FALSE. (c) Shift Left Arithmetic: It is used for arithmetic left shift.
The relational operators available in the VHDL are, Example: B = A SLA 1;
(a) Equality (=): It is used to check the equalance of (d) Shift Right Arithmetic: It is used for arithmetic right
operands (or) to specify the data to the operands. shift.
Example: A = 110, A = B etc. Example: B = A SRA 1;
B = 101. Rotate operators are used to shift bits from one end to
(b) Inequality (/=): It is used to specify the inequalance another end
of the operands. (i) Rotate Left: It is used for left rotation.
Example: B/= ‘010’.
Example: B = A ROL 2;
(c) Greater than: It is used to assign the greater values
(ii) Rotate Right: It is used for right rotation.
(or) to check the greater values.
Example: A > B. Example: B = A ROR 2;
(d) Less than (<): It is used to compare whether it is Q13. Discuss identifiers in VHDL.
less (or) not. Ans:
Example: A < B.
An identifier refers to the name given to the entities such
(e) Greater than or Equal to: as data objects, data types, operators etc.
Example: A > = B. VHDL supports two types of identifiers. They are,
C > = C. etc. 1. Basic identifiers
(f) Less than or Equal to: 2. Extended identifiers
Example: A < = B 1. Basic Identifiers
B < = C etc.
A basic identifier comprises a series of one or more
3. Arithmetic Operators character. The character can be an upper case letter, a lower
Arithmetic operators are used to do arithmetic operations case
like addition, subtraction, multiplication and division. letter or a special character i.e., “underscore”.
Addition + Example: C = A + B Rules For Basic Identifiers
Subtraction – Example: C = A – B
(i) The character in basic identifier must begin with a letter
Multiplication * Example: C = A * B. but, it should not end with an underscore.
Division / Example: C = A/B. (ii) The character can contain both upper case letter and
4. Concatenation Operators lower case letter.
The concatenation operator is used perform concatenate (iii) They must not contain two underscore characters
two or more vectors to create a large vector. together.
Example: D = A & B. Examples
C = D & A etc. (i) P3c4
5. Shift and Rotate Operators (ii) Select signal
The shift operators are used to shift the one bit into 2. Extended Identifier
another bit. There are logical and arithmetic shifts are
available in VHDL. They are, An extended identifier comprises a series of characters
enclosed between two back slashes. The characters can be
(a) Shift Left Logical (SLL): It is used for logical left shift.
letters, digits and special characters such as ., !, @, ‘ and $. It
Example: B = A SLL 1; is case sensitive.
Example
\ TEST \ -- Differs from the basic identifier TEST.
\ – 25 \
In identifiers, comments can be written anywhere within a description. The different symbols used for describing comments
are as follows.
Symbol Description
-- It represents the start of comment line.
; It represents the end of comment line
, It represents the continuation of comment onto next line.
1.1.5 Generic, Process, If, Case & Loop Statements

Q14. Write short notes on generic statement.
Ans:
Generics
A generic mechanism is a general means for passing data to an entity. The information given to the entity can be of any
type supported by VHDL.
Why would a designer wish to send information to an entity? The most evident, and usually the most used, piece of
information that is passed to an entity is the time it takes for the rising and falling delays of the device that is being modelled.
Generics can also be used to send any user-defined data kinds, such as load capacitance, resistance, and so on. Further, Generics
can be used to pass in synthesis parameters such as datapath width, signal widths, and so on.
The information supplied to an entity is instance-specific. In other words, the data value is specific to the instance to which
the data is being delivered. So, the designer can give different values to the same thing in his or her project at different times.
The data that is provided at an instance is always static. After the model is developed (connected to the simulator), the data
remains constant during the simulation. During a simulation run, information cannot be allocated to generics. The information
included in generics supplied into a device instance or a module can be utilized to change the simulation results, but the results
cannot change the generics.
An AND gate entity with three generics is shown below.
ENTITY and2 IS
GENERIC (rise,fall:TIME;Load:INTEGER);
PORT (a, b : IN BIT;
c : OUT BIT);
END and2;
This entity lets the designer specify the device’s rise and fall delays, as well as the amount of loading it has on its output.
When the model has this information, it can figure out how to model the AND gate in the design correctly.
Q15. Define sequential statements and list its types.
Ans:
The statements which are declared inside the process statements are termed as sequential statements. These are usually
employed with behavioral style.

The different types of sequential statements are, Example
1. Process statement Signal A, B : Integer
2. Variable assignment statement ........
Process (N)
3. Signal assignment statement
Variable N1, N2: STD-LOGIC ;
4. Wait statement
begin
5. If statement
N1 : = not (A) and not (B) ;
6. Case statement N2 : = not (A) nand not (B) ;
7. Loop statement end process ;
8. Null statement In the above example, N is the signal in the sensitivity
9. Exit statement list. Whenever an event occurs on the signal N, the sequential
statements inside the process statement executes.
10. Next statement
Q17. Explain about variable assignment statement,
11. Assertion statement signal assignment statement, wait statement.
12. Report statement Ans: (Model Paper-3, Q1(b) | Oct./Nov.-18, Set-1, Q4(b) M[7])
13. Produce call statement Variable Assignment

A variable is a data object that takes any single value
14. Return statement.
of a specific type. It can take various values at different time
Q16. With suitable example, explain PROCESS instances, but only a single value and that too only of the type
statement in VHDL. specified during its declaration. Variable assignment statement
Oct./Nov.-19, Set-1, Q4(a) M[7]
can be declared within a process statement.
Syntax
(or)
VARIABLE variable_name : variable type : = initial
What is a process statement? Give its syntax value;
and explain with an example.
Example
Ans: Process (B)
Process statement is the one which has sequential Variable Task_on_B: INTEGER: = –3;
statements defining the behavioral of a small portion of the
begin
design.
Task_on_B: = Task_on_B + 3;
Syntax
End process;
[Process-label :] process [(sensitivity-list)] [is] [ process-
item-declarations] Signal Assignment
A signal is a data object that can take a list of values at
begin
a time of a specified type. Signal assignment statement can be
sequential-statement ; declared inside or outside of a process statement.
...... Syntax
...... SIGNAL signal_name : type_name;

Example
end process [process-label];
Square_wave <= Squarewave + “0101”
The sensitivity list contains the list of signals for which
the process is sensitive i.e., if any event occurs on the signals, T < = T XOR D after 13 ns;
then the process gets executed in a sequential manner. After Y < = (a0 AND a1) or (b0 AND b1) after 5 ns;
the execution of all the sequential statements in the process, Wait Assignment
it waits for the occurrence of the event on the sensitivity list
signals. Process-item-declarations consists of various variable Wait statement is used to stop the execution of a process.
declarations which are local to the process in which it is defined. This statement is available in three forms. They are,
The sequential statements can be variable assignment statement, 1. Wait on
signal-assignment-statement, wait, if, case, loop, null, exit, next, 2. Wait until
assertion, report, procedure-call and return statements. These
statements may have or may not have or may not have a label. 3. Wait for
1. Wait On Example
The syntax is , Process
Wait on sensitivity-list ; begin
When the wait statement executes, it stops the execution x < = input ;
of the process and resumes its execution when any event occurs
on the signals in the sensitivity list. If the wait statement occurs wait for 10 ns ;
at the end of the process, then the process gets executed from y<=x;
the beginning. end process ;
Example
Initially, when the wait statement executes, the process
(i) Process stops its execution for 10 ns. After 10 ns, the execution will be
Variable X, Y, Z : INTEGER resumed.
begin Effects of Wait For 0 ns
X : = A and B ; Wait for ‘0’ ns indicates to wait the process for one delta
Y : A nand C ; cycle.
wait on A,B,C Example
Z : = B or C ; Pro`cess
end process ; begin
In the above example, when the wait statement is wait on input ;
executed, it stops the execution of the remaining statements in
x < = input ;
the process. Whenever an event occurs on A, B or C then the
remaining statements in process starts their execution. wait for ‘0’ ns ;
(ii) Wait Until y<=x;
The syntax is, end process
Wait until boolean-expression ; The above example is illustrated in the following
When the wait statement is executed, it stops the figure.
execution of the process statements. It evaluates the boolean
expression value and if it is true, then resumes the execution of
the process or else it waits until the expression becomes true.
Example
Process input
variable X, Y : INTEGER
begin
X : = A + 10 ;
A:=A+1; x
Wait until A = 15 ;
Y : = B +10 ; Wait for
‘0’ ns (10 + D)
end process
In the above example, when the wait statement is
executed, it stops the execution of the remaining statements. y
It checks for the expression and if it is true, then it resumes
the execution of the remaining statements or else it stops the 10 10 + D 10 + 2D
execution.
(iii) Wait For Figure
The syntax is, Q18. List out the differences between variable
assignment statement and signal assignment
Wait for time-expression ;
statement with example.
When the wait statement is executed, it stops the
execution of the remaining statements in the process. It waits Ans: Oct./Nov.-19, Set-2, Q4(b) M[7]
for the time specified in the time-expression and resumes its The differences between variable and signal assignment
execution after the time gets elapsed. statements are tabulated below.

Variable Assignment Statement Signal Assignment Statement

1. A variable is a data object that takes any single value 1. A signal is a data object that can take a list of values at
of a specific type. a time of a specified type.
2. Variable assignment statement can be declared within 2. Signal assignment statement can be declared inside or
a process statement. outside of a process statement.
3. It uses : = operator in the syntax. 3. It uses <= operator in the syntax.
4. Variables are local to a process or subprogram and as- 4. Signals must be global in a process or sub program and
signment takes place immediately. assignment takes place at the end of a process.
Example: For answer refer Unit-1, Q17, Topic: Example: For answer refer Unit-1, Q17, Topic: Signal
Variable Assignment (Refer only Example). Assignment (Refer only Example).
Q19. Explain IF statement in VHDL with example. Give the comparisons between CASE and IF statement.
Oct./Nov.-19, Set-3, Q4(b) M[7]
(or)
Explain with an example the syntax and the function of if statement.
Ans:
IF statement
The selection of the if statement is based on the boolean evaluation of the conditions. If all the conditions are not available
there is an absence of else results in implicit memory.
Syntax
if boolean_expression then sequential_statement
end if;
if boolean_expression then sequential_statement
else sequential statement;
end if;
if boolean _expression then sequential_statement
else boolean_expression then sequential;
end if;
Example
Process(N)
Variable N1 : INTEGER;
begin
N1 : = Conv_INTEGER (N) ;
if N1 = 1 or N1 = 2 then F < = ‘1’1 ;
elseif N1 = 3 or N1 = 5 or N1 = 7 or N1 = 11 or N1 = 13 then F < = ‘1’ ;
else F < = ‘0’
end if;
end process;
Comparison
The comparison between if and case statement in VHDL is that, selection of if statement depends on the Boolean evaluation
of the conditions whereas, the selection of case statement depends on the Boolean expression.
Q20. Explain the following terms in Behavioral (ii) Null statement
Modeling : For answer refer Unit-1, Q21 Topic: Null statement
(i) Case statement, (iii) Loop statement
(ii) Null statement Loop statements allow the user to execute a sequence of
(iii) Loop statement. statements several times.
(Model Paper-4, Q1(b) | March-21, Set-1, Q4(a) M[7]) In VHDL, there are three types of loop statements. They
are,
(or)
1. For loop
Explain the structure of various LOOP statements
2. While loop
in VHDL with examples. March-21, Set-4, Q3(a) M[7]
3. Simple loop.
(Refer only Loop statement)
1. For Loop
(or)
The statements are repeated number of times specified
Explain CASE statement in VHDL with example. by a count in the ‘For’ loop.
Oct./Nov.-19, Set-2, Q4(a) M[7]
Syntax
(Refer only case statement) [label] for counter in range loop
(or) statements sequence
Explain the structure of various LOOP statements end loop[label];
in VHDL with examples. Oct./Nov.-18, Set-1, Q3(a) M[7] Example
(Refer only Loop statement) To compute squares of integer value between 1 and 10.
Ans: for i in 1 to 10 loop
(i) Case statement Square (i) < = i × i;
‘Case statement’ is a simple construct used to execute end loop;
a single statement from many alternatives, the selection of the
Iteration of count is of type integer by default. Initially,
statement depends on the expression.
i value is 1, then after each iteration i is incremented by 1 and
Syntax continues till it reaches 10 and gets terminated from the loop.
Case expression is 2. While Loop
when choices = > sequential_statements In while loop, statements in the loop body are repeated
. until a condition specified become false.
Syntax :
.
[label] while condition loop
.
statement sequence
when others = > sequential_statements
end loop[label];
end case;
In this, the condition is tested before each execution of
In the above syntax, the expression should be a discrete the loop. If condition is true the sequence of statements executed
value or of 1-D array type. The choice can be a single value or with in loop. If condition is false loop terminates.
multiple values separated by a vertical bar ‘‘’. The “when others”
Example
clause may be optional and it must be at the last.
To count the rising edges of clock signal while level
Example
signal is 1.
Process(N)
Process
begin variable count: integer = 0;
Case CON_INTEGER is begin
when 1 = > F < = ‘1’; wait until clock = ‘1’;
when 2 = > F < = ‘1’; while level = ‘1’ loop
when 3/5/7/11/13 = > F < = ‘1’; count: = Count + 1;
when others = > F < = ‘0’; wait until clock = ‘0’;
end case; end loop;
end process; end process

3. Simple Loop Example
Simple loop statements specifies an indefinite repetition result : = 0 ; i : = 1 ;
of some statements. L2 : loop
Syntax : i = i + 1;
[label] loop
result : = result + i ;
statement sequence
if result > 5 then
end loop[label]
exit 12 ;
The statement has optional label that may be used to
end if
identify the statement. The only possibility to end the execution
is to use the ‘Exit’ statement. end loop L2 ;
Q21. Explain IF, exit, next, assertion, report and null Next Statement
statements. Next statement is one of the loop control statements
(or) which controls the execution of the loops. When the control
With examples explain the sequential assignment encounters a next statement, it stops the execution of current
statements. Oct./Nov.-18, Set-3, Q4(a) M[7]
iteration and goes to the first statement of the next iteration
omitting the next statements.
(or)
Syntax
Design a full subtractor with logic gates
and write VHDL data flow program for the next [loop-label] [when condition]
implementation of the above subtractor. If the when condition is true, then it stops the execution
March-21, Set-2, Q4(b) M[7] of the loop-label and goes to the next iteration. Next
statement
(Refer only Topic: Assertion statement)
syntax is similar to that of exit statement except the keyword.
(or)
Example
Explain Null, Next, Assertion, and Wait
statements. Oct./Nov.-20, Set-1, Q4(b) M[7] For i in 8 downto 4 loop
(Refer excluding Topics: IF statement, Exit statement, if result < final–result then
Report statement) result : = result + 1;
(or) elseif result = final-result then
Explain the following statements with examples: next ;
(i) IF statement else
(ii) EXIT statement null ;
(iii) Assert statement
end if ;
(iv) Report statement. Oct./Nov.-19, Set-4, Q4(a) M[7]
j=j+1;
(Refer excluding Topics: Next statement and null
end loop ;
statement)
In the above example, when the control encounters next
Ans:
statement, the control jumps to the end of the loop without
IF Statement executing remaining statements i.e., j : = j + 1 and starts the
For answer refer Unit-1 Q19. execution of next iteration.
Wait Statement Assertion Statement
For answer refer Unit-1 Q17, Topic: Wait Statement. A statement that is employed to model the constraints
Exit Statement of an entity is termed as assertion statement’. It checks the
valueof boolean expression and if it generates an unexpected
Exit statement is used inside the loop to terminate loop
value, then it displays the entity name, assigned string, current
statements unconditionally. It any loop encounters an exit
simulation time and severity level on simulator console. The
statement, it terminates immediately and the control passes to
predefined severity levels include note, warning, error and
the next statement.
failure depending on the severity intensity.
Syntax
Syntax
exit [ loop-label] [when condition];
Assert boolean_expression
The above, statement exits the loop named label. if the
when condition becomes true. The loop-label can be optional, if [report string_expression]
it is not defined then the control terminates the innermost loop. [severity expression] ;
Example Syntax
entity DFF is report string_expression
Port (D,clk : in BIT ; Q, NOTQ : out BIT); [severity expression];
end DFF Example
Architecture examine-Times of DFF is if CLR = ‘z’ then
Constant HLD-TIME :TIME = 10 ns ;
report “Signal CLR possess high impedance”;
Constants SETUP-TIME :TIME = 5 ns ;
Null Statement
begin
A null statement specifies that no action should be
process (D, CLK) performed and proceed to the next statement. It is mostly
Variable previousevent on D, previous event used in ‘if’
on CLK : TIME;
and ‘case’ statements to omit some conditions.
begin
Example
....examine for hold time :
Case operation is,
if D’ EVENT then
When “00” = > output : = A or B
asset Now = 0ns or
When “01” = > output : = A and B
(Now-previous event on CLK) > = HLD_TIME
report “HLD time very small!” When “10” = > output : = A nand B
severity FAILURE ; When other = > null ;
prevoiusevent on D : = Now ; end case
end if ; The above example is limited to perform only some of
...examine for setup time : the logical operations while others are blocked.
if CLK = 1 and CLK’EVENT then 1.1.6 VHDL Libraries
assert NOW = 0 ns or (Now_previousevent on D Q22. Explain about the following,
> = SETUP_TIME report “Setup time every short !”
Severity FAILURE
(ii) Libraries with syntax.
previousevent on CLK : = Now ;
Ans: Oct./Nov.-18, Set-4, Q3(a) M[7]
end if ;
... Behaviour of D flipflop : 1. Packages
if CLK = ‘1’ and CLK’ EVENT then For answer refer Unit-1, Q7.
Q<=D; 2. Libraries
NOTQ < = not D ; The VHDL compiler stores all the information related
end if ; to the design and utilities in a location known as library. It
stores the result of a VHDL model after analyzing it for no
end process ; errors. The primary use of the library is to promote the sharing
end examine-TIMES ; of previously compiled designs for future VHDL descriptions
In the above example, ‘EVENT is a predefined attribute and in subsequent simulation applications.
and its value will be true if any event occurs on it at times; when A library consists of following four segments,
the value of attributes are evaluated. ‘Now’ is also a predefined
(i) Package (shared declarations)
function whose function is to determine the current simulation
time. The sensitivity list of process is D and CLK. So, whenever (ii) Entity (shared designs)
an event occurs on ‘D’ or on ‘CLK’, the process starts its (iii) Architecture (shared implementations of design)
execution. If the event is occurred on D, then the assertion is
examined and determines whether the differences between the (iv) Configuration (shared versions of design)
current simulation time and the last simulation time are higher Basically, there are two classes of VHDL libraries
than the hold-time. If it is less, then a message is generated as namely, work library and resource libraries.
failure and the severity level will be returned to simulator.  Work Library: This library is the default working
Report Statement library which stores the results of current analysis.
A statement that is employed to display a message is  Resource Libraries: These libraries are used only for
termed as report statement. Report statement is same as assertion referencing during simulation and analysis (i.e., these
statement but there is no assertion check is required. cannot be written or edited).

(a) STD Library: It consists of basic definitions and Example
types of VHDL language.  STD_LOGIC_VECTOR is a package stored in the design
(b) IEEE Library: It consists of standard types library IEEE and STD_LOGIC is a type to be declared
and utilities for text, arithmetic and complex in that package, so, this can be written as,
mathematical computations. Library IEEE;
Example: Use ieee.std_logic_1164.all; USE IEEE.STD_LOGIC_VECTOR.STD_LOGIC;
Where,  In order to make all the items of package STD_LOGIC_
VECTOR to be visible, the command is written as,
ieee → library name
USE IEEE.STD_LOGIC_VECTOR.All.
std_logic_1164 → file name
Q24. Discuss the binding. Discuss the binding
all → use all definitions of the file. between entity and components.
Q23. What is the use of library clause and use clause? (Model Paper-1, Q2(a) | Oct./Nov.-18, Set-2, Q3(a) M[7])
Give examples. (or)

Ans: Oct./Nov.-19, Set-3, Q3(b) M[7] What are the functions to be formed by ALU?
LIBRARY CLAUSE March-21, Set-1, Q1(b) M[7]
In VHDL, library clause is employed to make the library (Refer only Topic: Binding between Entity and
name or logical name of designed libraries visible. Library Component)
clause never make design units visible. Ans:
SYNTAX Binding
Library list_of_logical_library_names; Bindings in VHDL can be defined as the process of
associating a design entity and an architecture to a component
Example
instance. Each component must be bounded inorder to complete
1. Library IEEE a design for simulation or synthesis purposes.
2. Library NMOS Binding of components can be indicated either by default
or by explicit representation. Basically, there are three possible
3. Library PMOS
ways for accomplishing component binding in VHDL. They are,
USE Clause  Default binding – Solving component configuration
In VHDL, USE clause is employed to import all the default.
declarations falling under the package. USE clause possess two  Configuration specification – Binding information is
forms. They are, specified in the architecture itself.
1. First Form  Configuration declaration – Binding information is
specified separately from the architecture.
USE library_name.primary unit_name;
Binding between Entity and Component
This form enables the specified primary unit name from
the specified design library to be referenced in the design. The binding between the entity and component depends
upon their names. If the names of entity and component are
Example same, then the component is automatically bounded to the entity.
Library ECL; Example
USE ECL.AND; Entity andgate is
Configuration....is port(I1, I2 : in std_logic;
... USE entity AND (.....); 01 : out std_logic);

end andgate.
END;
architecture gate of andgate is
(ii) Second Form
begin
USE library_name.primary_unit_name.item;
01 <= I1 and I2;
This form is employed to refer the items within a design
end gate;
unit that are visible in the primary unit. A keyword “all” is used
to make the items visible in primary unit. entity ent is
port (A, B : in std_logic;
sum, cout : out std_logic);
end ent;
architecture arch of ent is
component andgate
---------
---------
end component;
begin
---------
end arch;
Here entity name and component name both are and gate. So, these entity and component are bounded automatically.
Q25. List out the differences between VHDL functions and procedures with example.
Oct./Nov.-19, Set-4, Q3(b) M[7]
(or)
Explain the difference between function and procedure supported by VHDL. Give the necessary examples.
Oct./Nov.-16, Set-2, Q3(a)
(or)
What is subprogram? Give the syntax of VHDL functions. Oct./Nov.-19, Set-4, Q3(a) M[7]
(Refer excluding table)

(or)
Differentiate between functions and procedures in VHDL.
(Refer only differences)
Ans:
Generally, a subprogram is a group a sequential declarations and statements that can be called constantly from various
location in a VHDL description.
Types of Subprograms: In VHDL, there exists two types of subprograms. They are,
(i) Functions
(ii) Procedures
(i) Functions: In VHDL, functions consists of two parts namely, function declaration and function body.
Syntax
function name (parameter_list) return type;
function name: It is used for calling the function.
Example : function exam
parameter list: It is used for identifying the objects used in functions.
Example: signal signal_a : in BIT
return : It identifies the type of return value
Example: return BIT_indicates that the function can return either ‘0’ or ‘1’.
(ii) Procedures: In VHDL, procedures consists of two parts namely, procedure declaration and procedure body.
Syntax
procedure name (parameter_list);
procedure name : It is used for calling the procedure
Example: procedure result
parameter list: It is used for identifying the objects used in procedure
Example: (Signal a : in BIT)

The differences between functions and procedures are,
Functions Procedures
1. In functions, the values of parameters that are 1. In procedures, the values of parameters that are passed
passed remain constant. can be changed.
2. It consists of a return statement. 2. It may or may not have a return statement.
3. In function a single value is returned. 3. In procedures multiple output values are produced.
4. The values of objects passed in functions 4. The values of objects passed in procedures is badly
remains unaffected. affected
5. These are invoked by expression. 5. These are invoked by statements.
Q26. Design the logic circuit and write a structural style VHDL program for the following function.
F(A) = πp, q, r, s (1, 3, 4, 5, 6, 7, 9, 12, 13, 14).
Ans:
The given boolean function is,
F(A) = πp, q, r, s (1, 3, 4, 5, 6, 7, 9, 12, 13, 14)
The given function is in Product of Sum (POS) form and hence, it can also represented in Sum of Product (SOP) form as,
F(A) = Σp, q, r, s (missing terms in given pos form)
∴ F(A) = Σp, q, r, s (0, 2, 8, 10, 11, 15)
On applying Karnaugh map to above boolean expression, we get,
pq rs 00 01 11 10
00 1 1
0 1 3 2
qs
01
4 5 7 6
11 1 15
12 13 14
10 1 1 1
8 9 11 10
prs
Figure (1)
Thus, the simplified boolean expression is,
∴ F ( A) = q s + prs

Logic Circuit
The logic circuit for the above simplified boolean expression is shown in figure (2).
p q r s
s
qs
q
F(A) = q s + prs
prs
Figure (2)
VHDL Code in Structural Style Thus, the simplified boolean expression is,
The structural style of VHDL program for the simplified F(Q) = BD + B D = B  D
boolean expression i.e.,
Logic Circuit
F(A) = q s + prs is shown below.
The logic circuit for the above simplified boolean
library IEEE; expression is shown in figure (2),
use IEEE.STD_LOGIC_1164.all; A B C D
entity FunF is B
port(p, q, r, s: in STD_LOGIC; FA: out STD_LOGIC); BD
end FunF; F(Q) = B D + BD = B . D

D
BD
architecture FunF_arch of FunF is
signal F1, F2, sbar, qbar : STD_LOGIC;
component NOT1 Figure (2)
port(m : in STD_LOGIC; mbar : out STD_LOGIC); VHDL Code in Structural Style
end component; The structural style of VHDL program for the simplified
component AND1 boolean expression i.e.,
port(a, b : in STD_LOGIC; p1 : out STD_LOGIC); F(Q) = B D + BD is shown below.
end component; library IEEE;
component AND2 use IEEE.STD_LOGIC_1164.all;
port(a, b, c: in STD_LOGIC; p2 : out STD_LOGIC); entity FunF is
end component; port(B, D : in STD_LOGIC; F(Q) : out STD_LOGIC);
component OR1 end entity;
port(x, y: in STD_LOGIC; Z : out STD_LOGIC); architecture FunF_arch of FunF is
end component; signal F1, F2, Bbar, Dbar : STD_LOGIC;
begin component NOT1
X1 : NOT1 port map(q, qbar); port(p : in STD_LOGIC; pbar : out STD_LOGIC);
X2 : NOT1 port map(s, sbar); end component;
X3 : AND1 port map(qbar, sbar, F1); component AND1
X4 : AND2 port map(p, r, s, F2); port(x, y : in STD_LOGIC; FA : out STD_LOGIC);
X5 : OR1 port map(F1, F2, FA); end component;
end FunF_arch; component OR1
Q27. Design the logic circuit and write a structural port(r, t : in STD_LOGIC ; F0 : out STD_LOGIC);
style VHDL program for the following function. end component;
F(Q) = ∑ (0, 2, 5, 7, 8, 10, 13, 15) + d(11)

A,B,C,D
begin
X1 : NOT1 port map(B, Bbar);
Ans: Model Paper-3, Q2(a) X2 : NOT1 port map(D, Dbar);
The given boolean expression is, X3 : AND1 port map(Bbar, Dbar, F1);
X4 : AND1 port map(B, D, F2);
F(Q) = ∑ (0, 2, 5, 7, 8, 10, 13, 15) + d (11)
A,B,C,D X5 : OR1 port map(F1, F2, F(Q));
On applying Karnaugh map to above boolean expression, end FunF_arch;
we get, Q28. Design the logic circuit and write the data-flow
CD 00 11 10 style of VHDL program for the following function,
AB 01
00 1 1
BD
F(P) = πA,B,C,D (1, 7, 9, 13, 15).
0 1 3 2
1 5 1 7
Ans:
01 4 6 BD
11 1 1
12 13 15 14 F(P) = πA,B,C,D (1, 7, 9, 13, 15)
10 1
8 9
×
11
1
10
The given function is in Product of Sums (POS) form
and hence, it can also be represented in Sum of Products (SOP)
Figure (1) form as,

F(P) = Σ A, B ,C , D (Missing terms in given product of sum form)
F(P) = ΣA,B,C,D (0, 2, 3, 4, 5, 6, 8, 10, 11, 12, 14)
The above boolean function can be simplified using 4-variable K-map as,
CD
AB 00 01 11 10 BC
0 1 3 2
00 1 1 1
4 5 7 6
01 1 1 1
ABC
12 13 15 14
11 1 1
8 9 11 10
10 1 1 1
D
Thus. the simplified boolean expression is,

∴ F(P) = A BC + B C + D
Logic Circuit: The logic circuit for the above simplified boolean expression is shown in figure below,
A B C D
F(P) = A BC + BC + D
Figure
VHDL Code in Data Flow Style
The data flow style of VHDL program for the simplified boolean function is mentioned below,
library IEEE;
use IEEE . STD_LOGIC_1164.all;
entity function is
port (A, B, C, D : in STD_LOGIC;
F : out STD_LOGIC);
end function;
architecture function_1 of function is
begin
F < = ((NOT A) AND (B) AND (NOT C)) OR ((NOT B) AND (C)) OR ((NOT D))
end function_1;
Q29. Design the logic circuit and write a data-flow style of VHDL program for the following function,
F(Y) = ΣA,B,C,D (1, 4, 5, 7, 12, 14, 15) + d (3, 11).
Ans:
F(Y) = ΣA,B,C,D (1, 4, 5, 7, 12, 14, 15) + d (3, 11)
The above boolean function can be simplified using 4-variable K-map as,
CD AD
AB 00 01 11 10
0 1 3 2
00 1 x
4 5 7 6
01 1 1 1
BCD
12 13 15 14
11 1 1 1 ABC
8 9 11 10
10 x CD

F(Y) = ABC + BC D + A D + CD
Logic Circuit
The logic circuit for the above simplified boolean expression is shown in figure below,
A B C D
F(Y) = ABC + BC D + A D + CD
Figure
VHDL Code in Data Flow Style
The data flow style of VHDL program for the simplified boolean function is mentioned below,
library IEEE;
use IEEE . STD_LOGIC_1164.all;
entity function is,
port (A, B, C, D : in STD_LOGIC;
F : out STD_LOGIC);
end function;
architecture function_1 of function is
begin
F < = ((A) AND (B) AND (C)) OR ((B) AND (NOT C) AND (NOT D)) OR ((NOT A) AND (D)) OR ((C) AND (D));
end function_1;

Q30. Write a VHDL Entity and Architecture for the following function. F = a (XOR) b (XOR)c, Also draw the
relevant logic diagram.
Ans:
Given function is,
F(x) = a + b + c
= (ab + a b) + c
= (ab + a b) c + (ab + a b) c
= (ab + a b) c + (ab . a b) c
(
= a b c + a b c + (a + b) . (a + b ) c )
= a b c + a b c + [ a a + a b + ab + b b ]c
= a b c + a b c + [ a b + ab]c [ x. x = 0]
∴ F(x) = a b c + a b c + a b c + abc
The logic diagram of given function is,
a
b F(x)
c
Data Flow
Entity function is,
Port(a, b, c : in STD_LOGIC; F: OUT STD_LOGIC);
end function;
Architecture data_flow of function is,
begin
F <= (a and NOT b and NOT c) OR (NOT a and b and NOT c) OR (NOT a and NOT b and c) OR (a and b and c);
end data_flow;
Q31. Write a process based VHDL program for the prime-number detector of 4-bit input and explain the flow
using logic circuit.
Ans: Oct./Nov.-18, Set-2, Q3(b) M[7]
4-bit Prime-number Detector: In a 4-bit prime number detector, the 4-bits produce 16-input combinations (i.e., from 0 – 15)
among which 1, 2, 3, 5, 7, 11 and 13 are the possible prime numbers i.e.,
f = Σm (1, 2, 3, 5, 7, 11, 13)
If A, B, C and D are the 4-inputs, the Karnaugh-map for possible prime numbers is shown in figure (1),
CD
00 01 11 10
AB
0 1 3 2
00 1 1 1 A BC
4 5 7 6
01 1 1 AD
12 13 15 14
11 1 BC D
8 9 11 10
10 1 BCD
BCD
Figure (1): K-map for Prime Numbers
f (A, B, C, D) = A B C + A D + BC D + B CD
The logic circuit for the 4-bit prime detector can be obtained by implementing the above boolean expressions using logic
gates as shown in figure (2).
A B C D
f = ABC + AD + BCD + BCD
Figure (2): Logic Diagram of 4-bit Prime Detector

Process Based VHDL Program
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
entity prime4 is,
port(A, B, C, D : in std_logic;
f : out_std_logic);
end prime4;
Architecture behaviour of prime4 is,
begin
process (A, B, C, D)
begin
f < = (NOT A AND NOT B AND C) OR (NOT A AND D) OR (B AND NOT C AND D) OR (NOT B AND
C AND D);
end process;
end behaviour;
Q32. Write a VHDL program for comparing 8 bit unsigned integers.
Ans: (Model Paper-4, Q2(a) | Oct./Nov.-18, Set-3, Q3(b) M[7])
VHDL program for comparing 8-bit unsigned integers is given below,

entity Vcompare is
port(A, B ; in STD_LOGIC_VECTOR (7 down to 0);
EQ, NE, GT, GE, LT, LE : Out STD_LOGIC);
end Vcompare;
architecture Vcompare-archi of vcompare is
begin
process (A, B)
begin
EQ < = ‘0’;
NE < = ‘0’;
GT < = ‘0’;

GE < = ‘0’; Q34. Define the term “Verilog as HDL”.
LT < = ‘0’; Ans:
LE < = ‘0’; Verilog as HDL
if A = B then EQ < = ‘1’; end if; A verilog HDL is a high level programming language
used to model VLSI design. The language has special hardware
if A : = B then NE < = ‘1’; end if; related constructs, which are used to model digital systems for
if A > B then GT < = ‘1’; end if; simulation, synthesis and test.
if A > = B then GE < = ‘1’; end if; A Hardware Description Language (HDL) permits
describing the components present in a digital circuit in the
if A < B then LT < = ‘1’; end if; text format or symbols rather than using flow charts and block
if A < = B then LE < = ‘1’; end if; diagrams. It describes each component in terms of,
end process;  Inputs and outputs
end Vcompare-archi;  Logic functions and
 Timing parameters like delays and clocking.
1.2 Verilog HDL
All the components that build up a digital circuit can be
1.2.1 Introduction to Verilog HDL, Module described in the form of text by following some rules and using
Statement, Wire Statement some keywords. The file containing the text is compiled and
its operation is verified by analyzing the output. Verification
Q33. Explain in brief about development of Verilog of digital circuit using verilog HDL is an essential process to
HDL. validate the design.
Ans: Consider an example of a VLSI design flow as shown
Initially, verilog has begun as a proprietary hardware in figure,
modelling language by gateway design automation Inc. around
1984. It is reported that the original language was designed by
captivating features from the most widespread HDL language of
the time, named HiLo, also from computer languages such as C.
At that time, verilog was not stantandardized and the language
improved itself in almost all the revisions that came out within
1984 to 1990.
In the late 1990’s Cadence Design System decided
to purchase gateway automation system together with other
gateway products. Cadence now became the owner of the verilog
language, and continued to market verilog as both a language
and a simulator.
Cadence realized that if verilog remained a closed
language, the pressures of standardization would finally cause
the industry to shift to VHDL. Therefore, cadence organized
the Open Verilog International (OVI), and in 1991 gave it the
documentation for the verilog hardware description language.
This was the event which “opened” the language.
Soon it was understood that if there were too many
companies in the market for verilog, probably everybody
would like to do what gateway had done so far-modifying the
language for their own benefit. This would defeat the major
drive of releasing the language to public domain. Therefore,
in 1994 the IEEE 1364 working group was formed to turn the
OVI LRM into an IEEE standard. This effort was finished with a
successful voting in 1995, and verilog became an IEEE standard
in December 1995.
Verilog was initially designed for simulation and
verification of digital circuits. Later, with the CAD tools
synthesize the verilog code into a hardware unit that performs
the operation described by the code. Figure: Steps in VLSI Design
In the first phase, the architecture of the design is described in behavioral level, which is the highest abstraction level. This
level does not specify the design implementation. At every level, the design descriptions are verified for their functionality by a
simulation tool. After simulation, the behavioral description is converted to a RTL description using an algorithmic synthesis tool.
This is an automated design process that interprets the behavioral level description of a desired behaviour and creates hardware
that implements the behaviour. The Register Transfer Level (RTL) specifies the flow of data between registers and the processing
of data by the design. Further, the design is simulated and forwarded on to the next level.
In the next level, the RTL description is converted to a gate level description using a logic synthesis tool. The logic synthesis
tool generates a net list of logic gates that are required for implementing the total design.
Once the logic synthesis process is finished, the next step is to implement a logic network with the available gate level
net list. After implementation, the logic of the network is verified by carrying out simulation. If the logic is found correct, then
circuits are designed using the cell library.
During the next level, all the components are assembled. Once the assembling is completed, simulation is carried out for
verifying its electrical parameters and the logic. Now the design is carried on to the next phase i.e., physical design. Here conver-
sion of cell instances and their wirings into corresponding pattern of silicon is carried out. In other words, layout is done. In the
final stage, the layout is inspected and thus forwarded to the production unit where a silicon test chip is produced.
The levels in which the above design is carried out, is provided by verilog HDL. Here, the step by step design is implemented
by identifying the relation between each level and linking them through appropriate verilog code as each level has its own style
and reserved words. Also, there are various switch constructs for MOSFETs available in verilog HDL that makes it popular to
be used in VLSI design.
Q35. Compare VHDL and verilog HDL.
Ans:
VHDL and verilog HDL are two hardware description languages. These languages are designed to understand the behaviour
and hardware structure of a model. The comparison between VHDL and verilog HDL is as follows,
VHDL Verilog HDL
1. VHDL is a hardware description language employed Verilog HDL is a hardware description language used to
to model digital system at various levels, i.e., ranging define hardware at various levels i.e, gate level, register
from algorithm level to gate level. transfer level and algorithmic level.
2. Functions and procedure are assembled in a same Functions and procedure are assembled in a separate system
package. files.
3. VHDL language is unable to understand easily, as it Verilog HDL language is easy to understand.
is strongly typed.
4. It is difficult to compile. It is easy to compile.
5. In VHDL, data type used is user defined. In verilog HDL, data type used is not user defined and is
very simple to use.
6. In VHDL, the generate statement replicates a number The concept of structural replication is not possible in
of identical instances for the design unit and connect verilog.
them properly.
7. Compiled entities, architecture packages and The concept of library and package is not available or used
configurations are saved in libraries to manage many in verilog.
design projects.
8. VHDL enables concurrent procedures calls. Verilog HDL enables task calls.
9. Extensive set of operations are available in VHDL. Predefined unary and extensive set of operations are
available in verilog HDL.
10. It is not case sensitive. It is case sensitive language.

Q36. List the features of verilog HDL. Output[3 : 0]q;
Ans: input clk, reset;
The features of verilog HDL are, T_FF tff0 (q[0], clk, reset);
T_FF tff1 (q[1], q[0], reset);
1. Verilog HDL is a common language used for designing,
testing and verification. T_FF tff2 (q[2], q[1], reset);
2. It allows mixing of different abstraction levels. T_FF tff3 (q[3], q[2], reset);
endmodule
3. Verilog HDL libraries are used for post logic synthesis
and simulation. module T_FF (q, clk, reset);
output q;
4. It is mostly used in implementation of digital logic chips.
input clk, reset;
5. It is case sensitive.
wire d;
6. It uses 100 predefined keywords.
D_FF dff0 (q, d, clk, reset);
7. It is highly portable. not n1(d, q);
8. It is easy to learn and use. end module
Q37. Explain differences between module and In above program, a T-flip-flop module with four
module instances in verilog. different instances are created.
Ans: Q38. Explain different levels of design descriptions
Module in verilog.
Ans: Model Paper-1, Q2(b)
A module is a basic building block which is the
collection of lower-level design blocks. It provides the suitable Levels of Design Description
functionality to the higher level design blocks with the help In verilog HDL, a hardware design can be described in
of input and output ports. The ‘module’ and ‘end module’ four different styles (or levels). They are,
keywords are used to represent a module. 1. Circuit level or switch level
A module should have a module_name and module_ 2. Gate level or structural level
terminal_list. 3. Data flow level
Module_name: represents the identifier for the module. 4. Behavioral level.
Module_terminal_list: representsthe input and output 1. Circuit Level or Switch Level
terminals of a module. This is the basic or lower level of design description
An example for the representation of module is, in verilog. At this level, digital circuits are designed using
transistors. In verilog HDL, transistors are known as switches.
module<module_name>(<module_terminal_list>);
Verilog provides various mos switch constructs like nmos, pmos,
... cmos, rnmos, rpmos, rcmos, which are used to design digital
<module internals> circuits like inverters, logic gates, simple 1-bit dynamic and
... static memories.
For instance, design description for CMOS NOR gate
end module
as shown in figure (1) at circuit level is,
Depending on the design process, four levels of Supply1
abstraction are required for each module. They are, a
(i) Behavioral level in2
(ii) Dataflow level
b Out
(iii) Gate level
(iv) Switch level.
Module Instances
The process of creating objects from a module template is
called instantiation. The objects are created in module templates. in1
These created objects are called ‘instances’. Each object has
unique name, variables, parameters I/O interfaces etc. When
c
one module is instantiated within other module port connection
rules are used.
An example program for module instantiation is module Supply0
ripple_carry_counter (q, clk, reset); Figure (1): CMOS NOR GATE
Program
module npnor_2(out, in1, in2),
output out;
input in1, in2;
Circuit level description
supply a; //declaration of power

Supply0 c; //declaration of ground
Wire b; //declaration of internal wires
pmos (b, a, in2); //instantiation of pmos switch
pmos (out, b, int1); //instantiation of pmos switch
nmos (out, c, int1); //instantiation of nmos switch
nmos (out, c, int2); //instantiation of nmos switch
endmodule
2. Gate Level or Structural Level
The higher level of design description next to circuit level is the gate level. At this level, a digital circuit is described in
terms of basic gates like and, or, nand, nor, xor and xnor. All the basic gates are available as ‘primitives’ in verilog. Primitives are
general modules that are predefined in verilog. They can be incorporated (instantiated) directly in other modules. More complex
circuits can be modeled by repeated and successive instantiation of the ‘primitives’.
For instance, design description for a 2-to-1 multiplexer as shown in figure (2) at gate level is,
i1 y1
Out
i0 i0 y0
2-to-1
MUX Out
i1
S0n
S0
S0
Select pin
Block diagram Logic diagram
Figure (2): 2-to-1 Multiplexer
Program
module mux 2_to_1 (out, i0, i1, s0); //module of 2_to_1 multiplexer
output out; //declaration of output from I/O diagram
input i1, i0; //declaration of input from I/O diagram
input s0; //declaration of input from I/O diagram
wire s0n; //declaration of internal wire
Gate level description
wire y0, y1; //declaration of internal wire

not (s0n, s0); //instantiation of not gate
and(y0, i0, s0); //instantiation of and gate
and (y1, i2, s0n); //instantiation of and gate
or (out, y0, y1); //instantiation of or gate
endmodule

3. Data Flow Level
After gate level, the next higher abstraction level is data flow. At this level, simple continuous assignment statements
are used to describe digital circuits. A simple assignment statement ‘assign’ is used to define various operations on signals and
variables. For instance, design description for an AOI gate circuit shown in figure (3) in data flow style is,
a e
b g1 g
c f
d
Figure (3): Logic Diagram of an AOI Gate

Program
module aoi2(g, a, b, c, d);
output g; //declaration of output from the diagram
input a, b, c, d; //declaration of inputs from the diagram
wire e, f, g1, g; //declaration of internal wires
Data flow style
assign e = a & b; //“&” is the bit wise AND operator

assign f = c & d; //output of AND operation performed between c&d is assigned to f
assign g1 = e f; //“ ” is the bit wise ‘OR’ operator
assign g = ~g1; //“~” is the bit wise negation operator
endmodule
The order of assignment statements in the above is immaterial because all the assign statements are executed concurrently
(simultaneously).
4. Behavioral Level
Behavioral level is the highest abstraction level among others. At this level, procedural constructs such as initial statements,
always statements are used in the design. In addition to branching the control, looping of certain block of statements is possible.
Hence, behavioral level is a detailed description of a design with minimum statements that becomes an efficient and fast design
process. For instance, design description for an edge triggered flip-flop in behavioral style is as follows,
Program
module edge_tr_ff(q, q_bar, data, set, reset, clk);
input data, set, clk, reset; //declaration of input ports
output q, q_bar; //declaration on output ports
reg q;
assign q_bar = ~q; //assign statement

always @(posedge clk) //flip flop with synchronous set/reset
Behavioral design styles
begin
if(reset = = 0) q<=0;
else if(set = = 0) q<=1;
else q<=data;
end
endmodule
Design of a digital circuit in behavioral level resembles a program written in ‘C’ language.
Q39. Explain the components of a verilog module A module may or may not contain all the above
with block diagram. components and no rule is followed in the order of their
(or) placement although, a module should begin with a keyword
‘module’, end with ‘end module’ statement and should have a
What are the basic components of a module? module name.
Ans:
Block Diagram Showing Components of Verilog Module
Module
‘Module’ is a keyword from where a verilog code starts.
It is assigned a name and contains input and output terminals
known as ports.
Ports
The three kinds of ports are,
1. Input Ports
These are entry terminals from where input data enters
a module.
2. Output Ports
These are exit terminals from which data is sent out of
a module.
3. Inout Ports
There are two way terminals from which data enters at
some point of time and exits at some other points of time.
A module may contain any number of input ports,
output ports, inout ports and even no ports as it is decided by
the function given to a module.
A module contains various components as shown in
figure,
Module name(ports list);
(keyword)
Declaration of ports(if present); Figure: Module Components
Parameter declarations(if any);
Q40. Explain the port connection rules in a module
Wires declarations
instantiation?
regs declarations
Data flow statements(such as assign)
A port provides connectivity between the modules which
Lower level modules instantiation
are connected by name or by ordered list.
Behavioral statements
A port has two parts in a module. They are,
(such as always and initial blocks)
1. Internal module
Declaration of
2. External module
Tasks and functions
endmodule statement When these modules are instantiated within other
modules, then port connection rules are used.
(keyword)
The width of internal and external modules must be same.
The definition of a module starts only with ‘module’
keyword, followed by a module name, list of ports, their declarations, In verilog, unconnected ports are also allowed.
parameters declaration. Note that a module communicates with the Example
outside environment only through its ports.
Module fulladd (sum, a, b, c - out, C-in);
As shown in figure a module contains the following five
components. They are, fulladd fa0 (SUM, A, B, C_IN);
1. Declaration of variables Here, output port is not connected.
2. Data flow statements The three types of ports and verilog keywords used are,
3. Lower level module instantiation 1. Input port – Input
4. Behavioral statements 2. Output port – Output
5. Tasks and functions. 3. Bidirectional port – Inout

The port connection rules are shown in figure,
Net
Net Inout
External
Input Output module
reg or net Net reg or net
Internal module
Figure: Port connection Rules

Inputs
Internally, input ports must be net type. Externally, input ports are connected to ‘reg’ or ‘net’ type.
Outputs
Internally, output ports must be ‘reg’ or ‘net’ type. Externally, output ports are connected to ‘net’ type.
Inputs
Internally and externally, in-out ports are connected to net type.
Q41. Explain different number specifications used in verilog HDL.
Ans:
Number Specification
In Verilog two types of numbers can be used. They are,
1. Integer numbers
2. Real numbers.
1. Integer Numbers
The integer numbers can be specified in two ways. They are,
(a) Decimal form
(b) Base form.
(a) Decimal Form
A decimal number can be,
(i) Signed member (both positive and negative)
(ii) Unsigned number (positive only).
Example
5 These are the decimal numbers which are assigned
42 width of 4-bytes i.e., 32-bits by default as their
–123 size is not specified.
–5
10b
b5 These are not decimal numbers since
d8 they include alphabets.
–20c
The decimal form of representing numbers is mostly used in test benches.
(b) Base Form
It is possible to represent numbers in various formats namely,
(i) Binary form (Base of 2)
(ii) Decimal form (Base of 10)
(iii) Octal form (Base of 8)
(iv) Hexadecimal form (Base of 16).
The format to represent such numbers is given below with an example.
– 4 b 1 01 1
Number value is represented in this field

Base of the number is specified
Number width
Sign (exceptional)
This form of representation specifies,
 The sign of the number
 Width of the number (number of bits)
 Base representation of the number (whether binary, decimal, octal or hexadecimal)
 Value of the number.
The sign bit is optional, if it is not specified then positive number is assumed by default.
An integer value is used to specify the number width in all forms. If it is not specified then compiler allots some value by
default.
Base representation of a number and its value varies for different number systems.
(i) Binary
‘b’ or ‘B’ is used to represent binary numbers. No spaces are allowed between single quote (1) and base. Binary numbers
may be assigned four values. They are,
0 – Logic 0
1 – Logic 1
X or x – Unknown value
Z or z – High impedance state.
Example
 6' b 1 1 0 0 1 1 : Binary number of 6-bits
 5' b 1 _ 1 × 1 : Underscore _ is allowed within the value except at the first place i.e., 5'b _ 1 1 1 1 is not allowed.
 _ 4' b 1 0 1 : Here, negative is represented, where 0 1 0 1 is 2’s complement form.
 3' B 1 0 : Here, the value contains only two numbers which is less than its width
so 0’s can be added at the left end to file in empty bits.
\ 010 is the binary value.
If x or z is the value present at the extreme left then fill the empty bits with x or z respectively.
If 3' Bxx : The value is xxx.
It is a good practice to specify the value equal to its width to avoid confusion of filling the bits whether to the left or right.
(ii) Decimal Form
‘d’ or ‘D’ is used to represent decimal base. Its value takes numbers from 0 to 9.
Example
9' d 500
9' D 500 Decimal value stored is 500
9' D 5_00

(iii) Octal Form There are some rules to be followed for an identifier that
‘o’ or ‘O’ is used to represent octal base. It takes numbers are given below.
from 0 to 7. 1. Identifier names cannot start with a digit, special
Example characters except the underscore( _ ) character.
6' 0 1 0 0 1 1 0 1 0 0 1 1 is the octal value Examples
6' 0 1 0 0 1 1
name, out1, and_gate, _and. _can be used as identifiers.
5' 0 1 × 0 1 1 – 1 × 0 1 1 is the value
6' 0 1 0 z 1 1 – 0 1 0 z 1 1 is the value 20 out, $time cannot be used as identifier since they begin
with a digit, special character $.
(iv) Hexadecimal Form
‘h’ or ‘H’ is used to represent hexadecimal base. It takes 2. No spaces are allowed within identifier name.
numbers from 0 to 9 and alphabets a, b, c, d, e, f, A, B, C, D, E, Example
F.
“and a” cannot be used as an identifier rather “and _a”
Example
can be used as an identifier.
8'FA – 1 1 1 1 1 0 1 0 is the value
3. Except _and $, no other special characters are allowed
9'1, za – z z z z z 1 0 1 0 is the value
in an identifier name.
5'h ?a – Here ? represents z value
\ z 1 0 1 0 is the value Example
– 6'h1a – This is a negative number whose value in 2’s name + b, @ or, out & gate cannot be used as identifiers,
complement is 1a. rather name_b, name$ can be used.
2. Real Numbers 4. Keywords system tasks and functions are not allowed
There are two ways of representing real numbers. They to be used as identifiers.
are,
Example
(i) In decimal representation
Module, $monitor etc., cannot be used as identifiers.
(ii) Scientific representation.
Example of Decimal Representation But module can be used as identifier name as identifiers
1.1 are case sensitive.
–2.23 Apart from the above identifiers there are other identifiers
–1024.00 Here decimal point (.) separates the integer that begin with a character ‘backslash’ (\) named as ‘escaped
part from the fractional part identifiers’.
131 . 212 Example
\a
Integer Fractional
\control-signal
part part
\&logic
Example of Scientific Representation
\xyz
4.2e2 – i.e., 4.2 × 102
– 4.2E2 – – 4.2 × 102 Here identifiers are those characters that are enclosed
4.2e–2 – 4.2 × 10–2 within backslash character and white space i.e., a control-
signal, &logic, xyz.
– 4.2e–2 – – 4.2 × 10–2
Here e is the exponential specification (×10power) the Keywords
value after it is the power, the value proceeding it is mantissa. Every language contains certain reserved words known
Q42. Explain about identifiers and keywords used in as keywords. They describe the language constructs. Each
verilog HDL. keyword specifies a particular action to be performed, started
Ans: or ended. So, these keywords are used only for specific purpose
but not as variables, constants etc.
Identifiers
In verilog, identifiers are names assigned to various In verilog, there are many keywords and all are written
objects, signals to refer them. These identifiers are formed by in lower case letters. So, the same should be followed because
alpha numeric characters containing letters, digits and some verilog differentiates lower case letters and upper case letters
special characters $ (dollar) and_(underscore)). (case sensitive).
Some of the keywords are listed below, 3. Registers
1. module – A module is defined starting with this 1. Register datatypes are the variables that are used
keyword to store the data.
2. endmodule – The definition of a module ends with this 2. The variables present in the procedural blocks are
keyword register datatypes.
The register datatype is represented with “reg”.s
3. begin – A set of statements in a block start with
this keyword The default initialization value of register data type is
garbage value (i.e., unknown value ‘x’).
4. end – A set of statements within a block are
terminated using this keyword Example
reg x, y; // single bit variable register
5. if – Verifying the conditional statement.
reg [15 : 0]; // 16-bit variable register.
1.2.2 Data Types, Data Operators 4. Vectors
Q43. Explain about different data types used in 1. The vectors are declared using net data type or
verilog HDL. register data type.
2. The range of vectors is represented by two digits
Ans:
enclosed between two square brackets separated
Different data types used in verilog are, by a colon.
1. Value Set The representation of vector is as shown in figure.
The four basic states of value set in verilog HDL are,
1. Logic zero i.e., ‘0’ b[0]
Circuit 1 Circuit 2
2. Logic one i.e., ‘1’ b[1]
3. Unknown logic value i.e., ‘x’ b[2]
b[3]
4. High impedance state i.e., ‘z’
Where,
4-bit vector
Logic ‘0’ and logic ‘1’ are complement to each other. Part vectors
When high impedance state is present at the input of a Figure: Representation of Vectors
gate, then its function is same as that of ‘x’ i.e., unknown logic
value. Examples of vectors are,
wire [2 : 0]x; /* x is a net type of vector containing 3
2. Nets
bits referred as x[2], x[1], x[0]*/
A link (connection) between different circuits is reg [10 : 5]z; /* z is a reg type of vector containing 6 bits
represented by net data type. It transfers the signal value that it referred as z[10], z[a], z[8], z[7], z[6] and z[5]*/
drives to the circuit it is driven by when no driver is connected
The integer to the left colon represents MSB and to the
to the net, it takes ‘z’ logic value. There are two keywords to
right of colon represents LSB.
declare nets.
The two types of vectors are,
Wire
1. Signed quantities (or) vectors
It is used to declare a simple net that connects two 2. Unsigned quantities (or) vectors
circuits. It supports connection of single output that
Signed vectors are represented using the keyword
drives the net.
“signed”.
Example Vectors that are not represented as signed are assumed
wire x; //x is a net of 1 bit as unsigned vectors.
wire x = 1'b1 //x is a net of 1 bit assigned as logic 1. 5. Integer
Tri Integer is a keyword used to declare integers. It is a reg
data type that can store signed numbers. This data type
It declares a simple net and the number of signal outputs is mostly used to declare counter variables.
that can drive a net can be greater than one.
Example
Example integer count; /*count is a variables that can be store
tri out; //out is a net integer values*/
A part from wire and tri data types other net types are initial
wand, wor, tri, triand, trior, trireg etc. count = –3;

6. Real Data Type 9. Memories
Real is a keyword used to declare real number constants. Memories are represented by one dimensional array of
Note that either decimal notation (a b) or scientific registers.
representation can be used to declare a real number
RAM’s, ROM’s and register files are represented using
constant, ‘0’ is the default value stored in ‘real’ and
these arrays.
their exists no declaration of range. A real number when
specified as an integer variable, the variable stores the Each register in an array is called an “element”.
nearest integer value of the real number.
Examples for memory declaration:
Example
reg[7 : 0] mema[0 : 1023];
real pi; //pi is a real variable
mema consists of 1024 8-bit registers
pi = 3.14; //real number constant 3.14 is stored in pi
The array indices must have constant expressions.
integer i; //i is an integer variable
An n-bit vector register and memory of ‘n’.
r = pi; //i stores the value 3
1-bit registers are not same.
7. Time Register Data Type
i.e., reg[1 : n]reg a; ! reg mema [1 : n];
Time is a keyword used to declare a time variable that
Values to memory elements are not directly assigned
stores simulation time. Since, in verilog simulation is
instead they are assigned with index.
carried out at simulation time.
i.e.,
In order to know the present simulation time, $time is
the system function to be instantiated. mema = 0; wrong way of assigning
Example mema[1] = 0; right way of assigning.
Time current_time; //A time variable (current_time) is 10. Strings
declared initial.*/
A set of characters written between (“ ”) double quotation
current_time = $time; /*current simulation time is stored marks is known as a string. These set of characters are
in current_time*/ limited to one line, they are not extended to next line
using carriage return identifier. Any special character
8. Arrays
to be introduced in a string should be followed by a
An array is a collection of similar datatype variables. backslash “\” character.
The general format of an array is,
Example
a0 a1 a2 --- --- --- --- an  “Welcome to verilog”
Syntax  “The keyword \“module\” specifies module definition”.
Type array_name[size]; Output
Where, The keyword “module” specifies module definition.
‘Type’ is a datatype.  “One \n two \n three \n four”

One
‘array_name’ is the name of array. \n – Introduces a new line
Two
‘Size specifies’ the number of values assigned to \t – Tab space is introduced
Three
an array.
Output
Example
In Verilog, each character within a string is assumed
reg[7 : 0] r1[1:256];
as an 8-bit ASCII character. Hence, corresponding
Where, 8-bit ASCII value is assigned to individual character
[7:0] – Vector width in a string. Now, the string contains set of 8-bit binary
[1:256] – Array size numbers corresponding to each character, where 7-bits
represent the ASCII equivalent and a 0 is proceeded by
The size of the array is fixed at compile time and it cannot
them.
be changed during execution time.
Example
Arrays are used in matrix operations, sorting elements
etc. name = “verilog”
The corresponding ASCII values of individual characters are,
v – 118 – 0 1 1 1 0 1 1 0
e – 101 – 0 1 1 0 0 1 0 0
r – 114 – 0 1 1 1 0 0 1 0
i – 105 – 0 1 1 0 1 0 0 1
l – 108 – 0 1 1 0 1 1 0 0
o – 111 – 0 1 1 0 1 1 1 1
g – 103 – 0 1 1 0 0 1 1 1
\ The binary values are,
01110110 01100100 01110010 01101001 01101100 01101111 and 01100111.
Q44. Explain defparam and localparam keywords.
Defparam: This is the keyword used to change parameter values in any module instance in the design. This approach can use
hierarchical name of the module instance to override parameter values.
Usage of defparam to override parameter values in module instances is given in below verilog code.
module hello_world; //A module is defined as hello_world
parameter id_num=0; //A module identification number is defined as zero
initial
$display(“Displaying hello_world id number = %d”, id_num);
//displaying “Displaying hello_world id number” with defined value i.e., zero
endmodule
module top; //top-level module is defined
defparam W1.id_num = 1, W2.id_num = 2; //defparam statement is used to change id_num from zero to 1 and 2
hello_world W1( ); //one hello_world module is instantiated
hello_world W2( ); //another hello_world module is instantiated
endmodule
In the above example, initially a module is defined by hello_world then a parameter id_num is declared with zero. Further,
two module instances W1 and W2 are instantiated of hello_world type, then their respective id_num values are changed to 1 and
2 using the defstatement. Following output is obtained after simulation of above verilog code.
Output
Displaying hello_world id number = 1
Displaying hello_world id number = 2
Localparam
One of the parameters defined in verilog is localparam.
A localparam is constant i.e., similar to a parameter. The value of localparam cannot be changed with the help of defparam
statement or by any other method.
In other words, the values that do not require any alterations are declared as localparam. Overwriting of the values can be
prevented with the help of localparam. When one module is instantiated over another module, the passage of values for different
data types is not possible.
Syntax
localparam name = value;
Example
1. Localparam depth = width * 10;
2. localparam size = 8;
Q45. Explain different types of operators used in the verilog HDL.
Ans:
The different types of operators used in verilog HDL are,
Unary Operators: Unary operators are associated with a single operand. The operand is proceeded by the unary operator and the
result of operation is stored in the same operand. The list of unary operators with examples are given in table (1).
Let A = 1 0 0 1 0 0 1 1, B = 1

Unary Operator Name Example Output

Operator
! Logical NOT !B 0
~ Bitwise NOT ~A 01101100
& Reduction AND &A 0
~& Reduction NAND ~&A 1
| Reduction OR |A 1
~| Reduction NOR ~|A 0
^ Reduction XOR Â 0
~ ^ or ^ ~ Reduction XNOR ~Â 1
Table (1): Unary Operators
Apart from the above operators, + and – are also unary operators that change the sign of an integer.
Binary Operators
These operators perform operations on two operands. These two operands are separated by a binary operator.
There are different binary operators that are listed in table (2),
Let, A = 0 1 0 1 1 0 1 0
B=00000001
Binary Operators Symbols Example Result
Arithmetic operators + - Addition
– - Subtraction
* - Multiplication A–B 01011011
/ - Division
% - Modulus
** - Power
Bitwise operators & - Bitwise AND
| - Bitwise OR
^ - Bitwise XOR A&B 00000000
~ ^ - Bitwise XNOR
Logical operators && - Logical AND
|| - Logical OR A&&B 1
Relational operators > - Greater than
< - Less than
<= - Less than
or A>=B 1
equal to
> = - Greater than
or
equal to
Equality operators = = - Equality A ! = B 1
! = - Not Equal
Shift operators >> - Right shift
<< - Left shift
<<< - Arithmetic
left shift A >> B 00101101
>>> - Arithemetic
right shift
Table (2): Binary Operators
The few points to be noted are,
 The two operands are treated as two numbers by the arithmetic operators thus outputs the numerical value.
 Operands that are declared as net or reg type are assumed as unsigned numbers.
 Operands declared as real or integer types may be treated as signed numbers.
 If any of the operands contains value 0, then the result of operation would be zero.
 If any of the operands contains value x or z, then the result of operation will be the value x.
Arithmetic Operators
Table (3) shows various arithmetic operators.
Let, A = 1 0 1 0
B=0001
Arithmetic Operators Operator Name Example Result
+ Addition A+B 1011
– Substraction A–B 1001
* Multiplication A*B 1010
/ Division A/B 1010
% Modulus A%B 0000
** Power A ** B 1010
Table (3): Arithmetic Operators
In the table (3), the modulus % operator returns the remainder result of division between two operands.
The few points to be noted are,
 When the division operation is performed between two integer numbers, then the result contains only integer part truncat-
ing the fractional part.
 The arithmetic operation performed on the operands that contains the values x or 2 results in the value x.
 The result of a modulus operation contains a negative number if its first operand is negative.
Logical Operators
Table (4) contains various logical operators.
Let, A =100
B=0010
Logical Operator Operator Name Example Result
&& Logical AND A&&B 1
|| Logical OR A||B 1
~ Bitwise logical
negation ~A 0110
& Bitwise logical AND A&B 0000
| Bitwise logical OR A|B 1011
^ Bitwise logical XOR A∧B 1011
~ ∧ or ∧ ~ Bitwise logical XNOR A~∧B 0100
>> Logical right shift A >> B 0010
<< Logical left shift A << B 0100
Table (4): Logical Operators
 The operands can be either variables or expressions associated with variables.
 If one of the operands contain value x or 2, then the result of operation also contains a value x.

Syntax
1.2.3 I f - e l s e S t a t e m e n t , C a s e - e n d C a s e
Statement, Verilog Syntax and Semantics Syntax for initial block statement is as follows,
(Qualitative Approach)
Q46. What is behavioral modeling? And write a short
note on operations and assignments.
Ans:
Behavioral Modeling
In a circuit designing, data flow level and gate level both
constitute design description process which relates the modules,
instantiations and their interconnections. These processes are
effective as long as the gate count remains within a few hun- Initial Block
dreds. As the gate count increases, the vector size gets increased An initial block, as the name suggests, is executed only
to accommodate at the data flow level along with increased once when simulation starts, that is at time 0, and it will not
functional complexity. Hence, this approach is not suitable for execute again. If we have multiple initial blocks, then all of them
many designs. are executed simultaneously at the beginning of simulation. If
Therefore, behavioral level modeling is emerged for there are more than one behavioural statements inside an initial
design description at an abstract level. Constructs are used for statement then they must be grouped using the keywords ‘begin’
layered expansion of design in behavioral modeling and aim at and ‘end’. An example of Verilog code using initial statement
the system level description to simulate its functionality. is shown below,
module fancy2;
Operations and Assignments
integer i, j;
In the behavior modeling, the design description is
done through a sequence of assignments called ‘procedural initial repeat(5)
assignments’. begin
The procedure assignment is characterized by, #1 j = 0;
 As the continuous assignment, the procedural assignment while (j< = 10)
is also done through “=” or “<=” symbol. begin
 The result on the right side of “=” operator is assigned j = j + 1;
to an operand specified on the left side.
for(i = 0; i < = j; i = i + 1) $ write(“b”);
 The operation on the right involve operands and opera-
$display(“*”);
tors of net or variable type or scalars or vectors.
end
 Consistency of the operands should be maintained in the
operation expression. # 1 while(j > = 0)
 The operand to the left of the “=” operator involves begin

variables of scalar, vector, a part vector or a concatenated for(i = 0; i < = j; i = i + 1)$write(“c”);
vector. $display(“*”);
Q47. Write the syntax for the following constructs and end
give one example for each relevant to behavioral
verilog HDL modeling, initial #$stop;
(i) initial construct endmodule

(ii) always Construct
An always statement is the most basic statement in
behavioural modeling. All other behavioural statements
Ans: appear inside these structured procedure statement. An always
statement along with the behavioural statements inside it is
(i) initial Construct
known as always block. As the name suggests, an always block
An initial statement is the most basic statement in executes always, unlike initial which executes only once at the
behavioral modeling. All other behavioral statements appear beginning of simulation. An always block is associated with a
inside these structured procedure statement. An initial statement condition or a set of conditions, which tells the always block
along with the behavioural statements inside it is known as an when to execute the block of code. The syntax for an always
initial block. construct is,
always Q48. Draw the flowchart for the simulation flow.
[timing_control] procedural_statement (or)
An example of a Verilog code in behavioural style using Explain flowchart for the simulation flow.
always statement is as follows,
Ans:
module 2_1 mux(a, b, sel, y)
input a, b, sel; Figure shows the flowchart for the simulation flow.
output y;
always @ (a or b or sel)
begin
y = 0;
if(sel = = 0)
begin
y = a;
end
else
begin
y = b;
end
end
endmodule
(iii) wait Construct
The wait construct suspends a thread of an activity flow
within a behaviour until an expression is true. The syntax of
wait construct is,
wait (expression) statement 1;
Statement 1 is executed when the expression associated
with wait is true.
Example
wait(enable) p = q;
#10 x = y;
The assignment of value associated with q to p is
suspended until enable is asserted true. After the assignment
is made activity is again suspended for 10 time steps before
assigning the value associated with y to x.
An Example Verilog Code
module Ctr_wt (a, clk, N, En);
input clk, En;
input [3:0]N;
Figure
output [3:0]a;
Description
reg [3:0]a;
initial a = 4’ b1111; A verilog simulator does simulation in simulation time
that progress in equal time units. Multiple active events are
always
performed in sequence at each simulation phase. In Verilog, an
begin event queue namely “Stratified Event Queue” is maintained that
wait(En) contains events such as active events, inactive events, blocking
@(negedge clk) assignment events, monitor events, future events in which
active segment being the first event in the queue is executed
a = (a = = N)? 4'b0000:a + 1'b1;
subsequently. This active event may be either update event
end or evaluation event. If it is an evaluation event, it evaluates
endmodule variables, net values expressions and so on whereas if it is an

update event, it performs queue refresh and rearrangement. Also default : statement;
following the evaluation event an update event can be called endcase
and the converse can also happen. Once the execution of all the
The controlling expression is evaluated and compared
active events is finished, subsequent time phase is lapsed and
with the alternatives in the order they are written. If the evaluated
rest of the operations are executed. This type of execution is
value matches with alternative 1, statement 1 is executed and
referred as parallel processing.
the ‘case’ statement is terminated. If not evaluated value is
Since, all the active events are performed at the same compared with alternative 2, in case of a match, statement 2 is
simulation time, it is difficult to predict which event is executed executed. If not the above process is continued. The ‘default’
when and their sequence, as it depends on the simulator. statement is executed when no alternative matches the evaluated
Although the events that are timed at zero delay are executed value of the controlling expression.
last in that simulation time.
Observations
Q49. Write Verilog code using case statement for any
one example. 1. A statement in the ‘case’ construct is executed, only if
there is a precise bit by bit match between the evaluated
value of controlling expression and listed alternatives
Consider the example of 4 to 1 multiplexer, in which (alternative 1, alternative 2, .....).
select vector is taken of ‘v’. Even though, the four values taken 2. There can be a single statement or block of multiple
by this select vector can be binary numbers, we are considering statements within each of alternative 1, alternative 2,
those values as decimal numbers in writing verilog code for 4 ...., ‘default’ statement. The ‘begin-end’ construct must
to 1 multiplexer using case statement. be used to enclose the block of multiple statements.
module mux 4 to 1 (i, v, 0);
Example
input [0 : 3] i;
case(expression)
input [1 : 0] v;
alternative 1: begin
output reg 0;
statement 1;
always @ (i, v)
statement 2;
case (v)
statement 3;
0 : 0 = i[0];
end
1 : 0 = i[1];
2 : 0 = i[2]; alternative 2: begin
3 : 0 = i[3]; statement 1;
endcase
endmodule statement n;
Q50. Write the syntax for the following constructs and end
give one example for each relevant to behavioral
Verilog HDL modeling,
(i) The case statement default : begin
(ii) if and if-else constructs. statement 1;
Ans: statement 2;
(i) The case Statement

The ‘case’ statement is a simple construct used to execute
statement m;
a single statement from many alternatives, the selection of
statement is based on a condition. Figure, shows the structure end
of a ‘case’ construct. It encompasses the keywords ‘case’, endcase
‘endcase’, and ‘default’.
3. Multiple ‘default’ statements are not accepted in ‘case’
case (expression) statement. Only one ‘default’ statement is allowed and
alternative 1 : statement 1; it can be placed anywhere in the ‘case’ statement.
alternative 2 : statement 2; (ii) if and if-else Constructs
alternative 3 : statement 3; if and if-else constructs are conditional statements, which
..... check a condition to decide whether or not to execute a portion
of code. If the condition is satisfied, code is executed. Else, it
.....
runs other portion of the code. The syntax for both “if” and
..... “if-else” constructs is as shown below.
if syntax Q51. Write the syntax for the following constructs
if(<expression>) true_statement; and give one example for each relevant to
if-else syntax
if(<expression>) true_statement;
(ii) Repeat construct
else false_statement;
(iii) for loop.
When the number of statements to be executed (in a if
Ans:
or if-else construct) are more than one then they are grouped
using the keywords ‘begin’ and ‘end’. (i) assign-deassign Construct
“if” Statement Syntax for Multiple Statements In assign-deassign construct the keywords assign
and deassign are used to express the first type of procedural
if(condition or expression)
continuous assignment. The left-hand side of procedural
begin continuous assignments can only be a register or a concatenation
statement1; of registers. It cannot be a part or bit select of a net or an array
of registers. The procedural continuous assignments override
statement2; the effect of regular procedural assignments. These assignments
end are normally used for controlled periods of time.
“if-else” Statement Syntax for Multiple Statements Syntax
if(condition or expression) ----
begin assign variable = value;
statement1; deassign variable;

Example

Modeling of a negative edge-triggered D flip-flop with
statement n; asynchronous reset using assign and deassign statements is
end mentioned below.
else module edge_dff (q, qbar, d, clk, reset);
begin //Inputs and outputs
statement 1; output q, qbar;
input d, clk, reset;

req q, qbar; //Declare ‘q’ and ‘qbar’ as registers
statement n;
always @ (negedge clk) // assign value of q and
end qbar at active
A Verilog Code using if Statement // edge of clock
module ring_ct(a, clk, c); begin
input [7 : 0]a; q = d;
input clk; qbar = ~d;
output c; end
reg [7 : 0]a; always @ (reset) // Override the regular assignments to q
reg c; // and qbar whenever reset goes high.

Use
always@(posedge clk)
// of procedural continuous assignments.
begin
if (reset)
c = a[0]
begin // If reset is high, override regular
a = a >> 1’b1; assignments
if(c) // to q with the new values using procedural
a[7] = c; // continuous assignment.
end assign q = 1’b0;
endmodule assign qbar = 1’b1;

end end
else initial
begin
begin
// If reset goes low remove the override
clk = 1’b0;
// values by deassigning the registers. After this
// the regular assignments q = d and qbar = ~d i = 0;
// will be able to change the registers on the # 70 $stop;
// next negative edge of clock. end
deassign q;
always #2 clk = ~ clk;
deassign qbar;
endmodule
end
endmodule (iii) for Loop
(ii) repeat Construct In for loop construct of Verilog, the flow of control will
In repeat construct, a required block of statements are be same as that of “for loop” in “C” language. The syntax for
repeated for a specified number of times. The typical syntax for “for loop” is,
repeat construct is, ....
......
for(assignment 1; expression; assignment2)
repeat (a) // ‘a’ is either number or an
statement;
// expression simplified to a number
begin ....
assignment 1; Example
assignment 2; Write a verilog of HDL code to load a set of numbers
--- into set of 16-registers each with 8-bit wide using “for loop”.
end The contents of each register is displayed sequentially again
using a “for loop”.
---
Example module trial_8a;
Write a Verilog HDL code to load a set of numbers into reg [7 : 0] m [15 : 0];
set of 16 registers each 8 bits wide using repeat block. The integer i;
contents of each register is displayed sequentially again using
a repeat block. reg clk;
module trial_8b; always
reg[7: 0]m[ 15 : 0]; begin
integer i;
for(i = 0; i < 8; i = i + 1)
reg clk;
@ (negedge clk)
always
begin m [i] = i * 8;
repeat(8) for(i = 0; i < 8; i = i + 1)
begin @ (negedge clk)
@(negedge clk)
$display (“t = %0d, i = %0d, m[i] = %0d”, $time, i, m[i]);
m [i] = i * 8;
end
i = i + 1;
end initial clk = 1’b0;
repeat(8) always #2 clk = ~ clk;
begin initial # 70 $stop;
@(negedge clk)
endmodule
i = i – 1;
$display (“t = %0d, i = %0d, m[i] = %0d”, $time, i, m[i]);
end
Frequently Asked & Important Questions
Q1. Explain the VHDL program file structure with the syntax of a VHDL entity declaration and
REPEATED
architecture definition. 5
(March-21, Set-1, Q3(a) M[7] | Oct./Nov.-20, Set-1, Q3(a) M[7] | Oct./Nov.-19, Set-2, Q3(b) M[7]) TIMES
Ans: Refer Q4. (Oct./Nov.-19, Set-2, Q3(a) M[7] | Oct./Nov.-19, Set-3, Q1(a) M[7])
Q2. Explain the difference in program structure of VHDL and any other procedural language.
REPEATED
Give an example.
2
TIMES
Ans: Refer Q5. (Oct./Nov.-18, Set-1, Q3(b) M[7] | March-21, Set-2, Q3(a) M[7])
Q3. Explain in detail about the various abstraction levels in VHDL.
REPEATED
3
TIMES
Ans: Refer Q8. (Oct./Nov.-20, Set-1, Q3(b) M[7] | Oct./Nov.-18, Set-3, Q3(a) M[7] | Oct./Nov.-16, Set-2, Q3(b))
Q4. What are the different data objects supported by VHDL? Explain scalar types with suitable
REPEATED
examples. 4
(Oct./Nov.-16, Set-1, Q2(a) | Oct./Nov.-19, Set-1, Q3(b) M[7]) TIMES
Ans: Refer Q11. (Oct./Nov.-19, Set-3, Q3(b) M[7] | Nov.-15, Set-1, Q2(a))
Q5. Explain the following terms in Behavioral Modeling:
REPEATED
(i) Case statement (ii) Null statement (iii) Loop statement. 4
TIMES
(March-21, Set-1, Q4(a) M[7] | March-21, Set-4, Q3(a) M[7])
Ans: Refer Q20. (Oct./Nov.-19, Set-2, Q4(a) M[7] | Oct./Nov.-18, Set-1, Q3(a) M[7])
Q6. Explain IF, exit, next, assertion, report and null statements.
REPEATED
(Oct./Nov.-18, Set-3, Q4(a) M[7] | March-21, Set-2, Q4(b) M[7] 4
TIMES
Ans: Refer Q21. (Oct./Nov.-20, Set-1, Q4(b) M[7] | Oct./Nov.-19, Set-4, Q4(a) M[7])
Q7. Discuss the binding. Discuss the binding between entity and components.
REPEATED
2
TIMES
Ans: Refer Q24. (Oct./Nov.-18, Set-2, Q3(a) M[7] | March-21, Set-1, Q1(b) M[7])
Q8. With suitable block diagram explain about the design flow of VHDL.
Ans: Refer Q2. Important Question
Q9. Explain various data types supported by VHDL and give necessary examples.
Q10. Explain various types of operators used in VHDL.

Q11. With suitable example, explain PROCESS statement in VHDL.

Q12. Explain about variable assignment statement, signal assignment statement, wait statement.
Q13. List out the differences between variable assignment statement and signal assignment statement with
example.

Q14. Explain about the following (i) Packages with syntax (ii) Libraries with syntax.
Q15. Write a process based VHDL program for the prime-number detector of 4-bit input
and explain the flow using logic circuit.
Q16. Write a VHDL program for comparing 8 bit unsigned integers.

Q17. Explain different levels of design descriptions in verilog.

Q18. Explain about identifiers and keywords used in verilog HDL.

Q19. Explain different types of operators used in the verilog HDL.

Q21. Write the syntax for the following constructs and give one example for each relevant
to behavioral Verilog HDL modeling,
(ii) if and if-else constructs.
(ii) repeat construct
(iii) for loop.
UNIT-2 (Combinational Logic Design) 49
UNIT Combinational Logic
2 Design SI
A GROUP
Syllabus
COMBINATIONAL LOGIC DESIGN
Parallel binary adder, carry look ahead adder, BCD adder, Multiplexers and demultiplexers and their use in combinational logic
design, ALU, Digital comparators, Parity generators, Code converters, Priority encoders. (Qualitative approach of designing and
modeling the mentioned combinational logic circuits with relevant digital ICs using HDL)
Learning Objectives
C Function of Parallel binary adder its advantages and disadvantages.
C How carry look ahead adder overcomes the drawbacks of Parallel binary adder.
C Use of BCD adder and its function.
C How Multiplexers and de-multiplexers are used in combinational logic design.
C Special Integrated circuits that are designed to perform the functions of ALU.
C Digital comparators, parity generators, code converters and priority encoders.
Introduction
The traditional methods of designing combinational circuits, which involve simplification and realization through the use of gates,
enabled us to integrate complex functions and make them available in the form of integrated circuits (MSI). Numerous devices
are available in the form of IC’s; these include multiplexers, de-multiplexers, adders, parity generators/checkers, priority
encoders, decoders, and comparators. This unit introduces these complex integrated circuits and their use in combinational
system design. The difficult, lengthy, and time-consuming simplification approaches are no longer required when using these
ICs in system design. Therefore, the system design becomes easier. Also, the total cost of the system is lower because these
ICs drastically cut the number of IC packages that need to be made. Furthermore, having fewer cable connections to the
outside world makes the system more reliable. In order to get the most out of these ICs, the designer needs to learn more
about how they work, what options they have, and what they can’t do.

2.1 Parallel Binary Adder, Carry Look Ahead Adder, BCD Adder
Q1. Explain the operation of a ripple carry adder. (Model Paper-2, Q3(b) | March-21, Set-3, Q5(b))
(or)
Explain the implementation of N-bit binary adder using full adders.
Ans:
We can design adders for n-bit numbers using half-and full-adder circuits (that are used for adding two one-bit binary
values). Figure (a) illustrates an n-bit binary adder that is used for the addition of two n-bit binary numbers. The circuit contains
“n” full-adder circuits that accept two n-bit binary numbers as inputs and produce an (n + 1)-bit binary number as the sum. Figure
(b) illustrates the block diagram of the n-bit Binary Adder.
Bn – 1 An – 1 Bn – 2 An – 2 B1 A1 B0 A0
FA(n – 1) FA(n – 2) FA 1 FA 0 C–1
Cn – 2 C1 C0
Cn – 1 Sn – 1 Sn – 2 S1 S0
Figure (a): An n-bit binary adder using ‘n’ full adders
A Input B Input
An – 1 An – 2 A A Bn – 1 Bn – 2 B B
1 0 1 0
Adder Carry input

C–1
Cn – 1 Sn – 1Sn – 2 S1 S0
Output
Figure (b): Block diagram of n-bit binary adder

As illustrated in figure, an n-bit input A is added to another n-bit input B and the sum is Cn – 1, Sn – 1 Sn – 2 ... S2 S1S0. In this
case, it is necessary for the carry to ripple along the line of cascaded adders, from the LSB to MSB position, in order to create
the n-bit binary adder. This slows down the working speed of the adder. The time necessary to complete an addition operation is
controlled by the time required to complete a ripple-carry operation.
In other words, an N-bit binary adder (as depicted in the diagram) is a device in which the carry output of each full adder is
fed into the carry input of the next adder. Each stage creates sum and carry outputs only when there is input carry in the preceding
stage. This procedure requires a significant amount of time to complete the addition step, and the time delay experienced during
the process is referred to as “carry propagation delay (or) inter-stage carry delay.”
For implementation of n-bit binary adder we use 2-bit and 4-bit adder circuits that are readily available in the form of ICs.
By cascading the adders, it is possible to increase the bit lengths of the numbers to be added. Figure (c) depicts an 8-bit adder
constructed from two 4-bit adders. An n-bit adder can be constructed using an adder tree built in an identical manner.
B3 B2B1 B0 A3 A2 A1A0 B3 B2B1 B0 A3 A2 A1 A0
4-Bit Adder C–1 4-Bit Adder C–1

Logic 0
C3 S3 S2 S1 S0 C3 S3 S2 S1 S0
C7 S7 S6 S5 S4 C3 S3 S2 S1 S0
a
bb
bb
bb
bb
bb
bb
bb
bb
bb
bb
bb
`
bb
bb
bb
bb
bb
bb
bb
bb
bb
bb
bb
_
SUM
Figure (c): Two 4-Bit Adders are Combined to Form an 8-Bit Adder in a Cascade
Q2. Design 8-bit ripple carry adder using full adder and write the VHDL code to implement the 8-bit ripple
carry adder.
Ans:
The block diagram of an 8-bit ripple carry adder using full adder is shown in figure,
B8 A8 B7 A7 B6 A6 B5 A5 B4 A4 B3 A3 B2 A2 B1 A1
C7 C6 C5 C4 C3 C2 C1
Cout FA8 FA7 FA6 FA5 FA4 FA3 FA2 FA1 Cin = 0
S8 S7 S6 S5 S4 S3 S2 S1
Figure
The Cin (carry in) for the 1st full adder is zero.
C1, C2,....,C7 are the carry inputs to the full adders FA1, FA2,....., FA8 respectively. The truth table of a full adder is shown
in table below.
A B Cin Sum Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Table
The corresponding expressions for sum and carry out are obtained as,
Sum = A B Cin + A B Cin + A B Cin + ABCin
Sum = A ⊕ B ⊕ Cin ... (1)
Cout = A B Cin + A B Cin + AB Cin + ABCin
Cout = (A ⊕ B)Cin + AB ... (2)
For the first adder FA1, the Cin = 0 thus equations (1) and (2) are reduced to,
Sum = A ⊕ B
Cout = AB

VHDL Code
library IEEE;
entity Ripple-adder is
port ( A, B : in STD_LOGIC_VECTOR (8 down to 1);
Cin : inout STD_LOGIC_VECTOR (7 down to 1);
Cout : OUT STD_LOGIC;
S : OUT STD_LOGIC_ VECTOR (8 down to 1));
end Ripple-adder;
architecture Rippleadder_arch of Ripple-adder is
Constant Cin1 : INTEGER : = 0;
begin
S(1) <= Cin1 XOR B(1) XOR A(1);
C(1) <= B(1) AND A(1);
S(2) <= C(1) XOR B(2) XOR A(2);
C(2) <= ((A(2) XOR B(2)) AND C(1)) OR (A(2) AND B(2));
S(3) <= C(2) XOR B(3) XOR A(3);
S(4) <= C(3) XOR B(4) XOR A(4);
S(5) <= C(4) XOR B(5) XOR A(5);
S(6) <= C(5) XOR B(6) XOR A(6);
S(7) <= C(6) XOR B(7) XOR A(7);
S(8) <= C(7) XOR B(8) XOR A(8);
Cout <= ((A(8) OR B(8)) AND C(7)) OR (A(8) AND B(8));
end Rippleadder_arch;
Q3. Write the disadvantages in implementation of N-bit binary adder using full adders. How it is overcome
by “carry look ahead adder” Explain.
(or)
Explain the operation of a Look ahead carry generator. (Model Paper-1, Q3(a) | March-21, Set-4, Q5(a))
(or)
Write the disadvantages in implementation of n-bit binary adder using full adders. Oct./Nov.-16, Set-4, Q6(a)
(or)
Explain the working of carry look ahead adder and its advantages. Oct./Nov.-16, Set-4, Q6(b)
Ans:
Disadvantages in Implementation of N-bit Binary Adder
In order to create the n-bit binary adder, it is necessary for the carry to ripple along the line of cascaded adders, from the
LSB to MSB position. In other words, the carry output of each full adder is fed into the carry input of the next adder. Each stage
creates sum and carry outputs only when there is input carry in the preceding stage. As a result, the n-bit binary adder experiences
delay during the addition operation, which is referred to as ‘‘carry propagation delay (or) inter-stage carry delay.’’
To overcome this limitation and accelerate the addition process, a new technique called “Look ahead-carry addition” is
implemented. This technique makes use of two new functions “Carry generation” and “Carry propagation”.
Carry Look Ahead Adder
The Carry look-ahead adder incorporates additional circuitry to enhance its speed and make the addition process independent
of the number of bits. The added circuitry implements two new functions: “Carry generation” and “Carry propagation,” which
are both described in detail below.
Pi A B C C +1 Condition
Ai
Bi Si 0 0 0 0
0 0 1 0 No Carry
0 1 0 0 Generate
Gi 0 1 1 1
1 0 0 0 No Carry
Ci 1 0 1 1 Propogate
Ci – 1 1 1 0 1 Carry
1 1 1 1 Generate
Figure (a): EX-OR Implementation of Full-Adder and its truth table

Consider the full adder circuit illustrated in figure (a) along with its truth table. Here, we define two new variables, Gi
(carry generate) and Pi (carry propagate) as,
Pi = Ai Å Bi
Gi = AiBi
From the above expression it is evident that the G variables can be generated directly from A and B inputs using AND
gates and the P variables are obtained again directly from A and B inputs using EX-OR gates.
It is possible to express the sum output (Si) and the carry output (Ci + 1) in terms of carry generate Gi and carry propagate
Pi, which are both defined as
Si = Pi Å Ci
Ci + 1 = Gi + PiCi
Now, the expressions of sum and carry for each stage can be given as
Ci + 1 = C2 = Gi + P1C1 [Here i = 1 for stage 1]
C2 + 1 = C3 = G2 + P2C2 [Here i = 2 for stage 2]
= G2 + P2[G1 + P1 C1]
= G2 + P2G1 + P1P2C1
Similarly,
C4 = G3 + P3C3
= G3 + P3[G2 + P2G1 + P1P2C1]
= G3 + P3G2 + P2P3G1 + P1P2P3C1
We can see from the preceding Boolean equations that C4 does not have to wait for C3 and C2 to propagate; rather, C4
propagates concurrently with C3 and C2. In other words, the third stage inputs do not have to wait for the input carry provided by
the second stage bits and that the fourth stage is also carried out without the need for a wait. It is true that the addition process is
performed for all of the stages at once if carry is generated that can be added to the sum produced by the next stage.
C4
P3
G3
C3
P2
G2
P1
G1 C2
C1
Figure (b): Carry Generation-Circuit-of-Carry-Look-ahead-Adder

Figure (b) illustrates the Carry Generation-Circuit-of- Ans:
Carry-Look-ahead-Adder and figure (c) illustrates the Circuit- The VDHL code to implement 4-bit carry look ahead
Diagram of 4-bit-Carry-Look-ahead-Adder. adder is mentioned below.
Library IEEE;
A3 C3 C3 Use IEEE.STD_LOGIC_1164.all;
B3 P1 Use IEEE.STD_LOGIC_ARITH.all;
Entity CLA_ADDER4 is
G3 P3
C2 S3 port(A, B : in BIT_VECTOR (0 to 3);
A2 Look-ahead Cin : in BIT;
B2 P Carry
2 S : out BIT_VECTOR (0 to 3);
P2
G2 C1 S2 Cout : out BIT);
End CLA_ADDER4;
Generator Architecture CLA_ADDER4_arch of CLA_ADDER4 is
A1
P1 P1 Signal G0, G1, G2, G3, C1, C2, C3, P0, P1, P2, P3 : BIT;
B1 C0 S1
Begin
G1
G0 <= A(0) AND B(0);
A0 P0 S0 G1 <= A(1) AND B(1);
P0
B0 G2 <= A(2) AND B(2);
G0
G3 <= A(3) AND B(3);
C–1 P0 <= A(0) XOR B(0);
P1 <= A(1) XOR B(1);
Figure (b): 4-Bit Adder with Look-Ahead Carry P2 <= A(2) XOR B(2);
Q4. Draw the circuit of a 4-bit ripple carry adder P3 <= A(3) XOR B(3);
circuit and explain how it is different from look- C1 <= G0 OR (P0 AND Cin);
a-head carry circuit. Give the equation for C1 to C2 <= G1 OR (G0 AND P1) OR (P0 AND P1
C4 for a look-ahead carry adder circuit. AND Cin);
Ans: Oct./Nov.-18, Set-3, Q5(a) C3 <= G2 OR (G1 AND P2) OR (G0 AND P1
AND P2) OR (P0 AND P1 AND P2 AND
A carry look ahead adder circuit is used to speed up
Cin);
the addition process by reducing the time in intermediate
Cout <= G3 OR (G2 AND P3) OR (G1 AND P1
calculations.
AND P2) OR (G0 AND P1 AND P2 AND
4-bit Ripple Carry Adder P3)
For answer refer Unit-2, Q1. OR (P0 AND P1 AND P2 AND P3 AND
Equations for C1 to C4 for a Look-ahead Carry Adder Cin);
Circuit S(0) <= P0 XOR Cin;
C1 = Gi + Pi Ci S(1) <= P1 XOR C1;
C2 = G1 + P1 C1 S(2) <= P2 XOR C2;
C3 = G2 + P2C2 S(3) <= P3 XOR C3;
End CLA_ADDER4_arch;
C4= G3 + P3C3
Q6. How adders can be used for subtraction? Write
Q5. Write VHDL code for 4-bit look ahead carry
the algorithm for a subtractor using adder and
generator along with circuit diagram. explain its operation?
(Model Paper-2, Q3(a) | March-21, Set-1, Q5(b) )
Ans:
(or) In the case of negative numbers, when the 1’s and
Write a VHDL program for the Full Adder. 2’s complement representations are used, the problem of
(March-21, Set-4, Q5(b) | Oct./Nov.-18, Set-4, Q5(a))
subtraction is changed into a problem of addition. In other
words, subtraction of two binary numbers can be performed by
(or) adding 2’s complement of subtrahend to the minuend. Figure
Write a VHDL code to implement 4-bit carry look (1) depicts the algorithm for a subtractor that makes use of an
ahead adder. adder.
INPUTS
MINEND (A)
SUBTRAHEND (B)
(IN 2’s complement (form)
Find 2’s complement of

subtrahend = – B
Adder A + (– B)
OVERFLOW
MSB of Yes
MSB of Yes No
A = MSB SUM = MSB of Sn – 1 = 1?
of – B? A = MSB of
No
-B?
No UNDERFLOW
Yes
No MSB
of SUM (Sn – 1)
= 0?
Yes
OUTPUT OUTPUT
RESULT NEGATIVE (In 2’s RESULT
complement form) POSITIVE
Figure (1): Subtraction Algorithm Using Adder

The two binary inputs A and B, which are minuend (A) and subtrahend (B), might be of the same sign or of the opposite sign.
When the two numbers have opposite signs, we may have an overflow or underflow situation. When the result of the subtraction
operation is more than the greatest integer that can be represented in n bits, we say that an overflow has occurred. Underflow, on
the other hand, arises when the result generated is less than the smallest number that can be expressed by n-bits.
A Binary Adder-Subtractor circuit that is capable of performing both addition and subtraction of binary numbers in one
circuit itself is illustrated in figure (2).
B3 A3 B2 A2 B1 A1 B0 A0
C2 C1 C0
Full Adder Full Adder Full Adder
Full Adder
Cin
Cout S3 S2 S1 S0
Figure (2): A Binary Adder-Subtractor Circuit
The circuit has 4 full adders because we’re working with 4-bit numbers. There is a control line K that has a binary value
of 0 or 1, indicating whether the operation is addition or subtraction.
If the value of the Control line K is 1, the output of EX-OR gate is B0', which is the complement of B0. As a consequence,
the operation would be written as A + (B0'). Now, for two integers A and B, the 2’s complement subtraction is provided by the
expression A + B'. This means that when K is 1, the four-bit numbers are being subtracted from each other. Similarly If the value
of K is zero, the output of EX-Or gate is B0. In this case, the operation is A + B, which is a straightforward binary addition. This
indicates that when K= 0, the four-bit integers are being added.
As illustrated in the figure, the first full adder receives its input directly. The input carry Cin is given directly from the
control line, and A0, which is the least significant bit of A is also directly given to the first full adder. The Output of EX-OR gate
(i.e.., EX-OR of B0 and K) is used as the third input. Sum/Difference (S0) and Carry (C0) are the two outputs produced.
The least significant portion of the sum/difference is recorded as the sum/difference S0. After that, C0 is serially given to
the second full adder as one of its inputs. The second, third, and fourth full adders all get direct inputs from A1, A2, and A3. The
second input is the output of EX-Or gate, that is, B1, B2, and B3 EXORed with K, which is then sent to the second, third, and
fourth full adders, respectively. A serial transfer of the carry values C1, C2 is made to the succeeding full adder, which uses them
as one of its inputs. The total carry to the sum/difference is represented by C3. S1, S2, and S3 are recorded in order to create the
outcome with S0.

Q7. Write a VHDL code to implement binary adder subtractor. Oct./Nov.-19, Set-1, Q5(b)
Ans:
VHDL Code for 4-bit Adder / Subtractor is as follows
--FULL ADDER
library ieee;
use ieee.std_logic_1164.all;
entity Full_Adder is
port( X, Y, Cin : in std_logic;
sum, Cout : out std_logic);
end Full_Adder;
architecture bhv of Full_Adder is
begin
sum <= (X XOR Y) XOR Cin;
Cout <= (X and (Y or Cin)) or (Cin and Y);
end bhv;
--4 bit Adder Subtractor
library ieee;
entity addsub is
port( K: in std_logic;
A,B : in std_logic_vector(3 downto 0);
S : out std_logic_vector(3 downto 0);
Cout, OVERFLOW : out std_logic);
end addsub;
architecture struct of addsub is
component Full_Adder is
port( X, Y, Cin : in std_logic;
sum, Cout : out std_logic);
end component;
signal C1, C2, C3, C4: std_logic;
signal TMP: std_logic_vector(3 downto 0);
begin
TMP(0)<= K XOR B(0); -- when K=1 the adder/subtractor performs subtraction
TMP(1)<= K XOR B(1); -- when K=0 the adder/subtractor performs addition
TMP(2)<= K XOR B(2);
TMP(3)<= K XOR B(3);
FA0:Full_Adder port map (A(0),TMP(0),K, S(0),C1);
FA1:Full_Adder port map (A(1),TMP(1),C1, S(1),C2);
OVERFLOW <= C3 XOR C4 ;
Cout <= C4;
end struct;
--A port map maps signals in architecture to ports on an instance within that architecture. In this case it maps to Full adder.
Q8. Design a full subtractor with logic gates and write VHDL data flow program for the implementation of
the above subtractor. (Model Paper-3, Q3(a) | March-21, Set-1, Q5(a))
(or)
Design full subtractor circuit and write a VHDL code for implementation of full subtractor.
Ans: The truth table for a full subtractor is shown below.
A B C D Bi
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Table
Q D = A – (B + C)
Where, ‘Bi’ stands for BORROW and ‘D’ stands for DIFFERENCE.
Difference
D = A B C + A B C + A B C + ABC
= A ( B C + B C ) + A ( B C + BC)
= A (B ⊕ C) + A ( B ⊕ C )
∴D =A ⊕ B ⊕ C
Borrow
Bi = A B C + A B C + A BC + ABC
= A ( B C + B C ) + BC (A + A )
= A B C + A B C + BC
= A B C + B (C + C A )
= A B C + B (C + A )
= C + BC + B A
= C ( B + A)+BA
= C (B + A ) + B A
= BC + A C + A B
Therefore, the full subtractor circuit is as shown in figure (1).
A B C
Bi
Figure (1) : Logic Diagram of Full Subtractor

A full subtractor can also be designed by using a full
Decimal Binary Binary Coded
adder, IC 74 × 999 by replacing Y, Cin, COUT and sum with
number number Decimal(BCD)
active low ‘Y’. Active low ‘B in’, active low ‘B out’ and
difference(D) respectively. The logic symbol of full subractor 0 0000 0000
is shown in figure (2). 1 0001 0001
1 2 2 0010 0010
X Y 3 0011 0011
74 × 999
5 3 4 0100 0100
Bout Bin
5 0101 0101
D 6 0110 0110
4
7 0111 0111
Figure (2) : Logic Symbol of Full Subtractor 8 1000 1000
VHDL Code 9 1001 1001
library IEEE; 10 1010 0001 0000
use IEEE.STD_LOGIC_1164.all; 11 1011 0001 0001
entity F_S is 12 1100 0001 0010
port (A, B, C: in STD_LOGIC ; Bi, D : out STD_ 13 1101 0001 0011
LOGIC);
14 1110 0001 0100
end F_S;
15 1111 0001 0101
architecture F_S1 of F_S is
Table (1): BCD Equivalent of Decimal numbers
begin
process (A, B, C) BCD Addition
begin To make a BCD addition
D <= (A XOR B XOR C); 1. Add the BCD digits together as if they were conventional
Bi <= ((B AND C) OR (NOT A AND C) OR (NOT binary numbers.
A AND B)); 2. It is a valid BCD digit if the sum is 9 or less and no carry
end process; was created.
end F_S1; 3. If the addition yields a carry, the amount is incorrect,
Q9. What is BCD? Explain how to perform BCD and to obtain correct value we must add 0110 (6) to the
Addition. sum produced.
Ans: 4. If the result is more than nine, the result is incorrect, and
BCD is acronym for binary coded decimal. In this to obtain correct value we must add 0110 (6) to the sum
coding system each of the ten decimal digits (numbers) 0 -9 are produced.
represented by a four bit equivalent binary number as illustrated This procedure should be repeated for each BCD digit.
in table (1). In BCD, we can only utilize the binary numbers
0000-1001, which correspond to the decimal equivalents of 0-9 The addition of BCD values can be accomplished with
in the decimal equivalents. If a number has two decimal digits, the help of the 4-bit binary adder IC (7483). In this case, if the
its equivalent BCD will be an eight digit binary number obtained four-bit output produced is not a valid BCD digit, or if a carry
by replacing each decimal digit with its BCD equivalent. This C3 is produced, then decimal 6(0 11 0 binary) must be added to
is illustrated in table (1) for the numbers 10 to 15. For a clearer the sum in order to obtain the right result. A 1-digit BCD adder
understanding, decimal 45 is represented in BCD as of 0100 is depicted in Figure (1). It is possible to cascade BCD adders
0101. In BCD notation, the binary codes 10 to 15, i.e. 1010, in order to add numbers with multiple digits by connecting the
1011, 1100, 1101, 1110, and 1111, are prohibited (invalid). carry-out of one step to the carry-in of the following stage.
BCD Inputs
A B
A3 A2 A1 A0 B3 B2 B1 B0
4-bit Adder (AD1) C–1
Logic 0
C3 S3 S2 S1 S0
Logic 0
A'3A'2 A'1 A'0 B'3 B'2 B'1 B'0
4-bit Adder (AD2) C'–1
C3 S'3 S'2 S'1 S'0
Ones
Tens
BCD Outputs
Figure (1): One Digit BCD Adder

Q10. Write VHDL Code for BCD Adder?
Ans:
VHDL Code for BCD Adder is as follows
library ieee;
use ieee.numeric_std.all;
entity BCD_ADD is
port ( X,Y : in unsigned(3 downto 0); -- four digit input numbers to be added
CIN : in std_logic; -- Single digit Input carry
SUM : out unsigned(3 downto 0); -- four digit output sum
COUT : out std_logic ); -- single digit output carry
end BCD_ADD;
architecture arch of BCD_ADD is
begin
Process(X,Y)
variable sum_short : unsigned (4 downto 0); --five digit temporary variable output.
begin
sum_short := (‘0’ & X) + (‘0’ & Y) + (“0000” & CIN); -- Inputs are stringed with 0’s.
if (sum_short > 9) then
COUT <= ‘1’;
SUM <= resize((sum_short + “00110”),4);
else
COUT <= ‘0’;
SUM <= sum_short(3 downto 0);
end if;
end process;
end arch;
--In the above process as sum_short is a five digit number, the input X and Y are concatenated (combined/ linked) with
‘0’ and CIN with ‘0000’ (that is (‘0’ & X), (‘0’ & Y) and (“0000” & CIN)). This is because VHDL requires the operands of an
arithmetic operation to have the same number of bits as in the result.

2.2 Multiplexers Demultiplexers and

and their Integrated Description Output
circuit number
Use in Combinational Logic Design
74157 Quad 2:1 Multiplexer Same as input
Q11. What is a multiplexer? Explain its advantages.
74158 Quad 2:1 Multiplexer Inverted input
Also list the standard ICs available for
74153 Dual 4:1 Multiplexer Same as input
multiplexers.
74352 Dual 4:1 Multiplexer Inverted input
Ans: 74151 8:1 Multiplexer Complementary
outputs
The multiplexer, also known as a data selector circuit
is a unique combinational circuit that selects one of multiple 74152 8:1 Multiplexer Inverted input
inputs and routes it to a single output. The block diagram of a 74150 16:1 Multiplexer Inverted input
multiplexer with n input lines and one output line can be seen Table (1): Multiplexers available in IC’s
in Figure (1). The input chosen (for connection to the output)
Advantages
in a multiplexer is controlled by a set of select inputs. A set of
m select inputs, such that 2m = n, is needed to select one of n The following are some of the benefits of using
multiplexers:
inputs for connection to the output. Depending on the digital
code used at the select inputs, one of n data sources is chosen 1. It is not necessary to simplify the logic phrase.
and delivered to a single output channel. An enable input (G) is 2. It reduces the number of IC packages.
usually included to aid in cascading, and it is usually active-low,
3. The logic design process has been simplified.
meaning it carries its designated function when it is LOW.
Q12. Design a 2 to 1 multiplexer with logic gates and
I0 also write a VHDL code for it.
I1
Ans:
I2
Inputs n:1 The block diagram representation of 2 × 1 multiplexer
I3 Y
Multiplexer is as shown in figure (1).
Output
In–1
x0
G
2×1 y
MUX
Sm-1 S2 S1 S0 x0
Select inputs
Figure (1): 2 × 1 Multiplexer
Figure (1): Block Diagram of Multiplexer
2 × 1 multiplexer circuit consists of two inputs, one out-
Its output, Y, is calculated as follows put and one selection line. The truth table of 2 × 1 multiplexer
Y = G . [ S m – 1. S m – 2 ... S 1. S 0 .I0 + S m – 1. S m – 2 ... S 1.S0 .I1 + .... is as shown in below table.
+ Sm – 1.Sm – 2 ...S1. S 0 .In – 2 + Sm –1.Sm – 2 ...S1.S0 .In – 1] s y
In digital design, Multiplexer is one of the most 0 x0
extensively used standard logic circuits and is conveniently 1 x1
used as a logic element in the design of combinational circuits.
Table
Due to its frequent application, it has been built as an MSI
integrated circuit and is commercially available in a variety of From the above truth table, the Boolean expression for
configurations, like 2:1, 4:1, 8:1, and 16:1 multiplexers. Table 2 × 1 mux is obtained as,
(1) illustrates the standard 2:1, 4:1, 8:1 and 16:1 ICs available. y = x0 s + x1s
The logic diagram of 2 × 1 multiplexer is as shown in figure (2).
x0
s y
x1

VHDL Code
VHDL code for 2 × 1 multiplexer using selection signal assignment in data flow style is shown below,
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY MUX2to1 IS
PORT (x0, x1, s : IN STD_LOGIC;
y : OUT STD_LOGIC);
END MUX2to1;
ARCHITECTURE dataflow of MUX2to1 IS
BEGIN
WITH s SELECT
y < = x0 WHEN ‘0’,
x1 WHEN OTHERS;
END dataflow;
Q13. Design a 4 × 1 multiplexer and write a VHDL code for it.
Ans: 4 × 1 multiplexer circuit consists of 4-input lines, two selection input lines and single output line. The block diagram
representation of 4 × 1 multiplexer is as shown in figure (1).
x0
x1
4×1 y
x2
x3
s0 s1
Figure (1)
s0, s1 are the selection inputs, based on the selection input the output data is selected, that is illustrated in the following
truth table.
s1 s0 y
0 0 x0
0 1 x1
1 0 x2
1 1 x3
Table

From the above truth table the boolean expression for 4 × 1 multiplexer is obtained as,
y = s1s0 x0 + s0 s1 x1 + s0 s1 x2 + s0 s1 x3
The logic circuit of 4 × 1 multiplexer is as shown in figure (2).
s0
s1
x0
x1
x2
x3

VHDL Code
LIBRARY ieee;
ENTITY MUX4to1 IS
PORT (x0, x1, x2, x3 : IN STD_LOGIC;
s : IN STD_LOGIC_VECTOR (1 DOWN TO 0)
y : OUT STD_LOGIC);
END MUX4to1;
ARCHITECTURE dataflow OF MUX4to1 IS
BEGIN
WITH s SELECT
y < = x0 WHEN “00”,
x1 WHEN “01”,
x2 WHEN “10”,
x3 WHEN OTHERS;
END dataflow;
Q14. Using a process statement write a VHDL source code for 4 to 1 multiplexer.
Ans: (Model Paper-4, Q3(a) | Oct./Nov.-19, Set-4, Q5(b))
VHDL source code for 4 to 1 multiplexer using a process statement is given below.
library IEEE;
use IEEE. STD_LOGIC_1164. all;
entity MUX_4 to 1 is
port (w, x, y, z : in LOGIC;
S0, S1: in STD_LOGIC;
P : out STD_LOGIC);
end MUX_4 to 1
architecture behaviour of MUX_4 to 1 is
begin For S2 = 0, S1 = 0, S0 = 0, Y = I S S S
0 2 1 0
Process (w, x, y, z, S0, S1) is
For S2 = 0, S1 = 0, S0 = 1, Y = I S S S
begin 1 2 1 0
if (S0 = ‘0’ and S1 = ‘0’) then For S2 = 0, S1 = 1, S0 = 0, Y = I S S S

2 2 1 0
P <= w; For S2 = 0, S1 = 1, S0 = 1, Y = I S S S
3 2 1 0
els if (S0 = ‘1’ and S1 = ‘0’) then
For S2 = 1, S1 = 0, S2 = 0, Y = I S S S
P <= x; 4 2 1 0
elsif (S0 = ‘0’ and S1 = ‘1’) then For S2 = 1, S1 = 0, S0 = 1, Y = I S S S

5 2 1 0
P <= y; For S2 = 1, S1 = 1, S0 = 0, Y = I S S S
6 2 1 0
else P <= z;
For S2 = 1, S1 = 1, S0 = 1, Y = I S S S
end if; 7 2 1 0
end process; The expression for the output (Y) can be written as
end behaviour; S2 S1 S0 I0 + S2 S1S0 I1 + S2 S1 S0 I2 + S2 S1S0 I3 +
Y =
Q15. What is multiplexer? Draw the logic diagram of S2 S1 S0 I4 + S2 S1S0 I5 + S2 S1 S0 I6 + S2 S1S0 I7
8 to 1 line multiplexer.
Ans: (Model Paper-1, Q3(b) | Oct./Nov.-19, Set-3, Q5(a))
The implementation of 8 × 1 MUX requires 4-input
Multiplexer eight AND gates, three NOT gates and an OR gate. Each of the
For answer refer Unit-2, Q11, (Refer upto figure (1)). inputs I0, I1, I2, ...I7 are applied to the AND gates A0, A1, A2, ...
A 8 × 1 multiplexer is a combinational circuit that A7. The logic circuit for 8 × 1 multiplexer can be obtained by
consists of eight input lines (i.e., I0, I1, I2, ... I7), three selection implementing the output expression as shown in figure (2).
lines (S0, S1 and S2) and one output line Y. The block diagram
I0
of 8 × 1 multiplexer is shown in figure (1). A0
I0
I1 I1
I2 A1
I3 8×1 yY
I4 mux
MUX
I5 I2
I6
A2
I7
EN
I3
A3
S2 S1 S0
Figure (1): Block Diagram of 8 × 1 MUX Y

I4
The truth table of 8 × 1 multiplexer is shown in table. A4
Select Lines Output
S2 S1 S0 Y I5
A5
0 0 0 I0
0 0 1 I1 I6
A6
0 1 0 I2
0 1 1 I3 I7
1 0 0 I4 A7
1 0 1 I5
S2
1 1 0 I6 S1
S0 E
1 1 1 I7
Table: Truth Table Figure (2): Logic Circuit of 8 × 1 MUX

Q16. Design a 16 × 1 multiplexer using 4 × 1 multiplexers and also write a VHDL code for 16 × 1 MUX.
Ans:
16 × 1 multiplexer comprises of 16 input lines namely x0, x1....x15, four selection lines (s0, s1, s2 and s3) and a single output. It is
constructed by using five 4 × 1 multiplexers. The implementation of 16 × 1 multiplexer using 4 × 1 multiplexers is as shown in figure.
x0
x1
4×1
x2
x3
s1
s0
x4
x5
4×1
x6
x7
4×1 y
x8
x9
4×1 s2 s3
x10
x11
x12
x13
4×1
x14
x15
Figure: 16 × 1 Multiplexer
VHDL Code
LIBRARY ieee;
LIBRARY work;
USE work.MUX4TO1 _ package.all;
ENTITY MUX16to1 IS
PORT (x : IN STD_LOGIC_VECTOR (0 to 15);
s : IN STD_LOGIC_VECTOR (3 DOWN TO 0);
y : OUT STD_LOGIC);
END MUX16to1;
ARCHITECTURE struct of MUX16to1 IS
SIGNAL K : STD_LOGIC_VECTOR (0 to 3);
BEGIN
M1 : MUX4to1 PORT MAP (x(0), x(1), x(2), x(3), s(1 DOWN TO 0), k(0));
M4 : MUX4to1 PORT MAP (x(12), x(13), x(14), x(15), s(1 DOWN TO 0), k(3);
M5 : MUX4to1 PORT MAP (m(0), m(1), m(2), m(3), s(3 DOWN TO 2), y);
END struct;
Q17. Draw the logic diagram, logic symbol of 74 × 151.
Ans: 74 × 151 is a Medium Scale Integrated (MSI) multiplexer which selects 1 output for eight inputs i.e., it is an 8:1 MUX.
The logic diagram and symbol of 74 × 151 are shown in figure (1) and (2) respectively,
(7)
EN_L
(4)
A
(3)
B
(2)
C
(1)
D (5) M_OUT
(6) M_OUT_L
(15)
E
(14)
F
(13)
G
(12)
H
(11)
S0
(10)
S1
(9)
S2
Figure (1): Logic Diagram of 74 × 151

74 × 151
7
Enable input EN
11 S0
Select 10 S1
inputs 9 S2
4 5
A M_OUT
3 B 6 Output pins
2 M_OUT
C
Data 1 D
inputs 15 E
14 F
13 G
12 H
Figure (2): Logic Symbol Of 74 × 151

The truth table for a 74 × 151 8-input, 1-bit MUX is as The logic symbol of 74 × 157 IC is shown in figure (2).
shown in table. 15 G
1 S 74 ×157
Inputs Select Line Outputs 2 1A
1X 4
3 1B
2X 7
EN_L S2 S1 S0 M_OUT M_OUT_L 5 2A
3X 9
6 2B
11 3A 4X 12
1 X X X 0 1 10 3B
14 4A
0 0 0 0 A A' 13 4B
0 0 0 1 B B' Figure (2)

0 0 1 0 C C'
74 × 157 is a 16-pin package MUX, it selects between
0 0 1 1 D D' two 4-bit inputs applied to it.
0 1 0 0 E E' Q19. With the help of logic diagram explain 74×157
0 1 0 1 F F' multiplexer. Write the data flow style VHDL
program for this IC.
0 1 1 0 G G'
0 1 1 1 H H'
74 × 157 Multiplexer
Table
For answer refer Unit-2, Q18.
Q18. Give the logic diagram of 74 × 157 and explain
Data Flow Style
its truth table.
library IEEE;
Ans:
IC 74 × 157 is a 2-input and 4-bit multiplexer, whose
logic diagram is shown in figure (1). entity MUX is
G_L port (S : in STD_LOGIC_VECTOR (1 downto 0);

S
A, B : in STD_LOGIC_VECTOR (1 to 4);
X : out STD_LOGIC_VECTOR (1to 4));
1A
1X end MUX;
1B
architecture MUX1 of MUX is
2A
2B
2X begin
3A
process (S, A, B)
3B
3X
begin
4A with S select X < = A when “0”;
4X
4B B when “1”;
Figure (1): Logic Diagram of 74 × 157 Multiplexer end process;

The truth table for 74 × 157 multiplexer is shown below. end MUX1;
G_L S 1X 2X 3X 4X Q20. Design a 32 to 1 multiplexer using four 74 × 151

multiplexers and 74 × 139 decoder.
1 X 0 0 0 0
0 0 1A 2 A 3 A 4 A Ans:
0 1 1B 2 B 3 B 4 B A 32 to 1 multiplexer requires five select inputs, so in
order to design it, we require four 74 × 151 multiplexers and a
Table 74 × 139 decoder. The five selected inputs are namely XA0, XA1,
Where, G_L is active-low enable input and S is select XA2, XA3 and XA4. XA0, XA1 and XA2 are input to 74 × 151
input. multiplexers whereas XA3 and XA4 are inputs to 74 × 139 decoder.
The design is shown in the figure.
74 ×× 151
7
XA0 EN
11
XA1 10 A
XA2 B
9
C 5
4 Y
X0 3 D0
X1 D1 6 XO0_L
2 Y
X2 D2
1
X3 15 D3
X4 D4
14
X5 D5
13
X6 D6
12
X7 D7 U2
74 ×× 151
7
EN
11
A
10
B
9
C 5
4 Y
X8 D0
3
X9 2
D1 6 XO1_L
D2 Y
X10 1
X11 D3
15
X12 D4
14
X13 D5
13
X14 D6
12
X15 D7 U3 1 ½ 74 × 20
½74×139
74 × 2 6
1 4 74 ×× 151 4 Xout
XEN_L 1G 1Y0
5 5 U6
1Y1
2 1Y2 6 7 EN
XA3 1A
3 1Y3 7 11 A
XA4 1B
10 B
U1 9 5
C Y Y
4 D0
X16 6 XO2_L
X17 3 D1 Y Y
X18 2 D2
1 D3
X19
X20 15 D4
X21 14 D5
13 D6
X22
12 D7 U4
X23
74 ×× 151
7
EN
11
A
10
B
9
C 5
4 Y
X24 D0
3
X25 D1 6 XO3_L
2 Y
X26 D2
1
X27 D3
15
X28 D4
14
X29 D5
13
X30 D6
12 U5
X31 D7
Figure: Combining 74 × 151 ICs to Make a 32-to-1 Multiplexer
The output of respective multiplexers are given to OR gate (1/2 74 × 20) that produces the output Xout.

Q21. What is a Demultiplexer? Explain. Also list the standard ICs available for Demultiplexer.
Ans:
A demultiplexer is a device that accomplishes the opposite of a multiplexer. It takes a single input and splits it into many
outputs. The block diagram of a demultiplexer is as illustrated in Figure (1). The input data is sent to one of the outputs based on
the value (code) given to select input pins.
D0
D1
D2
Data input Demultiplexer/ D3
Di Decoder D4 Outputs
Dn – 1
Sm – 1 Sm – 2 S0
Select inputs
Figure (1): Block Diagram of Demultiplexer
As illustrated in figure (1), there are n output lines and m select lines, such that n = 2m. The input data Di will show up
on the output line specified by the select inputs S0….Sm – 1. For instance, the data will be displayed on the D4 output line, if the
decimal equivalent of the select inputs is 4. The logic I level should be connected to the data input line.
This device, on the other hand, is available as an MSI Integrated Circuit and may be used to create combinational
circuits in a convenient manner. Table (1) illustrates the available standard demultiplexer ICs there description and output. Few
of the ICs can be used as both Demultiplexers and Decoders.
Integrated circuit number Description Output
Dual 1:4 Demultiplexer Inverted input
74139
(2-line-to-4-line decoder)
Dual 1:4 Demultiplexer 1 Y-Inverted input
74155
(2-line-to-4-line decoder) 2Y-Same as input
Dual 1:4 Demultiplexer Open collector
74156 (2-line-to-4-line decoder) 1 Y-Inverted input
2Y-Same as input
1:8 Demultiplexer Inverted input
74138
1:16 Demultiplexer Same as input
74154
1:16 Demultiplexer Same as input
74159
(4-line-to-16-line decoder) Open-collector
Table (1): Multiplexers available in IC’s
2.3 ALU
Q22. What is ALU? Draw the block diagram of 74181ALU and Explain.
Ans:
ALU is an acronym for Arithmetic Logic Unit, and is the heart of any microprocessor. The ALU is a combinational
circuit that is extremely popular and frequently utilized since it is capable of performing both arithmetic and logical operations
on a pair of bit operands. In an ALU, a group of function select inputs are used to perform the required operation.
A 0 – A3 F0 – F3
Cn + 4 Carry output
B0 – B3 74181 ALU A = B Equality Output
G = Generate Output
P = Propagate Output
Cn Carry Input
Open-Collector Output
Select Inputs S0 – S3 Mode Control M

Figure (a): Block Diagram of 74181ALU
The block diagram of the 74181 ALU is as illustrated in figure (a). The roles of various input, output, and control lines are
described as follows :
v Four-bit binary data inputs are represented by the letters A0 - A3 and B0 - B3, respectively.
v The letter Cn and Cn + 4 represents carry input and carry output respectively and both are active low. Active low means that
signal will be performing its function when its logic level is 0. Further, when performing a subtraction operation, the Cn
+ 4 display the sign of the output result. A positive outcome is denoted by logic 0, and a negative result is denoted by logic
1, which is stated in the 2’s complement form.
v Four-bit binary data output is represented by the letter F.
v The output pins G and P are useful when the 74181ALU is cascaded along with a number of 74182 Carry-Look-ahead
adder circuits to make the arithmetic operations faster. In this, G represents Carry generate output and P represents Carry
propagate output.
v When the input A equals the input B, a logic 1 appears on the pin A = B.
v Whether ALU is used for arithmetic operation are logical operation is decided by the mode control pin M. M = 0 indicates
ALU is performing arithmetic operations and M = 1 indicates ALU is performing Logical operations.
v There are a number of different arithmetic and logical operations available. The select inputs S0 - S3 determine which arithmetic
or logical operation is to be executed. Table (1) gives the different operations performed for different values of S0 - S3.
Active High Data

Selection M=1 M = 0 ; Arithmetic Operations
Line Logic C n (no carry) C n = 0 (with carry)
S3 S2 S1 S0 Functions
0 0 0 0 0 F= A F=A F = A PLUS 1
1 0 0 0 1 A+B F=A+B F = (A + B) PLUS 1
2 0 0 1 0 F=0 F = MINUS 1 (2’s COMPL) F = (A + B ) PLUS 1
3 0 0 1 1 F = AB F = A PLUS A B F = ZERO
4 0 1 0 0 F= B F = (A + B) PLUS A B F = A PLUS AB PLUS 1
5 F = A5 B F = A MINUS B MINUS 1 F = A MINUS B
0 1 1 0
6 F = A B MINUS 1 F =AB
0 1 1 1 F =A B
7 F = A PLUS AB F = A PLUS AB PLUS 1
1 0 0 0 F= A+B
8
1 0 0 1 F=A5B F = A PLUS B F = A PLUS B PLUS 1
9
1 0 1 0 F=B F = (A + B ) PLUS AB F = (A + B ) PLUS AB PLUS 1
10
F = AB F = AB MINUS 1 F = AB
11 1 0 1 1
F=1 F = A PLUS A* F = A PLUS A PLUS 1
12 1 1 0 0
F=A+B F = (A + B) PLUS A F = (A + B) PLUS A PLUS 1
13 1 1 0 1
F=A+B F = (A + B ) PLUS A F = (A + B ) PLUS A PLUS 1
14 1 1 1 0
F=A F = A MINUS 1 F=A
15 1 1 1 1

Q23. Design an 8-bit ALU circuit using 74LS181 IC’s and write its VHDL code.
In order to cascade the 74181, you must connect the carry-out of one-stage to the carry-in of a subsequent stage.
Implementation of an 8-bit ALU Circuit using 74LS181 IC’s: A 74LS181 IC is a 4-bit Arithmetic Logic Unit (ALU), which
performs 16-bit arithmetic/logical operations on two 4-bit operands.
An 8-bit ALU circuit can be implemented by cascading two 74LS181 ICs that performs 16-bit arithmetic/logical operations
on two 8-bit operands as shown in figure below.
Cout
S0 – S3 S0 – S3 Cout G G2
M M P P2
x4 A0
x5 A1 F0 Z4
x6 A2 74LS181
(ALU2) F1 Z5
x7 A3
y4 B0 F2 Z6
y5 B1
y6 B2 F3 Z7
y7 B3 Cin A=B AL = BL
Cout
S0 – S3 G G1
M P P1
x0 A0 F0 Z0
x1 A1 74LS181
x2 A2 F1 Z1
(ALU1)
x3 A3 F2 Z2
y0 B0
y1 B1 F3 Z3
y2 B2
y3 B3 Cin A=B AH = BH
Figure
In the above figure, the mode and select inputs of ALU1 and ALU2 are connected in parallel such that the synchronization
between operating modes as well as the functions performed by both the ICs is maintained. The Cin of ALU 1 is connected to
ground. Inorder to have the carry propagation from one stage to next stage, Cout of ALU 1 is connected to Cin of ALU 2. The Cout
of ALU 2 represents the final carry. The functions performed by 8-bit ALU are shown in below table.
Inputs Function
S3 S2 S1 S0 M = 0 (Arithmetic) M = 1 (Logic)
0 0 0 0 Z = x – 1 + Cin Z = x'
0 0 0 1 Z = (x.y) –1 + Cin Z = x' + y'
0 0 1 0 Z = (x.y') – 1 + Cin Z = x' + y
0 0 1 1 Z = 1 1 1 1 + Cin Z=1111
0 1 0 0 Z = x + (x + y') + Cin Z = x'.y'
0 1 0 1 Z = (x.y) + (x + y') + Cin Z = y'
0 1 1 0 Z = x – y – 1 + Cin Z = x y'
0 1 1 1 Z = x + y' + Cin Z = x + y'
1 0 0 0 Z = x + (x + y) + Cin Z = x'.y
1 0 0 1 Z = x + y + Cin Z=x y
1 0 1 0 Z = (x.y') + (x + y) + Cin Z=y
1 0 1 1 Z = x + y + Cin Z=x+y
1 1 0 0 Z = x + x + Cin Z=0000
1 1 0 1 Z = (x.y) + x + Cin Z = x.y'
1 1 1 0 Z = (x.y') + x + Cin Z = x.y
1 1 1 1 Z = x + Cin Z=x
Table
VHDL Code
The VHDL code for 4-bit ALU (74 × 381 IC) chip is mentioned below,
Library IEEE;
Use IEEE.STD_LOGIC_1164.ALL;
Use IEEE.STD_LOGIC_UNSIGNED.ALL;
Entity ALU is,
Port (S : IN STD_LOGIC_VECTOR(2 downto 0);
AB: IN STD_LOGIC_VECTOR(3 downto 0);
F : OUT STD_LOGIC_VECTOR(3 downto 0);
CIN: IN STD_LOGIC);
End ALU;
Architecture ALU_arch of ALU is,
Begin
Process (S, A, B)
Begin
CASE S is
WHEN “000” F “0000”;
WHEN “001” F B – A – 1 + CIN;
WHEN “010” F A – B – 1 + CIN;
WHEN “011” F A + B + CIN;
WHEN “100” F A XOR B;
WHEN “101” F A OR B;
WHEN “110” F A AND B;
WHEN OTHERS F “1111”;
END CASE
END Process;
END ALU_arch;

Q24. Design a 16-bit ALU using 74 × 381 and 75 × 182 ICs. Implement VHDL code for the same.
Ans:
A 16-bit ALU can be designed using 74 × 381 and 74 × 182 ICs as shown in figure.
The 74 × 381 MSI ALU compactly encodes the select inputs and provides eight different functions. The 74 × 381 gives
provision for the cascading of multiple inputs without carries rippling between 4-bit groups as it provides group-carry look ahead
outputs.
The 74 ×182, a look ahead carry circuit combines the group-carry look ahead outputs of the cascaded ALU’s in only two
levels of logic by producing the carry input to every ALU.
S(2-0)
X(15-0)
Y(15-0)
S
S1 0 S
S0 3
S1 S
S0
S
S2 S
S1
S
S0 S
S1 J
S
S3 J S
S2
S
S2 S
S2
C IN K K
CIN
X0 X
X12
X0 X
X0
Y0 Y
Y12
Y0 Y
Y0
X1 X
X13 74 × 381
X1 X
X1
Y1 Z
Z0 Y
Y13 Z
Z12
Y1 Z
Z0 Y
Y1 Z
Z0
X2 Z
Z1 X
X14 Z
Z13
X2 Z
Z1 X
X2 Z
Z1
Y2 Z
Z2 Y
Y14 Z
Z14
Y2 Z
Z2 Y
Y2 Z
Z2
X3 Z
Z3 X
X15 Z
Z15
X3 Z
Z3 X
X3 Z
Z3
Y3 Y
Y15
Y3 Y
Y3
74×381
S0 2
S
S0 1 S
S0
S
S0 S1
S
S1 S
S1
S
S1 S2
S
S2 J S
S2 J
S
S2
C IN K
CIN K
X
X8
X
X4 X
X0
X0
X0 Y
Y8
Y
Y4 Y
Y0 74 × 381
Y
Y0 X
X9
X
X5 X
X1
X
X1 Y
Y9 Z
Z8
Y
Y5 Z
Z4 Y
Y1 Z
Z0
Y
Y1 Z
Z0 X
X10 Z
Z9
X
X6 Z
Z5 X
X2 Z
Z1
X
X2 Z
Z1 Y
Y10 Z
Z10
Y
Y6 Z
Z6 Y
Y2 Z
Z2
Y
Y2 Z
Z2 X
X11 Z
Z11
X
X7 Z
Z7 X
X3 Z
Z3
X
X3 Z
Z3 Y
Y11
Y
Y7 Y
Y3
Y
Y3
Z(15 – 0)
74×381
C
C0
C
C1 C
C2
C
C0 C
C3
J
J0
K
K0
J
J1 74×182
K
K1
J
J2
K
K2
J
J
J3
K
K
K3
Figure
VHDL Code
library IEEE;
entity ALU_16 bit is
port(A, B : in STD_LOGIC_VECTOR (15 down to 0);
S : in STD_LOGIC_VECTOR (2 down to 0);
EN : in STD_LOGIC;
F : out STD_LOGIC_VECTOR (15 down to 0));
end ALU_16 bit;
architecture ALU_16 bit_arch of ALU_16 bit is
begin
if(EN = = ‘1’) then
case S is
when “000” => F <= A AND B;
when “001” => F <= A OR B;
when “010” => F <= A XOR B;
when “011” => F <= NOT A;
when “100” => F <= A + B;
when “101” => F <= A – B;
when “110” => F <= A * B;
when “111” => F <= A/B;
when others => F <= “xxxxxxxxxxxxxxxx”;
end case;
end if;
and ALU_16 bit_arch;
2.4 Digital Comparators
Q25. What is a comparator? Draw and explain the structure and working of a comparator.
Ans: A digital circuit that compares two binary words is called as comparator.
The 1-bit comparator can be built using Exclusive OR and Exclusive NOR gates.
The 1-bit comparator using Exclusive OR is shown in figure (1).
x z (Difference of x and y)
F
y
Figure (1)
In the above comparator, the output z is the difference of inputs x and y.
The n-bit comparators are called as parallel comparators.
4-bit Equality Comparator: Logic diagram of 4-bit equality comparator is shown in figure (2).
A0
B0
A1
B1
Output
A2
B2
A3
B3
Figure (2)

4-bit Magnitude Comparator
The block diagram shown in figure (3) indicates the 4-bit magnitude comparator.
x3 y3 x2 y2 x1 y1 x0 y0
G4
G3 G2 G1 G0
1 bit comp. 1 bit comp. 1 bit comp. 1 bit comp.
L3 L2 L1 L0
L4
Figure (3)
The 4-bit magnitude comparators perform comparison of straight binary or BCD codes. These devices are fully expandable
to any number of bits without external gates.
The logic symbol for IC 74 × 85 4-bit comparator is shown in figure (4).
2 ALTBin ALTBout 7
3 AΕQBin AΕQBout 6
4 AGTBin AGTBout 5
10 A0
9 B0
12 A1 74 × 85
11 B1
13 A2
14 B2
15 A3
1 B3
Figure (4)
The 74 × 85 is a 4-bit magnitude comparator that can be expanded to almost any length. It compares two 4-bit binary,
BCD or other monotonic codes and presents the three possible magnitude results at the outputs.
Q26. Discuss about the implementation of comparator using digital IC.
The magnitude comparator comes under combinational circuits which performs comparison of magnitudes of any two
numbers and produces an output based on the comparison, whether the number is equal, greater or lesser than the other number
(i.e., A = B, A > B or A < B).
Let A0 and B0 are the inputs to be compared by a single-bit magnitude comparator as shown in figure(1).
A0 A0 > B0
Single-bit magnitude
comparator A0 = B0
B0 A0 < B0
Figure (1)
Consider, A = A3 A2 A1 A0 and B = B3 B2 B1 B0 are the two 4-bit numbers that are tho be compared using an IC7485 (a
4-bit magnitude comparator). It generates one output as a result of comparison i.e., either A = B, or A > B, or A < B.
The pin diagram of 4-bit magnitude comparator (IC7485) is shown in figure (2).
B2 VCC
A2 A3
(A=B)OUT B3
(A>B)IN 7485 (A>B)OUT
(A<B)IN (A<B)OUT
(A=B)IN B0
A1 A0
GND B1
Figure (2)
The input pins, i.e., (A < B)1N, (A = B)1N, (A > B)1N are meant for cascading. To realize an 8-bit comparator, cascading of
two 4-bit comparators is done as shown in figure (3).
Figure
The resultant cascaded comparator compares two 8-bit numbers, i.e., A7 A6 A5 A4 A3 A2 A1 A0 and B7 B6 B5 B4 B3 B2 B1 B0.
The the lower order comparator, the cascading input pins are connected as follows,
1. The cascading input (=) is connected to + 5 V (i.e., HIGH).
2. The cascading inputs (< and >) are connected to ground (i.e., LOW).
The truth table of 4-bit comparator IC is shown below.
Comparing Inputs Cascading Inputs Outputs

A3, B3 A2, B2 A1, B1 A0, B0 A>B AB A B2 × × × × × × 1 0 0
A3 < B3 × × × × × × 0 1 0
A3 = B3 A2 > B2 × × × × × 1 0 0
A3 = B3 A2 < B2 × × × × × 0 1 0
A3 = B3 A2 = B2 A1 > B1 × × × × 1 0 0
A3 = B3 A2 = B2 A1 > B1 × × × × 0 1 0
A3 = B3 A2 = B2 A1 > B1 A0 > B0 × × × 1 0 0
A3 = B3 A2 = B2 A1 > B1 A0 > B0 × × × 0 1 0
A3 = B3 A2 = B2 A1 > B1 A0 > B0 1 0 0 1 0 0
A3 = B3 A2 = B2 A1 > B1 A0 > B0 0 1 0 0 1 0
A3 = B3 A2 = B2 A1 > B1 A0 > B0 0 0 1 0 0 1
Table: Truth Table of IC 7485 4-bit Magnitude Comparator

Q27. Design a 12-bit comparator using 74×85 ICs.
Ans: 74 × 85 IC is a 4-bit MSI comparator, so in order to design a 12-bit comparator we have to cascade four 74 × 85 comparators.
The logic symbol for 74 × 85, 4-bit comparator is shown in figure (1).
2 ALTBin ALTBout 7
4 AGTBin AGTBout 5
10 A0
9 B0
12 A1 74 × 85
11 B1
13 A2
14 B2
15 A3
1 B3
Figure (1)
The 12-bit comparator using 74 × 85 IC is shown in figure (2).
2 ALTBin ALTBout 7 XLTY4 ALTBout XLTY8 ALTBin ALTBout XLTY
3 AEQBin AEQBout 6 XEQY4 AEQBout XEQY8 AEQBin AEQBout XEQY
4 AGTBin 5 XGTY4 XGTY8 XGTY
AGTBout AGTBout AGTBin AGTBout
a0 a4 a8
A0 A4 A8
b0 b4 b8
a1 B0 a5 B4 a9 B8
b1 A1 b5 A5 b9 A9
a2 B1 74 × 85 a6 B5 a10 B9 74 × 85
b2
A2 b6
A6 b10
A10
a3 B2 a7
B6 a11
B10
b3
A3 b7
A7 b11
A11
B3 B7 B11
A(11 : 0)
B(11 : 0)
Figure (2)
The outputs of each 74 × 85 IC are,
AGTBout = (A > B) + (A = B). AGTBin
AEQBout = (A = B) . (AEQBin)
ALTBout = (A < B) + (A = B) . ALTBin
Here, is the above equations ‘A’ stands for A3 to A0 and ‘B’ stands for B3 to B0.
Q28. Explain about comparator and design a 16-bit comparator using 74×85 IC’s. Write VHDL program.
For answer refer Unit-2, Q25 (Refer only 1st Paragraph).
16 bit Comparator using 74×85 ICs
74 × 85 IC is a 4-bit MSI comparator, so in order to design a 16-bit comparator four 74 × 85 comparators has to be cascaded.
The logic symbol for 74 × 85, 4-bit comparator is shown in figure (1).
2 ALTBin ALTBout 7
4 AGTBin AGTBout 5
10 A0
9 B0
12 A1 74 × 85
11 B1
13 A2
14 B2
15 A3
1 B3
Figure (1)
The 16-bit comparator using 74 × 85 IC is shown in figure (2).
74×85
Figure (2)
The outputs of each 74 × 85 IC are,
AGTBout = (A > B) + (A = B). AGTBin
AEQBout = (A = B) . (AEQBin)
ALTBout = (A < B) + (A = B) . ALTBin
In the above equations ‘A’ stands for A3 to A0 and ‘B’ stands for B3 to B0.
VHDL Code
Library ieee;
Use ieee_std_1164.all;
entity comp1 is
port(A, B: in STD_LOGIC;
EQ, GT: out STD_LOGIC);
end comp1;
architecture comp16_archi of comp16 is
component comp1
end comp1;
signal EQ16, GT16: STD_LOGIC;
signal SEQ, SGT: STD_LOGIC_VECTOR (16 down to 0);
SEQ(16) <= ‘1’; SGT(16) <= ‘0’;
U1 : for i <= ‘1’ generate
U2 : comp1 port map(A (1 + i * 16) down to i * 1), B(1 + i * 16 down to i * 1), EQ1(i), GT1 (i));
SEQ(i) <= SEQ(i + 1) and EQ16 (i);
SGT(i) <= SGT(i + 1) or (SEQ(i + 1) and GT16 (i));
end generate;
EQ <= SEQ(0);
GT <= SGT (0);
end comp16_archi;
Q29. What is meant by arithmetic comparison circuits? Design 4 bit comparator circuit using logic gates and
write a VHDL code for implementation of 4-bit comparator.
Ans: Model Paper-1, Q4(a)
Arithmetic Comparison Circuits

The combinational circuits which are used to perform the arithmetic operations are known as arithmetic circuits. Arithmetic
circuits which are used to perform the comparison operation are known as arithmetic comparison circuits. Usually the comparator
circuits perform equal to, greater than and less than operations.

Design of 4-bit Comparator
Comparator circuits consists of two inputs for comparison. In 4-bit comparator circuit each input consists of 4-bit length.
Consider input A = a3 a2 a1 a0 and input B = b3 b2 b1 b0. These inputs are subjected to comparator circuit then it performs a com-
parison operation by assuming the intermediate signal called ik = i3, i2, i1 and i0. If the indices of input A and B are equal and each
intermediate signal is ‘1’ then the output of comparator is given as,
ik = ak ⊕ bk
y ( A = B) = i3 i2 i1 i0
If a3 = 0 and b3 = 1 then comparator gives A B = a3b3 + i3 a2 b2 + i3i2 a1b1 + i3i2 i1a0 b0
Similarly,
A B) + ( A = B)
The logic circuit implementation above expressions of 4-bit comparator circuit is as shown in figure.
VHDL Code for 4-bit Comparator
LIBRARY ieee;
USE ieee.std_logic_unsigned.all;
ENTITY COMPARE IS
PORT (A : IN STD_LOGIC_VECTOR (3 DOWN TO 0);
B : IN STD_LOGIC_VECTOR (3 DOWN TO 0);
A = B : OUT STD_LOGIC;
A > B : OUT STD_LOGIC;
A3
B3
A2
B2
A1 A>B
B1
A0
B0
A3
B3
A2
B2
A=B
A1
B1
A0
B0
A3
B3
A2
B2
A1 A B < = ‘1’ WHEN A > B ELSE ‘0’;
A < B < = ‘1’ WHEN A < B ELSE ‘0’;
END Behaviour.
Q30. Write a VHDL code to implement the following,
(i) 1 bit comparator
(ii) 12 bit comparator using 1 bit comparator.
Ans:
(i) VHDL Program for 1-bit Comparator
Library ieee;
entity comp1 is
end comp1;
begin
EQ <= ‘1’ when A = B else ‘0’;
GT <= ‘1’ when A > B else ‘0’;
end comp1_archi;
(ii) 12-bit Comparator using 1-bit Comparator
Library ieee;
entity comp1 is
end comp1;
component comp1
end comp1;
signal EQ11, GT11: STD_LOGIC;
signal SEQ, SGT: STD_LOGIC_VECTOR (11 down to 0);
SEQ(11) <= ‘1’; SGT(11) <= ‘0’;
U1 : for i <= ‘1’ generate
U2 : comp1 port map(A (1 + i * 11) down to i * 1), B(1 + i * 11 down to i * 1), EQ1(i), GT1 (i));
SEQ(i) <= SEQ(i + 1) and EQ11 (i);
SGT(i) <= SGT(i + 1) or (SEQ(i + 1) and GT11 (i));
end generate;
EQ <= SEQ(0);
GT <= SGT (0);
end comp12_archi;

Q31. Design a 24-bit comparator using 74×682 ICs and explain the functionality of the circuit. Also implement
74 × 682 IC is an 8-bit comparator. It has 16 inputs and two outputs, one output expressing whether the input x is greater
than y and the second output expresses whether x is equal to y.
Where x and y are two sets of inputs, each having 8-pins.
In order to design a 24-bit comparator three 74 × 682 ICs are required. ( 3 × 8 = 24)
Figure: 24-bit Comparator Using 74 × 682 ICs

For x to be greater than y, any one of the following three equations is to be satisfied.
1. (x[23 : 16] > y[23 : 16]) OR
2. (x[23 : 16] = y[23 : 16] AND x[15 : 8] > y[15 : 8]) OR
3. (x[23 : 16] = y[23 : 16] AND x[15 : 8] = y[15 : 8] AND x[7 : 0] > y[7 : 0])
For x to be equal to y, the condition to be satisfied is
(x[23 : 16] = y[23 : 16] AND x[15 : 8] = y[15 : 8] AND x[7 : 0] = y[7 : 0])
The first IC is used to know whether the upper 8-bits of x is greater or equal to y and the second IC is used to know
whether the middle 8-bits of x is greater or equal to y and the third IC is used to know whether the lower 8-bits of x is greater or equal to y.
VHDL Source Code in Data Flow Style
entity comp is
port(A, B: in STD_LOGIC_VECTOR (23 downto 0);
end comp;
architecture comp_arch of comp is
component comp
port(A, B: in STD_LOGIC_VECTOR (23 downto 0);
end component;
signal EQ3, GT3: STD_LOGIC_VECTOR (2 downto 0);
signal SEQ, SGT: STD_LOGIC_VECTOR (3 downto 0);
begin
SEQ (3) <= ‘1’; SGT (3) <= ‘0’;
U1 : for i in 2 downto 0 generate
U2 : comp port map(A(7 + i * 3 down to i * 8), B (7 + i * 3 downto i * 8) , EQ 8(i), GT 8(i));
SEQ(i) <= SEQ(i+1) and EQ 3(i);
SGT(i) <= SGT(i+1) or (SEQ (i + 1);
end generate;
EQ <= SEQ(0);
GT <= SGT(0);
end comp_arch;
2.5 Parity Generators
Q32. What is Parity? Draw the Block Diagram of 74180 Parity Generator/Checker and Explain.
There is a concept known as parity, in which an additional bit known as the parity-bit is added to a binary word in
order to make the number of 1’s in the new word generated even (even parity) or odd (odd parity). The additional bit, known
as the parity bit, is added to each coded (binary) word for detection of errors.
The parity check detects the erroneous code at the receiving end if there is just one error. Also, parity check will
detect the incorrect code if an odd number of bits are transmitted incorrectly, but not if an even number of bits are received
incorrectly. The parity check method can only detect errors in the received word.
Using gates, we can make circuits that generate parity bits, as well as check the parity of a word. Due to the widespread
use of this circuit, an 8-bit parity generator/checker was developed and is made available in the form of an integrated circuit
(MSI chip) 74180. Figure (a) illustrates the block diagram of the 74180 parity generator/checker, which includes eight parity
inputs (designated A through H) and two cascade inputs. The two possible outputs are denoted as “Σeven” and “Σodd”.
Table 6.10 outlines the functions that it performs.
A
B
C
D
Parity Inputs
E EVEN
F 74180 Outputs
G ODD
H
EVEN
Cascading Inputs
ODD
Figure (a): Block Diagram of 74180 Parity Generator/Checker

The 74180 has dual functions; it can be used as a parity generator as well as a parity checker, depending on the application.
The function table (1) explains how it performs the role of a parity checker. Table (2) describes how it works as a parity generator.
Parity of Inputs Cascading Inputs Outputs

A through H EVEN ODD S EVEN S ODD
EVEN 1 0 1 0
ODD 1 0 0 1
EVEN 0 1 0 1
ODD 0 1 1 0
X 1 1 0 0
X 0 0 1 1
Table (1)
Parity of Inputs Cascading Inputs Parity of A through Parity of A through H

A through H EVEN ODD H and S EVEN and S ODD
ODD 1 0 ODD EVEN
EVEN 1 0 ODD EVEN
ODD 0 1 EVEN ODD
EVEN 0 1 EVEN ODD
Table (2)
Q33. What is parity? Describe how an odd parity can be generated for an n-bit input specification.
Ans: A term used to specify the number of ones in a digital word as odd or even is called as parity. Parity bit is an extra bit
attached to a binary word to make the parity of the resultant word even or odd.
Procedure to Generate Odd-parity for an n-bit Input Specification: In order to generate an odd parity, an extra bit (known as
parity bit) is included in the given binary number, such that the total number of 1’s in the entire group of digits (including parity
bit) is equal to an odd number i.e., if a parity bit included in the given n-bit digit, then the resultant (n + 1) bit digit should contain
an odd number of 1’s. Hence, the circuit that performs such operation is called as odd-parity generator. The logic diagram for an
n-bit odd parity generator is shown in figure.
D0
D1
D2
D3
D4
D5
D6
P
D7
Dn 2
Dn 1
Figure: Logic Diagram of n-bit Odd Parity Generator
The truth table of an n-bit odd parity generator circuit is shown in table (1).
Number of 1’s in the input Output (P)

0, 2, 4, 6, 8, … 1 (high)
1, 3, 5, 7, 9, 11, … 0 (low)
Table (1)
The truth table for a 3-bit odd parity generator (i.e., n = 3) is shown in table (2).
A B C Output (P)
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
Table (2): Truth Table of 3-bit Odd Parity Generator
During the transmission of data, odd parity generator circuit is used to detect the errors.
For example, if 0 0 0 is received instead of 0 1 0, then,
Parity check
Transmitted bit - 0 1 0 0 odd
Received bit - 0 0 0 0 even
As the received bit parity is even, the transmitted bit is not received properly and a trAns:mission error has occurred.
Q34. Design an n-bit input odd parity generator using daisy-chain structure.
Ans:
An odd-parity generator circuit will generate the output as ‘1’ or ‘0’, in order to make the total number of 1’s in the entire
group of digits, including parity bit an odd number i.e., if n inputs are considered, n + 1 (n inputs and 1 parity bit) input digit
should contain odd number of 1’s.
The function table of n-bit input odd parity generator circuit is shown in table (1 ).
Number of inputs that are high Parity bit

0, 2, 4, 6, 8, 10, … 1 (high)
1, 3, 5, 7, 9, 11, … 0 (low)
Table (1)
For simplicity, consider n = 4. As we know the possible number of input combinations for a n-bit binary digit is 2n, the
number of input combinations for n = 4 is 24 = 16. With the help of the truth table, the parity bit for the 16 input combinations is
shown in table (2).

A B C D Output (P)
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 0
1 0 0 0 0
1 0 0 1 1
1 0 1 0 1
1 0 1 1 0
1 1 0 0 1
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1
Table (2)
Simplification of the parity function using k-map is shown in figure (1).
CD
00 01 11 10
AB
00 1 0 1 0
01 0 1 0 1
11 1 0 1 0
10 0 1 0 1
Figure (1): K-map Reduction

Since there are no 1’s mapped adjacent to each other, the function cannot be simplified using k-map.
From the truth table shown in table (ii), the parity function ‘P’ can be expressed as,
P = A B C D + A B CD + A BC D + A BCD + ABC D + ABCD + AB C D + AB CD
Rearranging the terms,
P = A B C D + ABC D + A BCD + AB CD + A BC D + AB C D + A B CD + ABCD
= ( A B + AB )C D + CD ( A B + AB ) + ( A B + AB )C D + ( A B + AB )CD
= ( A . B)C D + CD ( A ⊕ B) + ( A ⊕ B)C D + ( A . B)CD
= [( A ⊕ B)C + ( A ⊕ B)C ]D + [( A ⊕ B)C + ( A . B)C ]D
= [( A ⊕ B )C + ( A ⊕ B)C ]D + [( A ⊕ B)C + ( A ⊕ B)C ]D

= [( A ⊕ B) . C ]D + [( A ⊕ B) ⊕ C ]D
= [( A ⊕ B) ⊕ C ]D + [( A ⊕ B) ⊕ C ]D
= [( A ⊕ B ) ⊕ C ] . D = [(( A ⊕ B) ⊕ C ) ⊕ D]
Thus from the above boolean expression, the logic diagram for 4-bit odd parity generator can be drawn as shown in figure (2).
P
C
D
Daisy-chain structure
Figure (2): 4-bit Odd Parity Generator
Similarly the structure for 8-bit odd parity generator is shown in figure (3).
D7
D6
D5
D4
D3
D2
D1
P
D0
Figure (3): 8-bit Odd Parity Generator
Hence the logic diagram for n-bit odd parity generator is as shown in figure (4).
D0
D1
D2
D3
P
Dn 1
Figure (4): n-bit Odd Parity Generator Circuit using Daisy Chain Structure
Q35. What are parity generator checker circuits? Explain the 9-bit odd/even parity generator.
Ans:
Parity Generator/Checker Circuits: Parity generator/checker circuits are very useful in error-detection and error correction
codes (i.e., during the trAns:mission of binary data, error detection can be done using parity bit.) The receiver checks for errors in
the message trAns:mitted including the parity. Parity bit is generally called an extra bit which is included with a binary message
to make the number either odd or even. The information or data along with the parity bit is trAns:mitted and at the receiving side,
this data will be checked for any possible errors. When the checked parity does not correspond with the bit trAns:mitted, then an
error is detected. The parity bit generated by the circuit in the trAns:mitter is called a parity generator. Parity checker is a circuit
that checks the parity in the receiver.

The bits p and q must be generated to make the total number even (including p),odd (including q) for even odd parity. As p
is equal to 1 for those minterms whose numerical values have an odd number of ones, so p constitutes an odd function. Similarly
as q is equal to 1 for those minterms whose numerical values have an even number of ones, so of constitutes an even function.
9-bit Even Parity Generator: Consider 9-bit message, which meAns: that it has 9-inputs, those are a,b,c,d,e,f,g,h and i. The
parity bit p and q are the outputs. The 9-bit message trAns:mitted together with an even /odd parity bit, where parity bit P/q is
generated in order to make even/odd number of 1’s along with it i.e. including the parity bit. Truth table for the even/odd-parity-
generator is as shown below.
9-Bit Message Even Parity Bit Odd Parity Bit
a b c d e f g h i p q
0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 1 1 0
0 0 0 0 0 0 0 1 0 1 0
0 0 0 0 0 0 0 1 1 0 1
0 0 0 0 0 0 1 0 0 1 0
0 0 0 0 0 0 1 0 1 0 1
0 0 0 0 0 0 1 1 0 0 1
0 0 0 0 0 0 1 1 1 1 0
0 0 0 0 0 1 0 0 0 1 1
· · · · · · · · · · ·
· · · · · · · · · · ·
· · · · · · · · · · ·
· · · · · · · · · · ·
· · · · · · · · · · ·
· · · · · · · · · · ·
· · · · · · · · · · ·
1 1 1 1 1 1 1 1 1 1 0
Table: Truth Table for Even/odd Parity Generator
From the truth table, it should be noted that the parity bit is 1/0, when the message or the inputs has odd/even number of
1’s. Therefore, it constitute an odd/even function. So, the parity bit p/q can be expressed as follows.
p = a ⊕ b ⊕ c ⊕ d ⊕ e ⊕ f ⊕ (g 5 h 5 i)
q = a ⊕ b ⊕ c ⊕ d ⊕ e ⊕ f ⊕ g ⊕ h ⊕ i and even logic diagram shown in the following figure (1).
A (8)
B (9)
C (10)
D (11)
(5)
E (12) EVEN
F (13)
G (1)
(2) (6)
H ODD
I (4)
Figure (1): 9-bit Even Parity Generator
The logic symbol of 9-bit odd parity checker is as shown in figure (2).
8 inputs from S Eeven Logic 0

A to H even parity
74180
Even input
S odd Logic 1 on
1 input Output odd parity
Figure (2): 9-bit Odd/Even Parity Generator

Q36. Draw the logic diagram of IC 74180 parity generator checker and explain its operation with the help of
a truth table.
Ans: (Model Paper-4, Q4(a) | Nov.-15, Set-1, Q6(b) M[8])
The logic symbol of IC 74180 is shown in figure (1).

Even 3
Odd 4
A 8 5 ΣEven
B 9
74180
C 10 6 ΣOdd
D 11
E 12
F 13
G 1
H 2
Figure (1)
The various functions performed by IC 74180 are,
1. Even Parity Generation: In the even parity generation, the four data bits are added using three EX-OR gates and the sum
will be the parity bit as shown in figure (2).
D0
D1
Original Parity
Data (P)
D2
D3
Figure (2): Even parity Generator

2. Odd Parity Generation: In the odd parity generation, the four data bits are added using three EX-OR gates and the sum
will be inverted to get the odd parity bit as shown in figure (3).
D0
D1
Original Parity
Data (P)
D2
D3
Figure (3): Odd Parity Generator
3. Even Parity Checker: In the even parity checker, the received four data bits are added using three EX-OR gates and the
sum will be again EX-ORED with even parity bit to obtain error bit (E) (i.e., E = 1 = Error, E = 0 = No error) as shown in
figure (4).

Using Gates, multiplexers, and Demultiplexers, we can
D0
D1 create various code converters. Due to the widespread use of
this converter circuits they are made available in the form of
Received Error (E) an integrated circuit (MSI chips).
data D2
Q38. Draw the block diagram of IC 74184 BCD-to-
D3
binary converter and explain its use as one and
P half decade BCD-to-binary converter.
Figure (4): Even Parity Checker Ans: Model Paper-2, Q4(b)
4. Odd Parity Checker: In the odd parity checker, the In BCD, ten decimal digits (numbers) 0-9 are represented
received four data bits are added using three EX-OR by a four bit equivalent binary number. If a number has two
gates and the sum will be again EX-ORED with odd decimal digits, its equivalent BCD will be an eight digit binary
parity bit to obtain error bit (E) (i.e., E = 0 = Error, E = number obtained by replacing each decimal digit with its BCD
1 = No error) as shown in figure (5). equivalent, that is, decimal 45 is represented in BCD as 0100
D0
0101 and decimal 31 is represented in BCD as 0011 0001.
D1 Figure (1) shows the block diagram of the IC 74184
BCD-to-binary converter. It has five input terminals A-E and
Received Error (E)
data D2 eight output terminals Y1-Y8. The BCD inputs are applied to
D3 input terminals A through E. As illustrated in figure (2), the
74184 IC accepts only six BCD digits out of eight BCD digits
P - a full digit D1 C1 B1 A1 and the two least-significant bits of a
second digit B2 A2. Further, the LSB of the least-significant BCD
Figure (5): Odd Parity Checker
digit skips the converter and appears as the binary output’s LSB
The truth table of IC74180 is shown in below table. (figure 2). In other words, using single 74184 IC we can convert
BCD codes in the range 00 to 39 to corresponding binary output.
Sum of 1’s Inputs Outputs
at A A
Even Odd Σ Even Σ Odd Y1
through H B
BCD Y2
C
Inputs Y3
Even 1 0 1 0 D Y4
E 74184 Y5 Outputs
Odd 1 0 0 1
Y6
Even 0 1 0 1 Y7
Y8
Odd 0 1 1 0
Enable Input (MSB)
X 1 1 0 0 (Active-Low)
X 0 0 1 1 Figure (1): Block Diagram of IC 74184 BCD-to-Binary Converter

Figure (2) illustrates the use of IC 74184 as one and
Table
half decade BCD-to-binary converter. Table (1) illustrates its
2.6 Code Converters and Parity Encoders corresponding truth table. The term one and half decade indicates
that in IC 74184 we can use only six bits out of 8 bits (that are used
Q37. Explain in brief about the need of code
to represent two decimal digits). In the truth table, LSB is missing
converters.
for both inputs and outputs. This is because LSB of input bypasses
Ans: Model Paper-1, Q3(b) the converter and directly emerges as LSB of binary output.
In digital systems, there are many different binary codes. A1 B0
Some of these codes include binary-coded-decimal (BCD), LSB
LSD B1 A
Excess-3, Gray, octal, hexadecimal, and several others. Often, Y1 B1
C1 B Outputs
it is necessary to switch from one type of code to another. For Y2 B2
D1 C
instance, a digital system’s input can be in natural BCD, and Y3 B3
BCD A2 D Y4
the system’s output can be 7-segment LED. In this case, the B4
Inputs B2 E 74184 Y5 B5
digital system processes data in pure binary format only. Before
(MSB)
the BCD output can be utilized to operate the LEDs, it must G
be converted to 7-segment code. As a result, at the output, the
data must be converted from BCD to binary. In a similar vein,
octal and hexadecimal codes are commonly used as inputs and
outputs in microprocessors and digital computers. Therefore,
these conversions are quite valuable in the design of digital Figure (2): IC 74184 as One and Half Decade BCD-to-Binary
systems. Converter
BCD Inputs Outputs

Words E D C B A G Y5 Y4 Y3 Y2 Y1
0-1 0 0 0 0 0 0 0 0 0 0 0
2-3 0 0 0 0 1 0 0 0 0 0 1
4-5 0 0 0 1 0 0 0 0 0 1 0
6-7 0 0 0 1 1 0 0 0 0 1 1
8-9 0 0 1 0 0 0 0 0 1 0 0
10 - 11 0 1 0 0 0 0 0 0 1 0 1
12 - 13 0 1 0 0 1 0 0 0 1 1 0
14 - 15 0 1 0 1 0 0 0 0 1 1 1
16 - 17 0 1 0 1 1 0 1 1 0 0 0
18 - 19 0 1 1 0 0 0 0 1 0 0 1
20 - 21 1 0 0 1 0 0 0 1 0 1 0
22 - 23 1 0 0 0 1 0 0 1 0 1 0
24 - 25 1 0 0 1 0 0 0 1 1 0 0
26 - 27 1 0 0 1 1 0 0 1 1 0 1
28 - 29 1 0 1 0 0 0 0 1 1 1 0
30 - 31 1 1 0 0 0 0 0 1 1 1 1
32 - 33 1 1 0 0 1 0 1 0 0 0 0
34 - 35 1 1 0 1 0 0 0 1 0 0 1
36 - 37 1 1 0 1 1 0 1 0 0 1 0
38 - 39 1 1 1 0 0 0 1 0 0 1 1
Any × × × × × 1 1 1 1 1 1
Table : Truth Table of 74184 BCD-to-Binary Converter

The BCD-to-binary conversion does not utilize the Y6, Y7, or Y8 terminals. These terminals are used to acquire the 9’s and
10’s complements of BCD numbers, which are helpful for BCD arithmetic operations.
Q39. Draw the block diagram of IC 74185A binary-to-BCD converter and Explain.
Ans:
Figure (1) illustrates the block diagram of the IC 74185A binary-to-BCD converter. The pin configuration of 74185A is
the same as the 74184. It has five input terminals A-E and eight output terminals Y1-Y8.
A
Y1
B
BCD Y2
C
Inputs Y3
D Y4 Outputs
E 74184 Y5
Y6
Y7
Y8
Enable Input Logic 1
(Active-Low) (MSB)
Figure (1): Block Diagram of IC 74185A BCD-to-Binary Converter
As illustrated in figure (2), the binary inputs are applied to input terminals A through E and the output terminals Y1, Y2,
Y3, Y4, Y5, Y6 are used to access the BCD output. The Y7 and Y8 terminals are never used to access BCD outputs and are set to
logic 1. Further, same as BCD-to-binary converter, the LSB of the binary input skips (bypasses) the converter and appears as the
LSB of BCD output.

B0 A0
(LSB)
B1 A LSB
Y1 B0
B2 B
6-Bit Binary Inputs Y2 C0 LSD
B3 C Y3 D0 2-Decade BCD Outputs
74185A
B4 D Y3 A1
B5 E Y4
(MSB) B1 MSD
Enable Input (Active-Low) G Y5 C1
Figure (2): Block Diagram of IC 74185A BCD-to-Binary Converter

Table (1) illustrates truth table of 74I85A Binary-to-BCD Converter. In the truth table, LSB is missing for both inputs and
outputs. This is because LSB of input bypasses the converter and directly emerges as LSB of output.
BCD Inputs Outputs
Words E D C B A G Y6 Y5 Y4 Y3 Y2 Y1
0-1 0 0 0 0 0 0 0 0 0 0 0 0
2-3 0 0 0 0 1 0 0 0 0 0 0 1
4-5 0 0 0 1 0 0 0 0 0 0 1 0
6-7 0 0 0 1 1 0 0 0 0 0 1 1
8-9 0 0 1 0 0 0 0 0 0 1 0 0
10 - 11 0 0 1 0 1 0 0 0 1 1 0 0
12 - 13 0 0 1 1 0 0 0 0 1 1 1 1
14 - 15 0 0 1 1 1 0 0 0 1 1 1 0
16 - 17 0 1 0 0 0 0 0 0 1 0 0 1
18 - 19 0 1 0 0 1 0 0 0 1 0 0 0
20 - 21 0 1 0 1 0 0 0 1 0 0 1 1
22 - 23 0 1 0 1 1 0 0 1 0 0 1 0
24 - 25 0 1 1 0 0 0 0 1 0 1 0 0
26 - 27 0 1 1 0 1 0 0 1 0 1 0 1
28 - 29 0 1 1 1 0 0 0 1 0 1 1 0
30 - 31 0 1 1 1 1 0 0 1 1 1 1 1
32 - 33 1 0 0 0 0 0 0 1 1 0 0 0
34 - 35 1 0 0 0 1 0 0 1 1 0 0 0
36 - 37 1 0 0 1 0 0 0 1 1 0 1 1
38 - 39 1 0 0 1 1 0 0 1 1 0 1 0
40 - 41 1 0 1 0 0 0 1 0 0 1 0 0
42 - 43 1 0 1 0 1 0 1 0 0 1 0 1
44 - 45 1 0 1 1 0 0 1 0 0 1 1 0
46 - 47 1 0 1 1 1 0 1 0 0 1 1 1
48 - 49 1 1 0 0 0 0 1 0 0 0 0 0
50 - 51 1 1 0 0 1 0 1 0 1 0 0 1
52 - 53 1 1 0 1 0 0 1 0 1 0 1 0
54 - 55 1 1 0 1 1 0 1 1 1 0 1 0
56 - 57 1 1 1 0 0 0 1 0 1 1 1 1
58 - 59 1 1 1 0 1 0 1 0 1 0 0 0
60 - 61 1 1 1 1 0 0 1 1 0 0 0 0
62 - 63 1 1 1 1 1 0 1 1 0 1 0 1
All × × × × × × 1 1 1 1 1 1
Table (1): Truth Table of 74I85A Binary-to-BCD Converter
Q40. What are the drawbacks of ordinary digital encoders? How are they over come using priority encoders?
Explain Decimal-to-BCD Priority Encoder using IC 74147.
One of the main drawbacks of ordinary digital encoders is that it would produce an error at its output if more than one input
is active at a given time. It generates an undefined combination of outputs, if the two inputs are logic 1 simultaneously. Consider
the following illustration: When we set two inputs D1 and D2 to logic “1” and make them both HIGH, the resulting output is “11,”
which is a binary number that differs from the real input present.
By “prioritizing” the levels of each input pin, this problem can be solved quickly and easily. As a result, if many logic
level “1” inputs are present at the same time, the actual output code will only correspond to the input with the highest designation
priority. A Priority Encoder, or P-encoder for short, is the name given to this type of digital encoder. Priority encoders are available
in the form of MSI integrated circuits. One such IC is explained below.
Decimal-to-BCD Priority Encoder using IC 74147: This sort of encoder encodes decimal digits into 4-bit BCD outputs in the
same way as a conventional decimal to BCD encoder does. However, it has an additional feature that allows you to set priority.
That means the BCD output is produced corresponding to the highest priority of a decimal digit appearing on the inputs irrespective
of all other inputs
1
2
A
3
4 B
BCD Inputs
Decimal Inputs 5 74147 C
6
D
7 (MSB)
8
9
Figure (a): Block Diagram of IC 74147 Decimal-to-BCD Priority Encoder.

The block diagram of IC 74147, which encodes 9 input lines into 4 output lines, is shown in Figure (a). The phrase “priority
encoder” refers to a device that prioritizes encoding of highest-order data lines. Its inputs and outputs are active-low. The truth
table in table (1) demonstrates the definition of the word priority: if inputs 2 and 5 are both LOW, the output will correspond to
5, which has a greater priority than 2, i.e. the highest numbered input take priority over lower numbered inputs.
Active Low Decimal Inputs Active Low BCD Outputs

1 2 3 4 5 6 7 8 9 D C B A
1 1 1 1 1 1 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1 1 1 1 1 0
× 0 1 1 1 1 1 1 1 1 1 0 1
× × 0 1 1 1 1 1 1 1 1 0 0
× × × 0 1 1 1 1 1 1 0 1 1
× × × × 0 1 1 1 1 1 0 1 0
× × × × × 0 1 1 1 1 0 0 1
× × × × × × 0 1 1 1 0 0 0
× × × × × × × 0 1 0 1 1 1
× × × × × × × × 0 0 1 1 0
Table (1): Truth Table of 74147

Q41. Explain about IC 74148 and its use as Octal-to-Binary priority encoder.
Digital circuits that require entry of large binary words manually, such as those used in medical devices, frequently employ
the octal code at their inputs. For this purpose, the priority encoder 74148 integrated circuit (IC) was developed.
Figure (a) illustrates the block Diagram of IC 74148 Octal-to-Binary Priority Encoder. Active-low inputs and outputs are
also available on this circuit. To handle multiple inputs, cascade circuits employ the enable input and carry output, both of which
are active-low as well. By taking use of this facility, it is possible to create an encoder that converts from hexadecimal to binary
code, which is also a very important circuit due to the ubiquitous use of hexadecimal code in computers, microprocessors, and
other electronic devices. It is convenient to utilize priority encoders in computers, microprocessors, and other electronic devices
to handle priority interruptions.
0
1
A
2 Binary Outputs
3 B (Active-Low)
Octal Inputs
(Active-Low) 4 74148 C
5 (MSB)
6
7 GS Carry Outputs
Enable Input (Active-Low)
(Active-Low) EO
Figure (a): Block Diagram of IC 74148 Octal-to-Binary Priority Encoder

The truth table of an octal - to - binary priority encoder is demonstrated in Table (1). The encoder has eight inputs and
three outputs, each of which generates a different binary code. Each input has a priority attached to it, so that when two or more
inputs are 1 at the same time, the output represents the input with the highest priority allocated to it.
Consider the following Scenario: If the input lines D2, D4, and D7 are all logic 1 at the same time, regardless of the other
inputs, only D7 will be decoded and the output will be 111. Additionally, if D3 = 1, the states of D2, D1, and D0 are unimportant,
and the output equals 011 in the same way.
Outputs Outputs
EI 0 1 2 3 4 5 6 7 C B A GS EO
1 × × × × × × × × 1 1 1 1 1
0 0 1 1 1 1 1 1 1 1 1 1 0 1
0 × 0 1 1 1 1 1 1 1 1 0 0 1
0 × × 0 1 1 1 1 1 1 0 1 0 1
0 × × × 0 1 1 1 1 1 0 1 0 1
0 × × × × 0 1 1 1 1 0 0 0 1
0 × × × × × 0 0 1 1 0 0 0 1
0 × × × × × × 1 0 1 1 1 1 1
0 × × × × × × × 1 0 1 0 0 1
0 1 1 1 1 1 1 1 1 1 1 1 1 0
Table (1): Copy Table 6.19 Truth Table of 74148 Pageno: 269
Q42. Design a 2 to 4 decoder circuit. Give its entity declaration behavioural model. Also draw the waveform
giving relation between its inputs and outputs.
2 to 4 Line Decoder
2 to 4 decoder consists of 2-input lines, 4 output lines and one enable (En) line. It is used to decode 2-bit information. The
decoder circuits can have two output modes either active high or active low. The representation of 2 to 4 line decoder is as shown
in figure (2).
x0 y0
x1 y1
Input 2× 4 Output
Decoder y2
En y3
Figure (2) : Block Representation of 2 to 4 Decoder

The truth table for 2 : 4 line decoder circuit is given below,
Inputs Outputs
En x1 x0 y0 y1 y2 y3
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1
0 × × 0 0 0 0
Table
From the above truth table the Boolean expressions for outputs are obtained as,
y0 = x0 x1 En
y1 = x0 x1 En
y2 = x0 x1 En
y3 = x0 x1 En
The logic circuit implementation of 2 to 4 line decoder is as shown in figure (3).
En
x1
x0
y3 y2 y1 y0
Figure (3) : Logic Circuit of 2 to 4 Line Decoder

Entity Declaration in Behavioural Model 1 1
0 0
The VHDL code for 2 × 4 decoder using process
statement is shown below, (a) Select line waveform
1 1
LIBRARY ieee;
USE ieee.std_logic_1164.all; 0 0
(b) Input waveform
ENTITY dec2to4 IS
PORT (x : IN STD_LOGIC_VECTOR (1 DOWN 1 0 0 0

D3
TO 0);
0 1 0 0
En : IN STD_LOGIC; D2
y : OUT STD_LOGIC_VECTOR (0 TO 3)); 0 0 1 0

D1
END dec2to4; 1 D0
ARCHITECTURE behaviour of dec2to4 IS (c) Output waveform
Figure
BEGIN
Q43. Design a function F = ABC + (A + B + C) by using
PROCESS (x, En) 74X138.
BEGIN Ans: Oct./Nov.-19, Set-2, Q5(a) M[7]
IF En = ‘0’ THEN Given function is,

F = ABC + (A + B + C)'
CASE x IS
Þ F = ABC + A'B'C' (Q (A+B)' = A'B')
WHEN “00” =>
F = Sm(7, 0)
y <= “1000”; The given function can be designed using 74×138 IC
WHEN “01” = > as shown in figure.
ABC
y<= “0100”; Y0
A BC F
WHEN “10” => A Y1
ABC
B Y2
y <= “0010”; A BC
C Y3
74×138 ABC
WHEN “OTHERS => VCC Y4
ABC
y <= “0001”; G1 Y5
Y6 ABC
END CASE; G2A
G2B Y7 ABC
ELSE
y <= “0000”, Figure
END IF;
END PROCESS;
END Behaviour;
Waveform giving relation between its inputs and outputs
The relation between inputs and outputs of 2 to 4 decoder

is shown in figure below.
Q1. Explain the operation of a Look ahead carry generator.
REPEATED
3
TIMES
Ans: Refer Q3. March-21, Set-4, Q5(a) | Oct./Nov.-16, Set-4, Q6(a) | Oct./Nov.-16, Set-4, Q6(b)
Q2. Write VHDL code for 4-bit look ahead carry generator along with circuit diagram.
REPEATED
3
TIMES
Ans: Refer Q5. (March-21, Set-1, Q5(b) March-21, Set-4, Q5(b) | Oct./Nov.-18, Set-4, Q5(a))
Q3. Explain the implementation of N-bit binary adder using full adders.
Q4. Draw the circuit of a 4-bit ripple carry adder circuit and explain how it is different from look-a-head carry
circuit. Give the equation for C1 to C4 for a look-ahead carry adder circuit.
Q5. Write a VHDL code to implement binary adder subtractor.
Q6. Design full subtractor circuit and write a VHDL code for implementation of full subtractor.
Q7. Using a process statement write a VHDL source code for 4 to 1 multiplexer.
Q8. What is multiplexer? Draw the logic diagram of 8 to 1 line multiplexer.
Q9. With the help of logic diagram explain 74×157 multiplexer. Write the data flow style VHDL program for
this IC.
Q10. What is ALU? Draw the block diagram of 74181ALU and Explain.
Q11. Discuss about the implementation of comparator using digital IC.
Q12. Explain about comparator and design a 16-bit comparator using 74×85 IC’s. Write VHDL program.
Q13. Design a 24-bit comparator using 74×682 ICs and explain the functionality of the circuit. Also implement

Q14. Draw the logic diagram of IC 74180 parity generator checker and explain its operation with the help of
a truth table.
Q15. Draw the block diagram of IC 74185A binary-to-BCD converter and Explain.
Q16. Design a 2 to 4 decoder circuit. Give its entity declaration behavioural model. Also draw the waveform
giving relation between its inputs and outputs.
Q17. Design a function F = ABC + (A + B + C) by using 74X138.
UNIT-3 (Sequential Logic Design) 97
UNIT
Sequential Logic Design
3 SI
A GROUP
Syllabus
SEQUENTIAL LOGIC DESIGN: Registers, Applications of shift registers, Ripple or asynchronous counters,
Synchronous counters, Synchronous and asynchronous sequential circuits, Hazards in sequential circuits.
(Qualitative approach of designing and modeling the mentioned sequential logic circuits with relevant digital ICs
using HDL)
Learning Objectives
C Operation of 4-bit and 5-bit registers
C Application of shift registers
C Design of synchronous counters with ICs and their VHDL programs
C Design of asynchronous counters
C Design of synchronous and asynchronous sequential circuits
C Types of hazards in sequential circuits
Introduction
Sequential logic circuit is the one whose output depends on the present input as well as on the previous output. It contains
atleast one memory element to store the binary information. Some of the sequential circuits include, flip-flops, registers and
counters.
Counters are useful subsystems in digital electronic circuits used to count or measure the number of clock pulses. They are a
special form of synchronous sequential circuits whose state depends on count held by flip-flops in the circuit.

3.1 Registers, Applications of Shift Registers

Q1. Define register. Mention its types. What is its need? Explain.
Ans:
Register
A group of flipflops, which stores binary information, is known as register.
Example: For Intel’s 8085 microprocessor chip has seven 8-bit general purpose registers and five 1-bit flag registers.
The data can be sent in serial (one bit at a time) or parallel (all bits at once) format, and it can be fetched in either format.
Data is referred to as temporal code in serial form and spacial code in parallel form. Figures (1)(a) and 1(b) shows a 4-bit data
1010 in serial form and parallel form respectively.
For serial input/output, only one line is necessary for data input and one line is required for data output, however for parallel
input/output, the number of lines required is equal to the number of bits.
1 1
0 0
D MSB
LSB
(a)
D0 0
(LSB)
1
D1
0
D2 0
1
D3
(MSB)0 (b)
Figure (1): Representation of 4-bit data 1010 in serial and parallel forms
Based on the way data is input and retrieved, registers are classified into four different modes of operation as follows,
1. Serial-in, serial-out (SISO) 2. Serial-in, parallel-out (S1PO)
3. Parallel-in, serial-out (PISO) 4. Parallel-in, parallel-out (PIPO).
Registers are provided as MSI devices and can be created using separate flip-flops (S-R or J-K or D-type). Table below
lists the registers accessible in the 54/74 TT’L and CMOS logic families. For each series, the full IC No. is different. 74AC164,
74ACT164, 74HC164, 74HCT164, 74ALS164A, and so on.
IC Number Logic Family Basic Function
7491,7491A TTL 8-bit shift register
7494 TTL 8-bit shift register
7495 TTL 4-bit universal shift register
7499 TTL 4-bit bi-directional, universal shift register
74165,74166 TTL 8-bit shift register
74178, 74179, 74194 TTL 4-bit universal shift register
74198 TTL 8-bit universal shift register
4014 CMOS 8-bit shift register
4034 CMOS 4-bit directional
Table
Need For Register
1. Registers are used to store the binary information temporarily in digital system.
2. They help in understanding the operation of digital computers and microprocessors.
3. They build an important link, between main digital systems and inputs, output channels in computers and microprocessor.
Q2. Explain in detail about shift registers.
Ans:
Shift Register
A register capable of shifting its binary information in one or both directions is called a shift register. Shift register consists
of a chain of flip-flops which are cascaded with output of one flip-flop connected to the input of the next flip-flop. A clock pulse
is given to all the flipflops which activates the shift from one stage to the next.
The simplest shift register is that which contains only one type of flip-flop as shown in the figure (1) i.e., 4 D flip-flops.
SI SO
D D D D
Serial Serial
Input Output
C inputs to
C C C C CLK D-flipflop
Shift
Control
CLK
Figure (1): 4-bit Shift Register Figure (2)
The output of given flip-flop is connected to the D input of the flip-flop at its right where each clock pulse shifts the contents
of the register one bit position to the right. The serial input determines what goes into the left most flip-flop during the shift. The
serial output is taken from the output of the right most flip-flop. Sometimes, it is necessary to control the shift so that it occurs
only with certain pulses, but not with others. This can be done by connecting the clock through an AND gate with an input that
controls the shift as shown in figure (2).
Applications of Shift Register
Primary use of shift register is temporary data storage and bit manipulations.
1. Delay Line
A serial-in serial-out shift register can be used to introduce time delay ∆t in digital signals. The time delay can be given
as,
1
∆t = N ×
fc
Where, N is the number of stages (i.e., flip-flops) and fc is the clock frequency.
Thus, an input pulse appears at the output delay by ∆t. The amount of delay can be controlled by the clock frequency or
by the number of flip-flops in the shift register.
2. Serial-to-Parallel Converter
A serial-in parallel-out shift register can be used to convert data in serial form to the parallel form.
3. Parallel-to-Serial Converter
A parallel-in serial-out shift register can be used to convert data in parallel form to the serial form.
4. Shift Register Counter
A shift register can also be used as a counter by connecting the serial output back to the serial input. Because of such a
connection, special specified sequences are produced as the output. The most common shift register counters are the ring
counter and the Johnson counter.

Q3. Write a VHDL code to instantiate a shift register.
Ans:
The VHDL code to instantiate a shift register is given below,
LIBRARY ieee;
LIBRARY 1pm;
USE 1pm.1pm_components.all;
ENTITY shiftreg1
PORT (Clock : IN STD_LOGIC;
Reset : IN STD_LOGIC;
Shiftin, Load : IN STD_LOGIC;
R : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END shiftreg1;
ARCHITECTURE Structure OF shiftreg1 IS
BEGIN
instance: 1pm_shiftreg
GENERIC MAP (LPM_WIDTH => 4, LPM_DIRECTION => “RIGHT”);
PORT MAP (data => R, clock => Clock, aclr => Reset load => Load, shiftin => Shiftin, q => Q);
END Structure;
In the code, GENERIC MAP construct which is similar to ‘PORT’ MAP is used to assign values to parameters of the sub
circuit.aclr represents asynchronous active high clear input load represents active-high parallel load input.
Q4. Write a VHDL for an n-bit register with asynchronous clear.
Ans: The VHDL for an n-bit register with asynchronous clear is given below,
LIBRARY ieee;
ENTITY asynregn IS
GENERIC (N : INTEGER : = 16);
PORT (D : IN STD_LOGIC_VECTOR (N – 1 DOWNTO 0);
Resetn, Clock : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(N – 1 DOWNTO 0));
END asynregn;
ARCHITECTURE Behavior OF asynregn IS
BEGIN
PROCESS (Resetn, Clock)
BEGIN
IF Resetn = ‘0’ THEN
Q <= (OTHERS => ‘0’);
ELSIF Clock’ EVENT AND Clock = ‘1’ THEN
Q <= D;
END IF;
END PROCESS;
END Behavior;
Q5. Write a behavioral VHDL code for a 4-bit shift register.
Ans:
The behavioral VHDL code for a four-bit shift register is given below,
LIBRARY ieee;
ENTITY shiftreg4 IS
PORT (R : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Clock : IN STD_LOGIC;
L, w : IN STD_LOGIC;
Q : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0));
END shiftreg4;
ARCHITECTURE Behavior OF shiftreg4 IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL Clock’ EVENT AND Clock = ‘1’;
IF L = ‘1’ THEN
Q <= R;
ELSE
Q(0) <= Q(1);
Q(1) <= Q(2);
Q(2) <= Q(3);
Q(3) <= w;
END IF;
END PROCESS;
END Behavior;
Q6. What is a shift register? Explain 5-bit and 3-bit shift registers.
Ans:
A register which shifts the binary data to left side or to right side is known as shift register. In these registers the
data entered in serial form and also the output available in the serial form. If the bits are shifted in the flipflops in the right
direction with the occurrence of the clock pulses then that type of shift register is called right-shift register. If the bits are
shifted in the flipflops in the left direction with the occurrence of clock pulse then that shift register is called left-shift
register. With the help of mode control of the binarydata can be shifted from left to right as well as in the reverse direction,
then those type of shift registers are called bi-directional shift register. If a register can be operated in all the four possible
modes and also as a bi-directional register then those register is called as universal register. Example for universal register
is 74194.
The registers are also available in 54/74 TTL series.
5-bit Shift Register
A shift register with 5 bits is as shown in figure (1). It uses five master-slave S-R (or J-K) flipflops. This circuit can
be operated in any of the four modes. Let the 5-bit data which is to be shifted is 10110. {Assume this data to understand
the working of this register and this working principle is same for any other combination of 5 bit data).

Figure (1): 5-bit Shift Register

Serial Input
The clear line in flipflops is used to clear the flipflops, when all the flip/flops get cleared the data word can be applied
in serial form at the serial input terminal. The preset enable input is maintained at logic 0 in order to have preset (pr) of
every flip flop equal to 1. The waveforms of shift register for serial input is as shown in figure.
Figure (2): Shift Register Waveforms for Serial Input

In this shifting registers the required clock pulses will be equal to the number of bits to be stored or to be shifted.
The entering and shifting of digital word 10110 is as follows.
(i) Initially the LSB of the digital word i.e. ‘0’ is entered at the serial input terminal at the occurrence of first clock pulse.
At the time of falling edge of this clock pulse i.e. at T1, the FF4 flip flop (which received the data bit) produces ‘0’
at the output i.e. Q4 = 0 and the outputs of remaining flip flops will be ‘0’ i.e. Q3 = Q2 = Q1 = Q0=0. The reason for
this is no input was applied to these filpflops.
(ii) Now next LSB of the digital word is entered so the ‘0’ bit which is already there in FF4 will be shifted to the next
right flipflop i.e. into FF3 and at the second clock pulse T2 the output of Q4 becomes ‘i’ and remaining flipflops have
still 0 at their outputs.
(iii) Now the next LSB (again 1) is entered. With this the bit ‘0’ present in FF3 shifted into FF2 and bit ‘1’ present in
FF4 will be shifted into FF3 and the new entered bit 1 will be stored in FF4. At the falling edge of T3, the output
Q4 = 1 and Q3 = 1, Q2 = Q1 = Q0 = 0.
This right shifted process continues for all the bits in the input digital word. At the end of this shifting operation the
input digital word appears at the outputs of the flip flops. i.e.,
Q4 =1, Q3 = 0, Q2 = 1–, Q1 = 1, Q0 = 0. i.e. the input data 10110 is obtained at the output.
The ‘entering of data inside the flipflops is known as writing into the register where as taking output from the register
is known as reading from the register.
The reading can be done in 2 methods
1. Serial out
2. Parallel out
Retrieving the data in serial form makes use of clock pulses. In this method output data is available at Q0 output
when clock pulse is applied. Here the input data has 5 bits it uses 5 clock pulse to get the output data in serial form.
The parallel out method uses no clock pulses and data can be read from Q4, Q3, Q2, Q1, Q0 outputs.
In serial out method as soon as the reading completes the registers becomes empty and data will not be available to
read once again. Whereas in parallel out method the data can be retrieved as many times as required unless and until new
data is entered into the registers. The input and the output data clock rate is different in case of serial-in, serial-out shift
register. So, this method can be used for buffering.
Parallel Input: By the use of preset inputs data can be entered in the parallel form. In this method or process also, all the
flip flops has to be cleared first, to write the data into the register. As soon as they get cleared enter or apply data at the
parallel inputs i.e., at Di4, Di3, Di2, Di1 and Di0 inputs and preset input level should be at logic 1. This process of writing the
data or loading the data into the register is known as asynchronous loading of data.
In parallel form the data can be entered by using D-type flipflop, and it is shown in figure (3). In this technique, the
data is written into the register when a clock pulse is applied. This process of loading or writing the data into the register
is known as synchronous loading of data.
Figure (2): 3- bit Register Using D Flipflops

Q7. Discuss the logic circuit of 74×377 register. Write a VHDL program for the same in structural style.
Ans: (Model Paper-1, Q5(a) | Oct./Nov.-19, Set-1, Q6(a) M[7] | Nov.-15, Set-1,Q7(b))
MSI Register
An MSI register is a medium-scale integrated register. For instance, 74 × 377 is an MSI register.
74 × 377 Register
Figure (1) shows the logic symbol of 74 × 377 register. It is an edge-triggered register. This register has an active low
clock enable input, EN_L instead of output enable pin OE_L and three state outputs as in 74 × 377 register.
Figure (1)

EN CLK if (Clk’ event and Clk = ‘1’) then
for i in 1 to 8 loop
Qn+1 Ü (En and Qn) or (D and NOT En);
D Q 1Q End loop;
1D
CLK End if;
End process;
D Q 2Q
2D End reg_8;
CLK
Q8. Draw the logic diagram of 74 × 174 IC and explain
the operation. Develop the VHDL model for this
D Q
IC.
3Q
3D
CLK Ans:
74 × 174 is a 6-bit register. It contains six edge-triggered
D
D flip-flops with a common clock and asynchronous clear inputs.
Q 4Q
4D It provides only active-high output at the external pins of the
CLK
device.
The logic diagram of 74 × 174 is shown in figure.
D Q 5Q (3)
5D (2)
CLK 1D D Q 1Q
CLK
CLR
D Q 6Q
6D (4) (5)
CLK 2D D Q 2Q
CLK
CLR
D Q 7Q
7D (6) (7)
CLK 3D 3Q
D Q
CLK
D Q 8Q CLR
8D
CLK (11) (10)
4D D Q 4Q
CLK
Figure (2)
CLR
The logic diagram of 74 × 377 is shown in figure (2).
(13) (12)
The flipflops are loaded from the data inputs, if the EN_L input 5D D Q 5Q
is asserted (LOW) at the rising edge of the clock.
CLK
VHDL Program:
CLR
Library IEEE;
(14) (15)
Use IEEE.std_logic_1164. all; 6D D Q 6Q
Entity reg8 is (9) CLK
CLK CLR
port(D : in std_logic_vector (8 downto 1);
CLR_L (1)
En, Clk: in std_Logic;
Qn: in Std_logic_Vector (8 downto 1); Figure
Qn + 1: out std_logic_Vector (8 downto 1));
The flip-flops in the IC are negative-edge triggered. The
End reg8; circuit also contains an inverter that makes the flip-flops positive
Architecture reg_8 of reg8 is edge triggered with respect to the external clock input pin of
begin the device. The active-low, clear signal (CLR_L) is connected
to asynchronous clear inputs of all six flip-flops. Both CLK and
process(D, En, Clk, Qn)
CLR_L are buffered before fanning out to the flip-flop, so that
variable i : INTEGER range 8 downto 1; the device driving one of these inputs sees only one unit load
begin instead of six.
VHDL Code for 74 × 174 IC
Library IEEE;
Use IEEE.STD_LOGIC_1164. all;
Entity 74 × 174 reg is
Port (D : in STD_LOGIC_VECTOR(6 downto 1);
CLK, CLR_L : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (6 downto 1));
End 74 × 174 reg;
Architecture behaviour of 74 × 174 reg is
Signal CLR : STD_LOGIC;
begin
Process (CLR_L, CLR, CLK)
begin
CLR Ü NOT CLR_L;
if (CLR = ‘1’) then
Q Ü ‘0’;
elsif (CLK’event and CLK = ‘1’) then
Q Ü D;
End if;
End process;
End behaviour;
Q9. Explain different types of shift registers.
Ans: April/May-13, Set-3, Q7(b)
Types of Shift Registers: Basically, shift registers are categorized into four different types. They are,
1. Serial-in serial-out shift register 2. Serial-in parallel-out shift register
3. Parallel-in serial-out shift register 4. Parallel-in parallel-out shift register.
1. Serial-In Serial-Out (SISO) Shift Register
The circuit diagram of serial-in-serial-out shift register is as shown in figure (1).
D 3 D2 D1 D0 D3 Q3 D2 Q2 D1 Q1 D0 Q0
DFF DFF DFF DFF
Clock
Figure (1): Serial-In Serial-Out Shift Register
v Initially, all flip-flops are cleared and data is entered serially bit by bit from the left most flip-flop i,e., from D-FF4.
v When the clock pulse is applied, the content of the register is shifted by one position to the right.
In the same way for each clock pulse data moves to the next flip-flop by one position and serial output is obtained at the
right most flip-flop i.e., D-FF1 after four clock pulses.
2. Serial-In Parallel-Out (SIPO) Shift Register: The circuit diagram of a 4-bit serial-in-parallel-out shift register is shown
in figure (2).
Q1 Q2 Q3 Q4
Serial in D1 Q1 D2 Q2 D3 Q3 D4 Q4
D-FF1 D-FF2 D-FF3 D-FF4
Clock
Clear
Figure (2): Serial-In Parallel-Out Shift Register

In this shift register, the data input bits are sent serially and the output is taken in parallel.
v Initially, all the flip-flops are cleared by applying active low signal on clear. Once, the flip-flops are cleared, clock signal
is applied and the data is entered serially from left most D-flip-flop (i.e., from D-FF1).
v After each clock pulse, one data bit is obtained at each output of the flip-flop.
v Thus, the complete serial input is obtained in parallel at each stage of output after four clock pulses.
3. Parallel-In Serial-Out (PISO) Shift Register
The circuit diagram of 4-bit parallel-in-serial-out shift register is shown in figure (3).
A B C D
Shift/Load
G4 G1 G5 G2 G6 G3
D1 Q1 D2 Q2 D3 Q3 D4 Q4
FF1 FF2 FF3 FF4
CLK
Figure (3): Parallel-In Serial-Out Shift Register

v In this type of shift register, data input is applied in parallel and the output obtained serially. First, all the flip-flops are
cleared and data bits are applied simultaneously into their corresponding flip-flops.
v When the control input SHIFT/ LOAD is low, gates G1, G2 and G3 are activated and the data bits are transferred to their
respective flip-flops.
v When clock pulse is applied, then all the flip-flops get activated and store their corresponding bits.
v Then the read operation is performed by making the control input SHIFT/ LOAD high, which enables the gates G4, G5,
G6 and disables the gates G1, G2, G3.
v Thus, gates G4, G5, G6 perform the shift operation and allows the data bits to move one position right from one flip-flop
to the next flip-flop until complete four bits are shifted.
4. Parallel-In Parallel-Out (PIPO) Shift Register
The circuit diagram of a 4 bit parallel-in-parallel-out shift register is shown in figure (4).
D0 D1 D2 D3
Parallel
Input
D0 Q0 D1 Q 1 D2 Q2 D3 Q3
Parallel
output
Clock
Q0 Q1 Q2 Q3
Figure (4): Parallel-In Parallel-Out Shift Register

It can be observed from figure (4) that the four D-type flip flops namely D-FF1, D-FF2, D-FF3 and D-FF4 form a 4-bit
parallel -in-parallel-out shift register.
v The bits D0, D1, D2, and D3 are the parallel inputs and Q0, Q1 Q2 and Q3 are parallel outputs.
v Once the clock pulse is applied, all the data at the D inputs appear at the corresponding Q outputs simultaneously.
v Thus, the complete data input will appear at the corresponding output after one clock pulse only.
Q10. Give the VHDL programs for different type of Parallel In-Serial Out (PISO)
shift register. Model Paper-2, Q5(a) library IEEE;
(or)
Use IEEE.STD _ LOGIC _ 1164. ALL;
Write VHDL code for 4-bit Serial-In Parallel-Out
register. Oct./Nov.-19, Set-3, Q6(b) M[7] Use IEEE.STD _ ARITH. ALL;
(Refer Only SIPO Shift Register) Use IEEE.STD _ LOGIC _ UNSIGNED. ALL;
Ans: entity PISOregister is
The VHDL code fof different types of shift registers are Port (C : in STD _ LOGIC;
as follows, S : in STD _ LOGIC;
Serial In-Serial Out (SISO)
P1 : in STD _ LOGIC _ VECTOR (7 downto 0);
Library IEEE;
S0 : Out STD _ LOGIC);
Use SISOregister is
port (C : in STD _ LOGIC; end PISOregister;
S1 : in STD _ LOGIC _ VECTOR (7 downto 0); architecture Behaviral of PISOregister is
S0 : OUT STD _ LOGIC _ VECTOR (7 downto 0); Signal tmp : std _ logic _ vector (7 downto 0);
end SISOregister; begin
Architecture Behavioral of SISOregister is
if S = '1' then
Signal tmp : std _ logic vector (7 downto 0);
tmp < = P1;
begin
Process (C) elsif (c' event and c = '1') then
begin S0 < = tmp (7);
if (c' event and c = ‘1') then for i in 6 downto 0 loop
for i in 0 to 6 loop tmp (i+1) < = tmp (i);
tmp (i + 1) < = Si(i);
end loop;
end loop ;
end if;
tmp (0) < = S1(6);
end if ; end process;
S0 < = tmp ; end Behavioral;
end Behavioral Parallel In-Parallel Out (PIPO)
Serial In-parallel Out (SIPO) library IEEE;
library IEEE;
Use IEEE.STD _ ARITH. ALL;
Use IEEE.STD _ ARITH. ALL;
Use IEEE.STD _ LOGIC _ UNSIGNED. ALL; Use IEEE.STD _ LOGIC _ UNSIGNED. ALL;
entity SIPOregister is entity SIPOregister is
Port (C : in STD _ LOGIC; Port (C : in STD _ LOGIC;
S1 : in STD _ LOGIC; P1 : in STD _ LOGIC _ VECTOR (7 downto 0);
P0 : Out STD _ LOGIC _ VECTOR (7 downto 0));
P0 : Out STD _ LOGIC _ VECTOR (7 downto 0));
end SIPOregister;
end PIPOregister;
architecture Behavioral of SIPOregister is
Signal tmp : std _ logic _ vector (7 downto 0); architecture behavioral of PIPOregister is
begin begin
Process (C) Process (C)
begin begin
if (c' event and c = '1') then if (c' event c = ‘1’) then
tmp < = tmp (6 downto 0) & S1;
P0 < = P1;
end if;
end process; end if;
P0 < = tmp; end process;
end Behavioral; end behavioral;

Q11. Write about 8-bit parallel-in, serial out shift register using 74 × 166 IC.
Ans:
The logic symbol of 74 × 166 ic is as shown in figure.
Figure: 74 × 166 IC
74 × 166 IC is an 8-bit parallel-in serial-out shift register with an asynchronous clear input.
When SH/LD = 1, the device perform shift operation otherwise (i.e., SH/LD = 0) it loads new data. The two clock inputs
CLK and CLKINH are connected as clock input to the internal flip-flops. The parallel data loaded from A to H appears at output
QH serially.
Q12. Draw the circuit of a bidirectional shift register with parallel loading using 2 to 4 line decoder and D-flip-
flops.
The circuit diagram of bidirectional shift register with parallel load using 2 to 4 liner decoder and D-flip-flops is illustrated
in figure below.
Parallel inputs
0
2:4 1
Decoder 2
3
SL1 SL0
Serial data in Serial data in
for right-shift for left-shift
D A QA DB QB DC QC DD QD
A B C D
CP
QA QB QC QD
Parallel outputs
Figure: Bidirectional Shift Register with Parallel Load using 2 to 4 Linear Decoder and d-flip-flops
Q13. Draw and explain the working of shift left register.
Ans: April/May-19, Set-3, Q6(b)
Shift Left Register
The register which shifts the bits from right to left direction is called shift left register. The circuit diagram of shift left
register is as shown in figure (1).
Data
After the fourth clock pulse, the last bit ‘B3’ = 0 is entered
Q1 D1 Q2 D2 Q3 D3 Q4 D4 Data
out in
from DFF4, by shifting the previous bits to its succeeding flip-
D-FF1 D-FF2 D-FF3 D-FF4 flops. Thus, all four bits are stored in register. The status of
register after fourth shift is as shown in figure (5).
Before Fourth Shift
CLK
0 1 1 0 0
Figure (1) After Fourth Shift

Operation
Initially, all the flip-flops are reset (i.e., Q1 = Q 2= Q3 = 1 1 0 0
Q4 = 0) and then, data is entered serially from right side i.e.,
Figure (5)
from D-FF4. When the positive edge clock pulse is applied data
is shifted by one position to the left and next bit is stored at the The timing diagram of shift left register is as shown in
right most flip-flop. For example, consider a 4-bit word, D = figure (6).
1100 to perform shift left operation. 1 2 3 4 5
1 1 0 0
D = CLK
B0 B1 B2 B3
After the first clock pulse, the most significant bit ‘B0’ 0
1 1 0
is entered from D-FF4. The status of register before and after Din
first shift operation is as shown in figure (2).
Before Shift Operation 0 0 0 1
Q4
0 0 0 0 1
1 1
0 0
Q3
After First Shift
0 0 0 1
1 1
0 0
Figure (2) Q2
For second clock pulse, the data stored at D4 is shifted
to D3 and at the same time second bit ‘B1’ (i.e., ‘1’) is entered 1 1
0 0
into D4. Therefore, the status of the bits after second shift is as Q1
shown in figure (3).
Figure (6)
Before Second Shift
Q14. Draw and explain the working of shift right
0 0 0 1 1 register.
Ans:
After Second Shift
Shift Right Register
0 0 1 1 A shift register, which shifts the bits from left to right
direction is known as shift right register. The circuit diagram
Figure (3)
of shift right register is as shown in figure (1).
After the third clock pulse, the Q4 bit is shifted to Q3 and
Q3 bit is shifted to Q2 and new bit ‘B2’ (i.e., 0) is entered into Data D1 Q1 D2 Q2 D3 Q3 D4 Q4 Data
D4. The status of register after third shift operation is shown in input output
figure (4). D-FF1 D-FF2 D-FF3 D-FF4
Before Third Shift
0 0 1 1 0
After Third Shift CLK

Figure (1)
0 1 1 0
The circuit consists of four D-flip-flops. After each clock
Figure (4) pulse, D-flip-flop moves the data to the next D-flip-flop.

Operation Before Third Shift
Initially, all the flip-flops (i.e., Q1 = Q2 = Q3 = Q4 = 0) are 1 1
1 1 0 0 1 0 0 0
reset and then , data is entered serially from left side i.e., from
D-FF1. For every clock pulse, data in shifted by one position After Third Shift
to the right and next bit is stored at the left most flip-flop.
Example 1 1 1 0
Consider a four bit word i.e., Figure (4)
D = 1111 to perform shift right operation. After the fourth clock pulse, the most significant bit i,e.,
B0 = 1 is entered into flip-flop, by shifting previous bits to their
1 1 1 1
next flip-flops. The status of register is shown in figure (5).
QD = Before Fourth Shift
B0 B1 B2 B3
1 1 1 1 0
After the first clock pulse, the LSB (i.e., Least Significant
Bit) ‘B3’ is entered into D-FF1. The status of the register before After Fourth Shift
and after shift operation is shown in figure (2).
Before Shift Operation 1 1 0 1
1 Figure (5)
0 0 0 0
The timing diagram of shift right register is shown in
After First Shift figure (6).
1 2 3 4
1 0 0 0
Clock
Figure (2)
After second clock pulse, the data stored at D1 is shifted
to D-FF2 and B2 bit is entered from D-FF1. The status of the
register is shown in figure (3).
Data in
Before Second Shift
1 1 0 0 0
After Second Shift Q1
1 1 0 0 Q1
Figure (3) Q3
After third clock pulse, the bit Q2 is shifted to next flip-flop Q4
and Q1 bit is shifted to Q2 and new bit B1 (i.e., B1 = 1) is entered
into register. The status of register is shown in figure (4). Figure (6)
Q15. Write a VHDL code for an n-bit left-to-right shift register using ‘FOR’ loop. Model Paper-3, Q5(a)
(or)
Write down the VHDL code for an n-bit left to right shift register. Oct./Nov.-19, Set-2, Q6(b) M[7]
Ans: The VHDL code for an n-bit left-to-right shift register using ‘FOR’ loop is given below,
LIBRARY ieee;
ENTITY lrshiftn IS
PORT (R : IN STD_LOGIC_VECTOR(N – 1 DOWNTO 0);
L, w : IN STD_LOGIC;
Q : BUFFER STD_LOGIC_VECTOR(N – 1 DOWNTO 0));
END lrshiftn;
ARCHITECTURE Behavior OF lrshiftn IS
BEGIN
PROCESS
BEGIN
IF L = ‘1’ THEN
Q <= R;
ELSE
Genbits : FOR i IN 0 TO N-2 LOOP
Q(i) <= Q(i + 1);
END LOOP;
Q(N – 1) < = W;
END IF;
END PROCESS;
END Behavior;
Q16. Draw a 4 bit bi-directional shift register logic diagram and explain its operation.
Ans: Nov-10, Set-4, Q6(b)
4-bit Bi-directional Shift Register

A shift register which is capable of shifting data either right-to-left or left-to-right is known as bi-directional shift register.
The logic diagram of a 4-bit bidirectional shift register is shown in figure (3).
Mode control
Shift left (DL)
M=1
Shift right (DR)
A4 B4 A3 B3 A2 B2 A1 B1
C4 C3 C2 C1
D4 Q4 D3 Q3 D2 Q2 D1 Q1
Clock
CLR
Figure
In figure, mode control (M) is used for performing either right shift or left shift for the given data. When M = 0, the data
is left shifted. When M = 1, the data is right shifted.
Operation
Case (i)
v When M = 1, the AND gates A4, A3, A2 and A1 are enabled, whereas B4, B3, B2 and B1 are disabled. The output of each OR
gate is applied to the respective D-flip-flop.
v When the clock = 1 and DR = 1, the data bits are shifted one place to right. Thus, the circuit acts as shift right register.
Case (ii)
v When M = 0, the AND gates B4, B3, B2, and B1 are enabled whereas A4, A3, A2 and A1 are disabled. The output of each
OR gate is applied to the respective D input of each flip-flop.
v When clock = 1 and DL = 1, the data bits are shifted one place to left. Thus, this circuit acts as shift left register.

Q17. Draw and explain 4-bit universal shift register.
Ans: (April/May-19, Set-4, Q6(b) | April/May-13, Set-3, Q7(a) | April-12, Set-2, Q7(b))
Universal shift register is defined as a register which has both right and left shifting functions along with parallel load
capability.
4-bit Universal Shift Register: The diagrammatic arrangement of a 4-bit universal shift register is shown in figure. It consists
of four D-flipflops and four multiplexers. Where S1 and S0 acts as two common selection inputs to the four multiplexers. When
S1S0 = 00, the input at pin 0 in each multiplexer is selected and when S1S0 = 01, the input at pin 1 in each multiplexer is selected,
and similarly for the other two inputs. Table shows the selection inputs control of the register operation.
Parallel inputs
I3 I2 I1 I0
Serial
input Serial
for input
shift-right for
shift-left
3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0
S1
4×1 4×1 4×1 4×1
S0 MUX MUX MUX MUX
f f f f
Clock
D D D D
Clear
Q Q Q Q
Q3 Q2 Q1 Q0
Parallel outputs
Figure: Parallel Outputs

Select Input
Register Operation
S1 S0
0 0 No change
0 1 Shift right
1 0 Shift left
1 1 Parallel load
Table
Operation
When S1S0 = 00, the D-inputs of the flipflops get the present value of the register. The above condition forms a path from
the output of each flipflop in to the input of the same flipflop. There is no change of the register state due to the next clock edge.
When S1S0 = 01, a path is formed from terminal 1 of the multiplexer inputs to the D-inputs of the flipflops. The applied serial
input is transferred into the Q2 flipflop due to a shift right operation. When S1S0 = 10, the other serial input is transferred into the
Q1 flipflop due to a shift left operation. Finally, when S1S0 = 11 the binary information on the parallel input lines is simultaneously
transferred into the register during the next clock edge.
Q18. Write down truth table, VHDL code for the 4 bit register with parallel load. Also draw the circuit and
output waveform.
Shift Register with Parallel Load

The logic symbol of IC 74194 is shown in figure (1)
+5 V
R 74 × 194
11 CLK
CLOCK
1 CLR
10 Wired as
S1 a shift-lett
9
RESET S0 shift register
(LOAD) 7 LIN
6 D QD 12
Q0
5 C QC 13
Q1
4 A QB 14 Q2
3 LIN QA 15
Q3
2
UT
Figure (1)
The logic diagram of 74 × 194 IC is shown in figure (2).
DSR DA DB DC DC DSL
(2) (3) (4) (5) (6) (7)
(9)
S0
S1(10)
(11)
CLK
CLR
(1)
R R0 R R0 R R0 R R0
CP CP CP
S Q S Q S Q S Q
(15) (14) (13) (12)
QA QB QC QD
Figure (2)
The 74 × 194 IC is called universal shifter register, because its contents can be shifted in either of the two directions (left
or right) depending on the control input. It has four parallel inputs i.e., DA, DB, DC, DD and two control inputs i.e., S0, S1. When
control inputs are S0 = 1 and S1 = 1, data presents at input i.e., (DA – DD) is shifted to output i.e., (QA – QD).
When S0 = 1 and S1 = 0, during 0 → 1 transition of clock. Shift-right takes place and serial data bit is applied at the DSR
(Shift-right serial input)
When S0 = 0 and S1 = 1, during 0 → 1 transition of clock shift - left takes place and serial data bit is applied at the DSL
(shift-left serial input).

Mode select function is shown in table (2).
Operation mode Inputs Outputs
CLK CLR S1 S0 DSR DSL Dn QA QB QC QD
Reset (clear) × 0 × × × × × 0 0 0 0
� 1 1 0 × 0 × QB QC QD 0
Shift-left
� 1 1 0 × 1 × QB QC QD 1
� 1 0 1 0 × × 0 QA QC QC
Shift-right
� 1 0 1 1 × × 1 QA QB QC
Parallel load � 1 1 1 × × Dn DA DB DC DD
Hold (do nothing) × 1 0 0 × × × QA QB QC QD
Table (1)
Select Inputs
Register operation
S1 S0
0 0 No change
0 1 Shift right
1 0 Shift left
1 1 Parallel load
Table(2)
VHDL Code
LIBRARY ieee;
USE ieee.std-logic-1164.all;
ENTRY univ-sr IS
PORT (CLR, S1, S0, CLK : IN STD-LOGIC;
LIN, RIN, A,B,C,D : IN STD-LOGIC;
QA, QB, QC, QD : OUT STD-LOGIC);
END univ-sr;
ARCHITECTURE Behavior OF Univ-sr IS
AQ = Qreg(3), QB = Qreg(2), Qc = Qreg (1), QD = Qreg (0)
SIGNAL Qreg : STD-LOGIC-VECTOR (3 down to 0);
BEGIN
PROCESS (CLR, CLK)
BEGIN
IF (CLK’ event and CLK = ‘0’) THEN
IF CLR = ‘0’ THEN
Qreg < = ‘0’;
Q19. Design a 4-Bit, 4-State Ring Counter With Circulating 1 Using IC 74194.
Ans:
The figure (1) illustrates the 4-bit, 4-state ring counter with circulating 1.
+5 V
R
74 × 194
11
CLOCK CLK
1
RESET_L CLR wired as a
10 S1 shift-left
9 shift register
S0
7 LIN
6 12
D QD Q0
5 13
C QC Q1
4 14
B QB Q2
3 15
A QA Q3
2 74 × 04
RIN
1 2
U1
Q3_L U2
Figure (1)
In the circuit, IC 74194, a universal shift register performs left shift operation on the contents loaded in it. The content,
0001 is loaded into the register when the input is RESET. It the RESET is denied, IC left shifts, the bits in it for each clock pulse.
To perform left shift, the input LIN is Connected to Q3 so that next states will be 0010, 0100, 1000, 0001...
The figure below represents the timing diagram of 4-bit, 4-state ring counter.
CLOCK
RESET
Q0
Q1
Q2
Q3
STATE S1 S2 S3 S4 S1 S2
Figure (2)
Since, a ring counter is not robust, it may go to 0000 states and stays forever. If the input state is changed i.e., two 1s are
given (for ex: 0101), then the counter counts for incorrect number of cycles. The figure below shows the state diagram of 4-bit
ring counter of 16 states.
0001
0000
0010 1000
0011 0111
0101
0100
0110 1001 1110 1011
1111 1101
1010 1100
Figure (3)
From the figure, it is clear that, out of 16 states, 12 are abnormal states. In order to avoid this case, self correcting counters
are used.

Q20. Design a self correcting counter using IC 74194.
Ans:
A self correcting counter is built to overcome the limitations of simple counters by moving the state to a safe state when any
problem is on contused. One such counter is 4-bit, 4-state self correcting ring counter with circulating 1 as shown in figure (1)
+5 V
R
74 × 194
11
CLOCK CLK
1
CLR
10 wired as a
S1 shift-left
RESET 9 S0 shift register
(load)
7
LIN
6 12
D QD Q0
5 13
C QC Q1
4 14
B QB Q2
3 15
A QA Q3
2
RIN 1 74 × 27
2 12
U1 13
ABC0 U2
Figure (1): Logic Diagram of Self Correcting Ring Counter

Unlike a simple ring counter, self correcting ring counter uses a NOR gate, which shifts the bit 1 to the input, LIN when
there least significant bits, Q0 ,Q1 and Q2 are 0. Figure (2) show the state diagram of self correcting ring counter.
0001 0000
0010 1000
1001 0100 1100
1010 0110 1110
0101 1101 0011 1011 0111 1111
Figure (2): State Diagram

From the state diagram, it can be observed that, the counter reaches the 0001 state four clock pulses, without depending
upon initial state. An external RESET signal is applied only if the simulation is at starting point and to make sure that counter is
in synchronous with other components in the system.
Generally, an n-bit self correcting ring, counter employs (n-1) NDR gates as input and leads the abnormal states to normal
states in (n-1) clock pulses.
Q21. Design a self-correcting 4-bit, 4-state ring counter with a single circulating 0 using IC 74LS194.
Design of a Self-correcting 4-bit, 4-state Ring Counter with a Single Circulating ‘0’ using 74 x 194
+5 V
R
74 × 194
11
CLOCK CLK
1
CLR
10 wired as a
S1 shift-left
RESET 9
S0 shift register
(load)
7
LIN
6 12
D QD Q0
5 13
C QC Q1
4 14
B QB Q2
3 15
A QA Q3
2
RIN 1 74 × 10
2 12
U1 13
ABC1_L U2
Figure (1)
A self-correcting counter is designed so that all abnormal states have transitions leading to normal states. If something
unexpected happens, counter or state machine should enter into a “Safe” state. The logic diagram of a self-correcting 4-bit, 4-state
ring counter with a single circulating ‘0’ using 74 × 194 is shown in figure (1). This is a most convenient way to design a self-
correcting ring counter.
The state diagram for a self-correcting ring counter with a single circulating ‘0’ is shown in figure (2).
0111
1110 1011
1101
Figure (2)
Q22. Discus in brief about 8-bit, 8-state Johnson counter and 4-bit, 8-state self-correcting Johnson counter.
Ans:
A counter which the complemented serial output of an n-bit shift register is Fed back to the serial input is known as Johnson
counter. It is also called as trusted ring counter and Mobius counter. It consists of 2n states.

The figure (1) represents the logic diagram of 8-bot, 8-state Johnson counter or 4-bit Johnson counter.
+5 V
R
74 × 194
11
CLOCK CLK
1
10 S1 shift-left
9 shift register
S0
7 LIN
6 12
D QD Q0
5 13
C QC Q1
4 14
B QB Q2
3 15
A QA Q3
2 74 × 04
RIN
1 2
U1
Q3_L U2
Figure (1): Logic Diagram of 4-bit Johnson Counter

Figure (2) shows the timing diagram of above circuit,
CLOCK
RESET
Q0
Q1
Q2
Q3
STATE S1 S2 S3 S4 S5 S6 S7 S8 S1 S2 S3
Figure (2)
The table below represents the states of 4-bit Johnson counter
State name Q3 Q2 Q1 Q0
S1 0 0 0 0
S2 0 0 0 1
S3 0 0 1 1
S4 0 1 1 1
S5 1 1 1 1
S6 1 1 1 0
S7 1 1 0 0
S8 1 0 0 0
Table
Usually, an n-bit Johnson counter contains 2n–2n
abnormal states. Similar to simple ring counter, Johnson counter is also
robust to The hardware problems. So, self-correcting 4-bit, 8-state Johnson counter is built as shown in figure (3).
+5 V
R
74 × 194
11
CLOCK CLK
1
10 shift-left
S1
9 shift register
S0
7
LIN
6 12
D QD Q0
5 C 13
QC Q1
4 14
B QB Q2
3 15
A QA Q3
2 2 74 × 02
RIN 1
3
U1
U2
74 × 04
1 2
Q3_L U3
LOAD
Figure (3): Logic Symbol of 4-bit, 8-state Self Correcting Johnson Counter
This circuit eliminates abnormal states by loading 0001 as next state, when the counter reaches 0000 state.
Q23. Write a VHDL program for 16-bit barrel shifter for left circular shift only?
VHDL program for 16 bit barrel shifter for left circular shift only is given below.
Library IEEE;
use IEEE. STD_LOGIC_1164.ALL;
use IEEE. STD_arith.all;
Entity barrelleft is
port (Din: in STD_LOGIC_VECTOR(15 downto 0);
S: in STD_LOGIC_VECTOR (3 downt 0);
Dout: out STD_Logic_Vector (15 downto 0))
end barrelleft;
architecture behaviour of barrelleft is
Subtype DATAWORD is STD_LOGIC_VECTOR (15 downto 0);
Variable N:Integer
Variable TEMPD:DATAWORD;
begin
process (Din, S)
N: = CONV_INTEGER(S);
for i IN 1 to N loop
TEMPD: = TEMPD (14 downto 0) & TEMPD (15);
end loop;
Dout < = TEMPD;
end process
end behaviour;

Q24. Write a VHDL code for a 4-bit universal shift temp (3) < = sir,
register.
q < = temp;
Ans:
--HOLD
A VHDL code for 4-bit universal shift register is as follows,
when “00” = >
library ieee;
temp < = temp;
q < = temp;
entity USR is
when others = > null;
port (clk : in std_logic;
end case;
rst : in std_logic;
end if;
sir : in std_logic;
end process;
sil : in std_logic;
end Behavioral;
d : in std_logic_vector (3 downto 0);
Q25. Discuss the realization of sequence generator
q : out std_logic_vector (3 downto 0); with diagram.
s : in std_logic_vector (1 downto 0)); Ans:
end USR; A sequence generator can be constructed in two methods.
architecture Behavioral of USR is 1. Sequence Generators using counters
signal temp : std_logic_vector (3 downto 0); 2. Sequence generators using shift registers
1. Sequence Generators Using Counters
begin
The block diagram of sequence generator using
process (rst, clk, s, d, sir sil) counter constants of counter and next state decoder as shown
begin in figure (1).
if rst = ‘1’ then
temp < = “0000”;
FF1 Next
q < = “0000”;
elsif (clk = ‘1’ and clk’event) then FF2 State
FF
case s is
inputs FFn Decoder
-- PARALLEL LOAD
when “11” = > Counter FF outputs
temp < = d; Figure (1)

q < = temp; Design Procedure
--SHIFT LEFT [0] [0] [0] [0] Step 1 : Determine the number of flip-flops required the number
of flip-flops used to generate a given sequence can be determined
-- [0] [0] [0] [sil] as follows
when “01” = > (a) Find the number of 1’s in the sequence
temp < = d; (b) Find the number of 0’s in the sequence
temp (3 downto 1) < = temp (2 downto 0); (c) Select the maximum value from both. Then,
the number of flip-flops ‘n’ selected using the
temp (0) < = sil; condition,
q < = temp; max (0’s, 1’s) £ 2n – 1
--SHIFT RIGHT [0] [0] [0] [0] Step 2 : State assignment
-- [sir] [0] [0] [0] Assign unique states corresponding to each bit in
the given sequence such that the flip-flop representing least
when “10” = >
significant bit generates the given sequence.
temp < = d; Step 3 : Draw the state diagram and derive the excitation table
temp (2 downto 0) < = temp (3 downto 1); for the counter.
Step 4 : Obtain the simplified Boolean expression for each flip- Step 3 : k-map simplification for Din
flop input and circuit output functions using k-maps.
Q1Q0
Step 5 : Sketch the logic diagram using the simplified
Q3Q2 00 01 11 10
expressions.
00 × × × × Q
2. Sequence Generator using shift Registers 3
The block diagram of a sequence generator using shift 01 × 1 1 ×

registers consists of shift registers and a next state decoder as
11 × 1 1
Clock 10 × × 1
SID Shift register Q Q

1 0
Q0 Q1 Qn \y = Q +Q +Q
Qn – 1 0 1 3
Step 5 : Draw the logic diagram
y Next state decoder The logic diagram of sequence generator to generate the
sequence is as shown in figure (4).
Figure (2)
Here, the initial state is 1101. Hence, the inputs are,
The output of next state decoder is a function of QA, QB
.... Qn. It decodes the output of shift register and generates the A = 1, B = 1, C = 0, D = 1.
given sequence.
Example : Design a sequence generator to generate the
sequence 1101011 by shift register method.
Solution : The given sequence is 1101011.
Step 1 : Determine the number of flip flops from the condition.
N £ 2n – 1
7 £ 2n – 1 < 2n
Þ 8 < 2n Þ n ³ 3
Figure (4)
Let, n = 4
Step 2 : State assignment 3.2 Ripple Aysnchronous Counters, Syn-
of
The functional table of the sequence is shown in table chronous Counters
below. Q26. Explain synchronous and ripple counters.
Compare their merits and demerits.
Clk Q0 Q1 Q2 Q3 y
Ans:
1 1 1 1 0 1
Counter
2 1 1 1 1 0
A sequential circuit which counts the number of clock
3 0 1 1 1 1 pulses is known as ‘counter’.
4 1 0 1 1 0 Synchronous Counter
5 0 1 0 1 1 A counter is said to be synchronous if individual clocks
6 1 0 1 0 1 of all the flipflops are connected i.e., in synchronous counter a
change in clock pulse can bring a change in flipflops input.
7 1 1 0 1 1
Asynchronous Counter
1 1 1 1 0 1
A counter is said to be asynchronous if all the clocks of
2 1 1 1 1 0 all the flip flops are not connected. The output of first flip-flop
is fed as clock pulse to next flip-flop. Asynchronous counter is
3 0 1 1 1 1
also known as ripple counter.

Difference between Synchronous and Asynchronous Counters
Synchronous Counter Asynchronous (Ripple) Counter

1. In synchronous counter, a single clock pulse is connected 1. In asynchronous counter, output of first flip flop is connected
to all the flip flops. drives the clock or next flip-flop.
2. Speed of operation is relatively high. 2. Speed of operation is very low.
3. Propagation delay is less. 3. Propagation delay is more.
4. The overall speed of synchronous counter depends only 4. The overall speed of the asynchronous counter depends not
on the frequency of the clock. only on the frequency of clock but also on propagation delay
of each flip flop.
5. Synchronous counters are parallel counters. 5. Asynchronous counters are serial or series counters.
6. The clock pulses are distributed throughout the system 6. Due to feedback among logic gates, the system may operate
in such a way that the effect takes place at the arrival of in an unpredictable manner and may become unstable.
each pulse, confirming the system to be stable.
7. Synchronous counters do not cause any difficulty to the 7. Asynchronous counters do cause many difficulties to the
designer. Hence, they are most frequently used. designer. Hence, they are very rarely used.
Table
Q27. Explain the operation of a BCD Ripple counter. For
Ans: For 2n ≥ N
Þ 2n ≥ 10
Operation of BCD Ripple Counter
Þ n ≥ log210
v Modulo-10 asynchronous counter is a type of decode
Þ n ≥ 3.32
counter that counts from 0 to 9 and it is also termed as
BCD ripple counter. Þ n=4
\ 4 flip flops are required.
v It is constructed by using four flip flops, because a very
small value of n satisfying the condition N ≤ 2n is n = 4 2. Select the type of flip flop to be used JK.
(i.e., 10 ≤ 2n). 3. Write the count table for the counter.
v Thus, the possible states in a mod-10 counter are 16
After Count
and out of these states only 10 states i.e., 0000 to 1001 Reset (R)
are valid and remaining 6 states are invalid. Initially Pulses
QA QB QC QD
the counter is in 0000 state, and after first clock pulse,
it goes to 0001 state, after second pulse, it goes to 0010 0 0 0 0 0 0
state and so on. 1 0 0 0 1 0
v Thus, after ninth clock pulse the counter is in 1001 state 2 0 0 1 0 0
and upon the application of tenth clock pulse, it goes to
3 0 0 1 1 0
1010 state temporarily, but suddenly resets to initial state
i.e., 0000. 4 0 1 0 0 0
v This happens, because of the feedback provided to the 5 0 1 0 1 0
counter.
6 0 1 1 0 0
v Thus, a glitch appears in the waveform of Q2 for tem-
7 0 1 1 1 0
porary state i.e., 1010, the reset signal R = 1, R = 0 for
0000 to 1001 and R = × for 1011 to 1111. The count 8 1 0 0 0 0
table for mod-10 counter is illustrated in table. 9 1 0 0 1 0
Design Steps 10 0 0 0 0 1
1. Determine the number of flip flops required. Table
Since the BCD counter has 10 states (0 – 9), N = 10 The states from 11 to 15 are considered don’t cares.
K-Map for Reset ‘R’
QC QD
QA QB 00 01 11 10
00
0 1 3 2
01
4 5 7 6
11 × × × × Q AQ C
12 13 15 14
10 × 1
8 9 11 10
∴ R = QA QC
Thus, from the K-map equation, it can be analyzed that, the feedback is given from second to fourth flip flop. For active-
high reset, QA QC is given to clear terminal and for active-low reset QA QC is connected to CLR of all the T flipflops.
5. Draw the logic diagram
Using JK Flip Flop
The J and K inputs can be connected to either to logic 1(high) or to the outputs of next flip flops as shown in
figure (1).
R
Logic 1
1
(high)
JA QA JB QB JC QC JD QD
CLR FF1
KB CLR QA KB CLR QB KC CLR QC KDCLR QD
Figure (1)
Timing Diagram
The LSB, QA of binary ripple counter is complemented for every clock pulse and QA changes its state from 1 to 0. Since
the complemented output of first flip flop (F0) is connected to the clock input of the second flip-flop (F1). This flip-flop changes
it state from 1 to 0 and so on for other higher order bits of a ripple counter. The wave form of 4 bit ripple counter is shown in
figure (2).
Figure (2): Waveform

For instance, to perform the transition from count-3 (0011) to count 4 (0100). The LSB i.e., QA is complemented with
clock pulse and changes from 1 to 0. This triggers QB and complements it. Therefore, QB changes from 1 to 0 which complements
output QC changes from 0 to 1 i.e., positive transition.
Thus, the transition of count 0011 to count 0100 is achieved by changing one bit at a time, succession and signal propagates
in ripple fashion from one stage to preceding stage.

Q28. Give classification of asynchronous counter ICs.
Ans: Asynchronous counters are classified into three types. They are,
1. Group A asynchronous counter ICs
2. Groups asynchronous counter ICs
3. Group C asynchronous counter ICs.
1. Group A Asynchronous Counter ICs: The BCD counter ICs 7490 and 74920 come under this category. The basic internal
structure of 7490 IC illustrated in figure (1).
Ouputs
(MSB)
QA QB QC QD
Input A FFB FFC FFD

FFA Mod-5 counter
Input B R1 R2 S1 S2
Reset inputs Set inputs
Figure (1)
The IC is made up of four flip-flops that are internally connected to form a mod-2 and mod-5 counters. Which can be used
together or separately. The fli-flop FFA is a mod-2 counter but the flip-flops FEB, FFC and FFD together from a mod-5
counter. The flip-flop is cleared by connecting reset inputs R1 and R2 to logic 1. At a logic 1 level, both set inputs S1 and
S2 set the counter to 1001.
2. Groups Asynchronous Counter ICs: The 4-bit ripple binary counter ICs 7493, 74293 and divide-by-12 counter IC7492
come under this category. The basic internal structure is illustrated in figure (2).
Ouputs
(MSB)
QA QB QC QD
Input A FFB FFC FFD

FFA Mod-6 in 7492
Mod-8 in 7493, 7493
Input B R1 R2
Reset inputs
Figure (2)
The function of these ICs is similar to that of IC 7490. The only difference is that IC7492 ha only reset inputs. Also, the
mod-6 counter does not count in binary order.
Table below shows the sequence of the mod-6 counter.
QD QC QB
0 0 0
0 0 1
0 1 0
1 0 0
1 0 1
1 1 0
Table: Sequence of Mod-6 Counter
These ICs are used for frequency division rather than counting operation.
3. Group C Asynchronous Counter ICs
The preset table BCD counters 74196 and 74196 (mod-5) and 4-bit binary counters 74177 and 74197 (mod-8) come under
this category. The basic internal structure is illustrated in figure (3).
Outputs
QA QB QC QD (MSB)
Input A FFB FFC FFD
FFA Mod-5 in 74176 & 74196

Mod-8 in 74177 & 74197
Load
Clear Input B PA PB PC PD (MSB)
Preset inputs
Figure (3)
The counter is cleared when CLR = 0 setting load input to logic 0 stops the counter and loads the binary number available
at the present inputs into the counter. By connecting load and clear inputs to logic 1, the circuit can be used as up counter.
The preset table 4-bit counters can be used as variable mod-n counter. The modulus of such counter is given by n = 15
binary number present at the preset inputs).
Q29. Design a normal mod-12 counter using IC 74161.
Ans:
The block diagram of mod-12 counter using 74161 is as shown in figure and the function table or these ICs are given
in figure. There are two independent enable inputs in this IC, denoted by the letters ENT and ENP. Asynchronous counting is
terminated, when either of these inputs is set to logic 0. Hence, we set these inputs are set to logic 1 figure. The ripple carry (RC)
output switches from logic 0 to logic, when the counter reaches its highest count. In this case, the highest count is 1011.
QA QB QC QD
Pulses CK
ENT 74161
Logic 1
ENP Load Cr
PA PB PC PD Logic 1
Figure: Mod-12 Counter Using IC 74161
The circuit is intended to be used for standard up-counting operations alone (last row of function table). The Cr terminal
is connected to the QD and QC outputs using a NAND gate, which clears the counter when the output reaches 1100, as seen here.
The mod-12 counter has a range of states ranging from 0000 to 1011. The functional table of IC 74161 is illustrated in table (1).
Load L ENP ENT Cr CK Mode
0 × × 1 ↑ Preset
1 0 1 1 × Stop count
1 × 0 1 × Stop count, disable RC
× × × 0 • Reset to zero
1 1 1 1 ↑ Up count
Table: Functional Table
Q30. Write the design steps of synchronous counters.
Ans:
The design procedure of synchronous counters for any given count sequence and modulus is as follows,
1. Makes use of the formula n 2N and calculate the required number of flip flops.
2. Count sequence should be written in the tabular form.
3. By making use of excitation table or truth table of flip flops find those inputs of flip flops which are available from the
present state to the next state.
4. Construct Karnaugh map for each input provided to the flip flop which is expressed in terms of flip flop outputs and the
input variables.
5. Now simplify the Karnaugh map to get the reduced form of expression.
6. For minimized expressions the circuit can be designed by using flip flops and other gates.
Q31. Design a 4 bit synchronous binary even counter and write its behavioural mode;.
Ans: (Model Paper-2, Q5(b) | Oct./Nov.-16, Set-2, Q7)
A synchronous binary even counter generates the sequence as 0 ® 2 ® 4 ® 6 ® 8 ® 10 ® 12 ® 14 ® 0

These are representd in binary as 0000 ® 0010 ® 0100 ® 0110 ® 1000 ® 1010 ® 1100 ® 1110 ® 0000
The undesired states 1, 3, 5, 7, 9, 11, 13 and 15 are considered as dont cares for the next clock pulse or state.
The design steps of a 4 bit synchronous binary even counter are as follows,
1. The state diagram of the counter that counts the possible 4-bit even states is as shown in figure (1).
0
14
12 2
10 4
8 6
2. The counter requires four JK flipflops since, it is a 4-bit counter.
3. The excitation table of JK flip flop is given in table (1).
Present state Next state Output
Qn Qn+1 J K
0 0 0 ×
0 1 1 ×
1 0 × 1
1 1 × 0
Table (1)
The excitation table for 4-bit synchronous even counter using JK flip-flops can be obtained from table (1) as shown in table (2).
Present State Next State Flip-flop Excitation Inputs
QA QB QC QD Q *A Q *B Q *C Q *D JA KA JB KB JC KC JD KD
0 0 0 0 0 0 1 0 0 × 0 × 1 × 0 ×
0 0 0 1 × × × × × × × × × × × ×
0 0 1 0 0 1 0 0 0 × 1 × × 1 0 ×
0 0 1 1 × × × × × × × × × × × ×
0 1 0 0 0 1 1 0 0 × × 0 1 × 0 ×
0 1 0 1 × × × × × × × × × × × ×
0 1 1 0 1 0 0 0 1 × × 1 × 1 0 ×
0 1 1 1 × × × × × × × × × × × ×
1 0 0 0 1 0 1 0 × 0 0 × 1 × 0 ×
1 0 0 1 × × × × × × × × × × × ×
1 0 1 0 1 1 0 0 × 0 1 × × 1 0 ×
1 0 1 1 × × × × × × × × × × × ×
1 1 0 0 1 1 1 0 × 0 × 0 1 × 0 ×
1 1 0 1 × × × × × × × × × × × ×
1 1 1 0 0 0 0 0 × 1 × 1 × 1 0 ×
1 1 1 1 × × × × × × × × × × × ×
Table (2): Excitation Table
4. The minimal expressions for JA, RA, JB, KB, JC, KC, JD and KD can be obtianed using k-maps as described below.
For JA For KA
QCQD QCQD
QAQB QAQB
00 01 11 10 00 01 11 10
00 × × 00 × × × ×
0 1 3 2 0 1 3 2
01 × 5 × 7 16 QBQC 01 × 4 × 5 × 7 ×6 QBQC
4
11 × 12 × 13 × 15 ×14 11 × 13 × 15 114
12
10 × × × × 10 × ×
8 9 11 10 8 9 11 10
` J A = K A = A B QC
For JB For KB
QCQD QCQD
QAQB QAQB
00 01 11 10 00 01 11 10
00 × × 1 00 × × × ×
0 1 3 2 0 1 3 2
01 × × 5 × 7 ×6 QC 01 × 5 × 7 16 QC
4 4
11 × 12 × 13 × 15 ×14 11 × 13 × 15 114
12
10 × × 1 10 × × × ×
8 9 11 10 8 9 11 10

` J B = K B = QC

For JC For KC
Q CQ D Q CQ D
QAQB QAQB
00 01 11 10 00 01 11 10
00 1 × × × 00 × × × 1
0 1 3 2 0 1 3 2
01 1 × 5 × 7 ×6 1 01 × × 5 × 7 16 1
4 4
11 1 12 × 13 × 15 ×14 11 × 12 × 13 × 15 114
10 1 × × × 10 × × × 1
8 9 11 10 8 9 11 10

` JC = KC = 1
For JD For KD
Q CQ D Q CQ D
QAQB QAQB
00 01 11 10 00 01 11 10
00 × × 00 × × × ×
0 1 3 2 0 1 3 2
01 × 5 × 7 01 × 4 × 5 × 7 ×6
4 6
11 × 13 × 15 11 × 12 × 13 × 15 ×14
12 14
10 × × 10 × × × ×10
8 9 11 10 8 9 11

` J D = K D = 0
The synchronous binary even counter is implemented using negative edge trigged JK flipflops with the help of obtained
minimal expressions which is as shown in figure (2).
QC
QB
1 0
JA QA JB QB JC QC JD QD
KA QA KB QB KC QC KD QD
Clock
Figure (2)
The behavioural style of VHDL code for 4 bit synchronous binary even counter is mentioned below:
library IEEE;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity evencounter_4bit is
port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR(3 downto 0) );
end evencounter_4bit; The truth table of twisted ring counter is shown in table.
architecture evencounter_4bit_arch of evencounter_4bit is Q0 Q1 Q2 Q3 After Clock Pulse
begin 0 0 0 0 0
process (clk, reset)
1 0 0 0 1
variable m : std_logic_vector (3 downto 0) := “0000”;
1 1 0 0 2
begin
1 1 1 0 3
if (reset=’1’) then
m:= “0000”; 1 1 1 1 4
elsif (rising_edge (clk) && m%2==0) then 0 1 1 1 5

m:= m + 2; 0 0 1 1 6
else 0 0 0 1 7
m:= “0000”; 0 0 0 0 8
end if; 1 0 0 0 9
dout <= m;
Table: Truth Table
end process;
end evencounter_4bit_arch;
Q32. Draw the circuit diagram of Johnson counter
using D flip-flops and explain its operation with
the help of bit pattern.
Ans:
Twisted Ring Counter (Johnson Counter)
Twisted ring counter is also known as Johnson counter or
switch-tail ring counter. It connects the complement of output of Figure (2): Timing Diagram of a 4-bit Twisted Ring Counter
last shift register to the input of first register and then circulates An n flip-flop Johnson counter can have 2n unique states
the stream of 1’s followed by 0’s around the ring. and can count up to 2n pulses. So it is a mod-2n counter.
The logic diagram of a 4-bit Johnson counter using Q33. Discuss about the working of Johnson counter
D-flip-flop is shown in figure (1). The Q output of each stage using 74 LS194.
is connected to the D input of next stage but the Q output of Ans: (Model Paper-3, Q5(b) | Oct./Nov.-16, Set-1, Q7(a) M[8])
the last stage is connected to the D input of the first stage. This The circuit diagram of 4-bit Johnson counter (or) twisted
feedback arrangement produces a unique sequence of states. ring counter using IC74LS194 is shown in figure (1).
+5 V
R
74 × 194
•
11
CLOCK CLK
Figure (1): Logic Diagram of 4-bit Twisted Ring Counter Using 1
D-flip-flops 10 S1 shift-left
9 shift register
Before applying the clock pulses, clear the output of all S0
the flip-flops to 0000 i.e., Q3 Q2 Q1 Q0 = 0000. 7 DSL
6 Q0 12
v Since the output of last stage, Q4 = 0, Q 4 = 1 is fed to D0. D
5 C Q1 13
4 14
v At the end of first falling edge of clock, Q0 = 1 and Q1 B Q2
15
3
= Q2 = Q3 = 0. A Q3
2 74 × 04
DSR
v For next clock pulse, Q0 = Q2 = 1 and Q2 = Q3 = 0. 1 2
Q3_L
v The counter counts the sequence for the next clock pulses
and it is repeated after states. Figure (1)

If the register operates in both serial and parallel modes, it is called as “Universal shift register. Here, IC74194 is a 4-bit
universal shift register which has 4-parallel data inputs and 2-control inputs (S0 and S1). DSL and DSR are the shift-left and shift-
right serial input pins. The register IC pins are connected as shown in above figure. An IC7404 (NOT gate) is connected between
Q3 and DSL inputs.
The four parallel data inputs (A, B, C, D) are given to inputpins of IC. Clock is applied at CP-pin attains certain state and
keeps on counting a set of 8-states over the time period during which the clock is active.
The timing diagram for 4-bit and 8-state Johnson counter is shown in figure (2).
CLOCK
RESET
Q0
Q1
Q2
Q3
STATE S1 S2 S3 S4 S5 S6 S7 S8 S1 S2 S3
Figure (2)
The output state-table consisting of 8-states (2N) is shown below.
State name Q3 Q2 Q1 Q0
S1 0 0 0 0
S2 0 0 0 1
S3 0 0 1 1
S4 0 1 1 1
S5 1 1 1 1
S6 1 1 1 0
S7 1 1 0 0
S8 1 0 0 0
Table
Q34. Draw the logic diagram of 74 x 163 binary counter and explain its operation.
Ans:
74 × 163 is a synchronous 4-bit binary counter. It has clear and load inputs, both of active-low type, two enables EN1, EN2,
both should be logic ‘1’ for normal operation of counter. It has four load inputs LA, LB, LC, LD. When LD pin is made logic ‘0’
then outputs Q0, Q1, Q2, Q3, gets values of LA, LB, LC, LD respectively. ‘C0’ is output pin which goes high to indicate count
over (i.e., Maximum count reached).
Logic symbol of 74 × 163 IC is shown in figure (1).
74 × 163
CLOCK CLK
CLR
LD
ENP
ENT Q0
Q1
LA
Q2
LB
Q3
LC
LD
CO
Figure (1)
TheWARNING:
internal logic diagram of 74 of
Xerox/Photocopying × 163 IC isisas
this book shown inact.
a CRIMINAL figure (2).found guilty is LIABLE to face LEGAL proceedings.
Anyone
CLK
LD P1
P2
CLR
P3
LA D0
D Q Q0 (LSB)
CLK
P4
P5
Q0
LB D1
P2 D Q1
CLK
P6
P8
Q1
LC D2
D Q2
P9
CLK
P10
Q2
LD D3
D Q3 (MSB)
CLK
Q3
C0
EN 1
EN 2
Figure (2): Logic Diagram of 74 × 163 IC

P1 to P10 ; D0 to D3 are points shown in figure (2).
When LD = ‘0’ and CLR = ‘1’ i.e., load condition is made, then D1 is LA, D2 is LB, D3 is LC and D4 is LD. Hence LA,
LB, LC, LD are loaded to outputs Q0, Q1, Q2, Q3. (Because when LD = 0, CLR = 1 then P1 = 1, P2 = 0, P3 = LA , P4 = 1, ∴
D1 = LA).
When CLR pin is made ‘0’ and LD = ‘1’ then D0, D1, D2, D3 become ‘0’ (Because when CLR = 0, LD = 1 then P1 = 0,
P2 = 0 ∴ P3 = P4 = 1 hence D0 = 0) and when operating as normal counter i.e., when LD = CLR = 1, EN1 = EN2 = 1 then P6
= 0 ∴ P7 = Q 0 and P8 is Q1 only when P7 = 0 i.e., Q0 = 1.
But in normal counter mode (LD = CLR = 1, EN1 = EN2 = 1), P1 = 0, P2 = 1
∴ P3 = 1 and P4 = P5 ∴ D0 = P5
Similarly, D1 = P8
i.e., in normal counter operation, D0, D1, D2, D3 gets the values of four XOR gate outputs respectively.
P9 = Q1 + Q 0 = Q 0Q1
∴ P10 = Q 2 only when P9 = 0 i.e., Q0 Q1 = 1
i.e., D2 = Q 2 when Q0 Q1 = 1 ( D2 = P10)
Hence, D2 = Q 2 when Q0 = 1, Q1 = 1
i.e., Q2(Next state) = Q 2 (when lower order outputs i.e., Q0, Q1 are ‘1’)
i.e., outputs are getting complemented (i.e., inverted) when its lower order outputs are all high. This is a general property
of binary number sequence, which is performed by 74 × 163 IC.

Q35. Write the VHDL program for 74×163 4-bit counter. Q36. Design a modulo-11 counter using IC 74163.
Ans: Ans:
The VHDL code for 74 × 163 4-bit counter is given below. Modulo-11 Counter using IC 74163.
library IEEE;
The IC 74163 is a modulo 11 counter with shorted clear
use IEEE.std_looic_1164.all; (CLR) and load (LD) inputs. The logic symbol of IC 74163 is
use IEEE.std_logic_arith.a11; as shown in the figure (1).
entity V74x163 is 74 × 163
port(CLK, CLR_L, LD_L, ENP, ENT in STD LOGIC; CLOCK CLK

D: in UNSIGNED (3 downto 0); CLR
Q: out UNSIGNED (3 do,,mts 0); LD
RCO: ous STD LOGIC ); ENP
ENT Q0
end V74x163:
Q1
architecture V74x163 arch of V74x163 is 1
Q2
R
signal IQ: UNSIGNED (3 downto 0): +5V
0
Q3
begin 1
0
process (CLK, ENT, IQ)
begin RCO
if (CLK’event and CLK= ‘1’) then

if CLR_L= ‘0’ then IQ <= (others => ‘0’) ;
elsif LD_L- ‘0’ then IQ <= D; Figure (1)
elsif (ENT and ENP)= ‘1’ then IQ <= IQ + 1
In this IC it can be observed that, the input load (LD)
end if; activates after the Ripple carry output (RCO) is activated. In this
end if; circuit, the load terminal adjusted to the state 5, so that IC starts
if (IQ-15) and (ENT= ‘1’) ‘Olen RCO <= ‘1’; counting from 5 to 15 and repeats the count for 11 states per
else RCO <= ‘0’; cycle. Therefore, counting sequence of the IC is 5,6,...15,5,6..15.
end if; The counting sequence can be changed by changing the
Q <= IQ; clean (CLR) input. Figure (2) shows the modulo - 11 counter
using IC 74163 with changed clear input.
end process;
74 × 163
end V74x163 arch;
architecture V74xs3_arch of V74x163 is CLOCK CLK
CLR
signal IQ: UNSIGNED (3 downto 0);
R LD
begin
+5V ENP
process (CLK, ENT, IQ) ENT Q0
begin Q1
if CLK’event and CLK= ‘1’ then A Q2
if CLR_L= ‘0’ then IQ <= (others => ‘0’); B Q3
elsif LD_L= ‘0’ then IC) <= D; C

D 74 × 00
elsif (ENT and ENP)= ‘1’ and (IQ=12) then IQ
RCO
<= (‘0’, ‘0’, ‘1’, ‘1’);
elsif (ENT and ENP)=’1’ then IQ <= IQ + 1;
end if;
end if;
if (1Q=12) and (ENT= ‘1’) then RCO <= ‘1’; Figure (2)
else RCO <= ‘0’; From figure (2) the load (LD) is adjusted to the state 0
end if; and the clear (CLR) input is connected to 2-input NAND gate.
The two inputs of NAND gate are Q1 and Q3 which allows
Q <= IQ;
the gate to detect the state 10. When the state 10 is detected,
end process; CLR input clears the count and the counting sequence i.e.,
end V74xs3_arch; 0,1,2...10,0,1...10,.. repeats for 11 states per cycle.
Q37. Design an excess-3 decimal counter using 74 × 163 and explain the operation.
Ans: 74 × 163 is a synchronous 4-bit binary counter as shown in figure (1) ,
Figure (1)
Excess-3 decimal counter can be designed using three 74 × 163 binary counters.
Three 74 × 163 binary counters are cascaded to obtain excess-3 decimal counter as shown in figure (2) below,
Figure (2)
A0, B0, C0 and D0 are the inputs to the excess-3 decimal counter whose corresponding outputs are QA2, QB2, QC2 and QD2.
The truth table is given in table below,
Inputs
Outputs
A B C D QA2 QB2 QC2 QD2
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 1 1 0 1
1 0 1 1 1 1 1 0
1 1 0 0 1 1 1 1
1 1 0 1 × × × ×
1 1 1 0 × × × ×
1 1 1 1 × × × ×
Table: Truth Table
Q38. Write a VHDL code for excess-3 decimal counter using IC 74163.
Ans:
LIBRARY ieee;
USE ieee.std-logic-1164.all;
USE ieee.std-logic-unsigned.all
ENTITY excess-3IS
PORT (CLK, CLR, LD, EM1, EN2 : IN STD-LOGIC;
D : IN UNSIGNED (3 down to 0);
Q : OUT UNSIGNED (3 down to 0);
RCO : OUT STD-LOGIC);
END excess-3;
ARCHITECTURE excess-3-arch of excess-3 IS
SIGNAL IQ : UNSIGNED (3 down to 0)
BEGIN
PROCESS (CLK, EN2, IQ)
BEGIN
IF CLK' event AND CLK= ‘1’ THEN
IF CLR = ‘0’ THEN IQ < = (others = >’0’);
ELS IF LD = ‘0’ THEN IQ < = D;
ELSIF (EN2 and EN1) = ‘1’ AND (IQ = 12) THEN
IQ < = (‘0’, ‘0’, ‘1’, ‘1’);
ELSIF (EN2 and EN1) = ‘1’ THEN IQ < = IQ + 1;
END IF;
IF (IQ = 12) and (ENT = ‘1’) THEN RCD< = ‘1’;
ELSE RCO < = ‘0’;
END IF
Q < = IQ;
END PROCESS;
END excess-3;
Q39. Explain about modulo-6 counter with synchronous reset.
Ans:
The graphical symbol of a modulo-6 counter with synchronous reset is shown in figure (1).
Figure (1)
The AND gate in the figure in used to clear inputs of the flip-flop once the ‘110’ state is reached. The parallel load feature
of the counter is used to reset its contents when the count reaches 5.
In this type of counters, output of one flip-flop is connected as clock input to the next flip-flop. Initially, all the flip-flops
of the counter are reset (i.e., ‘000’). When the first clock pulse is applied its output Q0 shifts from 0 to 1. Thus, the process of
counting begins. A mod-6 counter consists of truncated sequence i.e., it can count from 000 to 101. Once the counter reaches
110, the outputs Q0 and Q2 of flip-flops are connected to AND gate. This gate is used to decode the count and resets the flip-flops
back to ‘0001’. The truth table of mod-6 decade counter is shown in table below,
Clock Q2 Q1 Q0
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
Table
Figure (2)
Figure (2) represents the timing diagram of a modulo-6 counter with synchronous reset.
Q40. Write a VHDL program to design a modulo-6 counter.
Ans: Oct../Nov.-16, Set-4, Q7(a)
VHDL code for synchronous mod-6 counter,
LIBRARY IEEE;
USE IEEE. STD_LOGIC_1164.ALL;
USE IEEE. STD_LOGIC_unsigned. ALL;
ENTITY Counter3 IS
PORT(
CLK : IN STD_LOGIC;
Resetn : IN STD_LOGIC;
Setn : IN STD_LOGIC;
Q: INOUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END Counter 3;
ARCHITECTURE Synch_Cntr OF Counter3 IS
BEGIN
PROCESS(CLK, Resetn, Setn)
VARIABLE Qtemp: STD_LOGIC_VECTOR (2 DOWNTo 0);
BEGIN
Qtemp : = “000”;
ELSIF Setn = ‘0’ THEN
Qtemp : = “111”;
ELSIF CLK = ‘1’ AND CLK’ event THEN
IF Qtemp < 5 THEN
Qtemp : = Qtemp + 1;
Q < = ‘000’ AFTER 2ns;
END IF;
END PROCESS;
END ASYNCH _Glitch;

Q41. Write a VHDL code for a four-bit up-counter.
Ans:
The VHDL code for a four-bit up-counter is given below,
LIBRARY ieee;
USE ieee. std_logic_unsigned.all;
ENTITY upcount4 IS
PORT (Clock, Resen, E : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
END upcount4;
ARCHITECTURE Behavior OF upcount4 IS
SIGNAL Count : STD_LOGIC_VECTOR (3 DOWNTO 0);
BEGIN
PROCESS (Clock, Resetn)
BEGIN
Count <= “0000”;
ELSIF (Clock’ EVENT AND Clock = ‘1’) THEN
IF E = ‘1’ THEN
Count <= Count + 1;
ELSE
Count <= Count;
END IF;
END IF;
END PROCESS;
Q <= Count;
END behavior;
Q42. Explain the operation of a 4-bit synchronous binary counter with the required diagram and waveforms.
A counter is said to be synchronous, when a single clock pulse is connected simultaneously to all the flip-flops. A 4-bit
synchronous counter requires four flip-flops and two AND gates. The circuit diagram of a 4- bit synchronous counter using JK
flip-flop is shown in figure (1).
Figure (1): 4-bit Synchronous Counter

In this counter, the JK inputs of FF0 is connected to logic ‘1’ which responds for each positive clock edge. The output
of FF0 is directly connected to the input of FF1. While, the outputs Q0 and Q1 are applied as inputs to AND gate 1 such that the
output is indirectly connected to the input of the next flip-flop FF2. Similarly, the output of AND gate 1 and Q2 are applied to
AND gate 2 whose output is connected as input to FF3. This counter counts from 0000 to 1111 for each positive edge pulse.
Operation: Initially, all the flip-flops are reset i.e., 0000 when the first clock pulse is applied to FF0, the output Q0 toggles from
0 to 1 and the remaining outputs unchanged i.e., 0001. When the second clock pulse is applied, the outputs Q0 and Q1 changes
their values and the output becomes 0010. When the third clock pulse is applied, FF0 changes its output and the count becomes
as 0011. In the same way for each positive edge clock pulse FF0 toggles. FF1 toggles when Q0 = 1, FF2 toggles when Q0 = Q1 =
1 and FF3 toggles only when Q0 = Q1 = Q2 = 1.
The counting sequence of 4-bit synchronous counter is shown in table.
Clock Q3 Q2 Q1 Q0

Table
The timing diagram of a 4-bit synchronous counter is shown in figure (2).
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Q0
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
Q1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
Q2
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Q3
Figure (2): Timing Diagram of 4-bit Synchronous Counter

Q43. Give a VHDL code for a 4-bit up counter with enable and clear inputs.
(Model Paper-4, Q5(b) | Oct./Nov.-18, Set-3, Q6(b) M[7])
(or)
Give a VHDL code for a 4-bit upcounter with enable and clear inputs. Nov.-15, Set-2, Q7(b)
Ans: The VHDL code for a four bit up counter with parallel load is given below,
LIBRARY ieee;
ENTITY upcountl IS

PORT (R : IN INTEGER RANGE 0 to 15;
Clock, Resetn, L : IN STD_LOGIC;
Q : BUFFER INTEGER RANGE 0 to 15);
END upcountl;
ARCHITECTURE Behavior OF upcountl IS
BEGIN
PROCESS (Clock, Resetn)
BEGIN
Q <= 0;
IF L = ‘1’ THEN
Q <= R;
ELSE
Q <= Q + 1;
END IF;
END IF;
END PROCESS;
END Behavior;
Q44. Draw and explain 3-bit down-counter.
Ans:
Figure (1) illustrates the 3-bit down counter using positive edged triggered flip flop,
Figure (1): 3-bit Binary Ripple Down Counter Using Positive-edge Triggered Flip-flops
Figure (1) depicts the 3-bit binary ripple down counter using positive-edge triggered flip-flops. Here, the output of each
flip-flop is connected to the clock input of next flip-flop. The truth table of 3-bit binary ripple down counter is shown in table (i),
State
Clock Pulse
Q2 Q1 Q0
0 1 1 1
1 1 1 0
2 1 0 1
3 1 0 0
4 0 1 1
5 0 1 0
6 0 0 1
7 0 0 0
8 1 1 1
Table
Initially consider that all the flip-flops are reset. Then, we get the counter output as 111 because ‘T’ flip-flop gives the
complement of input as output. As soon as first positive clock pulse is applied, flip-flop FF0 is enabled. And, the output ‘Q0’
changes from 1 to 0 which doesn’t affect the next flip-flop FF1. Thus, the output of FF1 remains ‘1’ output of FF2 remains ‘1’.
The counter output becomes 110. When the second positive clock pulse is applied output of the flip-flop ‘FF0’ (i.e, Q0) changes
from ‘0’ to 1. This output ‘Q0’ enables the next flip-flop ‘FF1’. Then, the output of ‘FF1’ changes from ‘1’ to ‘0’ and doesn’t affect
its next flip-flop. Thus, the output of FF2 remains same. The counter output becomes 101.
In the similar manner, for subsequent clock pulses, counter counts till ‘000’ and comes back to its initial state 111. Then
the same process gets repeated. The timing diagram is as shown in figure (2).
Figure (2): Timing Diagram of 4-bit Binary Ripple Down Counter (using Positive Triggered Flip-flops)
Q45. Write a VHDL code for a down-counter.
Ans:
The VHDL code for a down-counter is given below,
LIBRARY ieee;
ENTITY downcnt IS
GENERIC (modulus : INTEGER : = 8);
PORT (Clock, L, E : IN STD_LOGIC;
Q : OUT INTEGER RANGE 0 TO modulus – 1);
END downcnt;
ARCHITECTURE Behavior OF downcnt IS
SIGNAL Count : INTEGER RANGE 0 to modulus – 1;
BEGIN
PROCESS
BEGIN
WAIT UNTIL (Clock’ EVENT AND Clock = ‘1’);
IF L = ‘1’ THEN
Count <= modulus – 1;
ELSE
IF E = ‘1’ THEN
Count <= Count – 1;
END IF;
END PROCESS;
Q <= Count;
END Behavior;

Q46. Design and implement counter using VHDL which counts up to 9 and down counts again from 9 to 0.
BCD Up/down Counter

The design procedure of a 4-bit or divide-by-16 up/down ripple counter involve following steps,
1. The number of flipflops required can be calculated as,
Number of flipflops = log2 N [ N = 16]
= log2 16 = 4
2. Connect the 4-flipflops as a ripple counter.
3. Find the binary representation of N – 1, here N = 16
∴ N – 1 = 15 = (1 1 1 1)2
4. Connect the AND gates such that Q output is given to clock pulse of next flipflop for up counter and output is given
to clock pulse of next flipflop for down counter.
The counter resets automatically, i.e., for up counter, when it comes to the last count i.e., 1 1 1 1, the next count goes to
0000 with carry 1.
 1111
+ 1
1000
CY

As carry is not considered here, again the count starts from ‘0 0 0 0’.
In the similar manner, for down counter 0000 minus 1 gives 1 1 1 1 with borrow 1 which is not considered.
The 4-bit up/down ripple counter with negative clock pulse is as shown in the figure (i),
up /down
J0 J1 J2 J3 Q3
Q0 Q1 Q2
CLK CLK CLK CLK
Q0 Q1 Q2
K0 K1 K3 K3 Q3
1 (high)
Figure (i): 4-bit Asynchronous up/down Counter

Case (i)
If up /down = 0, the circuit acts as up-counter figure (i) can be rearranged as shown in figure (ii).
Q0 Q1 Q2 Q3
J0 Q0 J1 Q1 J2 Q2 J3 Q3
CLK CLK CLK CLK
K0 K1 K2 K3 Q3
1 (high)
Figure (ii): Up-counter Q3 Q2 Q1 Q0
Let the present count be 5 = 0 1 0 1. The first flipflop with J0 = K0 = 1 as inputs, always toggles the present state (since clock
is enabled) and all other flipflops are enabled only when 1 → 0 transition of the clock occurs (since negative clock pulse is given).
Thus,

As 1 → 0 transition occurred 0 is toggled to 1 i.e.,

As 0 → 1 transition is occurred in Q1, the state remains same i.e.,

As 1 → 1 transition of Q2 does not enables the clock of Q3, the output remains same

Thus, 0 1 1 0 is the output which is equivalent to 6. The count takes place in forward direction and acts as up counter.
Case (ii)
If up /down = 1, the asynchronous counter shown in figure (i) can be rearranged as shown in figure (iii).
Q0 Q1 Q2 Q3
J0 Q0 J1 Q1 J2 Q2 J3 Q3
CLK CLK CLK CLK
K0 Q0 K1 Q1 K2 Q2 K3 Q3
1 (high)
Figure (iii)
Let the present count be 12 – 1100.
As, the transition depends on the complement of output consider, (1100)c = 0011
The MSB bit toggles, as the first flipflop inputs are J0 = k0 = 1 and clock is enabled i.e.,

As there is 1 → 0 transition in Q0 , the present state of output toggles i.e.,

The 0 → 0 transition in Q 2 , the present state of Q 2 is toggled.

The 1 → 0 transition in Q1 disables the clock of Q3 .
Thus, the output remains same i.e.,

VHDL Code
The complement of output is Q3 Q 2 Q1 Q0
0 1 0 0 The VHDL code for 4bit updown counter using dataflow
Q
model is given below.
The output is given as Q3 Q 2 Q1 0
1 0 1 1 library ieee;
Which is equal to 11 in decimal equivalent. use ieee.std_logic_1164.all;
Thus, the count occurs in backward direction i.e., it acts use ieee.std_logic_unsigned.all;
as down-counter.
entity UPDOWN_COUNTER is
The state transitions of a 4-bit asynchronous up/down
counter are shown in table. port ( clk: in std_logic; -- clock input
Present State Next State reset: in std_logic; -- reset input
Up/down
Q3 Q2 Q1 Q0 Q+3 Q+2 Q+1 Q+0 up_down: in std_logic; -- up or down
0 0 0 0 0 0 0 0 1 counter: out std_logic_vector(3 downto 0));
0 0 0 0 1 0 0 1 0 end UPDOWN_COUNTER;
0 0 0 1 0 0 0 1 1 architecture Behavioral of UPDOWN_COUNTER is
0 0 0 1 1 0 1 0 0 signal counter_updown: std_logic_vector(3 downto 0);
0 0 1 0 0 0 1 0 1 begin
0 0 1 0 1 0 1 1 0 process(clk,reset)
0 0 1 1 0 0 1 1 1 begin
0 0 1 1 1 1 0 0 0 if(rising_edge(clk)) then
0 1 0 0 0 1 0 0 1
if(reset=‘1’) then
0 1 0 0 1 1 0 1 0
counter_updown <= x“0”;
0 1 0 1 0 1 0 1 1
elsif(up_down=‘1’) then
0 1 0 1 1 1 1 0 0
counter_updown <= counter_updown -
0 1 1 0 0 1 1 0 1
x“1”; -- count down
0 1 1 0 1 1 1 1 0
else
0 1 1 1 0 1 1 1 1
counter_updown <= counter_updown +
0 1 1 1 1 0 0 0 0
x“1”; -- count up
1 1 1 1 1 1 1 1 0
end if;
1 1 1 1 0 1 1 0 1
end if;
1 1 1 0 1 1 1 0 0
end process;
1 1 1 0 0 1 0 1 1
counter <= counter_updown;
1 1 0 1 1 1 0 1 0
end Behavioral;
1 1 0 1 0 1 0 0 1
Q47. Design a 4-bit up/down counter using 74 × 169
1 1 0 0 1 1 0 0 0
IC and write the behavioral description of 74 ×
1 1 0 0 0 0 1 1 1
169 up/down counter.
1 0 1 1 1 0 1 1 0
Ans:
1 0 1 1 0 0 1 0 1
4-Bit Up/Down Counter Using 74 × 169
1 0 1 0 1 0 1 0 0
The IC 74169 is a 4-bit bidirectional synchronous counter
1 0 1 0 0 0 0 1 1
or an up-down counter write active low ripple carry output
1 0 0 1 1 0 0 1 0 (RCO) and enable inputs. Similar to general up/down counter,
1 0 0 1 0 0 0 0 1 IC 74169 also counts in both up and down directions. If the
1 0 0 1 1 0 0 0 0 input UP/ DN is logic 1, IC counts upwards and if UP/ DN is
1 0 0 0 0 1 1 1 1 logic 0, it counts downwards. The logic diagram of IC 74169
Table is shown in the figure below.
74 × 169 end counter;
2
CLK
architecture archi of counter is
1
UP/DN signal temp: std_logic_vector (3 downto 0);
9
7 LD begin
10 ENP process(c, CLR)
ENT 14
3 QA begin
A
4 13
B QB if (CLR = ‘1’) then
5 12
C QC temp < = “0000”;
6 11
D QD elseif (‘c’ event and c = ‘1’) then
15
RCO if (U_D = ‘1’) then
VHDL code: temp < = temp + 1;

The HDL behavioral description of the 4-bit up- else
down counter is shown below. temp < = temp – 1;
library ieee; end if;
use ieee.std_logic_1164.all; end if;
use ieee.std_logic_unsigned.all;
end process;
entity counter is
Q < = temp;
port(c,CLR, U_D:instd-logic; Q:Out std_logic_
vector (3 downto 0)); end archi;
Q48. Draw the structure of a 8-bit counter. Write a VHDL description for an 8-bit counter.
Ans:
The structure of 8-bit counter using two 4-bit counters is shown in figure below.
Figure: Two 4-bit Counters Cascaded to Make an 8-bit Counter

VHDL description for an 8-bit counter is given below.
LIBRARY ieee;
ENTITY count8 IS
PORT(clk, cin : IN STD_LOGIC;
clear, load, updown : IN STD_LOGIC;
x : IN INTEGER RANGE 0 to 31;
cout : OUT STD_LOGIC;
y : IN INTEGER RANGE 0 to 31);
END count8;
ARCHITECTURE behavior OF count8 IS
BEGIN
PROCESS(clk, clear, load)

VARIABLE c : INTEGER RANGE 0 to 31
BEGIN
IF(clear=’0’) THEN
c :=
0;
ELSEIF(load= ‘1’ and clear= ‘1’) THEN
c :=
x;
ELSE
IF(clk’ EVENT AND clk = ‘1’) THEN
c := c–1;
ELSEIF(cin = ‘1’ and updown = ‘0’) THEN
c := c+1;
END IF;
END IF;
y <= c;
IF(c = 0 and updown = ‘1’) THEN
cout <= ‘1’;
ELSE
cout <= ‘0’;
END IF;
END PROCESS;
END Behavior;
Q49. Design a 4-bit binary synchronous counter using 74×74. Oct./Nov.-19, Set-1, Q6(b) M[7]
Ans:
The 74 × 74 is a positive edge-triggered D-flip-flop with preset and clear inputs. The logic symbol of 74 x 74 IC is shown
in figure (1).
4
2 5
D Q
3 6
Clock
CLR Q
1
Figure (1)
Design of 4-bit Synchronous Counter Using 74 × 74
Initially, the excitation table for D-flip-flop can be written as,
Qn Qn+1 D
0 0 0
0 1 1
1 0 0
1 1 1
Table (1)
The state transition table for 4-bit synchronous counter is shown in table (2).
Present state Next State Input
Q0 Q1 Q2 Q3 Q+0 Q+1 Q+2 Q+3 D3 D2 D1 D0
0 0 0 0 0 0 0 1 0 0 0 1
0 0 0 1 1 00 0 0 0 1 0
0 0 1 0 1 10 0 0 0 1 1
0 0 1 1 0 00 1 0 1 0 0
0 1 0 0 0 10 1 0 1 0 1
0 1 0 1 1 00 1 0 1 1 0
0 1 1 0 1 10 1 0 1 1 1
0 1 1 1 0 01 0 1 0 0 0
1 0 0 0 0 11 0 1 0 0 1
1 0 0 1 1 01 0 1 0 1 0
1 0 1 0 1 11 0 1 0 1 1
1 0 1 1 0 01 1 1 1 0 0
1 1 0 0 0 11 1 1 1 0 1
1 1 0 1 1 01 1 1 1 1 0
1 1 1 0 1 11 1 1 1 1 1
1 1 1 1 0 00 0 0 0 0 0
Table (2)
The inputs to the D-flip-flop are simplified using K-map,
For D3 For D2
Q0 Q2
Q2Q3
QoQ1 00 01 11 10
0 1 3 2
Q2Q3
00 QoQ1 00 01 11 10
4 5 7 6 0 1 3 2
01 1 Q 0 Q1Q 2 Q 3 00 1
12 13 15 14 4 5 7 6
11 1 01 1 1 1
1 1
8 9 11 10 Q1 Q 2 12 13 15 14
10 1 1 1 1 11 1 1 1
8 9 11 10
10 1 1 Q1 Q 3
Q 0 Q1
Q0 Q3 Q1Q 2 Q 3 Q QQ
0 1 3
D3 = Q0 Q3 + Q0 Q1 + Q0 Q 2 + Q0 Q1Q 2 Q3 D2 = Q1 Q 2 + Q1 Q3 + Q0 Q1Q3 + Q1Q 2 Q3

= Q0 _ Q1 + Q 2 + Q3i + Q0 Q1Q 2 Q3 = _ Q 2 + Q3i + Q1Q3 _Q0 + Q 2i
For D1 For D0
Q2Q3 Q 2Q 3
QoQ1 00 01 11 10
QoQ1 00 01 11 10 0 1 3 2
0 1 3 2 00 1
00 1
1 1
4 5 7 6
4 5 7 6 01 1
01 1
1 1
12 13 15 14
12 13 15 14
1 1 11 1 1
11
8 9 11 10
8 9 11 10 10 1 1
10 1 1
Q2Q3 Q 2 Q 3 Q3
\ D1 = Q 2 Q3 + Q 2 Q3 = Q 2 5 Q3 ∴ D0 = Q3

Figure (2) shows the logic diagram for 4-bit synchronous counter using four 74 × 74 IC’s.
Q0 Q1 Q2 Q3 CLK
D3 Q3
Q3
D2 Q2
Q2
D1 Q1
Q1
D0 Q0
Q0
Figure (2)
3.3 Synchronous and Aynschronous Sequential Design

Q50. Discuss in detail about sequential circuit.
Ans:
Sequential Circuits
v The circuit which combines logic gates using storage elements (as feedback path) to generate a specific output for a speci-

fied combination of inputs is known as sequential circuit.
v This circuit consists of input variables, logic gates, memory elements and output variables.
v The output at any given instant of time depends not only depends on current input, but also on past output.
v The present state and the inputs applied give the output and the next state of the circuit.
Figure (1) represents the block diagram of a sequential circuit.
I/P Combinational
O/P
circuit
Memory
element
Figure (1): Block Diagram of Sequential Circuit
Example: Counters, Registers
Depending on the timing of signals, sequential circuits are classified as two types. They are,
1. Synchronous sequential circuit
2. Asynchronous sequential circuit.
1. Synchronous Sequential Circuit
A circuit is said to be synchronous circuit if its output depends on the input signals only at discrete interval of time i.e.,
memory device will undergo a change only at a discrete time interval. These circuits use flipflops as their memory device
for storing the binary information. A timing element known as clock generator is needed for synchronization and provides
a periodic pulse train signals.
Synchronous sequential circuit are also called as clocked-sequential circuits. If more than one flipflop is used, then they
have a common clock pulse. These circuits are simple to design and have limited speed of operation due to time delay.
At the time of unclock, the change input is simultaneous for clocked sequential circuits as shown in figure (2).
Figure (2): Timing Diagram of Clock Pulse

2. Asynchronous Sequential Circuit
A circuit is said to be asynchronous sequential circuit if its output depends on the input signals at all instance of time
i.e., the output changes accordingly with the input. Such circuits uses time delay latches, gate devices and their memory
element.
Asynchronous sequential circuits does not require clock pulses and are called as combinational circuit with feedback.
These circuits are more difficult to design and the speed of operation is high.
Q51. Write short notes on, Where,
(i) Finite state machine I1, I2 ,...., In = Input variables
(ii) State transition function O1, O2,...., Om = Output variables
(iii) Finite state model y1, y2, ...., yk = State variables.
(iv) Terminal state Consider a machine ‘M’ with a set of sequences as shown
in figure (2).
(v) Strongly connected machine.
Ans: April-11, Set-4, Q4(a)
(i) Finite State Machine

Finite state machine is a model which is used to describe
the synchronous sequential machine. It is a machine with
a fixed number of states. The block diagram of finite state
model is as shown in figure (1).
Figure (2)
Clockpulse
(ii) State Transition Function
I1 O1 The change in sequence of a machine from one state to

another is called transition and the function which defines
I2 O2
the transitions, of a finite state machine is called a state
In Om
transition function.
Example if the sequence of machine ‘M’ when applied
with input (either ‘1’ or ‘0’) then from initial state ‘X’ it
causes a transition to ‘Y’ and said to be a ‘Y’ is successor
y1 Y1 of ‘X’.
(iii) Finite State Model
The model which defines the number of transitions or
yk Yk
successions of a machine by its number of states is re-
Figure ferred to as a finite state model.

(iv) Terminal State If we implement this with a finite state machine capable
A machine is said to be in terminal state if it has Sink of performing serial multiplication, we can find that it is not
vertex or Source vertex. possible to multiply certain numbers.
From the above state diagram, it is clear that no sequence Such limitation does occur due to the limited “memory”
can take the machine ‘M’ out of state ‘A’ and therefore, available to the machine,
state ‘A’ is said to be terminal state. The terminal state
limits the state transitions of sequential machine. This memory is not sufficient to store arbitrarily large
Sink Vertex: The vertex in the state diagram which partial products resulted during multiplication.
does not have any outgoing arcs, which start from it and Q53. Explain the analysis of clocked sequential
terminate in other states is called sink vertex. circuits.
Ans:
X Y
Analysis of Clocked Sequential Circuits
No outgoing arcs
Source Vertex: The vertex in the state diagram which Digital circuit containing flip-flops with clock inputs is
does not have any incoming arc which start from other known as clocked sequential circuits. Figure (1) shows a clocked
vertices and terminate in it. sequential circuit containing two D flip-flops as an input (W)
X Y and an output (z).
No incoming arcs
(v) Strongly Connected Machine
The machines in which input sequence exists for each
pair of states Xi, Xj ... and takes the machine from one
state to another, are called strongly connected machines.
Q52. What are the capabilities and limitations of finite
state machines?
Ans: April-18, Set-4, Q7(b) M[5]
The capabilities and limitations of finite state machines are,

1. Periodic Sequence of Finite Series
A periodic sequence of n-states or (n – 1) states can be
obtained with an n-state machine.
For instance, if n = 6, then maximum periodic sequence
for a 6-state machine is 0, 1, 2, 3, 4, 5, 0, 1, ... Figure (1): Clocked Sequential Circuit
2. No Infinite Sequence The analysis of a clocked sequential circuit consists of
A finite state machine cannot produce an infinite study of its behaviour from the state table or state diagram for
sequence. For instance, a machine is designed such that the the time sequence of inputs, outputs and internal states.
P( P + 1) State Equations: State equation characterizes the behaviour of a
output is 1, and received number of inputs is equal to
2 clocked sequential circuit algebraically. It gives the relationship
for P = 1, 2, 3 ... The required input-output sequence thus between next state, present state and input of flip-flop i.e., it
obtained is of the form, expresses the next state in terms of present state and inputs.
Input : x x x x x x x x x x .... After a clocked transition in the sequential circuit shown
Output: 1 0 1 0 0 1 0 0 0 1 .... in figure (1), the next state of the two flip-flops F1 and F2 with
outputs D1 and D2 respectively, can be represented by the
3. Limited Memory
following state equations,
A finite state machine has limited memory, due to which
proper outputs cannot be obtained. D1 (t + 1) = D1 (t) W(t) + D2 (t) W(t) ... (1)
D2 (t + 1) = D1 (t) W(t)
Example
Where,
Binary multiplier circuit.
D(t + 1) – Next state of flip-flop
Consider that the circuit multiplier circuit for multiplying two
arbitrarily large binary numbers. D(t) – Present state of flip-flop.
Since all the variables are with respect to present state, Q54. Write short notes on the following with suitable
the equation (1) can be written as, examples.
D1(t + 1) = D1W + D2W ... (2) (i) State diagram
(ii) State table
D2(t + 1) = D1W ... (3)
(iii) State assignment.
and the output can be expressed algebraically as,
(Model Paper-1, Q6(a) | Oct./Nov.-18, Set-1, Q7(b) M[7])
z(t) = [D1(t) + D2(t)] W (t)
(or)
⇒ z(t) = [D1 + D2] W ... (4) Explain the terms state diagram and state table
∴ Equations (2), (3) and (4) represent the state equations with suitable example. April-18, Set-1, Q7(b) M[7]
of sequential circuit. (Refer Only Topics (a) and (b)
D1(t + 1) = D1W + D2W Ans:
D2(t + 1) = D1W (a) State Diagram: A state diagram is defined as the
diagrammatic representation of the performance of a sequential
z = (D1 + D2) W circuit. It is shown in figure (1).
State Table
The state equations can be implemented in a table called
state table. The state table has four columns namely current state
(or present state), input, next state and output.
If the sequential circuit has x-flip-flops and y input then
the number of rows in a state table are 2x+y. Under the present
state and input column, the binary number from 0 to 2x+y–1 are
listed and the next state contains x columns, one for each flip-
flop. State table for the clocked sequential circuit in figure (1)
is as shown in table below.
Present State Input Next State Output
Figure (1)
D1 D1 W D1 D2 z
In figure (1), the circles indicate the state of the sequential
0 0 0 0 0 0 circuit. Each circle consists of binary number, which represents the
0 0 1 0 1 0 specific state of the sequential circuit. The circles are connected
0 1 0 0 0 1 by means of two direct lines i.e., one line connects the two circles,
0 1 1 1 1 0 indicating the change in state whereas the other line connects the
1 0 0 0 0 1 circle itself indicating that the next state is similar to the present
1 0 1 1 0 0 state. Over the direct lines there are two binary digits separated by
1 1 0 0 0 1 the symbol ‘/’. The digit prior to the symbol indicates the input
1 1 1 1 0 0 value, which results in transformation of state and the digit after
the symbol indicates output value during the transition.
Table: State Table
Example: The Moore state diagram is shown in figure (2).
State Diagram
The graphical representation of state table is known as
state diagram. In state diagram, each state is indicated by a circle
and state transition due to clock trigger is represented by solid
lines. The state diagram is as shown in figure (2).
Figure (2): State Diagram Figure (2)

The direct lines have only one binary digit over them, Rule 1: The assignment of states with some ‘NEXT STATES’
which indicates the input resulting in the transformation of state must be in such a manner that, they can be grouped into logically
whereas the output is indicated within the circle exactly below adjacent cells in a K-map.
the present state. This is because the output state is independent Example
of input and depends only on the present state. 000
(b) State Table: A state table is a tabular representation of
information contained in a state diagram. With the help of state
table, it is easy to understand the implementation of a sequential
circuit. An example of state table is shown in table. 100 110 111 101
Next State Output Figure (4)

Present state
X=0 X=1 X=0 X=1 In figure (4), there are four states whose next state is same
AB
AB AB Y Y i.e., (000). If we assign the binary values for these four states as,
100, 110, 111, 101 then, they can be combined in a K-map.
a a c 0 0
Rule 2: The assignment of states, which are the ‘NEXT
b b a 0 0 STATES’ of a single state should be in such a way that they can
be grouped logically by using a K-map as shown in figure (5).
c d c 0 1
Example
d b d 0 0
000
Table
Table (1) comprises of 3 parts. They are, present state,
next state and the output. It basically provides relationship
among these three parameters. The present state is the state of
100 101 110 111
flip-flop before the application of clock pulse, the next state
indicates the state of flip-flop after the clock pulse application Figure (5)
and output state provides the values of output variables
Q55. Summarize the design procedure for a
according to the present state. It may be noted that both next
synchronous sequential circuit.
state and output have two sections corresponding to value of
X = 0 and X = 1 respectively. Ans: The following steps illustrate the procedure for the design
of sequential circuits,
(c) State Assignment: The performance of a sequential
circuit is expressed in terms of four parameters, namely input, Step-1:State table must be obtained from the given information
present state, the next state and the output. A specific flip-flop such as a state diagram, a timing diagram or any other information.
inputs are required to generate the next state at a particular Consider a state diagram shown in figure.
present state and input. These flip-flop inputs are obtained 0|0
from flip-flop input functions. In order to determine the flip-
flop input functions, the states in the state diagram must be
indicated with binary values rather than alphabets. This process 00
1|0 1|0
is termed as state assignment. The assignment of binary digits 0|0
to the states must be in a manner that minimum logic gates 01 10 1|1
are used to implement flip-flop input functions. An example
of state assignment is shown in figure (3). 0|0 0|0
11
1|0
Figure
The state table can be obtained as shown in table.
Next State Output
Present State
x=0 x=1 x=0 x=1
00 00 10 0 0
10 11 10 0 1
Figure (3)
11 01 11 0 0
We can assign the binary values by following the set of
01 01 00 0 0
rules for state assignment. Basically there are two rules for state
assignments. They are, Table
Step-2: Total number of states must be reduced using state The total output Y is dependent on the preceding
reduction technique. position’s carry as well as the current inputs. In the LSB (b0)
Step-3: If the represented states are in alphabetical form then binary position, both the input bits are zero and the output is also zero;
values must be assigned to each state in the state table. in the next position, i.e., b1 the sum of one and one is zero and
a carry ‘1’ is generated; in the next position b2, the two 1’s,
Step-4: In this step, the total number of flip-flops that are together with the carry 1 from b1 position are added, resulting
required to design the circuit are to be determined. in the sum bit Y = 1 and carry = 1; and so on. Now in the design
Step-5: Based on the obtained data, the type of flip-flop must we need a memory device to track the carry input. This means
be chosen. the memory encompasses two states, 0 and 1, that correspond
to carry = 0 and 1, respectively. From the foregoing discussion,
Step-6 : From the obtained state table, the circuit excitation and
we create a state transition and output table as follows:
output tables must be derived.
Step-7 : Circuit output functions and flip-flop input functions Present Inputs Next State
Output
must be derived using K-map or any other method. State PS(Q) X1 X2 NS(Q*)
Step-8: Finally, by using the circuit output functions and flip-flop 0 0 0 0 0
input function obtained in step-7, sketch the logic diagram. 0 0 1 0 1
Q56. Explain the state equivalence and machine 0 1 0 0 1
equivalence with reference to sequential machines. 0 1 1 1 0
Ans: Oct./Nov.-19, Set-2, Q7(a) M[7] 1 0 0 0 1
State Equivalence: While constructing the state diagram for 1 0 1 1 0
the finite state machine, there is a possibility of existence of 1 1 0 1 0
redundant states i.e., the states that defines the same function. State
1 1 1 1 1
equivalence is a diagram which doesn’t contain redundant states.
Table (1): State Transition and Output Table for Serial
Let us assume Si and Sj are the two states of the machine
Adder
‘M’. These two states are called equivalent, if there exist same
output sequence for all the possible input sequences irrespective From the above transition and output table using k-map
of the initial state. we derive inputs and outputs for D-flip flop. The k-maps are
illustrated in figure (1).
If an input W = 0 is applied to a FSM which is in state ‘Si’,
Q Q
it transits to state ‘Sp’. Then ‘Sp’ is called 0-successor of state ‘Si’. x1x2 0 1 x1x2 0 1
Similarly, if W = 1 is applied to FSM in state ‘Si’, it 00 00 1
transits to state ‘Sq’. Then ‘Sq’ is called 1-successor of ‘Si’.
01 1 01 1
Machine Equivalence: Consider two machines M1 and M2. These
11 1 1 11 1
two machines are equivalent when for every state in M1, there
is corresponding equivalent state in machine M2 and vice versa. 10 1 10 1
If the machine has no equivalent states then it is called
minimal or reduced form. Figure (1): K-maps for Flip-flop Input D and Output Y
The logic expression for D and Y are,
For every machine ‘M’ there exist corresponding
minimal machine M* which is equivalent to machine ‘M’. D = X1X2 + X1Q + X2Q
Q57. Design a serial adder circuit to add two binary Y = X1 X2 Q + X1X2 Q + X1X2 Q + X1 X2
numbers using D-flip flops. From the above input and output expressions the circuit
Ans: We have all done decimal addition with paper and pencil. of serial adder is as shown in figure (2).
Binary numbers are added serially in a similar manner. Starting
from the LSD, digits in the same significant position are added,
accompanied with a carry formed by adding digits from the
preceding significant position. This is as explained below.
Let us call the two binary inputs to be added as X1 and X2.
Inputs X1 and X2 are applied successively. Now if we presume
X1 = 10010110 and X2 = 11011110, then the output Y is,
b2 b1 b0
X1 = 1 0 0 1 0 1 1 0
X2 = 1 1 0 1 1 1 1 0
Y = 10 1 1 1 0 1 0 0 Figure (2): Serial Adder Circuit Using D-FLIP FLOP

Q58. Draw the logic diagram of Melay model & The features of Mealy machine are as follows,
explore its operation with examples. v Its output depends on both present input and present state,
Ans: Oct./Nov.-18, Set-3, Q7(a) M[7] v It requires less number of states for implementing the
The sequential circuit whose output depends on both same function.
present state and the inputs is known as Mealy machine. v During the clock pulse, if any variations occur in the
input, it affects directly on the circuit output.
The state of the flip flop is not affected by the changes
Q59. Draw the logic diagram of Moore model &
in inputs. The output may change for change in inputs using
explore its operation with examples.
the clock cycle and also may produce false output. The inputs
of the sequential circuit must be synchronized with clock. False
The logic diagram of Moore model is illustrated as shown
outputs can be prevented by making the inputs to change at the
in figure (1).
inactive edge of the clock such that the inputs of flipflop become
active edge of clock pulse.
Example
T1 y1 T2 y2 z
Consider a sequential circuit with two JK flip-flops x
and an AND gate as an example of Mealy machine as shown in
figure (1). The output Y depends on both x and states QA, QB. y1
y2
x
JA QA JB QB
x
clk Clk
1 KA QA 0 KB QB
Figure (1): Logic Diagram of a Moore Model
It consists of two T flip-flops, an input (x) and an output (z).
Y
In Moore model, the output depends only on the present state.
Figure (1) From figure (1), the input equations (T1 and T2) and
State diagram for Mealy model is shown in below output equation (z) is obtained as,
figure (2), T1 = y2 x
0/0
T2 = x
z = y1 y2
00
Generally, the characteristic equation of a T flip-flop can
1/0 1/0
be written as,
Q(t + 1) = TQ + T Q ... (1)
0/0
On substituting the corresponding values of T1 and T2 in
01 10 1/1 equation (1), the state equations for Moore model are obtained as,
y1(t + 1) = Y1 = ( y 2 x) ⊕ y1 = ( y 2 x) y1 + ( y 2 x) y1
0/0 0/0 = y1 y 2 + y1 x + y1 y 2 x ... (2)
y2(t + 1) = Y2 = x ⊕ y 2
11 = xy 2 + x y 2 ... (3)
1/0 And output z = y1y2 ... (4)
Figure (2): State Diagram of Mealy Model The state table for Moore model can be obtained using
equations (2), (3) and (4) as shown in table.
State table for Mealy model is given below,
Next State Output NS O/P
Present PS
State X=0 X=1 X=0 X=1 x =0 x=1
AB AB AB Y Y y1 y2 Y1 Y2 Y1 Y2 z
a a c 0 0 0 0 0 0 0 1 0
b b a 0 0 0 1 0 1 1 0 0
c d c 0 1 1 0 1 0 1 1 0
d b d 0 0 1 1 1 1 0 0 1
Table: State Table for Mealy Model Table: State Table
The corresponding state diagram is shown in figure (2).

Q60. What are the Moore and Mealy machines? Compare them.
Ans: (Model Paper-2, Q6(a) | Oct./Nov.-19, Set-1, Q7(a) M[7])
Mealy Machine: A sequential circuit whose output depends on both present state and present input is termed as Mealy machine
or Mealy circuit, which is shown in figure (1).
Figure (1): Mealy Circuit Model

(ii) Moore Machine: A sequential circuit whose output depends only on present state of the flip-flop is termed as Moore
machine, which is shown in figure (2).
Figure (2): Moore Circuit Model

Comparison
The difference between Moore and Mealy machines are mentioned below,
Moore Machine Mealy Machine
1. It is a type of sequential circuit. 1. It is also a type of sequential circuit
2. The output of Moore machine depends on the 2. The output of Mealy machine depends on the present
present state of the flip-flop i.e., state as well as present input
z (t) = λ{S(t)} where λ is a output function. i.e., z(t) = λ{S(t), x(t)} where λ is a output function.
3. Any change in the input does not affect the 3. Any change in the input may affect the output of the
output. circuit.
4. In this type of a circuit more number of states 4. In this type of circuit less number of states are required
are required for implementing the same function. for implementing the same function.
5. In the state diagram, for a output values are 5. Here, only the state identifiers are included within the
included within the circles containing the state circles, inputs as well as outputs are associated with the
identifiers and only inputs are associated with arrows interconnecting the states.
the arrows interconnecting states.

Q61. Draw and explain the diagram of Mealy-type FSM for serial adder.
Ans: Figure (1) shows a model of serial adder that should be realized as a Mealy network.
x Serial
Input binary adder z output
sequences y (binary)
clock
Figure (1): Structure of a Binary Serial Adder

A serial binary adder consists of two inputs x, y and a single output z. The operands of each binary sequence are applied
at x and y inputs respectively. The addition is performed bit by bit starting with a pair of Least Significant Bits (LSB’s). For the
synchronization purpose, the inputs at x and y are given before the triggering of clock pulse. An output z contains the sum result
of two binary sequences in the form of time sequence with LSB bit on the first position.
There exists four input combinations of x and y that are 00, 01, 10 and 11. The current output and next state is found only
when the sequential circuit stores the previous output state. According to binary addition excluding the least significant pair of bits
sum, the sum result of pair of bits of different order and position requires previously generated carry bit. Let the value of carry bit
be either 0 or 1, which should be stored for performing addition on other input bit pair. Hence, the present output is determined
by current pair of input bits with previous carry bit and the next state is determined by considering A as the initial state.
Consider a state diagram with each state as a node as shown in figure (2), four combinations are possible with two inputs,
a node should consider all combinations. Node A is sum of a pair of binary bits with no carry which result in a carry of either 0
or 1. For example, the sum of combinations 00, 01 and 10 yield a carry bit of 0 that remain in the initial state i.e., A, whereas the
addition of 11 combination yields a carry bit 1, hence the state is changed to B for the carry bit to be stored.
11/z = 0
00/z = 0 01/z = 0
01/z = 1 A B 10/z = 0
10/z = 1 11/z = 1
Initial
state 00/z = 1
Figure (2): State Diagram of Serial Binary Adder
At node B, the sum bit is the addition of input combination of bits along with the previous carry. For combination 00, the sum
bit is 0 + 1 = 1, with carry bit = 0 which indicates state A, hence state is changed from B to A. For all other combinations, i.e 01, 10,
11, carry is generated and there is no change in the state. The state table of a Mealy serial binary adder is shown in table (1)
Present state Next state Output (Z)
Inputs (xy) Inputs (xy(
00 01 10 11 00 01 10 11
A
A A A B 0 1 1 0
(Initial state)
B A B B B 1 0 0 1
Table (1) : State Table of a Mealy Serial Binary Adder

If A = 0 and B = 1, the state assigned table is shown in table (2).
Present Next State (Y) Output (Z)
State
xy = 00 01 10 11 xy = 00 01 10 11
a
0 0 0 0 1 0 1 1 0
1 0 1 1 1 1 0 0 1
Table (2): State-Assigned Table

On solving the state assigned table, the next-state and output equations are,
Y = xy + xa + ya
Z = x ⊕ y ⊕ a
The corresponding circuit using above expressions is Let,
shown in figure (3). A0 = 00
x z A1 = 01
Full B0 = 10
y
adder Y y
D Q And B1 = 11
Carry-out
Then the corresponding state assigned table is given in
table (2).
Clock Q Present Next State (Y2 Y1)
Output
State
00 01 10 11 (Z)
Reset y2 y1
00 00 01 01 10 0
Figure (3): Circuit for the Serial Adder Mealy FSM 01 00 01 01 10 1
10 01 10 10 11 0
Q62. Explain in detail about Moore-type FSM for serial
11 01 10 10 11 1
adder.
Table (2): State-assigned Table
Ans:
On solving the state assigned table, the next-state and
The state diagram for Moore-type serial adder FSM is output expressions are,
Reset
Y1 = m ⊕ n ⊕ y2
00 Y2 = mn ⊕ my2 ⊕ ny2
A0 |s = 0
Z = y1
01 11
Where,
10
00 Y1 = Sum
00
01 01 Y2 = Carry-out
10 A1 |s = 1 B0 |s = 0 10
01 Z = Output signal.
11 10
00 The corresponding circuit of above expressions is shown
11
in figure (2).
B1 |s = 1
Sum-bit Y1 y1
m D Q s
11 n Full
adder Carry-out
Figure (1): State Diagram of Moore-type Serial Adder FSM
Q
From figure (1), the state table using state diagram is
given in table (1),
Present Next State Output Y2 y2

State (Z) D Q
00 01 10 11
A0 A0 A1 A1 B0 0
A1 A0 A1 A1 B0 1 Clock Q
B0 A1 B0 B0 B1 0
B1 A1 B0 B0 B1 1 Reset
Table (1): State Table Figure (2): Circuit for the Moore-type Serial Adder FSM

Q63. Write a VHDL code for the serial adder.
Serial adder uses n-bit shift register contents in which enable input is specified. When E = 1, the shift register starts shifting
from left to right otherwise i.e., E = 0, it prevents changing of contents.
The VHDL code for a left to right shift register with an enable input is given below.
LIBRARY ieee;
// left-to-right register with parallel load and enable
ENTITY shiftl2r IS
PORT (R : IN STD_LOGIC_VECTOR(N – 1 DOWNTO 0);
L, E, w : IN STD_LOGIC;
Q : BUFFER STD_LOGIC_VECTOR(N–1 DOWNTO 0);
END shiftl2r
ARCHITECTURE Behavior OF shiftl2r IS
BEGIN
PROCESS
BEGIN
IF E = ‘1’ THEN
IF L = ‘1’ THEN
Q <= R;
ELSE
Genbits : FOR i IN 0 TO N – 2 LOOP
Q(i) <= Q(i + 1);
END LOOP;
Q(N – 1) <= w;
END IF;
END IF;
END PROCESS;
END Behavior;
The complete VHDL code of serial adder is given below.
LIBRARY ieee;
USE .std_logic_1164.all;
ENTITY serial IS
GENERIC (length : INTEGER : = 8);
PORT (Clock : IN STD_LOGIC;
Reset : IN STD_LOGIC;
A, B : IN STD_LOGIC_VECTOR(length – 1 DOWNTO 0);
Sum : BUFFER STD_LOGIC_VECTOR (length – 1 DOWNTO 0);
END serial;
ARCHITECTURE Behavior OF serial IS
COMPONENT shiftl2r
PORT (R : IN STD_LOGIC_VECTOR (N – 1 DOWNTO 0);
L, E, w : IN STD_LOGIC;
Q : BUFFER STD_LOGIC_VECTOR(N – 1 DOWNTO 0);
END COMPONENT;
SIGNAL QA, QB, Null_in : STD_LOGIC_VECTOR(length – 1 DOWNTO 0);
SIGNAL s, Low, High, Run : STD_LOGIC;
SIGNAL Count : INTEGER RANGE 0 to length;
SIGNAL State_type IS (G, H);
SIGNAL y : State_type;
BEGIN
Low <= ‘0’; High <= ‘1’;
ShiftA : shiftrne GENERIC MAP (N => length)
PORT MAP (A, Reset, High, Low, Clock, QA);
ShiftB ; shiftrne GENERIC MAP (N => length)
PORT MAP (B, Reset, High, Low, Clock, QB);
Adder FSM : PROCESS (Reset, Clock)
BEGIN
IF Reset = ‘1’ THEN
y <= G;
ELSIF Clock EVENT AND Clock = ‘1’ THEN
CASE y IS
WHEN G =>
IF QA(0) = ‘1’ AND QB(0) = ‘1’ THEN y <= H;
ELSE y <= G;
END IF;
WHEN H =>
IF QA(0) = ‘0’ AND QB(0) = ‘0’ THEN y <= G;
ELSE y <= H;
END IF;
END CASE;
END IF;
END PROCESS AdderFSM;
WITH y SELECT
s <= QA(0) XOR QB(0) WHEN G,
NOT (QA(0) XOR QB(0) WHEN H;
Null_in <= (OTHERS => ‘0’);
ShiftSum : shiftrne GENERIC MAP (N => length)
PORT MAP (Null_in, Reset, Run, s, Clock, Sum);
Stop : PROCESS
BEGIN
WAIT UNTIL (Clock’ EVENT AND Clock = ‘1’);
IF Reset = ‘1’ THEN
Count <= length;
ELSIF Run = ‘1’ THEN
Count <= Count – 1;
END IF;
END PROCESS;
Run <= ‘0’ WHEN Count = 0 ELSE ‘1’ ; -- stops counter and ShiftSum
END Behavior;

On synthesis of the above VHDL code resultant circuit and timing simulation is shown figures (1) and (2).
1 0 0 0
a7 a0 D3 D2 D1 D0
L
Counter
E
L
0 W Q 3 Q2 Q1 Q0
1 E
Adder
b7 b0 FSM
Run
L 0 0
0 W
1 E
L
W
E
Clock
reset
Sum7 Sum0
Figure (1): Synthesized Circuit from the Code
50.0 ns 100.0 ns 150.0 ns 200.0 ns 250
Reset
Clock
A 2D
B A5
Sum 00 80 40 20 90 48 A4 D2
y G H G H G H G
Figure (2): Simulation Results

Q64. Write a VHDL code for Mealy FSM.
Ans:
The VHDL code for Mealy machine is given below,
LIBRARY ieee;
ENTITY Mealyfsm IS
PORT (Clock, Resetn, w : IN STD_LOGIC;
z : OUT STD_LOGIC);
END Mealyfsm;
ARCHITECTURE Behavior OF Mealyfsm IS
TYPE State_type IS (A, B);
SIGNAL Y : State_type;
BEGIN
PROCESS (Resetn, Clock)
BEGIN
y <= A;
CASE y IS
WHEN A =>
IF w = ‘0’ THEN y <= A;
ELSE y <= B;
END IF;
WHEN B =>
IF w = ‘0’ THEN y <= A;
ELSE y <= B;
END IF;
END CASE;
END IF;
END PROCESS;
PROCESS (y, w)
BEGIN
CASE y IS
WHEN A =>
z <= ‘0’;
WHEN B =>
z <= w;
END CASE;
END PROCESS;
END Behavior;
Q65. Write a VHDL code for Moore-type FSM.
Ans: The VHDL code for Moore-type FSM is mentioned below:
LIBRARY ieee;
ENTITY simplefsm IS // entity declaration
PORT (Clock, Resetn, w : IN STD_LOGIC; // input ports clock, Resetn and w.
z : OUT STD_LOGIC); // output port z.
END simplefsm;
ARCHITECTURE Behavior OF simplefsm IS
TYPE State_type IS (A, B, C); // create a user-defined signal state-type
SIGNAL y : State_type; // define a signal named ‘y’ of ‘state_type’
BEGIN
PROCESS (Resetn, Clock) // FSM ds described as a sequential circuit.
BEGIN
IF Resetn = ‘0’ then // if reset = 0, the machine enters into reset state or state A.
y <= A;
ELSIF (Clock ‘EVENT AND Clock = ‘1’) THEN // the circuit waits for positive edge of clock. It implements
y as the output of one or more flip flops.

CASE y IS
WHEN A => // machine behavior at A
IF w = ‘0’ THEN
y <= A; // machine should be in state A
ELSE
y <= B; // machine should change to state B
END IF;
WHEN B => // machine behavior at B
IF w = ‘0’ THEN
y <= A; // machine should be in state A
ELSE
y <= C; // machine should change to state C
END IF;
WHEN C => // machine behavior at C
IF w = 0 THEN
Y <= A; // machine should be in state A.
ELSE
Y <= C;
END IF;
END CASE;
END IF;
END PROCESS;
z <= ‘1’ WHEN y = C ELSE ‘0’; // if machine is in state ‘C’ the output z = 1 otherwise z = 0.
END Behavior;
Q66. Design a Mealy model of sequence detector to detect the pattern 1001. Nov./Dec.-15, (R13), Q13(b)(ii)
Ans: In Mealy model, the state diagram has the states equal to the number of bits in the given input sequence. Since the given
sequence 1001 has 4-bits,. four states a, b, c, d are considered. The state diagram is as shown in figure (1).
1/0 1/1
0/0
1/0 0/0 0/0
a b c d
1/0
0/0
Figure (1) : State Diagram
When state a is zero, it remains in same state with zero output, otherwise, it shifts to state b with zero output. When b is
zero, it shifts to state c with zero output, otherwise, it remains in same state with zero output. When c is zero, it shifts to state d
with zero output, otherwise, it returns to state b with zero output. When d is zero, it shifts to state a with zero output, otherwise,
it shifts to state b with one as output.
State Table: The State table of the state diagram for sequence 1001 is shown in table (1).
Next State Output
Present State
x=0 x=1 x=0 x=1
a a b 0 0
b c b 0 0
c d b 0 0
d a b 0 1
Table (1)
Design of Mealy Sequence Detector that Detects the Sequence of 1001: Two D-flip-flops are required for four states.
Assign the states as,
a = 00; b = 01; c = 10; d = 11
Excitation Table: The excitation table of sequence 1001 is shown in table (2).
Present State Input Next State Flipflop Inputs Output
A B X A* B* DA DB Z
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0
0 1 0 1 0 1 0 0
0 1 1 0 1 0 1 0
1 0 0 1 1 1 1 0
1 0 1 0 1 0 1 0
1 1 0 0 0 0 0 0
1 1 1 0 1 0 1 1
Table (2): Excitation Table
Then, the simplified Boolean expression for flip-flop inputs can be obtained by using three variable K-map as,
For DA For DB For Z
BX BX BX
A 00 01 11 10 A 00 01 11 10 A 00 01 11 10
1 0
0 0 0 0 0 0 1 1 0 0 0 0 0
1 1 0 0 0 1 1 1 1 0 1 0 0 1 0

DA = AB'X' + A'BX' DB = X' + AB' Z = ABX
The logic diagram for implementation of 1001 sequence detector using D-flip-flops is as shown in figure (2).
X
DA QA A
clock A'
Q 'A
DB QB B
clock B'
Q 'B
Figure (2): Logic Diagarm of Sequence 1001

Q67. Give the comparison between synchronous sequential and asynchronous sequential circuits.
(Model Paper-4, Q6(a) | April/May-19, Set-1, Q6(a) | May/June-15, Set-4, Q1(e) M[4])
(or)
Distinguish between asynchronous and synchronous sequential circuit. April/May-13, Set-2, Q7(b)
Ans:
The differences between synchronous and asynchronous sequential circuits are mentioned below:

Synchronous Sequential Circuits

Asynchronous Sequential Circuits
1. The synchronous sequential circuits are also called 1. The asynchronous sequential circuits do not have a common
clocked sequential circuits as they have a common clock signal connection. Therefore, their state changes
clock signal connection, that changes the states with the changes in input.
of the circuits.
2. In these circuits, changes in the input are predicted 2. In these circuits, changes in the input must occur only when
to occur between the clock pulses. Thus, the circuit the circuit is stable.
must be in a stable state before the occurrence of
next clock pulse.
3. The operating speed of these sequential circuits 3. The operating speed of these sequential circuits is
depend on the clock frequency. independent of clock frequency but changes immediately
when the input changes. Thus, the asynchronous sequential
circuits are faster compare to synchronous sequential circuits.
4. In these circuits clocked flip-flops serve as 4. In these circuits latches (unclocked flip-flops) serve as
memory elements. memory elements. The gate circuits employing feedback
to perform the function of latch can also be used as memory
elements.
5. In synchronous sequential circuits, the inputs can 5. In asynchronous sequential circuits, the change of only one
change simultaneously in the absence of clock input at an instant is permitted. If more number of inputs
signal. change simultaneously, the circuit produces erroneous outputs.
6. The synchronous sequential circuits are costly 6. The asynchronous sequential circuits are economical
because they employ clocked flip-flops. compared to the synchronous circuits.
7. Mealy and Moore are the two types of synchronous 7. The asynchronous sequential circuits can be operated in two
sequential models used. modes based on type of inputs applied. They are,
(a) Fundamental mode
(b) Pulse mode.
Q68. Explain the fundamental and pulse mode asynchronous sequential circuit.
Ans: Based on the type of output variables, asynchronous circuits are divided into two types. They are,
1. Fundamental mode circuits and
2. Pulse mode circuits.
1. Fundamental Mode Circuits: Fundamental mode circuit has one output variable (y) and two input variables I0 and I1. The
two feedback paths provide inputs and generate state variables X0 and X1, which makes it necessary to carry out latching
operation in order to produce a sequential circuit.
Fundamental mode circuit assumes that,
(i) At any given instance of time, only one input variable can change.
(ii) Instead of pulses, levels are used as inputs and delay lines as memory elements.
(iii) An input variable must change only when the circuit is stable and between two successive input changes, a time
interval of at least ‘∆t’ must be maintained.
2. Pulse Mode Circuit: Pulse mode circuits are the circuits which assume that an ‘n’ input line circuit has only n + 1 conditions
and which do not wait for a clock signal before responding to the pulse on their input. Since, the state transition for such
circuit occur only when an input pulse arrives.
Pulse mode sequential circuit assumes that,
1. Flip-flops are often used as memory elements and these memory elements are initiated only by input pulses.
2. Width of pulse should be sufficiently large so that circuit can respond to input, conversely, it should not be too large that
it stay backs even when a new state is reached.
3. Pulses are used as input variables and they do not occur simultaneously on two or more inputs.
4. Input variables are used in either complemented or uncomplemented form. They cannot be simultaneously used on both.
Q69. Explain the analysis of fundamental mode circuits.
Ans: Fundamental mode circuits are classified into two types,
1. Circuits without latches
2. Circuits with latches.
Consider fundamental mode circuit shown in figure (1).
X1
External Next state Q1 Output
inputs logic Q2 logic
X2
(a)
Next state
X1
logic
X2
X2
Q1 Output
Q1
logic
Q2
X1
X1
Q1
Q2
X1
X2 X2
Q1
X1
Q2
Q2
X2
Q2
(b)
Figure (1)
There are no explicit memory elements in this circuit, which consists solely of gates. The next-sate logic circuit has two
feedback pathways from Q1 and Q2. Using this feedback, a sequential circuit can be created by introducing delays. It should be
noticed that feedback in the gate circuit creates a memory elements latch.
v Determine the states and their associated state variables. There are two types of inputs states, the input state and the input
state variables. The input state is made up of the level signals X1, X2 from external sources.
v Memory components combined outputs are known as secondary or internal states and these variables are referred to as
secondary state variables (or simply secondary states).
v Internal variables Q1 and Q2 are sued here because there are no explicit elements. The entire state is made up of the input
and secondary states (Q1, Q2, X1, X2) combined. The value of Y is the variable that is returned as a result of the computation.
v The logic circuit of the next-state logic block is used to determine the equations for the next secondary state
Q1+ = X1 X 2 + X4 X2 Q2 + X2 Q1 Q 2
Q 2+ = X1X2 Q 1 + X1Q2 + X2 Q2
Y = X1 ⊕ Q1 ⊕ Q2
v When X1, X2 input -state variables occur, the circuit transitions to the next secondary state These logic equations are used
to crate the state table displayed in table below.
v The total state Q1, Q2 X1, X2 is stable if the next secondary state is the same as the current state, i.e., Q1+ = Q1 and Q 2+ =
Q2. Otherwise, its prone to instability. A table showing the next total state’s stability is also included.

v The transition table for state table is shown below.
Next state
Input state
Present internal X 1X 2 Q1+ Q +2
state Q1Q2 00 01 11 10
00 00 01 00 10
01 00 11 01 11
11 00 11 01 11
10 00 10 10 10
Table
v In asynchronous sequential circuits, flow tables are usually preferred to transition table.
v The flow table corresponding to above transition table is shown below.
Input state
Stable state
Present internal X1X2
state Q 1Q 2 00 01 11 10
a a ,0 b, 0 a ,1 d, 1
b a, 1 c, 0 b ,0 c, 0
Output
c a, 0 c ,0 b, 1 c ,1
Unstable state
d q, 1 d ,1 d ,0 d ,0
Table
Q70. Explain the step wise procedure for analyzing an asynchronous sequential circuit with SR latches.
Ans:
Consider an SR latch using NAND gates and NOR gates as shown in figure (1).
R
S Qn
Qn
Qn Qn
R S
SR-Latch using NAND Gates SR Latch using NOR Gates
Figure (1)
The next state equation of equation of figure (1) is given by,
Q+ = S + RQ
The transition table of SR latch is shown in figure (2). The characteristics equations of latches are given by,
SR Q1+ = S1 + R1Q1 = X2 + X3 + X4 Q1 ... (6)
Q 00 01 11 10
Q 2+ = S2 + R2 Q2
0 0 0 0 1
= Q1X1 + X4 + Q1X3 .Q2
1 = Q 1X1 + X4 ( Q1X3) Q2
1 0 0 1
= Q1X1 + X4 (Q1 + X3) Q2
Figure (2) Q 2+ = Q1X1 + Q1Q2 X4 + Q2 X3 X4 ... (7)
Q+ = S + RQ The transistion table canbe developed using equations
v From the transition table of SR flip-flop, the circuit (5), (6) and (7).
entes the stable state when SR changes from 11 to 00. Since, only one input vairbale is allowed at each time,
v The circuit enters the stable state j if S first. the columns are for each input variable only. The row contains
v The circuit entes the stable state k if R fist changes to 0. a combination of state variables S1, S2, S3 and S4.
Q71. Explain pulse mode circuits in asynchronous The transition table of figure (1) is shown in table (1).
sequential circuits. Input
variables
Ans: Present
Puse Mode Circuits state Q Q X1 X2 X3 X4
1 2
In pulse-mode circuits, an input pulse canbe applied 00 01, 0 10, 0 10, 0 00, 1 Output
/occured only when the circuit is in stable state and the variables
anypulse is not applied at the other input.. When an input pulse 01 01, 0 11, 0 10, 0 00, 0
is transition from one stable state to other state. It allows the
circuit to receivers another input pusle. 11 11, 0 11, 0 11, 0 00, 0 Next state
value
For a pulse-mode asyhchronous circut, the number of
columns in the next-state table is equal to the number of input 10 10, 0 10, 0 10, 0 00, 0
terminals.
Consider a pulse-mode circuit logic diagram illustrated Table (1): Transition Table
in figure (1). The flow table of figure (1) is given in table (2).
Input
X2 S1 variables
X3 Q1 Present
FF1 state Q Q X1 X2 X3 X4
R1 1 2
X4 Q1
S0 S1, 0 S 3, 0 S 3, 0 S0, 1
F
S1 S1, 0 S 2, 0 S 3, 0 S0, 0
X1
Q2
Q1 S2 S2, 0 S 2, 0 S 2, 0 S0, 0
FF2
X4
Q2 S3 S2, 0 S 3, 0 S 3, 0 S0, 0
Q1
X3 Table (2): Flow Table
Q72. Explain the step wise procedure for analyzing
X4 an asynchronous sequential circuit with SR
Y
Q2 latches.
Figure (1) Ans:
The excitation and output equations are, Procedure for Analysis: The various steps involved in the
analysis of asynchronous sequential circuit with SR latch are
S1 = X2 + X3 ... (1)
as follows,
R1 = X4 ... (2) Step (i): In the first step, latch outputs are labelled with Yi and
S2 = X1 Q1 ... (3) the corresponding external feedback paths with yi (where
i = 1, 2 ... k).
R2 = X4 + Q1X3 ... (4)
Step (ii): In the next step, the Boolean functions for Si and Ri
Y = X4 Q2 ... (5) inputs are determined.

Step (iii): In this step, the condition for NOR latch i.e., SR = Example
0 and NAND latch i.e., S'R' = 0 (if present) must be x x x
y1y2 0 1 y1y2 0 1 y1y2 0 1
satisfied in order to ensure proper operation of the
00 0 0 00 0 1 00 00 01
circuit.
01 1 0 01 1 1 01 11 01
Step (iv): A transition table is constructed by following the
steps mentioned below. 11 1 1 11 1 0 11 11 10
Steps for Transition Table 10 0 1 10 0 0 10 00 10
Step (i): Obtain the excitation functions using the relation, (a) K-Map for (b) K-Map for (c) Transition Table
Y = S + R'y (For NOR latch) Y1 = xy1 + x’y2 Y2 = xy1’ + x’y2
Flow Table: A state table is modified with some input
Y = S' + Ry (For NAND latch). constraints, so as to stop certain input states from following
Step (ii): A map is then constructed wherein y’s represent the another input state. Table which is formed after this modification
rows and x inputs represent the columns. is called ‘flow table’.
Flow table is also like a state table, which contains three
Step (iii): The value of Y = Y1 Y2 ... Yk are plotted in the map. sections i.e., present state, next state and output. It describes
Step (iv): Finally, all the stable states are circled in the map the overall network behaviour, but it fails to put forth few
resulting in the transition table. operational details.
Steps to Construct a Flow Table
Q73. What are transition table and flow table? Give
1. The first step in construction of flow table from state
suitable examples. table is to replace all the unstable states by the symbol
Ans: of the corresponding state.
2. Second step involves deleting all the non-circled entries.
The analysis procedure of asynchronous sequential
3. Finally, the output of the flow table has entries only for
circuits involves the study of behavior of these circuits by
stable input states, while the unstable states are replaced
determining their transition tables and flow tables. These tables
by dashes. The circles in both the transition and flow
gives information about the sequence of internal states and
tables represent the stable states in the asynchronous
outputs which are represented as functions of changes in input sequential circuit.
variables.
Example
Transition Table: A transition table is a form of state table in x
y 0 1
which columns represent the input states and rows represent a a b
the secondary states. 00 01 11 10
b c b
Steps to Construct a Transition Table a a ,0 a ,0 a ,0 b, 0
c c d
1. Initially the feedback loops in the given circuit diagram b a, 0 a, 0 b ,1 b ,0
d a d
are identified.
(a) Four States with (b) Two States with Two Inputs
2. In the next step, the outputs and inputs of each feedback
One Input and One Output
loop are labelled as Yi and yi respectively, where i = 1, 2,
... k. Here, k represents the number of feedback loops. Q74. Explain cycles and races in asynchronous
sequential circuits.
3. Then, the Boolean functions of all Y’s in terms of external Ans:
inputs and y’s are derived. Cycles: A cycle is said to exist in an asynchronous circuit, if the
4. In the next step, each Y function is plotted in separate circuit perform transition through a series of unstable states. In
maps with y variables as rows and external inputs as case, there are no stable states, then the transition occurs from
columns. one unstable state to another unstable state by maintaining the
total circuit unstable.
5. All the maps are then combined into a single table, such The occurrence of cycle is explained with an example
that Y = Y1 Y2 .... Yk are represented in each square. given below.
6. Finally, the values of Y in squares that equally Example: Let, y1y2 = 00 and change of input ‘x’ from 0 to 1. The
corresponds to the value of y = y1 y2 ... yk in same row transition table that terminates with stable states is shown in figure
are circled. (a). Even if there is a transition of state variables from 00 to 11,
a unique transition is provided by the cycle from 00 to 01 and
The transition table so obtained helps in analyzing then to 11 as illustrated in figure (b). If there are no stable states,
the circuit behavior from the state transition as a function of then the transition occurs from one unstable state to another by
variations in input variables. maintaining the total circuit unstable as described in figure (c).
x x x
y1y2 0 1 y1y2 0 1 y1y2 0 1
00 00 00 00 00 00 00 00 00
01 11 01 11 01 11
11 10 11 11 11 10
10 10 10 10 10 01
(a) State Transition (b) State transition (c) Unstable

01 → 11 → 10
00 → 01 → 11 → 10 00 → 01 → 11
Figure: Occurrence of Cycle
Race: In an asynchronous sequential circuit, the race condition occurs when two or more binary state variables change value in response
to a change in an input variable. For unequal delays, race condition causes state variables to change in an unpredictable manner.
Critical Race: The race condition is said to be critical, if the final stable state rely on the order in which the change in state
variable occur.
Example
y y
x1 x2 x1 x2
0 1 0 1
00 00 11 00 00 11
01 01 01 11
11 11 11 11
10 10 10 10
Possible transitions are from Possible transitions are from

00 to 11 00 to 11
00 to 01 00 to 01 to 11
00 to 10 00 to 10
Noncritical Race: A noncritical race occurs when the order in which internal state variables that are changed does not alter the
final stable state.
Example
y y
x1 x2 x1 x2
0 1 0 1
00 00 11 00 00 11
01 11 01 01
11 11 11 01
10 11 10 11
Possible transitions are from Possible transitions are from

00 to 11 00 to 11 to 01
00 to 01 to 11 00 to 01
00 to 10 to 11 00 to 10 to 11 to 01
Q75. Describe gated ‘D’ latch as an asynchronous circuit. Model Paper-1, Q6(b)
Ans: The basic requirement of asynchronous sequential circuit is met when the input signals including clock on D latch do
not vaary simultaneously.
The circuit diagram of asynchronous gated D latches shown in figure (1).
D
Y y
Q
C
Figure (1)

In figure (1), y indicates present-state expression and Master Slave
Y indicates next-state expression. The next state expression is ym ys
given as, D D Q D Q Q
Y = CD + C y + Dy ... (1)
Here, Dy is the redundant term and it can be neglected C Clk Q Clk Q Q
to avoid race conditions. Thus, the minimized expression is,
Y = CD + C y … (2)
The excitation table for equation (2) is shown in
table (1). Figure (1) : Circuit for the Master-slave D Flip-flop
Present Next State Output From figure (1), the output of D-flip flops can be
state CD = 00 01 10 11 expressed as,
y Y Y Y Y Q Ym = CD + C ym + ymD ; for Master …(1)
0 0 0 0 1 0 Ys = C ym + C ys + ym ys ; for Slave …(2)
1 1 1 0 1 1 The terms ymD in equation (1) and ymys in equation (2)

are redundant and can be neglected to avoid race conditions.
Table (1): Excitation Table Thus, the minimized expressions are,
From the table (1), it is clear that the circuit change its Ym = CD + C ym …(3)
state only when C = 1 and D = y1
Ys = C ym + C ys …(4)
A flow table can be derived by assigning the state ‘D’
with A and state ‘1’ with B as shown in table (2). The excitation table for equations (1) and (2) as shown
in table (1).
Next State Output
Present Present Next State
state CD = 00 01 10 11 Q state CD = 00 01 10 11 Output
ym ys Q
YmYs
A A A A B 0
00 00 00 00 10 0
B B B A A 1
01 00 00 01 11 1
Table (2): Flow Table
A state diagram for the flow table is as shown in 10 11 11 00 10 0
figure (2).
11 11 11 01 11 1
11
CD
0X 0X Table (1) : Excitation Table
A/0 B/1
X0 X1
Flow table can be derived from the excitation table by
10 replacing the states, 00, 01,10 and 11 with S1, S2, S3 and S4
respectively as shown in table (2).
Next State
When A is 0X (i.e., 00, 01) and X0 (i.e., 00, 10), it Present Output
remains in same state, producing ‘0’ as output, otherwise, it state
CD = 00 01 10 11 Q
shifts to state B, producing ‘0’ as output.
When B is 0X (i.e., 00, X1) and X1(i.e., 01,11) it remains S1 S1 S1 S1 S3 0
in same state producing ‘1’ as output, otherwise, it shifts to state
A producing ‘1’ as output. S2 S1 S1 S2 S4 1
Q76. Describe master-slave D flip-flop as an
S3 S4 S4 S1 S3 0
asynchronous circuit.
Ans: S4 S4 S4 S2 S4 1
Master-slave D-flip-flop is formed by the combination
of two gated D-latches as shown in figure (1). Table (2) : Flow Table
The state diagram for the flow table is shown in figure (2).
CD
11
0X
S1/0 S3/0 11
X0 10
0X 0X
11
0X
10 S2/1 S4/1
10 X1
Figure (2) : State Diagram for the Master-slave D Flip-flop

The state diagram is described as follows :
When S1, is 01/00/10, it remains in same state producing ‘0’ as output, otherwise, it shifts to state, S3, producing ‘0’ as
output.
When S2 is,
(i) 0X (i.e., 00/01), it shifts to state, S1.
(ii) 10, it remains in same state.
(iii) 11, it shifts to state, S4.
When S3 is
(i) 00/01, it shifts to state S4.
(ii) 10, it shifts to state, S1.
(iii) 11, it remains in same state producing ‘0’ as output.
When S4 is, 00/01/11, it remains in same state by producing ‘1’ as output, otherwise, it shifts to state S2 producing ‘1’ as
output.
Q77. Discuss the design steps of asynchronous sequential circuits.
Ans:
The design procedure of asynchronous sequential circuits is used to minimize the complexity of the circuit. It is also used
to stabilize the circuit by reducing the critical races in the flow table. The design steps of asynchronous sequential circuit are
mentioned below.
1. Construct a primitive flow table from the design specifications.
2. Draw the merger graph from the primitive flow table by combining the stable states of separate rows into a single row.
3. The primitive flow table is then reduced to small rows if and only if there are two or more stable states in a row. Hence, in
a reduced flow table, the change in the input does not alter the state variables. This is possible only when the next stable
state is in the same row.
4. Obtain a transition table from the reduced flow table by assigning different binary values to each state. This assignment
makes the circuit free from critical races.
5. Develop the K-map by assigning the output values to the unstable states.
The procedure to assign output values are as follows,
(i) If the transient state lies between two stable states and have a ‘0’ in its corresponding output variable, then assign a
‘0’ to the output variable.
(ii) If the transient state lies between two stable states and have 1 in its corresponding output variable, then assign a ‘1’
to the output variable.
(iii) If the transient state lies between two stable states and have distinct values i.e., 0 and 1 or 1 and 0, then assign a don’t
care.
6. Group the output values in the K-map and obtain the Boolean expression for the excitation and output variables.
7. For the simplified Boolean function, draw a logic diagram using logic gates.

Q78. Explain the steps required to merge the rows of flow table.
Ans:
Most of the asynchronous sequential circuits have primitive flow table which is incomplete. Therefore those states are
termed as don’t care conditions.
These incompletely specified states can be combined to reduce the number of states in the flow table. Only the states which
are compatible can be combined (i.e., if each possible input has same output when specified and their next states are compatible).
Steps to Merge the Rows of Flow Table
1. Determine compatible pairs (their combinations) by using implication table.
2. Obtain maximal compatibles using a merger diagram.
3. Obtain minimal collection of compatibles which covers all the states and is closed.
Step 1: Determine Compatible Pairs
Consider the primitive flow table of gated-latch circuit employing two inputs and one output state.
(a) Primitive Flow Table (b) Implication Table

Table (1)
Note
(a) If input of the states are not equal then they are not compatible. Put a ‘×’ mark against such pairs.
(b) If the pair is compatible with its next state, then put it under square of such pairs for further investigation of the implication
table.
The compatible pairs for implication table are (a, b), (a, c), (a, d), (b, e), (b, f ), (c, d), (e, f )
Step 2: To Obtain Maximal Compatibility
Maximal compatibility set is a proof of compatibles that contains all the possible combinations of compatible states. This
can be achieved by using a merger diagram where each point on the circumference of a circle represents the state and each line
shows a pair which is compatible.
Figure
∴ Maximal compatibles are (a, c, d), (b, e, f), (a, b).
Step 3: To Obtain Minimal Collection of Compatibles
In this step, the compatible sets are chosen such that they cover all the states and are closed (closed covering condition).
The closure condition is satisfied if there are no implied states or those states are included within the set.
The smaller collection of compatibles which satisfy the above step is,
(a, c, d), (b, e, f )
The above combination is used for reducing the flow The corresponding flow table of initial state diagram is
table as mentioned in table (2). illustrated in table (1).
Next State
Present Output
state z
DN = 00 01 10 11
A A B C - 0
Table (2): Reduced Flow Table
Here, a, c, d are merged into a single row a and similarly B D B - - 0
b, e, f states to b.
C A - C - 1
Q79. Explain in detail about state reduction in
Asynchronous sequential circuits.
D D E F - 0
Note: For proper understanding refer vending-machine E A E - - 1
controller
Asynchronous sequential circuits can be easily F A - F - 1
implemented if number of states are reduced. State reduction
is a two-step process and is described as follows, Table (1) : Initial flow Table
1. Partitioning Procedure The reduction of flow table is as follows,
The following steps are required to reduce the state table, Step-1: Grouping the states those are at same position and have
Step-1: Group the states those are at same position having same same outputs for all input conditions.
outputs for all input conditions. P1 = (AD) (B) (CF) (E)
Step-2: Check the next states in each block of partition P1 belong Step-2: Checking the states in each block of P1 belong to same
to same block of P1 or not. If they differ, split the states. block of P1 or not. If they differ, states are splitted.
Step-3: Check the next states in each block of partition P2 belong For DN = 00 input,
to same block of P2 or not. If they differ, split the states. (A, D) has next states (A, D) which belong to same block
Step-4: If the states in partition P3 are equivalent. Then replace of P1. So, they are not splitted.
the state in flow table. For DN = 01 input,
Example: (A, D) has next states (B, E) which belongs to different
blocks of P1. So they are partitioned as,
Consider an initial state diagram of Moore model of
simple vending-machine controller as shown in figure (1). P1 = (A) (D) (B) (CF) (E)
For DN = 10 input,
(A, D) has next states (C, F) which belong to same block
of P1. So they are not partitioned.
∴ P1 = (A) (D) (B) (CF) (E)
Step-3: Checking the states in each block of P2 belongs to P2
or not. If they differ, states are splitted.
For DN = 0 input,
(C, F) has next state (A, A) which belong to same block
of P2. So, they are not splitted.
For DN = 10 input
(C, F) has next states (C, F) which belong to same block
of P2. So, P3 = P2
Step-4: Since, P3 = P2 the states C, F are equivalent i.e., C =
Figure (1) : Initial State Diagram F. Thus, the state F is replaced by state C.

∴ The reduced flow table is shown in figure(2) (i) Both Si and Sj have the same successor i.e., next state
Next State (or)
Present Output (ii) Both Si and Sj are stable
state z
DN = 00 01 10 11 (or)
(iii) The successor of Si or Sj or both is unspecified.
A A B C - 0
Moreover, both Si and Sj must have the same output
whenever specified.
B D B - - 0
Consider a primitive flow table of Moore-model as shown
in table (3).
C A - C - 1
Next State
Present Output
D D E C - 0 state z
w2w1 = 00 01 10 11
E A E - - 1
A A H B - 0
Table (2) : First-step reduction of the FSM B F - B C 0

Initial flow table corresponding to the initial state
C - H - C 1
diagram is shown in table (1).
The inputs of A and D are (A, D) for DN = 00 ; (B, E) D A D - E 1
for DN = 01 and (C,F) for DN = 10.
The states having same output in all the input conditions E - D G E 1
are grouped together, i.e., at DN = 00, A and D have same output
F F D - - 0
‘0’, at DN = 01, B has output ‘0’ i.e. at E has output ‘1’, and at
DN = 11, C and F have same inputs of A and D are (A,D) for G F - G - 0
DN = 00 ;
\ P1 = (AD) (B) (CF) (E) H - H - E 0
For DN = 00, the success of C are F are (A, A) and for

Table (3) : A Primitive Flow Table
DN = 10, the successors are (C, F). Since A and (C, F) are in
different blocks, (AD) is spitted into (A) and (D) From table (3), it is clear that. There is a compatibility
between the states A and H; B and F; B and G; D and F; F and
The next states of C and F are in the same block of P2. G and G and H. Hence, the compatible pairs are, (A, H), (B, F),
Hence, no further partition can be done. (B, G) (D, E), (F, G) and G, H) only state C is not compatible
\ P3 = P2 with any other state.
Merge diagram provides a compatible relationship
Therefore, it can be concluded that the equivalent
among various states by following the specifications i.e.,
states are C and F i.e C = F. Now, the rows of ‘C’ and ‘F’ are
combined and all F’ S are replaced by ‘C’. The resultant flow (i) Every row of the flow table is indicated as a point.
table is as shown in table (2). (ii) Compatible states are represented by a line drawn
between the two points.
2. Merging Procedure
Merge diagram corresponds to the flow table is shown
Most of the asynchronous sequential circuits have in figure (2).
primitive flow table which is incomplete and these incomplete A B C D
states are termed as don’t care entries. Merging procedure
eliminates don’t care entries by combining the incompletely
specified states which are compatible.
Two states (i.e., rows in a flow table), Si and Sj, are said
to be compatible if there are no state conflicts for any input
H G F E
valuation. Thus for each input valuation, one of the following
conditions must be true. Figure(2) : Merge Diagram for the Flow Table
Merge diagram represents that Example
(i) Row A and H can be merged. The figure (1) represents the state diagram of an arbiter,
(ii) Row B and F can be merged.
(iii) Rows D and E can be merged.
(iv) Row, C cannot be merged with any state.
The merging of the compatible pairs is (A,H), (B,F,G)
and (D,E) is shown in figure (3).
B C
A D
Figure (1) : State Diagram

H E
Table (1) represents the respective flow table (using
unique labels) for figure (1).
Next State
Present Output
G F state
r2r1 = 00 01 10 11 g2g1
Figure(3) : Complete Merge Diagram
This results into a reduced flow table as shown in A A B C - 00
table (4)
Next State B A B A B 01
Present Output
state z C A A C C 10
w2w1 = 00 01 10 11
Table (1) : Flow Table

A A A B D 0
The relabeled flow table is shown in table (2).
B B D B C 0 Next State
Present Output
state g2g1
r2r1 = 00 01 10 11
C - A - C 1
D A D B D 1 A 1 2 4 - 00
B 1 2 4 3 01
Table (4) : Reduced Flow Table
Q80. Explain the concept of transition diagrams in C 1 2 4 5 10
asynchronous sequential circuits.
Ans: Table (2): Reduced Flow Table
The diagrams which represent all the transitions of a From the flow table (2), it is observed that the label 1
for A, 2 and 3 for B, 4 and 5 for C states indicate the transitions
specific truth table are known as transition diagrams. These are
for respective input valuation. The corresponding transition
responsible providing the perfect state assignments. An easy
diagram for the flow table is shown in figure (2)
way of illustrating these diagrams is discussed below.
C = 10
A state for transition diagram includes all the state
transitions of respective state for every input estimation. while
representing a transition diagram, it is to be noted that the 1, 4 2, 4
hamming distance between the transitions must be ‘1’ irrespective
of their orientation. In flow table, each transition may pass through A = 00 B = 01
or more stable states,for every input estimation. These transitions 1, 2
can be uniquely labelled as 1, 2, ... Figure (2) Transition Diagram

From flow table (2), it can be observed that, state B Q81. For the machine given in table, find the
can reach the stable state 2 either from A or C state. So, label equivalence partition and a corresponding
2 is indicated on both paths AB and CB in figure (2). In order reduced machine in standard form and also
to obtain a perfect state assignment , diagonal paths need to explain the procedure.
be eliminated. From figure (2), CB is the diagonal path and is
NS, Z
eliminated by providing the alternative path for the transitions PS
from C to B through A. The transition from C to B through A X=0 X=1
can be made by indicating label 2 on the path CA. Similarly, the A B, 0 E, 0
transition from B to C through A is made by indicating label 4
on the path BA. B E, 0 D, 0
The complete transition diagram is as shown in C D, 1 A, 0

figure (3). D C, 1 E, 0
C = 10
E B, 0 D, 0
Ans: (Model Paper-3, Q6(b) | Oct./Nov.-19, Set-1, Q7(b) M[7])
1, 4, 2 2, 4, 1 The given state table is shown in table (1).
NS, O/P
B = 01 PS
A = 00 X=0 X=1
1, 2, 4
A B, 0 E, 0
Figure (3) Complete Transition Diagram
B E, 0 D, 0
In the flow table (2), there are similar encircled labels
which indicates the alternative paths to the states. From example, C D, 1 A, 0
for r1r2 = 00, all the three states (A,B,C) are indicated with D C, 1 E, 0
label 1 i.e., state A can be reached either from state B or C. The
E B, 0 D, 0
transition from B to A or C to A involves only the change in
one state variable. So,this transition is of no use. Because of Table (1)
the presence of diagonal path, this transition diagram cannot be The given table can be retabulated as shown in table(2).
inserted on two dimensional cube.
X=0 X=1
Since, the transitions from B to C and C to B have PS
NS Output NS Output
alternative paths via A, the path CB can be removed and the
resultant state diagram is as shown in figure (4). A B 0 E 0
C = 10 B E 0 D 0
C D 1 A 0
1, 4, 2 D C 1 E 0
E B 0 D 0
A = 00 B = 01 Table (2)
1, 2, 4
The following steps are required to reduce the state table.
Figure (4) Final Transition Diagram Step 1
Grouping the states that have same output for all input
The corresponding modified flow table is as shown in
conditions.
table (3)
P1= (A, B, E) (C, D)
Step 2
Check the next states in each block of P1 belongs to same
blocks of P1 or not. If they differ, split the states.
For X = 0 Input
v (A, B, E) and (C, D) has next states (B, E, B) and (D,
C) which belongs to same block of P1. So, they are not
Table (3) partitioned.
For X = 1 Input Ans:
v (A, B, E) has next states (E, D, D) which belongs to Given state table is,
different blocks of P1. So, they are spitted as, (A)(B, E)
NS, O/P
v (C, D) has next states (A, E) which belongs to same block PS
of P1. So, they are not partitioned. X=0 X=1
P2 = (A) (B, E) (C, D) a f, 0 b, 0
Step 3
b d, 0 c, 0
Check the next states in each block of P2 belongs to
same block of P2 or not. If they differ, split the states. c f, 0 e, 0
For x = 0 Input d g, 1 a, 0
v (A); (B, E) and (C, D) has next states (B), (E, B) and (D,
C) which belongs to same block of P2. So, they are not e d, 0 c, 0
partitioned. f f, 1 b, 1
For x = 1 Input
g g, 0 h, 1
v (A), (B, E) has next states (E), (D, D) which belongs to
same block of P2. So, they are not partitioned. h g, 1 a, 0
v (C, D) has next states (A, E) which belongs to different Table (1)
blocks of P2. So, they are splitted as,
The given state table can be retabulated as shown in
P3 = (A) (B, E) (C) (D)
table (2),
Hence, the equivalent state is B = E. E is the redundant
state and can be eliminated from the table and also it can be X=0 X=1
replaced by state B. PS
NS, Output NS Output
\ The corresponding reduced machine is as shown in
table (3). a f 0 b 0
NS,O/P b d 0 c 0
PS c f 0 e 0
X=0 X=1
A B, 0 B, 0 d g 1 a 0
B B, 0 D, 0 e d 0 c 0
C D, 1 A, 0 f f 1 b 1
D C, 1 B, 0 g g 0 h 1
Table (3) h g 1 a 0
Q82. Reduce the number of states in the state table, Table (2)
and tabulate the reduced state table and give
proper assignment. The following steps are required to reduce the state table,
Step-1
NS, Z
PS Grouping the states that have same outputs for all input
X=0 X=1 conditions.
A F, 0 B, 0 P1 = ( , b, c, e, g) (d, h) (f)
B D, 0 C, 0 Step-2
C F, 0 E, 0 Check the next states in each block of P1 belong to same
block of 1 or not. If they differ, split the states.
D G, 1 A, 0
For X = 0 Input
E D, 0 C, 0
v (a, b, c, e, g) has next states (f, d, f, d, g) which belongs
F F, 1 B, 1
to different blocks of P1. So, they are splitted as,
G G, 0 H, 0 (a, c) (b, e) (g)
H G, 1 A, 0 v (d, h); (f) has next states (g, g) and (f) which belongs to
Oct./Nov.-19, Set-2, Q7(b) M[7] same block of P1. So, they are not partitioned.

For X = 1 Input Race-free State Assignment Hazards: A flow table with four-
rows requires a minimum of two state variables. In many cases,
v (a, b, c, e, g) has next states (b, c, e, c, h) which belongs
the requirement of extra rows to avoid critical races decides the
to different blocks of P1. So they are splitted as,
use of three binary state variables.
(a, b, c, e,) (g) Consider a flow table having four-rows in which, one or
v (d, h); (f) has next states (a, a) and (f) which belong to two diagonal transitions requires three binary state variables to
same block of P1. So they are not partitioned. satisfy the adjacency requirement.
Þ P2 = (a, c) (b, e) (g) (d, h) (f) 00 01 11 10

a b
a b a d a
Step-3
b b d b a
Check the next states in each block of P2 belongs to same
block of P2 or not. If they differ, split the states. c c a b c
For X = 0 Input d c d d c d c

v (a, c); (b, e); (g); (d, h); (f) has next states (f, f) ; (d, d); (g); Flow Table Transition Diagram
(g, g); (f) which belong to same block of P2. So, they Figure (1)
are not partitioned.
This example clearly shows that it is possible to select
For X = 1 Input extra rows in a flow table in order to achieve a race-free
v (a, c); (b, e); (g); (d, h); (f) has next states (b, e); (c, c); (h); assignment. Figure (1) shows a state assignment map that is
(a, a); (b) which belong to same block of P2. So, they suitable for any four-row flow table. State a, b, c and d are the
are not partitioned. original states and e, f and g are extra states, state r placed in
adjacent squares in the map will have adjacent assignment.
Þ P3 = (a, c) (b, e) (g) (d, h) (f)
State b is assigned binary 001 and is adjacent to the other
Hence, the equivalent states are a = c, b = e, d = h. c, e three original states. The transition from a to d must be directed
and h are redundant bits and can be eliminated from the table through the extra state e to produce a cycle, so that only one
and also can be replaced by a, b, d in the table. binary variable changes at a time.
\ The reduced state table is as shown in table (3), Similarly, the transition from c to a is directed through
g and the transition from d to c goes through f.
NS,Output
PS By using the assignment given by the map, the four-row
X=0 X=1
table can be expanded to a seven-row table that is free of critical
a f, 0 b, 0 races as shown in figure (3).
b d, 0 a, 0
00 01 11 10
d g, 1 a, 0
0 a b c a
f f, 1 b, 1
1 c d f
g g, 0 d, 0
Figure (2)
Table (3)
00 01 11 10
3.4 Hazards IN Sequential Circuits 000 = a b a e a
Q83. What is critical and non-critical races in 001 = b b d b a
asynchronous circuits? How to avoid races? 011 = c c g b c
Illustrate with one example.
010 = g - a - -
Ans:Critical Race: The race condition is said to be critical, 110 = b - - - -
if the final stable state rely on the order in which the change in
111 = f c - - c
state variable occur.
101 = d f d d f
Non Critical Race: A noncritical race occurs when the order
100 = e - - d -
in which internal variables that are changed does not alter the
final stable state. Figure (3)
Q84. Discuss the hazards in asynchronous sequential (ii) Static-0 Hazard: Static-0 hazard refers to the output
circuits and the methods to eliminate them. state of a circuit which is supposed to stay at logic ‘0’
Ans: Model Paper-4, Q6(b) level, suddenly switches to logic ‘1’ for a short duration
(glitch) and returns to logic ‘0’ level.
Hazards: The small spike or glitch (sudden and temporary fault
This hazard occurs POS realization i.e., OR-AND or
for a short duration) at the output of asynchronous sequential
NOR-NOR realization.
circuits due to the propagation delay is called hazard. Hazard
causes a temporary false value at the output resulting in v The SR latch using NAND gates can be set or reset by
malfunctioning of circuit. transient 0 signal on either S or R inputs. When S
and R are both 1 at the same time, the state of the circuit
The hazard that occurs in combinational part of an
does not change. Hence, a transient 1 signal does not
asynchronous sequential circuit. are of two types. They are,
effect the circuit. Hence, circuit before NAND latch
1. Static hazards does not need to be free of static-0 hazards, but it must
2. Dynamic hazards avoid static-1 hazards.
1. Static Hazards: A static hazard occurs when a signal v The hazard free asynchronous circuit using 2 level OR-
is supposed to stay in one particular logic but changes AND or NOR-NOR realization for a NAND SR latch
to another logic. is illustrated in figure (3).
There are two types of static hazards. They are,
(i) Static-1 Hazard: Static-1 hazard refers to the output
state of a circuit which is supposed to stay at logic ‘1’
level, suddenly switches to logic ‘0’ for a short duration
(glitch) and returns to logic ‘1’ level.
This hazard occurs in SOP realization i.e., AND-OR or
NAND-NAND realization.
v A transient 1 is signal on either S or R input can trigger
the SR latch using NOR gates to set or reset, respectively.
v A transient 0 signal does not change the state of the circuit
Figure (3)
when S = R = 0. As a result combinational logic circuit
2. Dynamic Hazard: Dynamic hazard occurs when a signal
that goes before the input terminals of an SR latch does
has to change from 1 → 0 or 0 → 1. It involves a short
not need to be free of static-1 hazards, but it needs to be
oscillation before the signal settles down to another level.
free of static-0 hazard. 1 1
1
The hazard-free asynchronous circuits using 2-level
AND-OR or NAND-NAND realization is illustrated in 0 0 0
(a) Static-1 hazard (b) Static-0 hazard (c) Dynamic hazard
figure (2).
Figure (1): Types of Hazards
3. Essential Hazard
v The essential hazards are due to the unequal delays that
exist along the different paths that carry the same signal
to different destinations in the circuit.
v Essential hazard is caused when the delay of the inverter
circuit is more than the delay of the feedback path.
v These errors caused in the signals cannot be corrected
by adding gates (or) implementing the circuitry using
latch as in static hazards.
v These hazards can be corrected only by making some
Figure (2) adjustments in the path delay that cause errors.

In order to prevent the occurrence of essential hazard, there should be a large feedback delay than individual paths that
are coming from the same point at the input.
An asynchronous sequential circuit’s essential hazard can be identified using its flow table. Consider a total stable state
(S1) of a fundamental mode circuit. When an input variable ‘X’ is changed triggers a transition to another stable state (S2) in an
adjacent column, provided that all feedback channels have same delay. The essential hazard is said to be occurred in the flow table
of the circuit transitions to a different stable state (S3) after three consecutive changes in x due to unequal delays in the feedback
paths.
Example
Figure (4): Flow Table

Consider the flow table in figure (4). If the circuit is in a stable state (A), adjusting the input X from 0 to 1 will cause the
circuit to transition to a different stable (B). Dotted arrows show the state transition.
If the feedback channels are not delayed by an identical amount, there is no issue with the occurrent of an essential hazard.
Assume that the circuit proceeds to static (second row, first column), then to state (C) (Third row, first column), and finally to
state 0 due to unequal delays in the various feedback paths (third row, second column). The solid arrows the circuits represents
operation.
Q1. Discuss the logic circuit of 74×377 register. Write a VHDL program for the same in structural style.
REPEATED
2
TIMES
Ans: Refer Q7. (Oct./Nov.-19, Set-1, Q6(a) M[7] | Nov.-15, Set-1,Q7(b))
Q2. Draw and explain 4-bit universal shift register.
REPEATED
3
TIMES
Ans: Refer Q17. (April/May-19, Set-4, Q6(b) | April/May-13, Set-3, Q7(a) | April-12, Set-2, Q7(b))
Q3. Give a VHDL code for a 4-bit up counter with enable and clear inputs.
REPEATED
2
TIMES
Ans: Refer Q43. (Oct./Nov.-18, Set-3, Q6(b) M[7] | Nov.-15, Set-2, Q7(b)
Q4. Write short notes on the following with suitable examples.
REPEATED
(i) State diagram 2
TIMES
(ii) State table
(iii) State assignment.
Ans: Refer Q54. (Oct./Nov.-18, Set-1, Q7(b) M[7] | April-18, Set-1, Q7(b) M[7])
Q5. Give the comparison between synchronous sequential and asynchronous sequential circuits.
REPEATED
3
TIMES
Ans: Refer Q67. (April/May-19, Set-1, Q6(a) | May/June-15, Set-4, Q1(e) M[4] | April/May-13, Set-2, Q7(b))
Q6. Explain different types of shift registers.

Q7. Give the VHDL programs for different type of shift register.
Q8. Draw the circuit of a bidirectional shift register with parallel loading using 2 to 4 line decoder and D-flip-
flops.
Q9. Draw and explain the working of shift left register.

Q10. Write a VHDL code for an n-bit left-to-right shift register using ‘FOR’ loop.
Q11. Write down truth table, VHDL code for the 4 bit register with parallel load. Also draw the circuit and
output waveform.
Q12. Design a self-correcting 4-bit, 4-state ring counter with a single circulating 0 using IC 74LS194.
Q13. Write a VHDL program for 16-bit barrel shifter for left circular shift only?
Q14. Design a 4 bit synchronous binary even counter and write its behavioural mode.

Q15. Discuss about the working of Johnson counter using 74 LS194.
Q16. Explain the operation of a 4-bit synchronous binary counter with the required diagram and waveforms.
Q17. What are the capabilities and limitations of finite state machines?
Q18. Explain the state equivalence and machine equivalence with reference to sequential machines.
Q19. Draw the logic diagram of Melay model & explore its operation with examples.
Q20. Draw the logic diagram of Moore model & explore its operation with examples.
Q21. What are the Moore and Mealy machines? Compare them.
UNIT-4 (Combinational MOS Logic Circuits) 181
UNIT
Combinational MOS
4 Logic Circuits SI
A GROUP
Syllabus
COMBINATIONAL MOS LOGIC CIRCUITS : Introduction, MOS logic circuits with depletion nMOS loads:
two-inputNOR gate, generalized NOR structure with multiple inputs, transient analysis of NOR gate, two-input
NANDgate, generalized NAND structure with multiple inputs, transient analysis of NAND gate, CMOS logic
circuits:CMOS NOR2 gate, CMOS NAND2 gate,complex logic circuits, complex CMOS logic gates, AOI and
OAIgates, Pseudo-nMOS gates, CMOS full-adder circuit,CMOS transmission gates (Pass Gates), complementary
pass-transistor logic.
Learning Objectives
C Realization of two input NOR gate using MOS logic circuits with depletion nMOS loads.
C Generalized NOR structure with multiple inputs, transient analysis of NOR gate.
C Realization of two input NAND gate using MOS logic circuits with depletion nMOS loads.
C Generalized NAND structure with multiple inputs, transient analysis of NAND gate.
C CMOS logic circuits: Realization of two input NOR gate and NAND gate using CMOS Logic.
C Realization of Complex logic circuits using CMOS Logic, complex CMOS logic gates, AOI and OAI gates.
C Different methods to realize Boolean functions such as Pseudo-nMOS gates, CMOS transmission gates (Pass Gates),
complementary pass-transistor logic.
Introduction
Combinational logic circuits, often known as gates, are the fundamental building blocks of all digital systems. These circuits
carry out Boolean operations on multiple input variables and generate the outputs as Boolean functions of the input variables.
In this unit, we will look at the static and dynamic properties of a variety of combinational MOS logic circuits.
The first important category of combinational logic circuits to be introduced in this unit is the nMOS depletion-load gates.
The incorporation of nMOS depletion load circuits in this section is mostly informative, with the goal of drawing attention to
the load idea, which is still commonly employed in many areas of digital circuit design. We will begin by looking at simple
circuit designs such as two-input NAND and NOR gates, and then we will broaden our scope to include more typical situations
of multiple-input circuit topologies. A similar approach will be used to present the CMOS logic circuits in the subsequent
sections. A detailed examination of the design of complicated logic gates, which permits the implementation of complex
Boolean functions involving numerous variables, will be undertaken. CMOS transmission gates and transmission gate logic
circuits will be the last things we talk about in the unit.

4.1 Introduction, MOS Logic Circuits with Deplection NMOS Loads: Two Input NOR Gate, Generalized
NOR Structure with Multiple Inputs, Transient Analysis of NOR Gate
Q1. Draw the general block diagram of a combinational logic circuit and Explain.
Ans:
As illustrated in figure (1), a combinational logic circuit or gate, executing a Boolean function can be described as a multiple-
input/single-output system and is the most common description of this sort of logic circuit. Node voltages, referred to the ground
potential, are used to represent all input variables. In accordance with positive logic practice, a high voltage of VDD can be used
to represent the logic value “1,” and a low voltage of 0 can be used to represent the logic value “0.” The overall parasitic device
capacitances in the circuit, as well as the interconnect capacitance components observed by the output node, are represented by
the capacitance CL of the output node. The dynamic operation of the logic gate is largely reliant on the output load capacitance.
VDD
V1
V2 Combinational
V3 Logic Circuit Vout
Vn Cload
Figure (1): General Block Diagram of Combinational Logic Circuit

Performance Measure
A combinational logic gate’s voltage transfer characteristic (VTC) tells us a lot about the circuits DC performance. VOL,
or Vth, are critical voltage points for combinational logic circuits. They must be kept in mind when designing combinational logic
circuits. Other parameters that must be taken into account while designing a combinational logic circuit include the dynamic or
transient response characteristics. Further, we must consider the amount of silicon area occupied by the circuit, and the amount
of static and dynamic power dissipated by the circuitry.
Q2. Draw the two input NOR gate logic circuit with depletion nMOS loads and Explain.
Ans: Model Paper-1, Q7
Figure (1) depicts the circuit of two-input NOR gate design using MOS transistors. Figure (2) shows the logic symbol of
the two-input NOR gate as well as the truth table related to it.
VDD
(W/L)Load
Vout
(W/L)A (W/L)B
VA VB
Figure (1): The Circuit of Two-Input NOR Gate using MOS Transistors
VA VB Vout
A low low high
Z =A+B
B low high low
high low low
high high lower
Figure (2): The Logic Symbol of the Two-Input NOR Gate and the Truth Table
The two enhancement-type nMOS driver transistors connected in parallel carry-out the Boolean NOR function as follows:
1. When either of the input voltage VA or VB is at the logic-high level, the appropriate driver transistor switches on and creates
a conducting channel between the output node and the ground. As a result, the output voltage turns low that is to VOL. This
is illustrated in figure (3). VOL is the minimum output voltage when the output is at logic “0”
2. When both VA and VB are high, two parallel conducting routes are formed between the output node and the ground, yielding
the same outcome that is low (VOL). This is illustrated in figure (3).
3. On the contrary, when both VA and VB are low, both driver transistors stay turned off that is both the driver transistors acts
as open circuit. Consequently, the depletion type nMOS transistor, which is acting as load, raises the voltage at the output
node to logic high that is to VOH. This is illustrated in figure (4). VOH is the maximum output voltage when the output is at
logic “1”.
VDD VDD VDD
Depletion Type
NMOS Load
Vout = Low (VOL) Vout = Low (VOL) Vout = Low (VOL)

VB
VA
VA VB VA VB
Low
High
High
Low High High
Figure (3): Equivalent Circuit of Two Input NOR Gate using MOS Transistor for Different values of VA = VB
VDD
Depletion Type NMOS Load
Vout = VOH = VDD (High)(VOL)
VA VB
Low Low
Figure (4): Equivalent Circuit of Two Input NOR Gate using MOS Transistor for Different values of VA = VB = Low

Q3. Explain how to calculate VOH and VOL for two input NOR gate Logic Circuits with Depletion nMOS Loads.
VDD
(W/L)load
Vout
(W/L)A (W/L)B
VA VB
Figure (1): The Circuit Two-Input NOR Gate using MOS Transistors
Calculation of VOH
Figure (1) depicts the circuit of two-input NOR gate design using MOS transistors. The driver transistors are turned off
and do not conducts any drain current when both input voltages VA and VB are less than the appropriate driver threshold voltage.
Under this condition, the load device, which operates in the linear region, also have zero drain current. Then the linear region
current equation for load becomes
kn, load RS V
. S2 VT.load (VOH ) . (VDD – VOH ) – (VDD – VOH ) 2WW = 0
ID,load = ... (1)
2 T X
VOH = VDD is the solu tion obtained for this equation.
Calculation of VOL
The output low voltage VOL must be calculated by considering three different scenarios, i.e., three possible input voltage
combinations, which result in a conducting path from the output node to the ground. The three cases are,
(i) VA = VOH VB = VOL
(ii) VA = VOL VB = VOH
(iii) VA = VOH VB = VOH
The NOR circuit diminishes to a simple nMOS depletion-load inverter during first two cases,i.e.., (i) and (ii), respectively.
When the threshold voltages of the two driver transistors is same (VTO,A = VTO,B = VTO). Then the ratio of driver-to-load of equivalent
inverter can be calculated as,
For case (i), when the driver transistor A is ON, the ratio is
JW N
kdriver. A k' n.driver KK OO
kR = = L L PA ... (2)
kload JK W NO
k' n.load K O
L L Pload
For case (ii), when the driver transistor B is ON, the ratio is
JW N
kdriver.B k' n.driver KK OO
kR = = L L PB ... (3)
kload JK W NO
k' n.load K O
L L Pload
The output low voltage level VOL in both cases is found by using the following equation,
JK k N
load O
VOL = VOH – VT0 – (VOH – VT0) 2 – KKK O. V (V ) 2 ... (4)
kdriver OO T.load OL
L P
The output low voltage (VOL) values calculated for case (i) and case (ii) will be same, when the (W/ L) ratios of both drivers
transistors are same, i.e., (W/L)A = (W/L)B.
In the third case, in which both driver transistors are turned ON, the saturated load current equals the sum of the two linear-
mode driver currents of the first and second cases.
ID.load = ID.driverA + ID.driverB ... (5)
k 2 k R V k R 2 V
load VT.load (VOL) = driver.A SS2 (VA – VT0) VOL – VOL
2 W
W + driver.B SS2 (VB – VT0) VOL – VOLWW ... (6)
2 2 T X 2 T X
Because, VA = VB = VOH, that is the gate voltages of both driver transistors are the same. This means that we can figure
out an equivalent driver-to-load ratio for the NOR structure. Therefore, the NOR gate with both inputs connected to a logic-high
voltage is substituted by an nMOS depletion-load inverter circuit with a driver-to-load ratio equal to equation (7).
SRSJK W NO JK W NO WVW
kdriver.A + kdriver.B k' n.driver SSK L OA + K L OBWW
kR = = TL J P N L P X ... (7)
kload W
k' n.load KK OO
L L Pload
In this situation, the output voltage level is
2
JK kload NO 2
VOL = VOH – VT0 – _VOH – VT0i – KK O V (V ) ... (8)
K kdriver.A + kdriver.B OO . T.load OL
L P
Q4. Consider the depletion load nMOS NOR2 gate shown in figure with the following parameters: mnCox = 25
voltage levels for all four valid input voltage combinations.
Given,
mn Cox = 25 mA/V2
VT0,driver = 1.0V
VT0,load = –3.0 V
g = 0.4 V2
|2fF| = 0.6 V
(W/L) A = 2
(W/L)B = 4
1
(W/L)load =
3
VDD = 5V
We need to find output voltage levels VOH and VOL for all four valid input combinations.
VOH = ? and VOL = ? When any of the input is high
and VOL = ? When both inputs are high.
The expressions for VOH and VOL for different input combinations are as follows.
(i) When both the inputs are low the output is high and it is equal to VDD i.e.,
Vout = VOH = VDD ... (1)
\ VOH = 5V ... (2)

(ii) When any of the inputs is High, the output is low and its expression is
2 K k
J NO 2
VOL = VOH – VT0,driver – _VOH – VT0, driver i – KKK load OOO VT0, load _VOLi ... (3)
kdriverA
L P
2 K k
J NO 2
VOL = VOH – VT0,driver – _VOH – VT0, driver i – KKK load OOO VT0, load _VOLi ... (4)
kdriverB
L P
(iii) When both the inputs are High
To evaluate ‘VOL’ we need to find the values of VT0,driver, kload , kdriver,A & kdriver,B
VT,load , VT0,load
m n Cox KKJ W NOO 25 × 10 –6 JK 1 NO

kload = = × KK OO = 4.1 × 10–6
2 L L Pload 2 L 3P
m n Cox –6
KKJ W NOO = 25 × 10 × ]2g = 25 × 10–6
kdriver,A =
2 L L PA 2
m n Cox –6
KKJ W NOO = 25 × 10 × ]4g = 50 × 10–6
kdriver,B =
L
L PB 2 2
2 K
J kload NO 2
VOL = VOH – VT0,driver – _VOH – VT0, driver i – KKK OV _V i ...(5)
kdriverA + kdriverB OO T0, load OL
L P
VOL, when VA is high is obtained using equation (3) as
JK 4.1 × 10 –6 NO 2
VOL,A = (5 – 1) – (5 – 1) 2 – KK O
–6 O (–3)
L 25 × 10 P
VOL = 4 – 16 – 1.475 = 4 – 14.524
\ VOL,A = 0.189 V
VOL, when VB is high is obtained using equation (4) as

JK 4.1 × 10 –6 NO
2
VOL,B (5 – 1) – (5 – 1) 2 – KK O
–6 O –3
L 50 × 10 P
= 4 – 16 – 0.738 = 4 – 15.918 = 4 – 3.989
\ VOL,B = 0.011 V
VOL when both the inputs are high is obtained using equation (5) as
JK 4.1 × 10 –6 NO
2
VOL = (5 – 1) = (5 – 1) 2 – KK –6
O
–6 O –3
L 25 × 10 + 50 × 10 P
J 4.1 ON
K
=4– 16 – KK OO 9 = 4 – 16 – 0.492
L 75 P
\ VOL = 0.062 V
Therefore, the output voltage levels for different input combinations is
VOH = 5V, VOL, A = 0.189 V, VOL,B = 0.011 V, VOL = 0.062 V
Q5. Explain the generalized NOR structure with multiple inputs.
Ans:
Figure (1) illustrates the generalized n-input NOR gate that encompasses n-parallel driver transistors. In this circuit the
current ID flowing through the load transistor is the sum of currents supplied by the driver transistors that are turned ON. In other
words, when the gate voltage across the driver transistors input is greater than the threshold voltage VT0, the corresponding driver
transistor will conduct and supplies current to the load.
VDD
Vout
ID
ID1 ID2 ID3 IDn

V1 V2 V3 Vn
Figure (1): Generalized n-Input NOR Gate

Then for the generalized n-input NOR gate the combined current ID is the sum of currents supplied by the driver transistors
that are turned ON and is given as,
Z] m n Cox JK W NO RS
]] 2 V
/ ]] K O S2 (VGS, k – VT0) Vout –VoutWW linear
] k (on) 2 L L Pk T X
ID = / ID, k = []
m C J N
] n ox K W O … (1)
k (on) / ]]
]] 2
K O (VGS, k – VT0) 2 saturation
L k
k (on) L P
\
For k = 1, 2, 3,….n
VDD
(W/L)load
Vout
Vin (W/L)eq
Figure (2): Equivalent Inverter Circuit of n-Input NOR Gate

For the purpose of static analysis the multiple-input NOR gate must be converted into an equivalent inverter circuit, as
shown in Figure (2).This can be achieved by assuming the input voltage to all driver transistors is identical, that is, VGS,K = VGS.
Then equation (1) reduces to
Z]
]] m n Cox JKK / JK W NO NOR 2 V
K O OOSS2 (VGS – VT0) Vout –VoutWW linear
]] 2 KK L Pk OT
] k (on) L X
ID = ][ L P
]] m n Cox JKK KJK W ONO NOO
]] K / 2
O (V – V ) saturation … (2)
] 2 Kk (on) L L Pk O GS T0
\ L P
The term VGS,K in equation (1) is replaced with VGS.
The (W/L) ratio of the driver transistor in the equivalent inverter circuit is given as
JK W NO JK W NO
K O = / K O
L Pequivalent k (on) L L Pk
L
All enhancement-type nMOS driver transistors in the NOR gate have their source terminals linked to ground. As a result,
there is no substrate-bias effect on the drivers. However, depletion-type nMOS load transistors are sensitive to the substrate bias
effect because their source is connected to the output node (VDD), hence its source-to-substrate voltage is VSB = Vout.

Q6. Explain the transient analysis NOR gate using MOS transistors.
Ans:
The intrinsic parasitic capacitances associated with the NMOS transistors effects the behavior of two input NOR gate
illustrated in figure (1). Figure (2) illustrates the different parasitic capacitances related to NMOS transistors.
VDD
(W/L)Load
Vout
(W/L)A (W/L)B
VA VB
Figure (1): The Circuit of Two-Input NOR Gate using MOS Transistors
VDD
Cgd,load
Csb,load
Vout
Cwire
Cgd,A Cdb,A Cgd,B Cdb,B
VA VB
Figure (2): Parasitic Capacitances Related to MOS Transistors

VDD
Vout
Cload
VA VB
Figure (3): Single Lumped Capacitance Placed between the Output Terminal and the Ground
The capacitances shown in figure (2) can be combined into a single lumped capacitance and is placed between the output
terminal and the ground as shown in figure (3). The value of this combined load capacitance, Cload is calculated as
Cload = Cgd.A + Cgd.B + Cgd.load + Cdb.A + Cdb.B + Csb.load + Cwire ... (1)
Equation (1) is valid for both single-input switching and concurrent switching. In other words, even though just one input
is active and all other inputs are low, the load capacitance is always present at the output terminal. It does not matter if only one
input is active and the rest aren’t. The expression for Cload is remains valid. This simple truth must be taken into consideration
when performing analyses with the equivalent inverter circuit of n-input NOR gate. The load capacitance at the output terminal
of the NOR gate equivalent inverter is always greater than the lumped load capacitance of a real inverter which has the same
dimensions. As a result, the NOR gate and the corresponding inverter have virtually identical static (DC) characteristics. However,
the NOR gate’s actual transient response will be slower than the equivalent inverters.
4.2 Two Input NAND Gate, Generalized NAND Structure with Multiple Inputs, Transient Analysis
of NAND Gate
Q7. Draw the two input NAND gate logic circuit with depletion nMOS loads and Explain. Model Paper-3, Q7
Ans: Figure (1) depicts the circuit of two-input NAND gate design using MOS transistors. Figure (2) shows the logic symbol
of the two-input NOR gate as well as the truth table related to it.
VDD
(W/L)Load
Vout
(W/L)A
VA
(W/L)B
VB
Figure (1): The Circuit of Two-Input NAND Gate using MOS Transistors
VA VB Vout
A low low high
Z = A$B
B low high high
high low high
high high low
Figure (2): The Logic Symbol of the Two-Input NAND Gate and the Truth Table
The two enhancement-type nMOS driver transistors connected in series carry-out the Boolean NAND function as follows:
1. When both the input voltage VA and VB is at the logic-high level, than only the series connected driver transistor turn ON
and creates a conducting channel between the output node and the ground. As a result, the output voltage turns low that
is to VOL. This is illustrated in figure (3). VOL is the minimum output voltage when the output is at logic “0”.
2. When either of the input voltage VA or VB is at the logic-low level, the corresponding driver transistor turns OFF and acts
as open circuit. As a result, the depletion type nMOS transistor, which is acting as load, raises the voltage at the output
node to logic high that is to VOH. This is illustrated in figure (4). VOH is the maximum output voltage when the output is at
logic “ 1”

3. When both VA and VB are low, both the driver transistors in series stay turned off and acts as open circuit. Consequently,
the depletion type nMOS transistor, which is acting as load, raises the voltage at the output node to logic high that is to
VOH. This is illustrated in figure (4). VOH is the maximum output voltage when the output is at logic “ 1”.
VDD
Depletion Type NMOS Load
Vout – Low (VOL)

VA
High
VB
High
Figure (3): Equivalent Circuit of Two-Input NAND Gate for VA = VB = High

VDD VDD VDD
Vout = VOH = VDD Vout = VOH = VDD Vout = VOH = VDD

VA VA VA
Low High Low
VB VB VB
High Low Low
Figure (4): Equivalent Circuit of Two-Input NAND Gate for different values of VA and VB
Q8. Explain how to calculate VOH and VOL for Two input NAND gate Logic Circuits with Depletion nMOS
Loads. Also calculate drain current when the output voltage is VOL.
Calculation of VOH
In the two-input NAND gate logic circuit, when any of the two inputs of the driver transistors is at logic 0 or LOW, the
output is at logic 1 or HIGH. Under this condition, the driver transistors act as open circuits, and no current flows through the
circuit. Further, the load device, which operates in the linear region, also has a zero drain current. Then the linear region current
equation for load becomes
kn,load R V
ID,load = . SS2 VT , load (VOH ) . (VDD – VOH ) – (VDD – VOH ) 2WW = 0 ... (1)
2 T X
VOH = VDD is the solution obtained for this equation.
Calculation of VOL
For two input NAND gates, a deeper analysis is required for the calculation of the logic-low voltage VOL.The output of the
NAND gate is equal to VOL when both of its inputs are at VOH as shown in figure (1). From the figure, it is evident that the three
transistors are connected in series, so the drain current flowing through them is the same.
i.e., ID.load = ID.driverA = ID.driverB ... (1)
kload 2 kdriver.A RS 2 W V
V _V i = S2 _V – V iV – V DS .AW
2 T.load OL 2 T GS.A T.A DS.A X
kdriver.B RS V
= S2 _V – V iV – V DS.BWW
2
... (2)
2 T GS.B T.B DS.B X
VDD
(W/L)load
Vout = VOL
VA = VOH (W/L)A
VB = VOH (W/L)B
Figure (1): NAND Gate with Both of its Inputs Set to the Logic-High State
Since the input to both the driver transistors is VOH, it is apparent that their gate-to-source voltages are nearly equal to VOH.
Therefore, the drain-to-source voltages of both driver transistors can then be calculated using equation (2) as
2
JK k NO 2
VDS,A = VOH – VT0 – _VOH –VT0i – KK load OO . VT, load _VOLi ... (3)
K kdriver.A O
L P
J
2 K kload O
N 2
VDS,B = VOH – VT0 – _VOH –VT0i – KKK OO . V _VOLi ... (4)
k O T , load
L driver.B P
If the two driver transistors are similar, i.e. kdriverA = kdriverB = kdriver. The output voltage VOL is the total of the drain-to-source
voltages for both drivers, thus we get the following result:
JK KJ k ON 2O
N
VOL = 2 KKKVOH – VT0 – (VOH – VT0) 2 – KKK load OOO . VT, load _VOLi OOO ... (5)
k
L L driver P P
Calculation of drain current when the output voltage is VOL
In order to calculate the drain current ID flowing through the two input NAND logic circuit the gate terminals of the
two identical enhancement-type nMOS driver transistors are coupled together. Further, to simplify the analysis it is assumed
that VT,A = VT,B = VT,0. Now, whenever both of the driver transistors are operating in the linear region, the drain currents can be
expressed as follows:
kdriver RS 2 V
ID,A = S2 _VGS, A – VT0i VDS, A – V DS, AWW ... (6)
2 T X
kdriver SR V
ID,B = S2 _V – V iV – V DS, BWW
2
... (7)
2 T GS, B T0 DS, B X
Due to the fact that ID,A = ID,B, this current may alternatively be written as
I D, A + I D, B
ID = ID,A = ID,B = ... (8)
2
From equation (6) and equation (7), equation (8) can be written as
kdriver RS 2 V W
S2 _V – V iV _V – VT0i VDS.B – V DS
2
ID = – V DS, A + 2 GSB , BW ... (9)
4 T GS, A T0 DS, A X
Using VGS,A = VGS,B – VDS,B in equation (9), we get For k = 1, 2, 3….n
kdriver SR V VDD
ID = S2 _V – V i (V + V ) – _VDS, A + VDS, B iWW
4 T GS, B T0 DS, A DS, B X
... (10) (W/L)Load
Now if VGS,B = VGS and VDS,A + VDS,B = VDS, then expression
for drain current is,
Vout
kdriver SR 2V
ID = S2 _V – V i V – VDS WW ... (11)
4 T GS T0 DS X
Vin (W/L)eq
From the final equation we conclude that, two nMOS
transistors linked in series and having the same gate voltage act
as if they were one nMOS transistor with keq = 0.5 kdriver.
Q9. Explain the generalized NAND structure with

Figure (2): Equivalent Inverter Circuit of n-Input NAND Gate
multiple inputs.
For the purpose of static analysis the multiple-input
Ans: NAND gate must be converted into an equivalent inverter circuit
Figure (1) illustrates the generalized n-input NAND shown in Figure (2). The equivalent (W/L) ratio of the driver
gate that encompasses n-series driver transistors. In this circuit transistor in the equivalent inverter circuit is given as
JK W NO 1
since all the ‘n’ driver transistors are connected in series same K O = … (2)
current ID flows through the load transistor and the ‘n’ driver
L
L P equivalent/ 1
J N KW O
k (on) KK l OOk
L P
transistors, when all of them are turned ON.
For k = 1, 2, 3…. n
VDD
If all the ‘n’ series-connected driver transistors are
identical then we have (W/L)1 = (W/L)2 = (W/L)3 = (W/L)4 = ...
(W/L)Load = (W/L)n = (W/L). Substituting this in equation (2) and solving
we get
KJK W ONO 1 JW N
= KK OO
Vout L
L P equivalent nL L P
As a result of this analysis, the following design strategy
Vin (W/L)1 for an n-input NAND gate is proposed:
As a first step, we calculate the (W/L) ratios for the ‘n’
input NAND equivalent inverter that satisfies the required VOL,
Vin (W/L)2
value. This gives us (W/L) ratio of the load transistor (W/L)load
and the driver transistor (W/L)driver. After that, we fix the (W/L)
ratios of every NAND driver transistors to (W/L)1 = (W/L)2 =
(W/L)3 = (W/L)4 = …… = n(W/L)driver. When all the inputs are at
Vin (W/L)n logic high, this ensures that the series arrangement composed of
n driver transistors has an equivalent (W/L) ratio of (W/L)driver.
This means that for a two-input NAND gate, each driver
transistor need to have a (W/L) ratio that is twice as large as
Figure (1): Generalized n-Input NAND Gate
the equivalent inverter driver. This means that for a two-input
Presuming the threshold voltage of all driver transistors NAND gate, each driver transistor need to have a (W/L) ratio
to be equal to VT0, and omitting the effect of substrate-bias, the that is twice as large as the equivalent inverter driver. If the area
driver current ID, in the linear region is given as taken up by the depletion-type load transistor is very small,
JK 1 NO the resulting NAND2 structure will take up about four times
m C KK OOSR 2 V as much space as the equivalent inverter with the same static
ID = n ox
2 KK/ J N
1
K k (on) KKK Wl OOOk
OOS2 (Vin – VT0) Vout –VoutWW linear
OT X characteristics. It is important to remember that high (W/L)
L L P P
... (1) ratios will lead to high parasitic capacitances.
Q10. Explain the transient analysis NAND gate using MOS transistors.
Ans: The intrinsic parasitic capacitances associated with the NMOS transistors effects the behavior of two input NAND gate
illustrated in figure (1). Figure (2) illustrates the different parasitic capacitances related to nmos transistors.
VDD
(W/L)Load
Vout
(W/L)A
VA
(W/L)B
VB
Figure (1): The Circuit of Two-Input NAND Gate using MOS Transistors
The capacitances shown in figure (2) can be combined into a single lumped capacitance and is placed between the output
terminal and the ground as shown in figure (3). The input voltage conditions determine the value of the lumped capacitance Cload.
For instance, if we presume the input VA is equal to VOH and the other input VB is switching from VOH to VOL. In this situation, both
the output voltage Vout and the internal node voltage Vx will increase and, the value of load capacitance, Cload is calculated as
Cload = Cgd.load + Cgd.A + Cgd.B + Cgs.A + Cdb.A + Cdb.B + Csb.A + Csb.load + Cwire ... (1)
This estimate is fairly conservative as it includes the internal node capacitances into the lumped output capacitance Cload
completely. In practice, cload includes just a small percentage of the total internal node capacitance. The use of excessively cautious
capacitance values in the design will force the designer to increase transistor size to compensate for the large delays expected.
VDD
Cgd, load
Csb,load
Vout
Cwire
Cgd,A Cdb,A
VA
Cgs,A Csb,A
Cgd,B Cdb,B
VB
Figure (2): Parasitic Capacitances Related to MOS Transistors

Now consider the case when the input VB is equal to VOH and input VA switches from VOH to VOL. The output voltage Vout
will raise in this circumstances, but the internal node voltage Vx will remain fragile due to the fact that the bottom driver transistor
is turned on. Hence, the lumped output capacitance, Cload is calculated as
Cload = Cgd,load + Cgd,A + Cdb,A + Csb,load + Cwire ... (2)

From equation (2), it is evident that the load capacitance in this situation is less than the load capacitance determined in the
preceding case. As a conclusion, we say that the high-to-low switching delay from signal B to the bottom transistor is anticipated
to be longer than the high-to-low switching delay from signal A to the top transistor.
VDD
(W/L)Load
Vout
Cload
(W/L)A
VA
(W/L)B
VB
Figure (3): Single Lumped Capacitance Placed between the Output Terminal and the Ground
4.3 CMOS Logic Circuits : CMOS NOR Gate, CMOS NAND Gate
Q11. Draw the two input CMOS NOR gate logic circuits and Explain its operation.
The circuit diagram of a two-input CMOS NOR gate is illustrated in Figure (1). The circuit is composed of two networks:
an nMOS-network and a pMOS-network connected in series with each other. The nMOS-network contains nMOS transistors that
are connected in parallel and the pMOS-network contains pMOS transistors that are connected in series Figure (1). The gates of
one nMOS and one pMOS transistor are activated by applying the input voltages VA and VB.
VDD
VDD
M3
VA
M4 pMOS
VB Network
VB
Vout Vout
VA
M1 M2 pMOS
VA Network
VB
Figure (1): The Circuit Diagram of Two-Input CMOS NOR Gate and its Schematic Diagram
1. When either of the input voltages, or both the input voltages, VA or VB is at the logic-high level, the nMOS-network generates
a conducting channel between the output node and the ground and the pMOS network acts as open circuit. As a result, the
output voltage turns low that is to VOL.
2. When both the input voltages VA and VB are at the logic-low level, the pMOS-network generates a conducting path between
the output node and supply voltage VDD and the nMOS network acts as open circuit. As a result, the output voltage turns
high that is to VOH.
The dual or complementary circuit design enables the output to be attracted either to VDD or to ground via a low-resistance
route for any input data combination. None of input combinations creates a DC current route between VDD and ground. Therefore,
we have a totally complementary method of functioning.
Q12. Explain how to calculate switching threshold for two input NOR gate using CMOS Logic Circuits.
The switching threshold (Vth) is a critical voltage point for CMOS logic circuits. When it comes to circuit design, the CMOS
gate’s switching threshold voltage, Vth, is a critical design factor to be considered. In order to calculate the switching threshold
for the two- input CMOS NOR gate three assumptions are made
1. Input voltages switch concurrently, that is, VA = VB
2. The transistor sizes in each block are the same, i.e.., (W/L)n,A = (W/L)n,B and (W/L)p,A = (W/L)p,B
3. To keep things simple, the substrate bias effect for pMOS transistors is not taken into consideration.
As per definition, at the point of switching threshold, the output voltage is equal to the input voltage
VA = VB = Vout = Vth ... (1)
Since VGS = Vps, it is apparent that the nMOS transistors that are connected in parallel reach the saturation point. Therefore,
the total combined drain current of the two nMOS transistors is
ID = kn(Vth – VT,n)2 ... (2)
Equation (2) gives the first expression for the switching threshold Vth, which is written as
ID
Vth = VT,n + ... (3)
kn
Inspection of the p-network of the two input NOR gate reveals that one pMOS transistor (M3) operates in the linear region,
while the other pMOS transistor (M4) is in saturation for Vin = Vout. Therefore, the currents flowing through the transistors M3 &
M4 are
k p SR 2 W V
ID3 = S2 (V – V – | VT, p |) VSD3 – V SD 3W ... (4)
2 T DD th X
kp 2
ID4 = (V – V – | VT, p | – VSD3) ... (5)
2 DD th
Both pMOS transistors carry same drain currents, i.e., ID3 = ID4 = ID. Therefore,
kp R 2 VWW = k p (V – V – | V | – V ) 2
SS2 (VDD – Vth – | VT, p |) VSD3 – V SD3 ... (6)
2T X 2 DD th T, p SD3
Upon analysis we get,

ID
VDD – Vth – |VT.p| = 2 ... (7)
kp
From Equation (7), we get the second expression for the switching threshold Vth. Combining Equation (2) with Equation
(7), the switching threshold for the CMOS NOR gate is found to be,
1 kp
VT, n + (V – | VT, p |)
2 kn DD
Vth(NOR) =
1 kp
1+
2 kn
Q13. Draw the two input CMOS NAND gate logic circuits and Explain its operation.
Ans:
The circuit diagram of a two-input CMOS NAND gate is illustrated in Figure (1). The circuit is composed of two networks:
an nMOS-network and a pMOS-network connected in series with each other. The nMOS-network contains nMOS transistors that
are connected in series and the pMOS-network contains pMOS transistors that are connected in parallel Figure (1). The gates of
one nMOS and one pMOS transistor are activated by applying the input voltages VA and VB.

1. When either of the input voltages, or both the input voltages, VA or VB is at the logic-low level,, the pMOS-network creates
a conducting path between the output node and the supply voltage VDD and the nMOS network acts as open circuit. As a
result, the output voltage turns HIGH that is to VOH.
2. When both the input voltages VA and VB are at the logic-high level, the nMOS-network creates a conducting path between the
output node and ground and the pMOS network acts as open circuit. As a result, the output voltage turns LOW that is to VOL.
VDD
VDD
kp kp
VA
pMOS
Network
VB
Vout
Vout
kn
VA
nMOS
Vin kn Network
VB
Figure (1): The Circuit Diagram of Two-Input CMOS NOR Gate and its Schematic Diagram
Switching Threshold for NAND Gate
In order to calculate the switching threshold for the two-input CMOS NAND gate we assume that the device sizes in each
network block are identical, that is, with (W/L)n,A = (W/L)n,B and (W/L)p,A = (W/L)n,B. Upon analysis and assessment the switching
threshold for CMOS NAND gate is found as
kp
VT, n + 2 (V – | VT, p |)
kn DD
Vth (NAND) = … (1)
kp
1+2
kn
From equation (1) it is evident that a switching threshold voltage of VDD/2 (for simultaneous switching) is achieved by
setting VT,n = V|T,p| and kn = 4 kp in the CMOS NAND gate as shown in figure (2).
VDD
2kp
Vin Vout
kn/2
Figure (2): Two-Input CMOS NAND Gate Equivalent
4.4 Complex Logic Circuits, Complex CMOS Logic Gates, AOI and OAI Gates, Pseud - nMOS Gates,
CMOS Full Adder Circuit
Q14. Draw and explain the layout for CMOS NOR and NAND gates. Model Paper-2, Q8(a)
Ans: A layout prototype of a CMOS NOR gate adopting single layer metal and single-layer polysilicon is depicted in figure (1).
In this arrangement, P-type and n-type diffusion regions for pMOS transistors and nMOS transistors are positioned in parallel,
that is, placed next to each other. This makes it easy to route gate signals through two parallel polysilicon lines that run vertically
in the same direction.
VDD VDD
VA M3
M3 M4 n-well
VB M4
Vout OUT
M1 M2
VA M2 VB M2
GND
VA VB
Figure (1): Layout Prototype of a CMOS NOR Gate
Stick diagram representation of the CMOS NOR gate layout seen in figure (1) is as shown in figure (2). In this figure,
rectangles illustrate the diffusion regions, solid lines illustrate metal connections, circles represent the contacts, and crosshatched
strips represent the polysilicon columns. The stick-diagram is a simplified layout drawing that encompasses useful information
about the relative arrangement of transistors and their interconnections.
VDD
WP
OUT
Wn
GND
A B
Figure (2): Stick Diagram of CMOS NOR Gate
A layout prototype of a CMOS NAND gate is similar to NOR gate, that is, it also employs single layer metal and single-layer
polysilicon and is as illustrated in figure (3). In this arrangement also, P-type and n-type diffusion regions for pMOS transistors
and nMOS transistors are positioned in parallel, that is, placed next to each other. This makes it easy to route gate signals through
two parallel polysilicon lines that run vertically in the same direction.
VDD
VDD
VA M3 M4 n-well
M3 VB M4
Vout OUT
VA M1
M1 M2
VB M2
GND
VA VB
Figure (3): layout Prototype of a CMOS NAND Gate

Q15. Explain about Implementation of Complex Boolean functions using nMOS Logic Circuits.
The fundamental circuit topologies and design ideas defined for simple NOR and NAND gates using nMOS logic circuits
can be easily expanded to complex logic gates to realize arbitrary Boolean functions of multiple input variables. One of the most
appealing aspects of nMOS logic circuits is their capacity to realize complex logic functions with a minimal number of transistors.
As an illustration, observe the Boolean function given below.
Z = A (D + E) + BC ... (1)
The above Boolean function is implemented using nMOS depletion-load logic and is as shown in figure (1). Analysis of
the circuit in figure (1) reveals the information given below.
1. Driver transistors connected in parallel carry-out OR operations.
2. Driver transistors connected in series carry-out AND operations.
3. Inherent nature of MOS circuit performs NOT (inverter) operation.
It is easy to execute Boolean OR & AND operations in a nested circuit structure utilizing the design principles described
here for individual inputs and the corresponding driver transistors. As a consequence, we get a circuit topology that is made of
branches that are coupled in series and parallel, as seen in the figure below.
VDD
(W/L)Load
Vout
A (W/L)A B (W/L)B
D E C
(W/L)D (W/L)E (W/L)C
Figure (1): nMOS Complex Logic Gate Realizing the Boolean Function Z
We can use the equivalent inverter method to analyze and design more complex logic gates. Therefore, the equivalent-
driver (W/L) ratio of the pull-down network consisting of five nMOS transistors (figure.1), when all the input variables are at
logic-high, may be calculated as
JW N 1 1
KK OO = + ... (2)
L
L P equivalent 1 1 1 1
+ +
KJ W ON KJ W ON JK W NO JK W NO KJ W ON
KLO KLO KLO K L O +K L O
L P B L P C L P A L PD L PE
To calculate the equivalent-driver (W/L) ratio of the five nMOS driver transistors (figure.1), when all the input variables
are at logic-low, different cases must be taken into consideration; The design purpose is to set the driver and load transistor sizes
in such a way that the complicated logic gate achieves the desired VOL value even in the worst situation. The following ratios are
produced by this design method for the three worst-case situations.
JK W NO JK W NO JW N
K O = K O = 2 KK OO
L
L PA L PD L L L Pdriver
JK W NO JK W NO JK W NO
K O = K O = 2K O ... (3)
L L PA L L PE L L Pdriver
JK W NO KJ W ON JW N
K O = K O = 2 KK OO
L L PB L L PC L L Pdriver
The transistor sizes determined using the above equations ensure that the logic-low output voltage level will be less than
the set VOL for all other input combinations.
Q16. Explain about Implementation of Complex Boolean functions using CMOS Logic Circuits.
The fundamental circuit topologies and design ideas defined for simple NOR and NAND gates using CMOS logic circuits
can be easily expanded to complex logic gates to realize arbitrary Boolean functions of multiple input variables. One of the most
appealing aspects of CMOS logic circuits is their capacity to realize complex logic functions with a minimal number of transistors.
As an illustration, observe the Boolean function given below.
Z = A (D + E) + BC ... (1)
The initial step in the implementation of the Boolean function is to design the pull-down network, as seen in Figure (1),
which makes use of the fact that NMOS devices in series perform the AND function and NMOS devices in parallel implement the
OR function, as shown in Figure 1. The subsequent step is to use duality in order to derive the pull-up network in a hierarchical
manner.
Z VDD
A B
A D
E
D E C
B C

Figure (1): Pull-Down Network Figure (2): Pull-Up Network
The PDN network is divided into smaller networks (i.e., subsets of the PDN) that are referred to as sub-nets. Next, the
sub-nets that are in parallel in PDN after applying duality they will be in series. Similarly, the sub-nets that are in series in PDN
after applying duality they will be in parallel. The resulting pull-up network is as shown in figure (2). The implementation of the
complete Boolean function F using CMOS Logic Circuits is illustrated in figure (3). For every possible input combination, there
always exists a path to either VDD or GND.
VDD
A D
B C
A B
D E C
Figure (3): CMOS Complex Logic Gate Realizing the Boolean Function Z

Q17. Explain about problem of constructing a minimum-area layout for the complex CMOS logic gate.
Ans:
In an initial attempt, the polysilicon gate columns are arranged in an arbitrary order as depicted in the stick-diagram layout
of Figure (1). In this, Polysilicon columns must be separated enough to allow for one diffusion-to diffusion separation and two
metal-to-diffusion contacts in the middle of the polysilicon. For this obviously we need significant amount of additional silicon
surface area.
We wish to reduce the number of diffusion-area breaks in both nMOS and pMOS transistors. This ensures that the spacing
between polysilicon gate columns can be reduced, Which in turn reduces the overall horizontal dimension and, thus, the circuit
layout area, saving us space. The number of diffusion breaks can be reduced by changing the sequencing of the polysilicon
columns.
VDD
D S S D S D
pMOS
D S S D
OUT
D S
D nMOS
D S D S D S S
GND
A E B D C
Figure (1): Stick-Diagram Layout of the Complex CMOS Logic Gate, with an Arbitrary Ordering of the Polysilicon Gate Columns
A straightforward way for determining the best gate ordering is the Euler-path technique: identify an Euler path in both
the pull-down graph structure and in the pull-up graph structure with same ordering of input labels. The Euler path is described
as an unbroken path that crosses every edge (branch) of the graph exactly once. Figure (2) shows how to make a common Euler
path for both of our graphs. Identifying a common Euler path in both graphs for n-net and p-net gives a gate ordering that reduces
the number of diffusion breaks and, hence, minimizes the logic- gate layout area. In both situations, the Euler path begins at (x)
and ends at (y).
B Common Euler Path A

A
x E
x E-D-A-B-C y
D E B C
C
y
nMOS Network pMOS Network
Figure (2): Common Euler Path
From figure (2) it is evident that for both graphs there is a common sequence (E - D -A - B - C), that is, Euler path. This
sequence may be used to organize the polysilicon gate columns, resulting in continuous (uninterrupted) p-type and n-type diffusion
regions. Figure (3) illustrates the stick diagram of the revised layout. The polysilicon column separation Δd in this situation will
permit only for one metal-to-diffusion contact. The benefits of this revised layout include more compressed (smaller) layout area,
simplified routing of signals, and subsequently, less parasitic capacitance.
VDD
S D D S
pMOS
D S D S S D
OUT
D S
nMOS
D S S D S D D S
GND
E D A B C
Figure (3): Revised Layout
Q18. Explain about AND-OR-INVERT (AOI) and OR-AND-INVERT (OAI) gates in CMOS logic.
Ans:
While there are no strict restrictions on the structure of the pull-down and associated pull-up networks in a complex CMOS
logic gate, designers identify two essential circuit types as subsets of the overall complex CMOS gate structure. The AND-OR-
INVERT (AOI) and OR-AND-INVERT (OAI) gates are subsets of the overall complex CMOS gate structure.
AOI gates are used to implement the Boolean functions in the form of sum-of-product in a single logic step. This is illustrated
in figure (1). The pull-down network of the AOI gate is composed of parallel branches of nMOS driver transistors that are coupled
in series with one another. It is very simple to find the equivalent p-type pull-up network by employing the dual-graph notion.
VDD
Dual pMOS
pull-up Network
A1 Vout
A2
A3
A1 C1
B1
B2 B1
C1 A2 C2
C2 B2
C3 A3 C3
Figure (1): AOI Gate and Respective Pull-Down Network
On the other hand, OAI gates are used to implement the Boolean functions in the form of product-of-sum in a single
logic step. This is illustrated in figure (2). The pull-down network of the OAI gate is composed of series branches of nMOS
driver transistors that are coupled in parallel with one another. It is very simple to find the equivalent p-type pull-up network by
employing the dual-graph notion.

VDD
Dual pMOS
pull-up Network
Vout
A1
A2 C1
A3
B1 B1 B2
B2
A1 A2 A3
C1
Figure (2): OAI Gate and Respective Pull-Down Network

Q19. Write short notes on Pseudo-nMOS gate.
Due to the high space requirements of complicated CMOS gates, high-density designs are difficult to implement because
each input requires two complementary transistors, one nMOS and one pMOS. One method of decreasing the number of transistors
is to employ a single pMOS transistor as the load device and connect its terminal to ground as illustrated in figure (1). In this
way, using the simplified pull-up configuration, the complex gate can be realized with significantly lesser number of transistors.
Obviously, this structure is very similar to depletion-load nMOS logic gates. Hence, the name “Pseudo-nMOS gate.”
VDD
pMOS Transistor
acting as Load
Vout
C1
B1 B2
A1 A2 A3
Figure (1): Pseudo-nMOS Implementation

While using a pseudo-nMOS gate rather than a full-CMOS gate, there are several disadvantages. The most significant
drawback is the nonzero static power dissipation caused by the always-ON pMOS load device. The pMOS load in the ON state
conducts a steady-state current while the output voltage is less than VDD. Further, a new factor has been added to the equation,
which is the ratio of the pMOS load transconductance to the pull-down or driver transconductance. The value of VOL and the noise
margins are now calculated using this factor.
Q20. The simplified layout of a CMOS complex logic circuit is given in figure below. Draw the corresponding
circuit diagram, and find an equivalent CMOS inverter circuit for simultaneous switching of all inputs,
assuming that (W/L)p = 15 for all pMOS transistors and (W/L)n = 10 for all nMOS transistors.
D E A B C Z
VDD
DIFF.
NWELL
P+
POLY
GND MET-1
Figure
Ans:
The circuit diagram is obtained by analyzing the layout and is as shown in figure (1).
VDD
D
C
E
B
A
B C
D E A
Figure (1): Circuit Diagram Realized from Layout
Given KJK W ONO = 15

L L Pp
JK W NO
and K O = 10
L L Pn
The three parallel transistors with inputs A, D, E and the two parallel transistors B, C perform OR operation. Together,
they are ANDed and inverted and the Boolean function realized by this circuit is
Z = (D + E + A) (B + C) ... (1)
Therefore, the equivalent-driver (W/L) ratio of the pull-down network consisting of five nMOS transistors, when all the
input variables are at logic-high, is calculated as,

JW N 1
KK OO =
L L Pn, eq 1 1
JK W ON JK W NO KJ W ON + JK W ON KJ W ON
K O +K O +K O K O +K O
L L PD L L PE L L PA L L PB L L PC
1 600
= = = 12
1 1 50
+
30 20
JK W NO
\ K O = 12
L L Pn, eq
Similarly, the equivalent-driver (W/L) ratio of the pull-UP network consisting of five pMOS transistors, when all the input
variables are at logic-LOW, is calculated as
JW N 1
KK OO =
L L Pp, eq 1 1 1 1 1
JK W NO + KJ W ON + KJ W ON + JK W ON + KJ W ON
K O K O K O K O K O
L L PD L L PE L L PA L L PB L L PC
1 15
= =
1 1 1 1 1 5
+ + + +
15 15 15 15 15
JK W NO
\ K O =3
L L Pp, eq
Q21. Explain implementation of full adder using CMOS logic circuits.
A Full adder is a combinational logic circuit, it encompasses three input variables (A, B, and C) and two outputs (Sum &
Carry). The Boolean functions of the full adder are defined as the sum_out and carry_out and are given as
sum_out = A5B5C
= ABC + A B C + A B C + A C B
carry_out = AB + AC + BC
In figure (1), we can see the implementation of the two functions at the gate level. The crucial thing about this circuit is, rather
than performing the two functions independently, we generate the sum output by using the carry-out signal. This implementation
will, in the end, minimize the complexity of the circuit and, as a result, save chip area. Aside from that, two distinct sub-networks
are identified, each of which has a number of gates (outlined with dotted boxes), that are used for the transistor-level implementation
of the full-adder circuit.
A
B carry_out
C
A
B
C
sum
Figure (1): Gate-Level Schematic of the One-Bit Full-Adder Circuit
Figure (2) illustrates the transistor-level design of the CMOS full-adder circuit in CMOS technology. Also take note that
the circuit is comprised of an overall total of 14 nMOS transistors and 14 pMOS transistors, along with two CMOS inverters that
are employed to generate the outputs.
VDD
A B A B C
C VDD
B carry_out
B
C A A
sum
A
C A
B
B C
A B A B C
Figure (2): Transistor-Level Schematic of the One-Bit Full-Adder Circuit

The full-adder circuit shown in figure (2) can be used as fundamental building unit of a basic n-bit binary adder that receives
two n-bit binary digits as inputs and generates the binary sum at the output. The n-bit binary adder using basic full adder unit is
illustrated in figure (3). The adder is made by connecting a series of full adders together in a cascade fashion, in which each adder
stage carry out a two-bit addition and outputs the associated sum bit and transmits the carry output to the subsequent stage in the
cascade. Because of the carry bits rippling the cascade-connected adder design is known as carry ripple adder. The delay of the
carry bits rippling through the carry chain limits the overall speed of the carry ripple adder; thus, a quick carry-out response is
critical for the adder chain’s complete performance.
S0 S1 S2 S7
Full Adder C1 Full Adder C2 Full Adder C3 C7 Full Adder

C0 C8
(FA) (FA) (FA) (FA)
A0 B0 A1 B1 A2 B2 A7 A7
Figure (3): Block Diagram of a Carry Ripple Adder Chain consisting of Full Adders
4.5 CMOS Transmission Gates (Pass Gates), Complementary Pass Transistor Logic
Q22. What is CMOS transmission gate? Explain its operation.
CMOS transmission gate (TG) also known as pass gate is a simple switch circuit, which is used as a basic building block in
the design of new class logic circuits. One nMOS and one pMOS transistor are linked in parallel to form the CMOS transmission
gate, and the gate voltages for the two transistors are adjusted to be complimentary to each other. This is illustrated in figure (1).
So the CMOS Transistor Gate (CMOS TG) functions as a bidirectional switch between the nodes A and B, with the switch being
controlled by signal C.
A logic-high on control signal C (that is, one that is equivalent to VDD ) causes both transistors to TURN ON and create a
current route between the nodes A and B that has low resistance. Contrarily, a logic-low on control signal C causes both transistors
to TURN OFF, and there will be an open circuit between the nodes A and B. This is often referred to as the high-impedance state.

C C
A B A B
C
C
C
C
A B A B
C
C
Figure (1): CMOS Transmission Gate Circuit Diagram and Symbols
Further, the nMOS transistor’s substrate terminal is linked to ground, whereas the pMOS transistor’s substrate terminal is
linked to the VDD supply voltage (see figure).Therefore, based on the bias conditions, it is essential to consider the substrate-bias
impact for both transistors. Figure (1) illustrates three more frequently used symbolic representations of the CMOS transmission
gate.
Q23. Explain the DC analysis of the CMOS transmission gate.
Ans:
In order to perform full DC analysis of the CMOS transmission the bias condition illustrated in figure (1) is taken into
account. A steady logic-high voltage, Vin = VDD, is applied to both the input node (A) and the control signal C. Because the control
signal is also logic-high, both transistors are switched on. Alternatively, the output node (B) might be linked to a capacitor, which
would simulate capacitive loading of the succeeding logic stages driven by the transmission gate. We shall now analyze the CMOS
TG’s input-output current-voltage relationship as a function of the output voltage Vout.
0V
ID ISO,p
Vin= VDD Vout
IDS,n
VDD
Figure (1): Bias Conditions of CMOS Transmission Gate

VDS,n = VDD – Vout
VGS,n = VDD – Vout … (1)
Equation (1) gives the voltages between drain-to-source ( VDS ) and the gate-to-source ( VGS ) of the nMOS transistor. This
means that when Vout > VDD – VT,n the nMOS transistor will be switched off, and when Vout < VDD – VT,n is reached, the transistor
will function in saturation mode.
VDS,p = Vout – VDD
VGS,p = – VDD … (2)
Equation (2) gives the voltages between drain-to-source ( VDS) and the gate-to-source ( VGS ) of the pMOS transistor. This
means that when Vout > |VT,p|the pMOS transistor operates in the linear region, and when Vout < |VT,p | the pMOS transistor operates
in the saturation region. It should be noted that, in contrast to the nMOS transistor, the pMOS transistor maintains its ON state
regardless of the output voltage level Vout.
This analysis reveals that, based on the output voltage level, the CMOS transmission gate can be operated in three distinct
regions. This regions are illustrated in figure (2) as a function of Vout. The total current flowing through the transmission gate is
equal to the sum of the nMOS drain current and the pMOS drain current, which is given as
ID = IDS,n + ISD,p ... (3)
Region 1 Region 2 Region 3
nMOS:saturation nMOS:saturation nMOS:cut-off

pMOS:saturation pMOS:linear reg. pMOS:linear reg.
Vout
|VT,p| (VDD – VT,n) VDD
0V
Figure (2): Operating Regions of CMOS Transmission Gate
VDD – Vout
Req,n =
IDS, n
VDD – Vout
Req,p = ... (4)
ISD, p
Equation (4) gives the equivalent resistance of each transistor in this configuration. The parallel equivalent of these two
resistances, Req,n and Req,p, will equal the total equivalent resistance of the CMOS TG.
Q24. Explain about the equivalent resistances of the three operating regions of the transmission gate.
Ans:
Region 1 Region 2 Region 3
nMOS:saturation nMOS:saturation nMOS:cut-off

pMOS:saturation pMOS:linear reg. pMOS:linear reg.
Vout
|VT,p| (VDD – VT,n) VDD
0V
Figure (1): Operating Regions of CMOS Transmission Gate
Figure (1) illustrates the three operating regions of CMOS Transmission gate. The equivalent resistance values for the
three operating regions of the transmission gate are as follows:
Region 1
From figure (1) it evident that in region 1 the output voltage Vout is less than the pMOS transistor threshold voltage
|VT,p |, that is, out < |VT,p|. Further, in this regions both the nMOS and pMOS transistors are in saturation. The equivalent resistance
of both the nMOS and pMOS transistor’s for this region is given as,
2 (VDD – Vout)
Req,n = ... (1)
kn (VDD – Vout – VT, n) 2
2 (VDD – Vout)
Req,p = ...(2)
k p (VDD – | VT, p |) 2
It is evident that the nMOS transistor’s source-to-substrate voltage is equal to the output voltage Vout, while the pMOS
transistor’s source-to-substrate voltage is zero. So, in our equivalent resistance calculations for the nMOS transistor, we must
consider the substrate-bias impact.

Region 2 For dynamic analysis, a CMOS pass gate that is activated
From figure (1) it evident that in region 2, the output by a logic-high control signal can be substituted by a simple
voltage Vout lies between |VT,p |and (VDD - VT,p) that is, equivalent resistance, as illustrated in Figure (3).
|VT,p| < Vout < (VDD – VT,p).
As a result, the pMOS transistor is now operating in the
linear region, while the nMOS transistor is still operating in the
saturation region. The equivalent resistance of both the nMOS + Vout
and pMOS transistor’s for this region is given as, VDD IC
2 (VDD – Vout) Cload
Req,n = ... (3)
kn (VDD – Vout – VT, n) 2
2 (VDD – Vout)
Req,p = R V
k p S2 (VDD – | VT, p |) (VDD – Vout) – (VDD – Vout) 2WW
S t=0
T X
=
2
... (4) + Vout
RS VW
k p S2 (VDD – | VT, p |) – (VDD – Vout)W VDD Req IC
T X
Region 3 Cload
From figure (1) it evident that in region 3, the output
voltage Vout > (VDD – VT,n). As a result, the nMOS transistor will
be switched off, resulting in the equivalent of an open circuit. Figure (3): For Transient Analysis, the CMOS TG is Replaced by a
while the pMOS transistor is still operating in the linear region. Resistor Equivalent
The equivalent resistance of the pMOS transistor for this region Q25. What is the advantage of implementing logic
is given as, circuits using CMOS transmission gates?
2 Implement a Two-input multiplexor circuit using
Req,p = R V … (5)
k p SS2 (VDD – | VT, p |) – (VDD – Vout)WW two CMOS TGs and explain its working.
T X
Figure (2) depicts a plot of total resistance of CMOS Ans:
transmission gate as a function of output voltage V0, which is When CMOS transmission gates are used in logic circuit
obtained by merging the equivalent resistance values determined design, the logic circuits become compact. In other words,
for the three operating regions together. Logic circuit designs need fewer transistors than normal CMOS
R equivalents. However, for TG applications, the control signal
and its complement must be accessible at the same time.
Req,p Req,n A
F = A S + BS
Req,n Req,p
S
Vout
0 (VDD – VT,n) VDD
Figure (2): CMOS Transmission Gate Equivalent Resistance Figure (1): A Two-Input Multiplexor Circuit Constructed using Two
Displayed as a Function of the Output Voltage CMOS TGs
Figure (2) illustrates how the total equivalent resistance A two-input multiplexor circuit made up of two CMOS
of the Transmission Gate (TG) continues to remain fairly transmission gates is illustrated in figure (1). The multiplexor’s
constant, that is, its value is almost completely independent of operation is relatively simple and easy to understand: When the
the output voltage, but the individual equivalent resistances of control input S is logic high, the bottom TG conducts, and the
the nMOS and pMOS transistors are substantially dependent output equals the input B. The lower TG will switch off if the
on output voltage (VO). This is a much desired attribute of the control signal is low, and the top TG will link the input A to the
CMOS TG. output node.
Q26. Explain the Implementation of the logic XOR function, using two CMOS TGs and two CMOS inverters.
Ans:
Eight transistors are needed to implement the logic XOR operation, which is as shown in figure (1). As demonstrated in
figure (2), the same logic XOR function may be accomplished utilizing only six transistors.
A
F = AB + AB
Figure (1): Eight-Transistor CMOS TG XOR Function Implementation
A F = AB + AB
Figure (2): The XOR Function in Six-Transistor CMOS TG

Every Boolean function can be implemented using TG logic circuits that use the generalized multiplexor technique. For
instance, figure (3) illustrates the implementation of a three-variable Boolean function using a TG logic circuit. From the figure it
is evident that the three input variables and their inverses are used to control the CMOS gates. Further, the three input variables
control the three inverters that aren’t shown in the figure (3). A total of 14 transistors are required for the TG implementation. One
of the most significant aspects of TG logic design is that the output node and one of the inputs must always have a conducting TG
network (low-impedance link). This ensures that the output node is never left in a high-impedance condition with its capacitive load.
B F = AB + A C + ABC
VDD A
B B
A
C
A F
B
C
A
Figure (3): Realization of a Three-Variable Boolean Function Using CMOS TG
A large increase in total area may result from the discontinuous n-well architectures of the pMOS transistors and the
diffusion contacts used in TG logic circuits when each CMOS transmission gate is implemented with a complete nMOS-pMOS
pair in the logic circuit. To decrease the silicon space used by TG circuits, the transmission gates can be configured as distinct
nMOS-pMOS pairs, with all pMOS transistors put in a single n-well, as illustrated in figure (4). However, careful consideration
must be given to the routing area necessary to connect the p-type diffusion zones to the input signals.

VDD F
B B A A
Figure (4): To Save Area all pMOS Transistors are Placed into one n-well
Q27. Explain about Complementary Pass-Transistor Logic (CPL).
Complementary Pass-transistor Logic is a circuit approach that can drastically decrease the complexities of full-CMOS
pass-gate logic circuits (CPL). The primary concept underlying Complementary Pass-transistor Logic is to perform logic opera-
tions using a completely nMOS pass-transistor network rather than a CMOS TG network. This means that every input signal must
be delivered in complimentary form (figure 1); the circuit also creates complementary outputs that may be used by succeeding
CPL stages. So the CPL circuit is composed mostly of complimentary inputs, a nMOS pass transistor logic network that generates
complementary outputs, and CMOS output inverters that restore the output signals to their original state of operation. Figure (1)
depicts the circuit schematics of a CPL NOR2 and a CPL NAND transistor.
A B B A A B B A
B B
B B
AB AB A+B A+B
CPL NAND Gate CPL NOR Gate
Figure (1): Circuit Schematics of Complementary Pass-Transistor Logic NAND and NOR Gates
The removal of pMOS transistors from the pass-gate network minimizes the parasitic capacitances related with every
node in the circuit, resulting in a faster operating speed than a full-CMOS equivalent. However, the enhancement in transient
characteristics results in a greater complexity of the process. So as to eradicate the threshold-voltage drop in CPL circuits, the
threshold voltages of the nMOS transistors in pass-gate networks must be decreased to approximately 0V using threshold-adjustment
implants. Besides, this makes the transistors more vulnerable to subthreshold conduction when they’re in off-mode and overall
noise immunity is decreased. Further, the CPL design style is very flexible. By using the same basic pass-transistor structures, a
wide range` of functions can be accomplished.
A XOR
6 (CPL)
B 4 10,12
A O
B 6
A
B 6
4 10,12
A O
B 6
Figure (1): Circuit Schematics of Complementary Pass-Transistor Logic Based XOR Gate
When it comes to transistor count, CPL circuits do not usually provide a significant benefit over regular CMOS circuits.
A total of 8 transistors are used in each of the NAND and NOR circuits depicted in figure (1). The CPL implementations of the
XOR and XNOR functions have a similar complexity (i.e., transistor count) as the standard CMOS implementations. The similar
remark can be made about the implementation of complete adders using CPL as well. Figure (2) depicts the schematic diagram of
a CPL-based XOR gate in more precision. Cross-coupled pMOS pull-up transistors are employed in this application to accelerate
the output response. The widths of transistors are specified in λ-units.

Important Questions
Q1. Draw the two input NOR gate logic circuit with depletion nMOS loads and Explain.
Q2. Explain how to calculate VOH and VOL for two input NOR gate Logic Circuits with Depletion nMOS Loads.
Q3. Draw the two input NAND gate logic circuit with depletion nMOS loads and Explain.
Q4. Explain how to calculate VOH and VOL for Two input NAND gate Logic Circuits with Depletion nMOS
Loads. Also calculate drain current when the output voltage is VOL.
Q5. Draw the two input CMOS NOR gate logic circuits and Explain its operation.
Q6. Explain how to calculate switching threshold for two input NOR gate using CMOS Logic Circuits.
Q7. Explain about Implementation of Complex Boolean functions using nMOS Logic Circuits.
Q8. Explain about Implementation of Complex Boolean functions using CMOS Logic Circuits.
Q9. Explain about problem of constructing a minimum-area layout for the complex CMOS logic gate.
Q10. Write short notes on Pseudo-nMOS gate.
Q11. What is CMOS transmission gate? Explain its operation.
Q12. Explain the DC analysis of the CMOS transmission gate.
Q13. Explain about the equivalent resistances of the three operating regions of the transmission gate.
Q14. Explain about Complementary Pass-Transistor Logic (CPL).
UNIT-5 (Sequential MOS Logic Circuits) 213
UNIT
Sequential MOS
5 Logic Circuits SI
A GROUP
Syllabus
SEQUENTIAL MOS LOGIC CIRCUITS
Introduction, behavior bistable elements, SR latch circuit, clocked latch and flip-flop circuits: clocked SR latch,
clocked JK latch, master-slave flip-flop, CMOS D-latch and Edge triggered flip-flop, Schmitt trigger circuit, basic
principles of pass transistor circuits.
Learning Objectives
C Classification of logic circuits
C Behavior of bistable elements
C Operation of CMOS SR latch
C Operation of clocked SR latch and JK latch
C Operation of master-slave flip-flop
C Operation of CMOS D-latch and edge triggered flip-flop
C Operation of Schmitt trigger
C Basic principles of pass transistor circuits.
Introduction
Sequential logic circuit is the one whose output depends on the present input as well as on the previous output. It contains
atleast one memory element to store the binary information. Some of the sequential circuits include flip-flops, registers and
counters.
Flip-flops are the memory elements that store or delay certain bits. They depend on previous input stages to retain the
information. Based on information storage and retrieval, there are several types of flip-flops. Some of them are RS, JK,
master slave JK, D, T-flip-flop. The two output signals of flip flop are complement to each other.

5.1 Introduction
Q1. What is a sequential circuit? Give its classification.
Ans:
Sequential Circuit
v The circuit which combines logic gates using storage elements (as feedback

path) to generate a specific output for a specified combination of inputs is
known as sequential circuit. I/P Combinational
O/P
circuit
v This circuit consists of input variables, logic gates, memory elements and
output variables.
v The output at any given instant of time depends not only depends on current Memory
input, but also on past output. element
v The present state and the inputs applied give the output and the next state
of the circuit. Figure (1): Block Diagram of
Figure (1) represents the block diagram of a sequential circuit. Sequential Circuit
The feedback link between the output and the input causes regenerative behaviour in sequential circuits.A basic memory
function describes how regeneration works under specific circumstances.
Regenerative circuits are classified based on their output states as follows,
v Bistable circuits: They have two stable states.
v Monostable circuits: They have one stable state.
v Astable circuits: They have two quasi-stable states.
5.2 Behaviour of Bistable Elements
Q2. Explain bistability principle. According to the bistability principle, if the inverter
Ans: Model Paper-4, Q10(b) gain in the transient region is greater than 1, then ‘A’ and ‘B’
Static memories with positive feedback forms a bistable becomes the two stable operating points and ‘C’ becomes the
circuit. A bistable circuit consists of two stable states i.e., metastable operating point.
‘0’ or ‘1’. The concept of bistability is described using the fol- The V-I characteristics of cascaded inverters is shown
lowing example.
in figure (3).
Consider that, two inverters are cascaded as shown in
figure (1). A
Vi2 = Vo1
Vi1 Vo1 = Vi2 Vo2
Vo2 = Vi1
Figure (1)
B
The V-I characteristics of each inverter is shown in
figure (2). Vi1 = Vo2
Figure (3)
Vo1
Vi2 = Vo1
From figure (3), it is observed that, the combined voltage

transfer characteristics curve have three operating points (A, B
and C).
Consider that, the cross coupled inverter pair is made to
Vi1 Vo2 operate at point ‘C’. If any variations occur at the point ‘C’, they
(a) (b) can be amplified and reconstructed in the circuit. It is shown in
Figure (2) transfer characteristic curve illustrated in figure (4).
A A
Vi2 = Vo1
Vi2 = Vo1
C C
B B
Vi1 = Vo2 Vi1 = Vo2
d d
(a) (b)
Figure (4): Metastable and Stable Operating Points
A small deviation applied at the first inverter is amplified and fed to the second inverter. The deviation is further amplified
and fed back as an input to the first inverter. This results in the moving of operating point away from ‘C’ towards any of the
operating points A (or) B as shown in figure 4(a). Thus ‘C’ is a meta stable (unstable) state.
Consider that, the inverter is made to operate at points A and B with very small loop gain (<1). Then if large deviation
occurs it reduces its size and vanishes. This phenomenon is shown in transfer characteristic curve as shown in figure 4(b).
Thus, the two cross coupled inverters acts as a bistable circuit with two stable states A, B and one metastable state ‘C’.
This circuit acts as a memory element which stores 1 or 0 based on the positions of operating points A and B.
The stored value can be changed by shifting the circuit from operating point A to B or from B to A. This can be accomplished
by making one of the operating point temporarily unstable providing high gain (>1). As trigger pulse is used to change the state
of an inverter.
Q3. Explain the operation of CMOS bistable element and its transient analysis. Model Paper-1, Q9
Ans:
The CMOS two-inverter bistable element is shown in figure (1)(a). At its unstable operating point, it has maximum loop
gain when all four transistors are saturated. The operating modes of the transistors will drastically vary if the initial operating
condition is not changed. Figure (1)(b) illustrates that the output voltages of the two inverters will finally settle at VOH and VOL .
VDD VDD
VOH
VO1
Vi2
Vo1 Vth
Vo2
Vi1 VOL
VOL t
(b) One Possibility for the Expected Time-Domain

Behaviour of the Output Voltage, if the Circuit
(a) Circuit Diagram of a CMOS Bistable Element is initially set at its Unstable Operating Point
Figure (1)
The polarity of the initial disturbance determines the direction of each output voltage divergence. Using a small-signal
analysis method, the output voltage can be observed.
Figure (2) shows a bistable circuit which operates at vo1 = vo2 = Vth, i.e., at the unstable operating point. The input (gate)
capacitance Cg of each inverter is assumed to be substantially bigger than the output (drain) capacitance Cd for our analysis.
ig1 i d1
1
vg1
id2 ig2
2
vg2
Figure (2): Small-signal Input and Output Currents of the Inverters

The small-signal drain current provided by each inverter (1 and 2) can be represented as follows. Here, each inverter’s
drain current equals the other’s gate current.
i.e.,
ig1 = id2 = gm vg2
...(1)
ig2 = id1 = gm vg1

Where, gm- small signal transconductance of inverter
q1 q2 ...(2)
vg1 = vg2 =
Cg Cg
And the small-signal gate currents of each inverter are expressed as,
dvg1 _bb
ig1 = Cg b
dt bb
` ... (3)
dvg2 bbb
ig2 = Cg b
dt b
a
Substituting equation (3) in equation(1), we get,
dvg1
gm vg2 = Cg ...(4)
dt
dvg2
gm vg1 = Cg ...(5)
dt
The differential equations (4) and (5) can be re-written interms of gate charges as,
gm Cg d 2 q1 d 2 q1 JK gm NO2
q = & 2 = KKK OOO q1
Cg 1 gm dt 2 dt C
L gP ... (6)
This equation can also be expressed in a more simplified form by using to, the transit time constant as,
d2 q 1 Cg
21 = 2 q1 with to = ... (7)
dt to gm
The time-domain solution of (7) for q1 with initial conditions q1 (0) = Cg . vg1 (0) is given by,
q1(0) – to q1' (0) – t1 q1(0) – to q1' (0) + t1
q1 (t) = e o+ e o ... (8)
2 2
Replacing the gate charge of both inverters with their output-voltage variables i.e., vg1 = vo2 and vg2 = vo1, we get,
1 1 1 1
vo2 (t) = (vo2 (0) – to v o' 2 (0) e – to + (vo2 (0) – to v o' 2 (0) e + to ... (9)
2 2
1 1 1 1
vo1(t) = (v (0) – to v o' 1(0) e – to + (vo1(0) – to v o' 1(0) e + to ... (10)
2 o1 2
For large values of t, the above equations are approximated as,
1 1
vo1(t) . (v (0) + to v o' 1(0) e + to ... (11)
2 o1
1 1
vo2 (t) . (vo2 (0) + to v o' 2 (0) e + to ... (12)
2
Both output voltages grow exponentially in magnitude over time. Both inverters’ output voltages will diverge from their
starting value of Vth to either VOH or VOL depending on the polarity of the initial minor perturbations dvo1 (0) and dvo1(0). In general,
due of the charge-conservation principle, the polarity of the output-voltage perturbation dv01 must always be the polarity of dvo2.
As a result, the two output voltages diverge in different directions. The operational point (vo1 = Vth, vo2 = Vth) is unstable, as seen
in figure (3). Small-signal models at the appropriate operating points can be used to show that the two operating points (vo1 = VOL,
vo2 = VOH) and (vo1 = VOH, vo2 = VOL) are stable.
vo2
vOH
(unstable)
vth
vOL
vo1
vOL vth vOH
Figure (3): Phase-Plane Representation of the Bistable Circuit Behaviour

The two-inverter bistable element has an interesting feature. Assume a signal travelling the loop consisting of the two
cascaded inverters numerous times while the bistable circuit settles from its unstable operating point into one of its stable operat-
ing points as shown in figure (4).
Loop 1 Loop 2 Loop n

1
A1 A2 An
Loop
et/t
2
t=0
t
T
Figure (4): Propagation of a Transient Signal in the Two-Inverter Loop during Settling
During this time, the time-domain behaviour of the output voltage v01 is approximately given as,
vo1(t) 1
= e + to ...(13)
vo1(0)
When a signal travels the loop n times in a time interval T, it is similar to the same signal propagating down a cascaded
inverter chain of 2n inverters.
The loop gain is equal to the combined voltage gain of two cascaded inverters and is expressed as, ...(14)
t
n + t0
A =e
Equation (14) describes the time-domain behaviour of the diverging process until it reaches stable points.
5.3 SR Latch Circuit

Q4. Explain the operation of an SR latch using NOR gates. Implement it with CMOS design.
The logic symbol and logic diagram of an SR latch using NOR gates is as shown in figure (1).
R
Qn
S Qn
CP
R Qn
Qn
S
(a) Logic Symbol (b) SR Latch using NOR Gates
Figure (1)

Working
The SR latch has active high inputs S, R and two complementary outputs Q and Q .
v If S = R = 0, output does not change i.e., Qn+1 = Qn. Here, the latch behaves like a cross-coupled bistable element.
v If S = 0 and R = 1, then the latch enters into reset mode. The output Qn+1 = 0. Here, the output Q = 0 and Q = 1.
v If S = 1 and R = 0, then the latch enters into set mode. The output Qn+1 = 1. Here, the output Q = 1 and Q = 0.
v If S = R = 1, then the latch outputs are undefined. This state is called indeterminate state or not allowed condition.
The truth table of SR latch using NOR gates is shown in table (1).
S R Qn + 1 Qn + 1 Operation
0 0 Qn Qn hold
1 0 1 0 set
0 1 0 1 reset
1 1 0 0 not
allowed
Table (1) : Truth Table of the NOR-based SR Latch Circuit
CMOS NOR-based SR Latch: Consider the operating modes of the four nMOS transistors, M1, M2, M3, and M4, to better
understand the operation of the CMOS SR latch circuit depicted in figure (2).
VDD VDD
Q
Q
S M1 M2 M3 M4 R
Figure (2): CMOS SR Latch using NOR gates

v If S = R = VOL, output does not change i.e., Qn+1 = Qn. The transistor either M2 or M3 will be on depending on the previous
state of the SR latch, but both trigger transistors M1 and M4 will be off.
v If S = VOH and R = VOL, then the latch enters into set mode, the parallel-connected transistors M1 and M2 will be on. So,
the output Qn+1 = VOH. Here, the output Q = 1 and Q = 0.
v If S = VOL and R = VOH, then the latch enters into reset mode. The transistors M1 and M2 will be off while M3 and M4 are
on. The output Qn+1 = 1. Here, the output Q = 0 and Q = 1.
v If S = R = VOH, then the latch outputs are undefined. This state is called indeterminate state or not allowed condition.
Table (2) summarizes the NOR-based CMOS SR latch circuit’s static operation modes and voltage levels.
VOH VOL VOH VOL M1 and M2 on, M3 and M4 off

VOL VOH VOL VOH M1 and M2 off, M3 and M4 on
VOL VOL VOH VOL M1 and M4 off, M2 on, or
VOL VOL VOL VOH M1 and M4 off, M3 on
Table (2) : Truth Table
The NOR-based CMOS SR latch circuit can also be CMOS NAND-based SR Latch
realized using two cross-coupled depletion-load nMOS NOR The realization of CMOS NAND-based SR latch using
gates as shown in figure (3). NAND2 gates is illustrated in figure (2). One of each NAND
VDD VDD gate’s inputs is used to cross-couple to the output of the other
NAND gate, while the other input is employed to permit external
Q Q triggering.
VDD VDD
S M1 M2 M3 M4 R
Q Q
Figure (3): Depletion -nMOS NOR-Based SR Latch
Q5. Explain the operation of an SR latch using NAND
gates. Implement it with CMOS design.
S R
Ans:
The logic symbol and logic diagram of an SR latch using
NAND gates is as shown in figure (1). Figure (2): CMOS SR latch using NAND2 gates
S The NAND-based SR latch can also be realized using
Qn
depletion-load nMOS as shown in figure (3).
S Qn
VDD VDD
CP
R Qn
Qn
R
(a) Logic Symbol (b) Logic Diagram Q Q
Figure (1): Depletion-nMOS NOR-Based SR Latch
Working
S R
The NAND-based SR latch has active low inputs S, R
and two complementary outputs Q and Q .
v If S = R = 0, then the latch outputs are undefined.
Figure (3): Depletion-nMOS NAND based SR latch
This state is called indeterminate state or not allowed
condition. 5.4 Clocked Latch and Flip-Flop Circuits-Clocked
v If S = 0 and R = 1, then the latch enters into set mode. SR Latch, Clocked JK Latch, Master-Slave
The output Qn+1 = 1. Here, the output Q = 1 and Q = 0. Flip-Flop
v If S = 1 and R = 0, then the latch enters into reset mode. Q6. Explain the operation of a clocked NOR based
The output Qn+1 = 0. Here, the output Q = 0 and Q = 1. SR-latch with timing diagram. Implement it with
v If S = R = 1, output does not change i.e., Qn+1 = Qn. Here, CMOS gates.
the latch behaves like a cross-coupled bistable element. Ans:
The truth table of SR latch using NAND gates is shown The gate-level logic circuit of a clocked SR latch using
in table (1). NOR gates is as shown in figure (1).
S
Q
0 0 1 1 not allowed
0 1 1 0 set CK
1 0 0 1 reset
1 1 Qn hold Q
Qn R
Table (2) : Truth Table Figure (1): Clocked SR Latch Using NOR Gates

The output of clocked SR latch changes its states with respect to the inputs on the occurrence of clock pulse.
v When the clock signal is low, the inputs does not affect the output i.e., remains in no change state.
v When the clock signal is HIGH, the following changes occur based on applied inputs.
Case (i): If S = R = 0, output does not change i.e., Qn+1 = Qn.
Case (ii): If S = 0 and R = 1, then the latch enters into reset mode. The output Qn+1 = 0.
Case (iii): If S = 1 and R = 0, then the latch enters into set mode. The output Qn+1= 1.
Case (iv): If S = R = 1, then the latch outputs are undefined. This state is called indeterminate state.
The timing diagram of a clocked NOR-based SR latch is shown in figure (2).
Figure (2): Timing Diagram

CMOS clocked NOR-based SR latch: The CMOS realization of clocked NOR-based SR latch uses AOI gates is as shown in
figure (3).
VDD VDD
CK
Q
Q
R S
CK CK
Figure (3): CMOS Clocked NOR-Based SR Latch using AOI Gates

Q7. Explain the operation of clocked NAND based SR-latch.
Ans:
The gate-level logic circuit of clocked NAND based SR latch with active low inputs is as shown in figure (1).
S
Q
CK
Q
R
Figure (1): Latch with Active Low Inputs
The output of clocked SR latch changes its states with respect to the inputs on the occurrence of clock pulse.
Working
v When the clock signal is high, the inputs does not affect the output i.e., remains in no change state.
v When the clock signal is low, the following changes occur based on applied inputs.
Case (i): If S = R = 0, output does not change i.e., Qn+1 = Qn.
Case (ii): If S = 0 and R = 1, then the flip-flop enters into reset mode. The output Qn+1 = 0.
Case (iii): If S = 1 and R = 0, then the flip-flop enters into set mode. The output Qn+1 = 1.
Case (iv): If S = R = 1, then the flip-flop outputs are undefined. This state is called indeterminate state.
The gate-level logic circuit of clocked NAND based SR latch with active high inputs and corresponding block diagram is
as shown in figure (2).
S
Q
CK
Q
R
Figure (2): Clocked NAND Based SR Latch with Active High Inputs
The operation is analogous to above stated except that clock must be HIGH for the circuit to respond to change in inputs.
Q8. What is the advantage of JK latch over SR latch. Explain the operation of clocked JK-latch.
Ans:
Advantage of JK latch over SR latch
The major advantage of using JK latch is that it operates in toggle mode (J = K = 1) which is very much important in
counting applications. Whereas, the RS latch does not operate in toggle mode since, R = S = 1 provides ambiguous output.
Clocked JK-latch
The logic symbol and circuit diagram of clocked NAND-based JK latch with active high inputs is as shown in figure (1).
Its gate-level schematic is illustrated in figure (2).
CP JK
Latch
Figure (1): JK Latch with Preset and Clear
J S Q
NAND
CK
SR
K R Q
Figure (2): Gate Level Schematic of JK-Latch

The truth table of JK latch is as shown in table.
Inputs Outputs
J K S R Qn Qn+1 State
0 0 1 1 0 0 No
0 0 1 1 1 1 change
0 1 1 1 0 0
0 1 1 0 1 0 Reset
1 0 0 1 0 1
1 0 1 1 1 1 Set
1 1 0 1 0 1
1 1 1 0 1 0 Toggle
Table (1):Truth Table

Working: The operation of JK latch is described as follows,
Case (i): For J = K = 0 the does not change i.e., Qn = Qn+1.
Case (ii): For J = 0, K =1, the latch enters into reset mode i.e., Qn+1 = 0.
Case (iii): For J = 1, K = 0, the latch enters into set mode i.e., Qn+1 = 1.
Case (iv): For J = 1, K = 1, the latch enters into toggle mode, in which output continuously shifts between logic ‘0’ and logic
‘1’ for complete clock pulse. Thus, uncertain output is obtained.
Q9. What is the disadvantage of JK latch? Draw the logic diagrams of clocked NOR based JK-latch and its
CMOS realization.
Ans:
Disadvantage of JK latch
When a clock input is applied (i..e., clk = 1) to a JK latch for inputs J = K = 1, the state of the latch toggles continuously
between 0, 1 and 1, 0. This phenomenon is called race-around condition.
v Such unstable behavior of latch is observed due to the feedback from complementary output signals to the input.
v The toggling stops only when the clock is disabled (i.e., clk = 0).
v To understand the concept of race around condition, consider a JK latch as shown in figure (1).
Qn
Qn
Figure (1)
v In the above figure, consider that the initial output for input J = K = 1 is 0 (i.e., Qn = 0).
v When a clock signal of pulse width tp is applied to latch, after a time duration of ∆t output changes to Q = 1.
v This interval of ∆t specifies the propagation delay due to the logic gates. If tp > ∆t, then the output changes again from ‘1’

to ‘0’ after another ∆t as shown in figure (2).
v This process continues till the end of the clock pulse, which results in an uncertain value at the output.

v This situation of changing output values is known as race around condition (i.e., output varies from 0 to 1 and 1 to 0).
v This condition can be over come by using master slave JK latch.
CLK tp
Dt
Qn+1
Figure (2)
Clocked NOR based JK-latch: The gate-level schematic of clocked NOR based JK-latch and its CMOS realization using
AOI gates are as shown in figure (3).
VDD VDD
CK
R
K
Q
CK
Q Q
Q K J
J
S
CK CK
(a) Logic Diagram (b) CMOS NOR Based JK Latch using AOI Gates
Figure (3)
Q10. Explain master-slave JK latch in detail. Model Paper-3, Q9
Ans: A master slave JK latch is a combination of two SR latches, with feedback connection from output to input. The first
latch is referred as master and second latch is referred as slave. In this latch, the master latch operates during positive level of
clock cycle and the slave latch operates during negative level of clock cycle.
The operation of JK latch as toggle switch is as shown in figure (2).
J=1 Q CK
JK
CK
Latch
Q Q
K=1
Figure (1): JK Latch as Toggle Switch
The logic diagram of msaster-slave JK latch using NAND gates is as shown in figure (2).
Qm
J S S Qs
NAND NAND
CK
SR Qm SR
Qs
K R R
CK
Figure (2)

Working
Case (i): When J = K = 0 and CLK = 0 (or) 1, both NAND gates of master flipflop are disabled. So the output of master remains
same at the positive clock. Hence, the output of slave remains same at the negative edge of clock and circuit is inactive. Thus,
no change in output, i.e., Qn = Qn+1.
Case (ii): When J = 0, K = 1 and CLK = 1, the master flip-flop enters into reset state, and produces outputs S = 0, R = 1. These
output are fed to the slave flip-flop. When clock signal goes low, the S and R inputs force the slave flip-flop to reset the output
because, slave flip-flop operates only during low clock signal. Therefore, the outputs are Qn+1 = 0 and Q n+1
= 1.
Case (iii): When J = 1, K = 0 and CLK = 1, the master flip-flop enters into set state and produces outputs S = 1, R = 0. But, the
output Qn+1 remains constant because the slave flip-flop is inactive during the high clock. Thus, when clock signal goes low, slave
flip-flop becomes active and set the outputs to Qn = 1 and Q n + 1 = 0.
Case (iv): When J = K = 1 and CLK = 1, the master slave flip-flop enters into toggle state. Thus, the outputs of master flip-flop
toggle between ‘0’ and ‘1’ till the completion of positive level of clock cycle. As soon as the negative level of clock cycle starts,
slave flip-flop takes the outputs of master flip-flop and produces its corresponding outputs i.e., Qn+1 = 1, Q n + 1 = 0.
The timing diagram of master slave it JK flip flop is as shown in figure (3).
CK 0 1 1 0 0 0 1 0 0 1 1 1 0 0 0 1 1
J 0 0 1 1 0 0 0 0 0 0 1 0 0 0 1 1 1 1
0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 0 0
K
0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0
Qm
Qm
1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1
0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0
Qs
Qs
1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1
Q11. The voltage waveforms shown in Figure below are applied to the nMOS JK master-slave flip-flop shown
in Figure below. With the flip-flop initially reset, show the resulting waveforms at nodes QM. (master
flip-flop output) and Qs (slave flip-flop output).
CK
K
Figure
Ans:
The output QM remains unchanged when clock input is LOW. When clock is HIGH, the truth table of nMOS JK master-slave
flip-flop is as follows,
S R QS (n+1) QM (n+1)
0 0 0/1 QM (n)
0 1 0 QM (n)
0 1 1 0
1 0 0 1
1 0 1 QM (n)
1 1 0 1
1 1 1 0
Table: Truth Table
The corresponding timing waveform is as shown in figure below.
CK
QM
QS
Figure : Timing Diagram
5.5 CMOS D-Latch and Edge-Triggered Flip-Flop

Q12. Explain the working of a basic CMOS D-latch with neat diagram.
The clocked NOR-based SR latch circuit can be modified to represent the D-latch at the gate level as shown in figure (1).
The circuit has only one input D, which is connected to the latch’s S input. The input variable D is inverted and connected to the
latch’s R input.

D
Q
D Q
CK D-Latch
CK Q
Q
(a) Logic Diagram (b) Logic Symbol

Figure (1): Gate Level Schematic of D-Latch
Operation
The output of the D-latch depends on the clock signal applied at its input.
v When clock signal is low (i.e., clock = 0) there is no change in the output.
v If clock signal is high (i.e., clock = 1), data storage takes place.
For D = 0; Reset = High; Q = 0
For D = 1; Set = High; Q = 1
This indicates that the input data appears at the output after some delay i.e., at the end of the clock pulse. Thus, it is also
referred to as delay flip-flop.
Figure (2) depicts a basic two-inverter loop with two CMOS transmission gate (TG) switches.
VDD VDD
CK
Q
D Q
CK
CK
CK
Figure (2): CMOS Implementation of D-Latch (Version 1)
The TG in the inverter loop is activated by the active-low clock input (CK).
v When CK =1, the input signal is accepted (latched) into the circuit.
v When CK= 0, the state of the inverter loop is unchanged.
The operation of CMOS D-latch circuit can be understood in figure (3) in which CMOS transmission gates are replaced
by simple switches.
D Q
CK = 1
D Q
CK = 0
Figure (3)
Figure (4) illustrates the timing diagram in valid time intervals for the input and output signals.
Figure (4): Timing Diagram of D-Latch

Figure (5) shows a different CMOS implementation of D-latch. Its basic working is similar to that of figure (2).
VDD VDD
VDD
CK CK
Q
D Q
CK CK
Figure (5): CMOS Implementation of D-Latch (Version 2)

The clock signal and its inverse drive two tristate inverters in the circuit. When the clock is high, the first tri-state inverter
acts as an input switch and store the input. Meanwhile, the second tristate inverter is in high-impedance mode,so its output Q
follows the input signal. The input buffer is idle when the clock is low, and the second tristate inverter completes the two-inverter
loop. The state of the input remains same until the next clock pulse.
Q13. Explain the working of an edge-triggered CMOS master-slave D flip-flop with neat diagram.
Ans:
The logic diagram of Master-Slave D flip-flop is shown in figure.
CK
VDD VDD VDD VDD
CK
CK Qm Qm Qs
D Qs
CK CK
CK CK
CK
CK
CK CK
Figure: CMOS Negative Edge-Triggered Master-Slave D Flip-Flop
The Master-Slave D flip-flop consists of two gated D latches cascaded together. The first latch is considered as Master
that changes its state when clock = 1. The second latch is called as slave that changes its state when clock = 0.
When clock = 1 or high, the master D-latch tracks the D input signal and Qm follows any changes in D.
The slave does not change and hence Qs remains constant.
When clock = 0 or low, the master D-latch stops following the D input signal. The slave starts responding to Qm and changes
its state accordingly. In this, the slave undergoes only one change of state for a clock cycle.

The truth table and output waveforms of master-slave D-flip flop are shown in table and figure (2) respectively.
Clk D Qn Qn
0 × × ×
1 0 0 1
1 1 1 1
Table: Truth Table of Master-Slave D-Flip-Flop
Q14. Draw the schematic circuit of a D flip-flop with positive edge triggering using NAND gates. Give its
timing diagram and explain its operation.
The circuit diagram of a positive edge triggered D flip-flop using NAND gates is illustrated in figure (1).
v If the input D = 0 when clock pulse is not applied, the flipflop will set and D = 0 is stored by the flipflop on the falling
(positive) edge of the clock pulse and Q = 0.
v If the input D = 1 when clock pulse is applied, the flipflop will set and D = 1 is stored by the flipflop on the falling (positive)
edge of the clock pulse and Q = 0 initially.
R Q
CK Q
Figure (1): Positive Edge Triggered D Flip-Flop using NAND Gates

The timing diagram of positive edge-triggered D flip-flop is illustrated in figure (2).
0 0 1 1 0 0 1 1 0 0 1 1 0 0
CK
0 1 1 1 1 0 0 1 1 1 1 0 0 0
D
0 1 1 1 1 1 1 1 1 1 1 1 1 1
R
S
1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 1 1 1 1 0 0 0 0 1 1 1 1
Q
Initially all signal values except S are 0 i.e., (S, R, CK, D) = (1, 0, 0, 0) and Q = 0. In the second phase, D and R both
become 1, while Q remains at 0. This causes gate 2’s output to switch to 0, which then sets the output of the last stage SR latch
to 1. The output of this D flip-flop is 1 when the clock signal is positive. However, as seen in the ninth phase of the waveform
diagram, the negative edge of clock has no effect on Q output.
Similarly, for high-to-low transition Schmitt trigger
5.6 Schmitt Trigger Circuit acts a CMOS inverter with PMOS inverter M2, as a pull-up
Q15. Illustrate the CMOS implementation of Schmitt network and two parallel transistors (M3 and M1), as a pull down
trigger. network. The effective transistor of this inverter configuration is
6kM3 + kM1@
Ans: Model Paper-4, Q10(a) . This shifts the switching threshold in downward
k M2
The CMOS implementation of a Schmitt trigger is shown direction which is equal to VM–.
in figure. Q16. Briefly explain the Schmitt trigger circuit.
The CMOS Schmitt trigger consists of two PMOS and Ans:

nMOS transistors connected in parallel and followed by on A Schmitt trigger circuit is a slowly varying waveform
inverter. that has fast transition times at the output. It is mainly used to
convert a noisy or a slow varying input waveform into a perfect
The switching threshold, VM of CMOS inverter depends
digital output signal.
SRS kn WVW
on the effective transistor ratio SS WW of PMOS and NMOS The schematic symbol of a Schmitt trigger is shown in
S kp W
T X figure (1).
transistors. The ratio is configured into the Schmitt trigger
circuit using feedback to achieve desired switching threshold
and hysteresis based on the transition path. in out
VDD
Figure (1): Schematic Symbol of Schmitt Trigger

The V-I characteristic of a Schmitt trigger circuit is shown
M2 M4 in figure (2).
Vin X Vout
M1 M3
Figure: CMOS based Schmitt Trigger

Figure (2): V-I Characteristics of Schmitt Trigger
For low-to-high transition of input, i.e., if Vin = 0, the
output Vout also equals to ‘0’. As Vout = 0, the feedback connected From figure (2), the threshold voltage from low to high
from Vout to PMOS transistor M3 and NMOS transistor M4 to transition is represented by VM+ and high to low transition is
turn ‘ON’ and M3 to turn OFF. At this instance, Schmitt trigger represented by VM–. The difference of the two threshold voltage
acts a CMOS inverter with two parallel PMOS transistors (M2 is called hysteresis voltage.
and M4) as a pull-up network and NMOS transistor (M1) as pull Q17. Give step-by step analysis of a CMOS Schmitt trig-
down network. ger with required assumptions. Assume VDD = 5V,
2fF = – 0.6V.
The effective transistor ratio of this inverter configuration
Ans:
k M1
is . This ratio shifts the switching threshold in the The Schmitt trigger has a voltage transfer characteristic
^ k M2 + k M4 h
upward direction which is equal to Vm+. similar to that of an inverter, but with two separate logic
threshold levels for increasing and decreasing input signals.
If Vin = 1, the feedback loop makes M4 to turn ‘OFF’ and The circuit can be used to detect low-to-high and high-to-low
M3 to turn ‘ON’. This transistor ‘M3’ enhances the transition and switching events in noisy situations because of this unique
helps to obtain a clear digital output signal with steep slopes. characteristic.

A CMOS Schmitt trigger’s circuit diagram and typical properties of its voltage transfer characteristic (VTC) are depicted
in figure shown below.
VDD
M1
M3 Vout
Vy
M2
Vin Vx Vout
M4 VDD
Vz
M6
M5
Vin
Vth– Vth+
Figure: Schmitt Trigger

Consider a positive input sweep, i.e., assuming that the input sweep, i.e., assuming that the input voltage is increasing from
0 to VDD.
(i) At Vin = 0 V:
M1 and M2 are turned on,
VS = Vy = VDD = 5 V
At the same time, M4 and M5 are turned off. M3 is off; M6 is on and operates in the saturation region. The threshold
voltage of M6 with 2fF = – 0.6 V is given by,
Vz = VDD – VT,6 = 3.5 V
(ii) At Vin = VT0,n = 1.0 V:
M5 starts to turn on, M4 is still off.
Vx = 5 V
(iii) At Vin = 2.0 V:
Assume M4 is off, while both M5 and M6 operate in the saturation region.
1 JW N 1 JW N
k' KK OO (Vin – VT0,n)2 = k' KK OO (VDD – Vz – VT,6)2
2 L L P5 2 L L P6
(2 – 1)2 = 3(5 – Vz – [1 + 0.4 ( 0.6 + Vz – 0.6)]) 2
Solving this equation for Vz , we get,
Vz = 2.976 V
Since, M4 is indeed turned off,
VGS,4 = 2 – 2.976 = – 0.976 < VT0,n = 1
(iv) At Vin = 3.5 V:
Vi continues to decrease. Assuming M5 in linear region and M6 in saturation, take the current equation as follows,
1 JW N 1 JW N
k' KK OO [2(Vin – VT0,n) Vz – Vz2] = k' KK OO (VDD – Vz – VT,6)2
2 L L P5 2 L L P6
[2(3.5 –1.0)Vz – Vz 2] = 3(5 – Vz – [ 1 + 0.4 ( 0.6 + Vz – 0.6)]) 2
Solving this equation for Vz , we get, Vz = 2.2 V, Then the gate-to source voltage of M4 is obtained as,
VGS,4 = 3.5 – 2.2 = 1.3 > VT0,n = 1
Here, M4 is already on. Thus, the analysis above, which is based on the assumption that M4 is not conducting, can no
longer be valid. At this input voltage, node x is being pulled down toward “0”. Hence, the upper logic threshold voltage
Vth+ is approximately equal to 3.5 V.
Next, consider a negative input sweep, i.e., assume that the input voltage is decreasing from VDD to 0.
At Vin = 5.0 V:
(i)
M4 and M5 are on, so that the output voltage is Vx = 0 V. The pMOS transistors M1 and M2 are off, and M3 is in saturation,
thus,
1 JW N
k' KK OO (0 – Vy – VT,3)2 = 0
2 L L P3
Vy = –VT,3 = –[VT0,p – 0.4 ( 0.6 + VDD –Vy – 0.6)]
Vy =1.5 [V]
(ii) At Vin = 4.0 V:
M4 is at the edge of turning on, M2 is off, and M3 is in saturation. The output voltage is still unchanged.
(iii) At Vin = 3.0 V:
M1 is on and in saturation region. M3 is also in saturation, thus,
1 JW N 1 JW N
k' KK OO (Vin – VDD – VT0,p )2 = k' KK OO (0 – Vy – VT,3)2
2 L L P1 2 L L P3
[3 – 5 – (–1)]2 = 3 (0 – Vy – [–1 – 0.4 ( 0.6 + 5 – Vy – 0.6)]) 2
On simplification, we get,
Vin = 2.02 V
The gate-to-source voltage of M2 is obtained as,
VGS,2 = 3.0 – 2.02 = 0.98 > VT0,p = –1
which indicates that M2 is still turned off at this point.
(iv) At Vin = 1.5 V:
If M2 is still off, M1 is in the linear region, and M3 is in the saturation region:
1 JW N
k' KK OO (2(Vin – VDD – VT0,p )(Vy – VDD) – (Vy – VDD)2)
2 L L P1
1 JK W NO
k' K O (0 – Vy – VT0,3 )2
2 L L P3
2(1.5 – 5 + 1)(Vy – 5) – (Vy – 5)2
= 3(– Vy – [–1 – 0.4 ( 0.6 + 5 – Vy – 0.6)]) 2
Solving this quadratic equation yields
Vy = 2.79 V
It can be seen that at this point, the pMOS transistor M2 is already turned on. Hence, the output voltage is being pulled up
to VDD. It can be concluded that the lower logic threshold voltage Vth– is approximately equal to 1.5 V.
Q18. Consider the monostable multivibrator circuit drawn in figure below. Calculate the output pulse width.
VT(dep) = –2V
VT(enh) = 1 V
k' =20 µA/V2
y = 0.
5V
2/4 2/16 2/4
1nF Vout
Vin 4/2 4/2 4/2
Figure
Model Paper-1, Q10(b)

Ans:
For the given monostable multivibrator,
The output pulse width tpw can be expressed
C.DV
tpw = ...(1)
Icap
Where,
DV = VTH – VOL
When Vout is high, the current through the capacitor can be calculated by
1 2 1 2 mA
Icap = k _VGS – VT, dep i = . . 20 2 (0 + 2) 2 = 5mA
2 2 16 V
VOL is found when the inverter driver operates in linear region while the load operates in saturation region. Thus,
4 JK V NO k' 2
k' . . KK5 – 1 – OL OO .VOL = . . (0 + 2) 2
5 L 2 P 2 4
For VTH, any of VIL, VIH, and VT (enh) are valid assumptions, here we use VIL
The output voltage of the circuit is, Vout = VOL = 0.
Neglecting body effect, we have
k 2 k
driver _Vin –VT, ehni = load (2 (0 – VT, dep) (VDD – Vout) – (VDD – Vout) 2) ...(2)
2 2
Differentiate both sides of the above equation with respects to Vin and using the condition for VIL, i.e.,
dVout
= –1
dVin V – V
in IL
We obtain,
kdriver (Vin – VT,enh) = kload [VT, dep – (VDD – Vout)]
VDD – Vout = VT, dep – kR (Vin – VT,enh)
Substituting the above equation into equation (2), VIL can be evaluated as,
VT, dep
VIL = VT,enh +
kR (1 + kR)
2
VIL = 1 + = 1.45 V
4 (1 + 4)
1×10 –9 . (1.45 – 0.13)
& tpw = = 0.26 ms
5×10 –6
\ tpw = 0.26 ms
Q19. Shown in figure is an nMOS Schmitt trigger. Draw the voltage transfer characteristic. Include values
for all important points on the graph. Use the parameters in Problem 8.4 and A = 0. W/L ratios for the
transistors are given below :
M1 M2 M3 M4
W/L 1 0.5 10 1
5V
M4
Vout
Vin M3
M1
M2
Figure
Ans:
The nMOS Schmitt trigger VTC curve goes from high to low in the forward direction when the input of M3 is VIL, and
goes from low to high in the reverse direction when the input of M3 is Vin . So, these two points for the given circuit configuration
are to be known.
VIL of M3 and M4 Depletion Load Inverter
When Vin = VIL, M3 in saturation and M4 in linear region,
k k
M3 (Vin – VTo) 2 = M4 (2 (0 – VT, 4) (VDD – Vout) – (VDD – Vout) 2) ...(1)
2 2
dVout
Since, = –1
dVin Vin = VIL
k M4
VIL = VT,0 + [V – VDD – VT, 4] ...(2)
kM3 out
Also,
RS 1 VW
VIL = VT,0 – VT,4 SSS k (1 + k ) WWW
S R R W
T X
Thus,
RS kR WW V
S
Vout = VDD + VT,4 SS1 – W
S 1 + kR WW
T X
Where,
k
kR = M3 = 10
k M4
RS 10 VWW
Vout = 5 + (–2) SSS1– = 4.91 V
1 + 10 WW
T X
RS VW
1
VIL = 1 – (–2) SS WW = 1.19 V
S 10 (1 + 10) W
T X
Vin of M1
Since ID, M1 = ID, M2, both M1 and M2 operates in linear region.
k k
M2 _2 _VGS2 – VT0i VDS2 –VDS22i = M1 _2 _VGS1 – VT0i VDS1–VDS12i
2 2
1 2
^2 ]4.91 – 1g 1.19 –1.19 2h = _2 ]5 –1.19 – 1g (Vin –1.19) – (Vin –1.19) 2i
2 2
Vin2 = 8Vin + 12.04 = 0
V+ = Vin = 2.01V
Vin of Depletion Load Inverter (M3 and M4)
M3 is in linear and M4 operates in saturation regions. Following the same steps in calculating VIL. The two equations to
solve VIH and Vout are,
k R V k R V2
M3 SS2 _VIH – VT0i Vout –Vout2WW = M4 SS0 – VT, 4WW ...(3)
2 T X 2 T X
VIH = VT, 0 + 2Vout ...(4)
2VT, 4 4
VIH = VT, 0 – =1+ = 1.73 V
3k R 30
VT, 4
Vout = – = 0.37 V
3k R
Since VG2 = Vout = 0.37 V < 1V, M2 i off, M1 is also off, thus
V– = VIH = 1.73 V

VOL for the VTC Curve Q21. Explain the logic 1 transfer in a pass transistor
circuit.
When Vin = 5 V for the nMOS trigger, Vout = VOL, M1 and
M2 are off, M3 is linear region and M4 is saturated. Ans: Model Paper-1, Q10(a)
kM3 RS k Figure (1) depicts the basic building block of nMOS dynamic
2V 2
S2 _ 4 – VT0i VOL – VOL WW = M4 _0 – VT, 4i logic circuit. It has an nMOS pass transistor driving the gate of
2 T X 2
another nMOS transistor. Based on the input signal Vin, the pass
VOL = 0.067 V
transistor MP charges up or charges down the parasitic capacitance
VTC Curve Cx. When the clock signal is active (CK = 1). the capacitor either
charges (logic 1 transfer) or discharges (logic 0 transfer).
The VTC curve is illustrated in figure below.
Vout (V)
5 MP Vx
Vin
Cx
CK
0.067 Figure (1)

1.73 2.01 Vin (V) The equivalent circuit for the logic ‘1’ transfer event of
Figure a pass transistor circuit is as shown in figure (2).
MP Vx
5.7 Basic Principles of Pass Transistor Circuits Vin = VOH
ID
Q20. Mention the basic principle of a pass transistor Cx
circuit. CK
Ans:
Figure (2)
Figure depicts the basic building block of nMOS dynamic
Assume Vx (t = 0) = 0 V for the soft node voltage initially.
logic circuit. It has an NMOS pass transistor driving the gate
The input terminal is set to logic “1” (Vin, = VOH = VDD). At
of another nMOS transistor. Based on the input signal Vin, the
t = 0, the pass transistor’s clock signal changes from 0 to VDD.
pass transistor MP charges up or charges down the parasitic
Since VDS = VGS, the pass transistor MP conducts as soon as the
capacitance Cx. When the clock signal is active (CK = 1). the
clock signal is activated in saturated region as VDS > VGS – VT,n.
capacitor either charges (logic 1 transfer) or discharges (logic
0 transfer). Depending on the voltage Vin, the output of the The transistor MP operating in the saturation region starts
depletion-load nMOS inverter is logic low or high. to charge up the capacitor Cx. It is given by,
dV k
Cx x = n (VDD – Vx – VT,n)2 ... (1)
dt 2
In logic 1 transfer, the pass transistor’s threshold voltage
MP Vx is affected by substrate bias and hence depends on the voltage
Vin
level Vx. To simplify the analysis, neglect the substrate bias
Cx
effect. Integrating equation (1), we get,
CK t 2Cx Vx dVx
#0
dt = #
kn 0 (VDD – Vx –VT, n) 2
Figure : nMOS Dynamic Logic Circuit
2C xJK 1 NO Vs
= KK O ... (2)
Only the pass transistor MP offers a current route to the kn (VDD –Vx – VT, n O
L P0
soft node X. When the clock signal is off (CK = 0), the pass R J NO JK NOVW
2Cx SSK 1 1
transistor stops conducting and the charge stored in the parasitic t = SSKK (V –V – V OO – KK (V – V OOWWW ... (3)
kn S DD x T, n W
TL P L DD T, n PX
capacitor Cx determines the inverter’s output level.
Using these equations, Vx(t) is obtained as,
JK k (V –V ) NO
KK n DD T, n OO t
K 2C x O
Vx (t) = (VDD –VT, n) L J P ... (4)
KK kn (VDD –VT, n) NOO
1 + KK OO t
2C x
L P
Using equation (4), the time variation of the node voltage Vx is plotted as shown in figure (3). From 0 V to large t,
the voltage increases, but not beyond Vmax = (VDD – VT, n). When Vx = Vmax, the pass transistor’s gate-to-source voltage equals
the threshold voltage. As a result, during a logic “1” transfer, the voltage at node X can never reach VDD.
The substrate bias effect for MP can be used to find the real maximum achievable voltage Vmax at node X as,
Vmax = Vx t " 3 = VDD – VT, n
Vmax = VDD – VT0, n – g _ 2f F + Vmax – | 2f F i ... (5)
Vx
Vmax = VDD– VT,n
Vmax
t
0
Figure (3)
Thus, the voltage Vx at node X after a logic “1” transfer can be much lower than VDD. Also, using the zero-bias threshold
voltage VT, 0 will reduce the rising time of the voltage Vx. The real charge-up time will be greater than obtained in equation (3)
because the substrate bias effect reduces the drain current of the nMOS transistor.
Q22. Explain the impact of node voltage Vx during logic 1 transfer in a pass transistor circuit.
Ans:
In a pass transistor circuit, during logic 1 transfer the node voltage Vx has an upper limit of Vmax = (VDD – VT,n) which
impacts the circuit design. For instance, consider the following two cases.
1. Case when a logic “1” at the input node (Vin = VDD) is transferred via a cascaded pass transistor chain as shown in figure (1).
(VDD – VT,n1) (VDD – VT,n2) (VDD – VT,n3)
VDD M1 M2 M3 M4
Vmax4 = VDD – VT,n4
V1 V2 V3
VDD VDD VDD VDD
Figure (1)
With VDS1 > VGS1 – VT, n1, M1 functions in saturation. As a result, the voltage at node 1 cannot exceed the limit,
Vmax1 = VDD – VT, n1. The second pass transistor M2 functions at the saturation boundary, assuming the pass transistors in
this circuit are similar. Then Vmax2 = VDD – VT, n1 will be the voltage at node 2. The node voltage becomes one threshold
voltage lower than VDD independent of the number of pass transistors in the chain. Also, regardless of the initial voltages,
the steady-state internal node voltages are always one threshold value below VDD .
2. Case when each pass transistor’s output drives the gate of another pass transistor, as shown in figure (2).
M3
VDD +Vmax3 = VDD – VT,n1– VT,n2– VT,n3
M2
VDD +Vmax2 = VDD – VT,n1– VT,n2
VDD M1
+Vmax1 = VDD – VT,n
VDD
Figure (2)
The output of the first pass transistor M1 can approach the limit Vmax1 = VDD – VT, n1 in this case. This voltage is used to drive
the second pass transistor’s gate, which operates in the saturation area. Its gate-to-source voltage cannot exceed VT, n2 therefore
Vmax2 = VDD – VT, n1 – VT, n2 is the upper limit for V2. In this case, a significant voltage drop occurs at every stage.
The voltage drop at each stage can be estimated by considering their respective equivalent substrate bias effect as,
VT, n1 = VT0, n – g ` 2f F + Vmax1 – | 2f F |j ... (1)
VT, n2 = VT0, n – g ` 2f F + Vmax2 + | 2f F |j ... (2)

h
Q23. Explain the logic 0 transfer in a pass transistor circuit. Model Paper-2, Q10(a)
Ans: The equivalent circuit for the logic “0” transfer event of a pass transistor circuit is as shown in figure (1). The depletion
load nMOS inverter has no effect on this event.
MP Vx
Vin = 0
ID
Cx
CK
Figure (1)
Assume that the soft node voltage Vx initially equals a logic “1” level, i.e. Vx (t = 0) = Vmax = (VDD – VT, n). The input terminal
is given a logic “0” level (Vin = 0V). At t = 0, the pass transistor’s clock signal moves from 0 to VDD. When the clock signal is
active, thhe drain current flows in opposite direction as when the pass transistor is charged up (logic “1” transfer). That is, the
intermediate node X now corresponds to the MP drain terminal, and the input node to its source terminal. Taking VDS = Vmax and
VGS = VDD, the pass transistor functions in the linear region throughout this cycle since VDS < VGS – VT, n.
The linear pass transistor MP discharges the parasitic capacitor Cx, as,
dV k
–Cx x = n `2 (VDD – VT, n) Vx – V x2j ... (1)
dt 2
2Cx dVx
dt = . ... (2)
kn 2 (VDD – VT, n) Vx – V x2
The nMOS pass transistor’s source voltage if 0 V during this event, hence there is no substrate bias impact for MP
(VT, n =VT0, n). Integrating equation (2) on both sides, we get
JK 1 1 NO
t 2Cx Vx KK O
# dt = – # KK 2 (VDD – VT, n) 2 (VDD – VT, n) OO dV ... (3)
0 kn VDD – VT, n K + OO x
K 2 (VDD – VT, n) – Vx Vx O
L P
RS J 2 (V – V ) – V NVW Vx
Cx SS KK DD T, n xOOOWW
t= ln K ... (4)
kn (VDD – VT, n) SS K Vx OWW
T L PX VDD – VT, n
The fall-time expression for the node voltage Vx can be obtained as,
Cx JK 2 (V – V ) – V NO
DD T, n xO
t= ln KKK OO ... (5)
kn (VDD – VT, n) Vx
L P
Figure (2) shows the fluctuation of the node voltage Vx as a function of time. The voltage lowers from Vmax to 0 V. Unlike
during charge-up, the applied input voltage level (logic 0) can be passed to the soft node unchanged.
Vx
Vmax = VDD– VT,n
Vmax
0 t
Figure (2)
The fall time of the soft-node voltage Vx is the difference between t10% and t90% which are times at 0.9 Vmax and 0.1 Vmax
respectively, i.e.,
tfall = t10% – t90% ... (6)
The times t10% and t90% are determined from equation (5) as,
Cx JK (2 – 0.9) (V – V ) NO
ln KK
DD T, n O
t90% = O
kn (VDD – VT, n) K 0.9 (VDD – VT, n) O
L P
Cx JK 1.1 NO
t90% = ln K O ... (7)
kn (VDD – VT, n) KL 0.9 OP
Cx J 1.9 N
t10% = ln KKK OOO ... (8)
kn (VDD – VT, n) L 0.1 P
Substituting equations (7) and (8) in equation (6), we get,
Cx
tfall = [ln (19) – ln (1.22)]
kn (VDD – VT, n)
Cx
tfall = 2.74 ... (9)
kn (VDD – VT, n)
Q24. Explain charge storage charge leakage at the soft node X during the inactive clock cycle in an nMOS
pass transistor.
In an nMOS pass transistor, when clock is LOW, the correct logic level at the soft can be preserved by maintaining sufficient
charge in capacitor Cx despite the leakage currents. Consider the situation during the inactive clock phase as shown in figure (1).
MP Vx
Vin= 0
Ileakage Igate = 0
Cx
CK
Figure (1)
Assume that during the active clock phase, a logic-high voltage level has been passed to the soft node. Now, both Vin and
CLK = 0. The leakage currents connected with the pass transistor will gradually drain the stored charge in C. For the most part,
the gate current of the inverter driver transistor is insignificant.
An nMOS pass transistor with lumped node capacitance Cx is shown in simplified cross-section in figure (2).
VCK = low
Ileakage
Vin = low Vx
Cx
n+ n+
Isubthreshold
p-type Si
Ireverse
Figure (2)

The subthreshold channel current and the reverse dQ j (Vx) dVx dV
conduction current at the drain-substrate junction make up the Ileakage = + Cin x ... (3)
dVx dt
bulk of the leakage current that drains the soft-node capacitance
over time i.e., Where,
Ileakage = Isubthreshold (MP) + Ireverse(MP) ... (1) dQ j (Vx) A.C j0 qe si N A
= C j (Vx) = = A. ... (4)
The equivalent circuit to analyze the charge leakage dVx V 2 (f0 + Vx)
1+ x
process is illustrated in figure (3). f0
The actual charge leakage time from the soft node’s
Ileakage Vx
charge can be estimated by solving equation (3) considering the
voltage-dependent capacitance components and the nonlinear
Cj Cin leakage currents. For instance, the worst-case leakage behaviour
Isubthreshold Ireverse can be estimated as follows.
The minimum combined soft node capacitance is given
by,
Drain-Substrate PN-Junction Cx.min = Cgb + Cpoly + Cmetal + Cdb.min ... (5)
Figure (3) The worst-cast holding time (thold) is defined as the
The soft-node capacitance Cx is a function of the reverse shortest time it takes for the soft-node voltage to drop from its
biased drain substrate junction as well as the soft node voltage initial logic-high value to the logic threshold voltage due to
Vx . The components of Cx , due to oxide-related parasitic are
leakage. It is expressed as,
considered constants and this quantity is represented by Cin.
DQcritical. min
The total charge is soft-node capacitance is expressed thold = ... (6)
Ileakage. max
as sum of two components as,
Q = Qj(Vx) + Qin where Qin = Cin . Vx Where,
Cin = Cgb + Cpoly + Cmetal ... (2) KJ V ON
DQcritical.min = Cx.min KKVmax – DD OO ... (7)
The total leakage current in terms of soft node charge Q L 2 P
is expressed as, The logic state being driven by this soft-node will lose its
dQ dQ j (Vx) dQin previously held state once the voltage on the soft-node crosses
Ileakage = = +
dt dt dt the logic threshold.
Q25. Consider the soft-node structure shown on the next page, which consists of the drain (or source,
depending on current direction) terminal of the pass transistor, connected to the polysilicon gate of
an nMOS driver transistor via a metal interconnect. The power supply voltage used in this circuit is
VDD = 5V, and that the soft node has initially been charged up to its maximum voltage.
MPass
M1
Vx
CK
Soft Node
3 6 5 6
1 2
4 5 M1 2
Mpass
2 1
1
4
3
CK Diffusion Metal Polysilicon
Figure
All dimensions are given in micrometers. The Then, the minimum value of the drain junction
critical material parameters to be used in this capacitance is calculated as,
problem are listed below. Cbottom Csidewall
Cdb,min = +
V V
VT0 = 0.8 V 1 + x.max 1 + x.max
f0 f0sw
g = 0.4 V1/2
4.56 f F 6.0 f F
= + = 4.71 f F
| 2fF | = 0.6 V 3.68 3.68
1+ 1+
0.88 0.95
Cox = 0.065 f F/mm2
C'metal = 0.036 f F/mm2 The minimum value of the total soft-node capacitance
is expressed as,
C'poly = 0.55 f F/mm2
Cx,min = Cgb + Cmetal + Cpoly + Cdb,min
Cj0 = 0.096 f F/mm2
= 0.52 f F + 0.90 f F + 2.42 f F + 4.71 f F
Cj0sw = 0.2 f F/mm
Calculate the work-case holding time. = 8.55 f F
Ans: The amount of the critical charge drop in the soft node,
which will eventually cause a change of logic state, is
The oxide-related (constant) parasitic capacitance
KJ V ON
components ashciated with the soft node are given by, DQcritical = Cx.min $ KKVx, max – DD OO
L 2 P
Cgb = Cox⋅W ⋅ Lmask = 8.55 f F $ (3.68 V – 2.5 V)
= 0.065 f F/mm2 ⋅ (4 mm × 2 mm) = 10.09 f C
= 0.52 f F Assuming that the logic threshold voltage of the next
Cmetal = 0.036 f F/mm ⋅ (5 mm × 5 mm)
2
gate is (VDD/2). The maximum leakage current responsible for
= 0.90 f F charge depletion is given from the MOS characteristics and the
junction diode characteristics as,
Cpoly = 0.055 f F/mm2 ⋅ (36 mm2 × 8 mm2)
Ileakage = Isubthreshold + Ireverse = 0.85 pA
= 2.42 f F
The worst-case (minimum) hold time for the soft node
Next determine the parasitic junction capacitance
using the expression,
associated with the drain-substrate pn-junction of the pass
transistor. Using the zero-bias unit capacitance values given DQcritical 10.09 f C
thold, min = =
here, we get, Ileakage.max 0.85 pA
Cdb,max = Cbottom Csidewall = 11.87 ms

= Abottom ⋅ Cj0 + Psidewall ⋅ Cj0sw ` thold,min = 11.87 ms
= (36 mm2 + 12 mm2) ⋅ 0.095 f F/mm2 + 30 mm $
0.2 f F/mm
= 4.56 f F + 6.0 f F
= 10.56 f F
The minimum value of the drain junction capacitance
is achieved when the junction is biased (in reverse) with its
maximum possible voltage, Vmax.
Vmax = VDD – VT0, n – g ( 2 | f F |+ Vmax – 2 | f F |)
Vmax = 5.0 – 0.8 – 0.4 ( 0.6 + Vmax – 0.6)
Vmax = 3.68 V

Important Questions
Q1. Explain bistability principle.
Q2. Explain the operation of CMOS bistable element and its transient analysis.
Q3. Explain the operation of an SR latch using NOR gates. Implement it with CMOS design.
Q4. What is the advantage of JK latch over SR latch. Explain the operation of clocked JK-latch.
Q5. Explain master-slave JK latch in detail.
Q6. Explain the working of an edge-triggered CMOS master-slave D flip-flop with neat diagram.
Q7. Mention the basic principle of a pass transistor circuit.
Q8. Explain the logic 1 transfer in a pass transistor circuit.
Q9. Explain the logic 0 transfer in a pass transistor circuit.
Q10. Explain charge storage charge leakage at the soft node X during the inactive clock cycle in an nMOS
pass transistor.

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B.Tech : III-Year II-Sem

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Syllabus as per R20 Curriculum

Model Paper-1 MP.1 - MP.2

Model Paper-2 MP.3 - MP.4

Model Paper-3 MP.5 - MP.6

Model Paper-4 MP.7 - MP.8

UNIT-WISE QUESTIONS WITH SOLUTIONS

Unit No. Unit Name

UNIT - I HARDWARE DESCRIPTION LANGUAGES Q1 - Q51 1 - 48

1.1.1 Introduction to VHDL Q1 - Q3 2

1.1.2 Entity Declaration, Architecture, Configu-ration

1.1.3 Data-Flow, Behavioral and Structural Style of

1.1.6 VHDL Libraries Q22 - Q32 19

1.2 Verilog HDL 28

1.2.1 Introduction to Verilog HDL, Module Statement,

1.2.2 Data Types, Data Operators Q43 - Q45 37

1.2.3 If-else Statement, Case-end Case Statement,

FREQUENTLY ASKED & IMPORTANT QUESTIONS 47

UNIT - II COMBINATIONAL LOGIC DESIGN Q1 - Q43 49 - 96

2.2 Multiplexers and Demultiplexers and their Use in

2.3 ALU Q22 - Q24 68

2.4 Digital Comparators Q25 - Q31 73

2.5 Parity Generators Q32 - Q36 81

2.6 Code Converters and Parity Encoders Q37 - Q43 88

FREQUENTLY ASKED & IMPORTANT QUESTIONS 95

UNIT - III SEQUENTIAL LOGIC DESIGN Q1 - Q84 97 - 180

3.1 Registers, Applications of Shift Registers Q1 - Q25 98

3.2 Ripple of Aysnchronous Counters, Synchronous Counters Q26 - Q49 121

3.3 Synchronous and Aynschronous Sequential Design Q50 - Q82 146

3.3 Hazards in Sequential Circuits Q83 - Q84 176

FREQUENTLY ASKED & IMPORTANT QUESTIONS 179

4.1 Introduction, MOS Logic Circuits with deplection NMOS

4.2 Two Input NAND Gate, Generalized NAND Structure with

4.4 Complex Logic Circuits, Complex CMOS Logic Gates,

4.5 CMOS Transmission Gates (Pass Gates), Complementary

FREQUENTLY ASKED & IMPORTANT QUESTIONS 212

UNIT - V SEQUENTIAL MOS LOGIC CIRCUITS Q1 - Q25 213 - 240

5.1 Introduction Q1 214

5.2 Behaviour of Bistable Elements Q2 - Q3 214

5.3 SR Latch Circuit Q4 - Q5 217

5.4 Clocked Latch and Flip-Flop Circuits-Clocked SR Latch,

5.5 CMOS D-Latch and Edge-Triggered Flip-Flop Q12 - Q14 225

5.6 Schmitt Trigger Circuit Q15 - Q19 229

5.7 Basic Principles of Pass Transistor Circuits Q20 - Q25 234

IMPORTANT QUESTIONS 240

S.No. Unit Name Description

SPECTRUM ALL-IN-ONE JOURNAL FOR ENGINEERING STUDENTS

SPECTRUM ALL-IN-ONE JOURNAL FOR ENGINEERING STUDENTS

12. ________ is a pictorial representation of the behavior of a sequential circuit. [ ]

(a) State table

(b) State diagram

(c) State assignment

(d) Flow table

13. _______ is the next portion of state table. [ ]

(b) Flow table

(d) State diagram

(a) Library support

(b) Timing control