Andreic Master

Medical Implant NFC Embedded System
Andrei Costescu
Thesis submitted for the degree of

Master in Nanoelectronics
60 credits
Department of Informatics
Faculty of mathematics and natural sciences
UNIVERSITY OF OSLO
Spring 2019
Andrei Costescu
© 2019 Andrei Costescu
http://www.duo.uio.no/
Printed: Reprosentralen, University of Oslo

Abstract
This work is part of the SUPRE (SUbcutaneous PREssure sensor system) [1] research
project with the goal of developing health services for patients with dysfunctional
urinary bladders. The NANO group at UiO has previously designed and implemented
an ASIC SoC (System-on-Chip) using NFC for a blood glucose sensor, while the
Polytechnique Montreal has developed an embedded system based on MICS (Medical
Implant Communication Service) for a bladder pressure sensor.
The system in this work is an alternative to the ASIC design, aiming to achieve
similar results using an embedded system. The goal is to achieve a more flexible system
with shorter redesign times at the cost of a larger form factor with higher power draw.
The design is based around a Xilinx FPGA with an integrated ADC, further increasing
flexibility at the cost of size and power.
The functionality is implemented primarily using finite state machines, the code
was written in VHDL. The goal is to be able to communicate with an NFC tag through
SPI and use its on-board memory to temporarily store the pressure sensor readings.
The system is idle until a request is initiated externally, for example by an NFC capable
mobile phone, after which the analog input is sampled and written back to the tag.
A prototype system has been implemented with the AMS 3955 NFC tag and a
Basys3 FPGA development board. A custom PCB is the next step for an embedded
system, a proposal of which is included in this thesis.
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Contents
I Introduction 1
1 Goals of this thesis 3
2 Background 5
2.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Previous work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3 Fundamental Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3.1 NFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3.2 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3.3 Android Application . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3.4 FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3.5 XADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3.6 Vivado . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3.7 Basys3 development platform . . . . . . . . . . . . . . . . . . . . . 9
2.4 Usage illustration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
II The project 11
3 Planning 13
3.1 Microcontroller Based Design . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1.1 All-in-One NFC Tag . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1.2 Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1.3 Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1.4 NFC Tag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1.5 Component summary . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1.6 AS3955 Demo Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1.7 PIC Reprogramming . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2 FPGA Based Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4 Digital design 19
4.1 AS3955 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1.1 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1.2 Data structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1.3 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.1.4 Interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.2 System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.2.1 Decision diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.3 SPI module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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4.3.1 Module overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.3.2 FSM diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.3.3 SCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.3.4 Internal setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.3.5 Command decoding . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.3.6 Sending and receiving data . . . . . . . . . . . . . . . . . . . . . . 30
4.4 ADC module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.4.1 Module overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.4.2 FSM diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.4.3 XADC Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.4.4 Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.5 Control module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.5.1 Module overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.5.2 FSM diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.5.3 Interrupt and its registers . . . . . . . . . . . . . . . . . . . . . . . 36
4.5.4 Reading EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.5.5 Sample and write . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.5.6 Overall timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5 PCB 39
5.1 Why a custom PCB? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.2 Proposal limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.3 FPGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.4 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.5 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.6 Digital IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.7 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.8 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.9 Bill-Of-Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
III Results 55
6 Simulation 57
6.1 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.1.1 Register R/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.1.2 EEPROM R/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.2 XADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.3 System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.3.1 Reading registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6.3.2 Reading ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.3.3 ADC sample . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.3.4 ROM write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.3.5 ROM clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
7 Measurements 69
7.1 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
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IV Conclusion 71
8 Discussion 73
8.1 Areas of improvement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
8.1.1 FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
8.1.2 PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
8.2 Possible applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
8.3 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
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List of Figures
2.1 AMS Demo App . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 Vivado main project menu . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Example usage illustration . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 Microcontroller system diagram based on the AMS SL13A . . . . . . . . 13

3.2 Proposed system diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3 AS3955 demo kit contents . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4 FPGA system diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1 System diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.2 System decision diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.3 SPI module diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.4 SPI module FSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.5 Shift register operation when writing . . . . . . . . . . . . . . . . . . . . . 28
4.6 Shift register operation when reading . . . . . . . . . . . . . . . . . . . . 28
4.7 Single register write timing [Fig. 59 17, p. 63] . . . . . . . . . . . . . . . . 30
4.8 ADC control module diagram . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.9 XADC functionality overview . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.10 Main control module diagram . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.11 Main control module FSM . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.1 Basys3 prototype system . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.2 Bank 0 with its configuration IC . . . . . . . . . . . . . . . . . . . . . . . . 45
5.3 Bank 15, used for analog inputs. 332-06 is a female 6 pin header. . . . . . 46
5.4 Bank 14 with its connections to the AS3955 and main clock generator . . 47
5.5 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.6 Board layout, dimensions are in mm . . . . . . . . . . . . . . . . . . . . . 49
6.1 Writing 10011001 to register at address 01 . . . . . . . . . . . . . . . . . . 58

6.2 Reading from register at address 01 . . . . . . . . . . . . . . . . . . . . . . 58
6.3 EEPROM R/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.4 Simulation of single ADC conversion . . . . . . . . . . . . . . . . . . . . 61
6.5 Reading interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6.6 Reading ROM address 0A . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.7 Waiting for ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.8 Writing ADC result at ROM address 0B . . . . . . . . . . . . . . . . . . . 66
6.9 Writing 0s to address 0A . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.10 Complete simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
7.1 Plot of data in table 7.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
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List of Tables
1 Abbreviations used in this paper . . . . . . . . . . . . . . . . . . . . . . . xiv
3.1 Proposed components to be used in project . . . . . . . . . . . . . . . . . 15
4.1 Table of registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.2 Table of EEPROM blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3 SPI commands used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.4 Interrupt register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.5 Interrupt register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.6 Send shift register data for register commands . . . . . . . . . . . . . . . 29
4.7 Send shift register data for EEPROM commands . . . . . . . . . . . . . . 29
4.8 Standout XADC wizard options . . . . . . . . . . . . . . . . . . . . . . . . 33
4.9 Time to perform various operations . . . . . . . . . . . . . . . . . . . . . 37
5.1 Pin assignment for PCB design . . . . . . . . . . . . . . . . . . . . . . . . 42

5.2 BOM, totalling 77.3 Euro . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
7.1 ADC measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
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Preface
This thesis is part of my masters studies for a degree in Nanoelectronics at the

Department of Informatics, University of Oslo. I started research fall 2017, selected
parts spring 2018 and the next 6-8 months were spent working on the VHDL code.
My interest in programming and miniaturization made this project appealing to me.
Although writing HDL code is distinct from standard programming, they both require
the same problem solving and creative skills to succeed.
I would like to thank my supervisor, Prof. Philipp Dominik Häfliger, for giving me
the opportunity to write my thesis on an interesting and impactful subject. His advice
throughout the project has been valuable as well as giving understandable answers to
all my questions, both simple and hard.
I would also like to thank my co-supervisors, Girish Aramanekoppa Subbarao and
Behnam Samadpoor Rikan, for their help along the way.
Finally I would like to thank my friends and family.
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List of Abbreviations
ADC Analog to Digital Converter

AMS Austria Mikro Systeme, semiconductor designer and manufacturer
ASCII American Standard Code for Information Interchange, character encod-
ing standard for English letters
BGA Ball Grid Array
BOM Bill Of Materials
CLK Master Clock, 100 MHz main clock for the FPGA
EEPROM Electronically Erasable Programmable ROM
EOC End Of Conversion, active high signal indicating a conversion has
completed
EOL End Of Life
FF Flip-Flop
FPGA Field Programmable Gate Array
FSM Finite State Machine
GND Ground
HDL Hardware Description Language, class of computer languages used to
describe digital circuits
I2C Inter-Integrated Circuit
IC Integrated Circuit
IDE Integrated Developement Environment
IP Intellectual Property
IRQ Interrupt Request Output
JTAG Joint Test Action Group, debugging standard for PCBs
LED Light Emitting Diode
LSB Least Significant Bit, bit corresponding to 20
LUT Look-Up Table
MCU Microcontroller Unit
MICS Medical Implant Communication Service, specification used for im-
plants, known as MedRadio in the US
MSB Most Significant Bit, bit corresponding to 2n−1 where n is the number of
bits
NFC Near Field Communication
OTP One Time Programming
PCB Printed Circuit Board
RFID Radio-frequency identification
RO Read Only
ROM Read-Only Memory, a type of non-volatile memory
RW Read Write, also R/W
SAR Successive Approximation ADC
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SCLKSerial Clock, 195 kHz clock used by SPI
SMDSurface Mount Device, also written as SMT
SPI
Serial Peripheral Interface
TI
Texas Instruments
VCCPositive supply voltage, also VDD
VHDL VHSIC Hardware Description Language, one of the two main HDLs in
use, the other is Verilog
XML Extensible Markup Language
Table 1: Abbreviations used in this paper
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Part I
Introduction
1
Chapter 1
Goals of this thesis
Goal: Evaluate an alternative to the ASIC design that is more flexible with shorter
redesign cycle but that is less compact and consumes more power.
Objective: Find suitable components, implement them on a test board and propose design
of implantable PCB.
Scope: – Research suitable components

– Acquire demo kits
– Modify and extend so that the functionality we’re after is demonstrably
possible
– Evaluate performance and power consumption
– Investigate the possibility of integrating components onto a single PCB
– Bill-of-materials and size estimate for PCB
3
4
Chapter 2
Background
2.1 Motivation
For many, including myself, working in a field where one could positively impact
people’s lives is a great motivator. The intended application of the system, namely
urinary bladder pressure sensors, has the potential to help over 220 000 people in
Norway alone [2]. The opportunity to work on something which could improve some
of their lives is fantastic.
Any new project involves learning new skills, whether we are aware of what they
are when we start or not. For me personally, learning something new about areas of
interest is always an opportunity I take advantage of. This project would expand my
horizons regarding hardware as well as software.
Small integrated devices have been rising in popularity in recent years, from Internet-
of-Things to medical implants saving people’s lives. The task of making the smallest
possible device is generally reserved for ASICs, having to achieve a similar result using
multiple off the shelf components makes the hardware choices for this project a non-
trivial task.
The software aspect was one of the most appealing as I enjoy the problem solving
skills required by programming languages, whether they are meant for traditional
computers, embedded systems or digital circuits. Deciding on a particular way of
solving a problem is difficult and always results in some kind of tradeoff, be it related
to code complexity (making further work more difficult) or performance.
2.2 Previous work

Ali Zaher [3] published a series of papers detailing a whole system architecture starting
from the transistor level up to an end-user mobile phone application. The toolset
is designed to be usable with a variety of sensor inputs, such as blood glucose and
pressure sensors, among others. The implantable hardware was presented in a paper
by Ali Zaher, Joar Særsten, Thanh Trung Nguyen and Philipp Häfliger in [4]. The
system consisted of a dual ASIC and one FPGA with the goal of integrating everything
on one ASIC in the future.
The task of integrating the system was done by Joar Særsten for their master thesis [5].
They were successful in producing and testing their design, although not without some
faults. The single ASIC solution was not capable of powering itself through harvested
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power alone.
An embedded system based on MICS was presented in a paper by A. Tantin et al. in
[6]. In their work they develop a wireless system for monitoring bladder pressure, the
implant utilizing a MICS transceiver, microcontroller, two amplifiers and two sensor
probes. This system is also relying on a battery to supply power and it is the only
system utilizing FDA approved RF technologies.
2.3 Fundamental Concepts

This section briefly introduces the technologies and protocols used by this project.
2.3.1 NFC
NFC [7] is a set of short-range communication protocols, typically used for contactless
cards (such as payment, identity and keycards). A notable entity is the NFC Forum
non-profit association, it is responsible for setting up standards and certifying devices.
The NFC tag used in this project is NFC Forum Type 2 compliant, the carrier frequency
is 13.56 MHz with an expected bitrate of 106 kbps.
So why are we using NFC? Its first advantage over other solutions is security. The
very short communication range (a couple centimeters) compared to other protocols
such as MICS or Bluetooth (ranges measured in meters), makes unauthorized access
much more difficult, as the reader would have to be practically touching the NFC tag
to establish a connection.
Another advantage is its wide compatibility, something it shares with Bluetooth.
Most modern smartphones are capable of reading and writing NFC tags, making
them compatible with the system. MICS is typically only compatible with medical
equipment, making larger scale adoption more difficult.
A disadvantage is that while the 13.56 MHz carrier frequency is approved for use in
human implants, NFC’s viability in particular is unknown. Another issue stems from
its limited range which could make it challenging to find the right positioning in order
to establish a connection.
2.3.2 SPI
SPI [8] is a communication specification operating on a master-slave principle. That is
to say, there is one controlling device and one or more "slaves" or listeners. The slaves
cannot initiate communication themselves, they have to wait for the master to do so.
Multiple slaves are possible by using an SS line for each of them. They may all share
the same clock and data connections.
This is in contrast to another similar technology, I2C which uses addresses in order to
support multiple masters and slaves. SPI was chosen for this application because only
one slave is required (the AMS3955 NFC tag), making it easier to implement.
SPI requires 4 signal lines to function:
SCLK Serial Clock, clock provided by the master
MOSI Master Out Slave In, output data from the master
MISO Master In Slave Out, output data from the slave
6
SS Slave Select, active low signal provided by the master initiating communication
2.3.3 Android Application

Reading and writing to the NFC tag can be done with a variety of Android
applications, the demo application provided by AMS with the AS3955 demo kit was
used. NFC Tools by wakdev [9] has been confirmed to work as well, in principle any
application capable of reading and writing a type 2 tag can be used.
The Android application included with the AS3955 demo kit is shown in figure 2.1 and
supports a variety of features but the one we are interested in is reading and writing
the tag’s EEPROM.
Dealing with raw hex values for addresses and data is not ideal, a user friendlier
application that abstracts these details away would be the best solution. Such an
application would perhaps display the measured bladder pressure as a percentage
instead of hex or volts. The application developed for the ASIC solution could be
adapted to work with our system so we would not have to start from scratch.
(a) Information page (b) Memory page
Figure 2.1: AMS Demo App
2.3.4 FPGA
FPGAs [10] are highly flexible integrated circuits intended to be reconfigured after
manufacture. The basic building blocks of FPGAs are look-up tables, flip-flops and
full-adders. Using VHDL or Verilog, an engineer can program the FPGA to form other
logic gates and more complex combinational logic in hardware. This ability makes FP-
GAs excellent for low-level applications where logic gate precision is required.
7
Further, it is possible to reprogram an FPGA as many times as required. A single chip
can change its configuration completely and there are emerging techniques to do this
without a complete restart (partial reconfiguration).
Due to this extreme flexibility, FPGAs have been on the radar for many industries
for years, however when compared to ASICs they are significantly slower (under 1
GHz while ASICs can exceed 5 or more) and larger in area while consuming more
power. In low quantities, FPGAs are orders of magnitude more affordable than ASICs,
but as the volume increases, the FPGA prices remain relatively constant while ASICs
drop to a couple of pennies in comparison.
FPGAs are therefore excellent for prototyping and low quantity projects, but if mass
production or lowest power consumption is required, ASICs remain the better choice.
The process of transforming HDL code into logic gates is called synthesis and is
done by a synthesis tool, for Xilinx FPGAs it is the Vivado software suite. After
synthesis there is another process called implementation, this is what determines how
the basic building blocks (LUTs, FFs) are used in order to form the logic gates dictated
by the code. During implementation, the tool decides which parts of the chip are used
and how, although this could be done manually if needed.
2.3.5 XADC
The XADC is a pair of 12 bit, up to 1 mega sample per second ADCs included with 7
series Xilinx FPGA’s (Spartan and higher, excluding XC7S6 and XC7S15). It is capable
of a variety of operations (such as temperature measurements) but we are mainly
interested in its ability to sample analog differential inputs using an event driven
model, that is, it remains idle until told to start a conversion.
The exact number of auxiliary inputs depends on the specific FPGA PCB used, the
XADC itself supports up to 16 different channels. For this project, only one of them
was used.
The output is a hexadecimal number between 0x000 and 0xFFF, corresponding to 0 V
and 1 V respectively. Voltage can be converted to a hex number with equation 2.1, the
voltage can be calculated back from the hexadecimal number by dividing it by 0xFFF.
Vin
FFFh = HEXin (2.1)
1.0
As an example, in figure 2.1b the value 0xB60 at address 0x0B corresponds to 0.7111 V.
2.3.6 Vivado
The Vivado software suite is being developed by Xilinx Inc. primarily for use with
their FPGAs. It includes an IDE, simulator and synthesis tool.
Its primary role is to generate the proprietary files used to program the FPGA, called
bitstreams. The included hardware manager can then program the FPGA via USB
using these bitstreams. It is also possible to generate binary files which can be flashed
to the SPI flash on the board, this is useful because the FPGA will then program itself
on start-up instead of needing to be programmed manually each time.
In addition, the software provides useful statistics such as resource utilization (how
8
many LUTs and FFs we’re using), timing information (whether a piece of code is
too slow) and estimated power consumption figures. The accuracy of the power
consumption figures are unknown, but they are the only way to get any information
about this when using a development board such as the Basys3.
Figure 2.2: Vivado main project menu
2.3.7 Basys3 development platform

A Digilent Basys3 board [11] was used for development. The primary reason for
choosing this board was that it was already on hand and, as a dedicated development
board, it is equipped with a large selection of buttons, switches, LEDs as well as four
7-segment displays. None of these features are used in the final, non-debug code but
they have been absolutely crucial in the debugging and verification process.
The FPGA used by the board is a Xilinx Artix 7 XC7A35T-1CPG236C, making the Vivado
suite ideal. This chip is much more capable than required, but this isn’t an issue when
considering the purpose of the board.
9
2.4 Usage illustration
Figure 2.3 is an illustration of how the complete system might be used. The goal is to
develop a small enough device such that it can be implanted, enabling the use of an
NFC enabled mobile phone to read data from it. This thesis concerns itself with the
design and implementation of the implanted device.
Consider contacting
a professional
Bladder pressure
implant
!
Figure 2.3: Example usage illustration
10
Part II
The project
11
Chapter 3
Planning
3.1 Microcontroller Based Design

This section discusses possible implementations using all-in-one solutions or discrete
component solutions based around a microcontroller.
3.1.1 All-in-One NFC Tag

A design based around the AMS SL13A NFC tag [12] seemed like a natural fit for
the project. This chip integrates several of the desired aspects, specifically a resistive
analog input, a 10-bit ADC and the ability to transmit the digitized data over NFC. An
example of such an implementation is shown in figure 3.1.
Unfortunately the SL13A was discontinued in late 2015 [13] to be replaced by the AMS
AS39513. Complications arose due to the replacement encountering multiple delays
and having a 28 week factory lead time as of April 2018, making it unsuitable for use
in this project. The decision was made to replace this single chip with multiple discrete
components, those being a passive NFC tag (3.1.4) and a microcontroller (3.1.3) with
an integrated ADC.
Mobile Preamp Pressure

SL13A
Phone Sensor
Figure 3.1: Microcontroller system diagram based on the AMS SL13A
13
3.1.2 Amplifier
The expected voltage swing of the pressure sensor is in the 100 mV range, however,
in order to reach the advertised accuracy of an ADC, one must use the entire input
range. Typically this is between ground and the supply voltage and so the input must
be amplified before going in to the ADC in order to maximize accuracy.
The amplifier must have differential input and tunable gain, a type of amplifier par-
ticularly well suited to this application are instrumentation amplifiers. [14] Standout
features are input buffers which eliminate the need for impedance matching.
An example of such an amplifier is Texas Instruments’ line of low power instrumen-
tation amplifiers, prefixed with INA. For example the INA317 [15] has programmable
gain, tuned by an external resistor, of up to 1000.
3.1.3 Microcontroller
A microcontroller is required because both the NFC tag and a potential dedicated ADC
chip can only operate as SPI slaves. Thankfully, many MCUs include an ADC so there
is no need to add another discrete component to the system, one would only have
to replace the ADC with an MCU. Microcontrollers are a diverse and broad type of
component, here are a couple of options that were narrowed down, both are TI parts.
• MSP430FR2000 Cheapest option, 0.5 kB RAM with a slope ADC. Claimed power
consumption 120 µA/MHz. [16]
• MSP430FR2100 More expensive but seemingly a better choice, 1 kB of memory

and 0.5 kB of RAM with a 10-bit SAR ADC. Same power consumption metrics.
3.1.4 NFC Tag

The specifications for the SL13A were used to find a suitable replacement. AMS
has recommended we use their AS3955 [17] NFC tag together with a microcontroller.
Standout specifications:
• Claimed energy harvesting up to 5 mA at 4.5 V (22.5 mW)
• Able to write to the EEPROM using NFC, 472 bytes of user data
• Only slave in SPI, but can send interrupts
14
3.1.5 Component summary
All prices in table 3.1 are based on data from Mouser Electronics.
The ASIC project has run into difficulties regarding NFC power harvesting, the
figures given in AMS’ datasheet are best case scenarios with unspecified antenna
configurations. Actual current output is likely to be lower than the quoted 5 mA
figure (potentially significantly so) and must therefore be validated before we can state
whether or not the system can run battery-less.
Mobile TI Preamp Pressure

AS3955
Phone MCU Sensor
Figure 3.2: Proposed system diagram
Manufacturer Name Power use Price (100 units)

Tag AMS AS3955 harvest up to 5000 µA 14.96 NOK
MCU TI MSP430FR2100 -150 µA/mHz 6.12 NOK
Amplifier TI INA317 -50 µA quiescent 15.6 NOK
Table 3.1: Proposed components to be used in project
15
3.1.6 AS3955 Demo Kit
Due to lack of experience in working with the NFC protocol, a demo kit for the
AMS 3955 NFC tag was acquired. The demo kit [18] is intended to demonstrate
the functionality of the NFC tag using a Windows program as well as an Android
application. It quickly became clear that the demo applications are too limited to
be of much use to this project. Fortunately, the source code used to program the
microcontroller (Microchip PIC24FJ128GB202 [19]) was included so the intention then
was to modify it such that it is able to read external analog input, convert it using the
integrated ADC and send it to the AS3955 via I2C or SPI.
Figure 3.3: AS3955 demo kit contents
3.1.7 PIC Reprogramming

Typically, external reprogrammers are used when working with microcontrollers,
however the Windows application included a firmware update option. The source
code was successfully recompiled and re-flashed to the demo board, but a major
potential issue was noticed early in the process. The main function of the code (the
first code to run when the MCU starts) included the USB controller. The concern was
16
that if something were to go wrong in the main function, causing it to stall or otherwise
break in some fashion, the USB part of the code would never load, rendering the MCU
impossible to reprogram via software.
During the early phases of experimentation, an attempt was made to assign one of the
unused pins to a variable. This seemingly harmless piece of code was added too early
in the main function, causing the exact problem described above. With no reply from
AMS support and no hardware reprogrammers on hand, the decision was made to use
something else that was, specifically an FPGA.
3.2 FPGA Based Design

Switching to an FPGA as the controller is a relatively straight forward thing to do.
The main problem now would be that we’re starting from scratch. There is no code
available that automatically communicates via SPI, no code for using any I/O, buttons,
LEDs etc on the board and the programming language is considerably lower level.
The major advantage is that it is practically impossible to repeat the same mistake with
an FPGA, an intentional attempt at interrupting USB communication would have to
be made in order to render the device difficult to reprogram.
There are more advantages when it comes to developing with a Basys3 as opposed to a
microcontroller, mainly the user input and outputs available for use. The switches and
display were of particular help as they enable real-time monitoring of what the FPGA
is doing. Another advantage which cannot be understated is the ease of simulation,
being able to simulate the code and view not only actual hardware outputs but also
internal signals makes debugging significantly easier than having to rely on hardware
indicators such as LEDs.
Figure 3.4 is a top level overview of the discrete components required. In fact, this is
the same as the proposed system in figure 3.2 with the TI MCU being replaced by an
FPGA.
The work for this thesis focused on implementing SPI communication with the AS3955
tag and using the FPGA’s internal ADC. Additional code was written to help with
debugging, including but not limited to, drivers for the 7 segment display, ability to
manually set the values of internal FPGA registers (such as SPI commands, addresses
and data), and continuous sampling modes for the ADC. All of these features are
toggled via buttons and were removed for the final implementation.
Mobile Preamp Pressure

AS3955 FPGA
Phone Sensor
Figure 3.4: FPGA system diagram
17
18
Chapter 4
Digital design
19
4.1 AS3955
This section is focused on explaining the AS3955’s capabilities and functionality.
4.1.1 Power supply
The chip is advertised as being capable of supplying up to 5 mA at 4.5 V (22.5

mW). Unfortunately even if this figure was reliably achievable, Vivado estimates the
FPGA’s power consumption to be around 76 mW, far more than the energy harvesting
capabilities of the NFC tag. Additionally, that power consumption figure is only for
the FPGA itself, it does not include any other losses and ICs that must be present for
the system to be operational (more details on the power supply for a PCB can be found
in section 5.7).
The tag alone could theoretically power itself, but the rest of the system requires an
external power supply, such as a small battery. During development, the NFC tag was
powered by the 3.3 V supply voltage of the FPGA.
4.1.2 Data structures
The chip has two means of storing data, its internal registers and 472 bytes of EEPROM.
A register is a very fast, limited capacity volatile memory-like circuit typically
implemented using FFs. This makes them ideal for applications such as status
indicators or basic configuration. They are not used for data storage due to their lack
of capacity and volatility, meaning they will erase themselves after losing power. The
configuration registers are automatically loaded from the EEPROM during power-up.
The EEPROM is non-volatile and thus it is where all persistent data must be stored in.
Compared to the registers, its capacity is much higher but it suffers from slow read
and write speeds, as well as having limited rewrite counts (the EEPROM eventually
becomes unusable after being overwritten too many times). After a write command,
once SS goes high we must wait a minimum settling time of 8.3 ms and maximum of
9.5 ms, as per the datasheet ([17, p. 77]).
In addition to the registers and EEPROM, there is also a 32 byte buffer available which
behaves the same as register operations (no delay after writing). Its contents might not
be predictable (other internal operations of the chip might write data to it), so it has
not been explicitly used for this project.
The list of all registers is shown in table 4.1, while the list of EEPROM blocks (a block
is comprised of 4 bytes) is shown in table 4.2.
20
Address [hex] Description Access
00 IO config RW
01 IC config 0 RO/RW
02 IC config 1 RO
03 IC config 2 RO/RW
04 RFID status RO
05 IC status RO
08 Mask interrupt 0 RW
09 Mask interrupt 1 RW
0A Interrupt 0 RO
0B Interrupt 1 RO
0C Buffer status 2 RO
0D Buffer status 1 RO
0E Last NFC address RO
1E Major version RO
1F Minor version RO
Table 4.1: Table of registers
Block [hex] Description Access

00 UID RO
01 Fabrication data RO
02 Internal/Lock OTP
03 CC OTP
04-79 User data RW
7A Lock OTP
7B Lock OTP
7C Auth. password RW
7D Auth. settings RW
7E Config 0 RW
7F Config 1 RW
Table 4.2: Table of EEPROM blocks
21
4.1.3 Commands
Table 4.3 shows the commands that were implemented, following the specification
from [Fig. 55 17, p. 60] in the datasheet. All commands start with 3 bits indicating
what the operation we are about to perform is.
For register operations the next 5 bits are the address, after which we will either send
or receive 8 bits of data. All register operations must therefore complete in 16 clock
cycles.
For EEPROM operations we send the 3 command bits as usual, but this time they are
followed by 5 copies of the LSB (five zeroes for writes and five ones for reads). The
EPPROM is much larger than the registers, so its addresses are 7 bits wide.
Note that SPI is expected to work in byte sized chunks, that is, 8 bits at a time. As a
result of this, the 7 bit address is padded with an extra 0 at the end in order to complete
a byte.
Following the 2 bytes we’ve sent now, we will either have to send an additional 4
bytes with the data to be written or start reading 4 bytes, depending on the requested
operation. All EEPROM operations must complete in 48 clock cycles.
Mode Command Trailer Extra

Reg Write 000 5-bit address N/A
Reg Read 001 5-bit address N/A
ROM Write 010 00000 7-bit address
ROM Read 011 11111 7-bit address
Table 4.3: SPI commands used
4.1.4 Interrupt registers

Interrupts occur after specific events, some examples include after power-up, wake-
up, ROM reads or writes. The complete list can be found in tables 4.4 and 4.5. The
AS3955 uses a separate interrupt line (labelled IRQ), that is pulled high (set to logical
1) whenever any of the bits in either interrupt register is set. It is therefore extremely
important that the controlling device, in this case the FPGA, is aware of this fact and
reads the contents of both registers whenever the IRQ line is high.
The tag is programmed to automatically reset a register after its contents have been
read, both of them are read-only because of this.
Bit Name Trigger

7 I_pu Power-Up
6 I_wu_a Wake-Up
5 I_slp SLP_REQ command
4 I_eew_rf RF EEPROM Write
3 I_eer_rf RF EEPROM Read
2 I_rxe End of Receive
1 I_txe End of Transmission
0 I_xrf Exit RF field
Table 4.4: Interrupt register 0
22
Interrupt register 0 structure is shown in table 4.4, based on [Fig. 92 17, p. 85] in
the datasheet. Of particular interest is bit 4 which is triggered when the EEPROM has
been written to through RF, such as by an NFC enabled mobile phone.
Some of the other bits could prove useful for catching potential errors during
operation, for example one would expect bit 2 to be set after we write something to
the tag, if it is not, that would indicate a failure in the system that should be handled
(for example by retrying the operation). Such measures have not been implemented as
they were deemed unnecessary.
Bit Name Trigger

7 I_rxs Start of Receive
6 I_frm_err Lower Layer error
5 I_parr_err Parity error
4 I_crc_err CRC error
3 I_bf_err Buffer error
2 I_io_eewr Successful EEPROM write (SPI)
1 I_eeac_err Write protected/inexistent EEPROM address
0 I_acc_err Interrupted SPI operation
Table 4.5: Interrupt register 1
Interrupt register 1 structure is shown in table 4.5, based on [Fig. 93 17, pp. 85, 86]
in the datasheet. This register is read but none of the values are used.
4.2 System Overview
Figure 4.1 is a top level overview of the entire system. Outside of the FPGA, every
block is a dedicated component, and on the inside they are separate modules. There
is a section dedicated to each of the FPGA’s modules following this one, only a brief
description of each will be given here.
Starting with the main control module (labelled CTRL module), its job is to wait for
interrupts from the AS3955 and send the appropriate commands over internal buses to
the SPI and ADC CTRL modules. Depending on the data received from the NFC tag,
the control module will now send an enable pulse to the ADC controller and wait for
its response. Finally, the data from the ADC is sent to the SPI module to be written to
the NFC tag, making it available to other devices.
The SPI module sends the data on its input buses serially over SPI, it automatically
adjusts between the various commands described in AS3955 section 4.1.3.
The ADC control module sends the conversion start pulse, waits for EOC and places
the relevant 12 bit result on the DOUT bus.
The XADC module is proprietary Xilinx IP, it is automatically generated by Vivado. Its
inputs are external analog connections, with the possibility for differential input.
23
Implant
FPGA
IRQ
EN
SCLK SCLK
MOSI DOUT32
SPI / CTRL
AS3955 SS
/
3 CMD
MISO module 7 ADR
module
/
32 DIN
/
EN
12
/
DOUT
DONE
CONV
DEN
VAUXP EOC
Pressure DRDY ADC CTRL
XADC BUSY
sensor VAUXN module
DOUT 16
/
7 ADR
/
Figure 4.1: System diagram
24
4.2.1 Decision diagram
Figure 4.2 shows the basic decisions taken by the control module and by extension, the
entire system.
At idle, we are simply waiting for the IRQ line to go high, once it does both interrupt
registers are read. If bit 4 in register 0 (I_eew_rf, indicating the EEPROM has been
written to) was set, then we proceed by reading a dedicated "command" address in the
EEPROM. This is done so that the user can still write something else to the EEPROM
without triggering a conversion. If any of these steps fail, either by not detecting an
EEPROM write or detecting that something unexpected was written, we go back to
idle and wait for the next interrupt.
If they both succeed, a sample is taken, the result is written to a set EEPROM address
and finally the command address is zeroed out. The clear operation is done to ensure
that we only perform one sample per request.
Wait
interrupt
No
EEPROM
written to?
Clear
Yes command
No
address in
EEPROM
Conversion
request?
Yes
ADC Write
sample result to
EEPROM
Figure 4.2: System decision diagram
25
4.3 SPI module
4.3.1 Module overview
Figure 4.3 shows all the connections related to the SPI module.
Description of module inputs (right arrows) and outputs (left arrows):
↔ AS3955 I/O Described previously in sections about SPI 2.3.2 and the tag’s
interrupt registers 4.1.4
→ CLK 100 MHz clock

→ EN Global module enable signal
→ CMD 3 bit SPI command bus
→ ADR 7 bit SPI address bus, may be 5 bit
→ DIN Data going into SPI module, data sent to tag
← DOUT Data coming out of SPI module, data received from tag
CLK
EN
SCLK
SS
SCLK 3 CMD
SS /
SPI CTRL
AS3955 MOSI
ADR
MISO module 7
/ module
32 DIN
/
DOUT 32
/
IRQ
Figure 4.3: SPI module diagram
26
4.3.2 FSM diagram
Figure 4.4 shows the possible states of the SPI module. Any state which involves
data transmission takes more than one SCLK cycle to complete, this is represented by
"counter" in the figure. Its initial value depends on the operation, it can be 8 (register
command and data), 16 (EEPROM command) or 32 (EEPROM data).
en=0
Idle
counter=0
en=1
counter=0
Decode
cmd
Send counter=0 & read

Send data Recv data
counter=0 & write cmd
counter>0 counter>0
counter>0
Figure 4.4: SPI module FSM
4.3.3 SCLK
The SPI module generates the serial clock (SCLK) using a simple clock divider. The
generating process is running off of the FPGA master clock (100 MHz) and inverts
SCLK every 256th rising edge, the resulting frequency for SCLK is approximately 195
kHz (a period of 5.12 µs). This frequency was arbitrarily chosen, the most important
requirement is that it adheres to the NFC tag’s specification (100 kHz - 5 MHz).
One must also take note of the EEPROM read specification which dictates a minimum
of 1 µs SCLK period, and since we are reading from the EEPROM, the practical
frequency range is between 100 kHz and 1 MHz. Another consideration is that the
control module also uses SCLK for its internal clock divider, that must also be modified
should SCLK change its period.
27
4.3.4 Internal setup
The module’s operation is based on two 32 bit shift registers and two corresponding
counters. A shift register is analogous to a stream of bits, inserting a bit in one end leads
to another bit "falling out" the other, this behaviour makes them suitable for sending
or receiving serial data.
When writing data, a 0 is inserted as the LSB, the MSB pops out and is placed on the
output line (MOSI). By repeating this process n times for n bits, we would have serially
sent all the data. A step by step example of a 4 bit shift register is shown in figure 4.5
below, suppose the output data is 1011.
MOSI: 1 MOSI: 0 MOSI: 1 MOSI: 1

1011 0110 1100 1000 0000
Figure 4.5: Shift register operation when writing
When reading data, the incoming bit is inserted into the LSB instead of a 0, the MSB
popping out is discarded. Step by step example of a 4 bit shift register reading data is
shown in figure 4.6, suppose the input data is 1010.
MISO: 0 MISO: 1 MISO: 0 MISO: 1

1010 0101 0010 0001 0000
Figure 4.6: Shift register operation when reading
This architecture allows for total flexibility when it comes to the number of bits in
any given operation, however one must account for the difference in bit orders be-
tween sending and receiving. Sending starts from the MSB going down, while reading
starts from the LSB going up, as a direct result of this, the bits we wish to send have to
start from the MSB, while if we received less than maximum, we must read them from
the LSB.
This fact is reflected in the design when looking at how register and EEPROM op-
erations differ, register data to be sent is placed as the 8 MSBs of the data in bus (in/out
refer to the direction in reference to other FPGA modules, data in to the SPI module,
going out serially via SPI), while data that has been read is placed as the 8 LSBs of the
32 bit data out (serial data coming in from the tag) bus.
To keep track of the number of bits we should be expecting, two separate counters are
used that are set during command decoding.
The drawback is that we are using more resources in the FPGA, however even the
smallest FPGAs should easily fit two 32 bit registers together with their respective
counters. A possible optimization is to use one 8 bit shift register (both for sending
and receiving), this would increase FSM complexity slightly as we would have to keep
track of which byte we are dealing with, i.e when receiving 32 bits we’d have to know
when byte 1 ended and when byte 2 started.
28
4.3.5 Command decoding
The first step after an enable pulse is to determine whether the operation requires 8 or
32 bits. If the middle CMD bit is 1, then we are dealing with 32 bit EEPROM data and
if it is 0 we have to adjust for 8 bit data (refer to table 4.1.3 for specifics about what each
bit means).
For register R/W, preparation is simple, we only have to concatenate the 3 command
bits with 5 address bits (assumed to be placed as LSBs in the 7-bit wide ADR data bus).
The counter here is set to 8.
OP B31-B29 B28-24 B23-0

R/W CMD ADR 0
Table 4.6: Send shift register data for register commands
For EEPROM R/W, preparation is a bit more complicated, we prepare a 16 bit

value containing the 3 command bits, 5 trailer bits (0’s or 1’s), the 7-bit address and
the remaining spaces are filled with zeroes. Finally, the send counter is set to 16.
OP B31-B29 B28-24 B23-17 B16-0

R CMD 1 ADR 0
W CMD 0 ADR 0
Table 4.7: Send shift register data for EEPROM commands
Tables 4.7 and 4.6 show more clearly where the bits are placed in the shift register.
Intervals such as B28-B24 mean that all bits between 28 and 24 (5 total) are the same
value, 1 for reading and 0 for writing.
Once the counter and shift registers are set up, the only thing left to do is to repeat the
shift process as many times as the counter dictates. Upon sending the command and
address information, we are ready to send or receive data.
29
4.3.6 Sending and receiving data
Now we must prepare the shift registers again, for EEPROM commands the counter
will always be 32 and for register commands it will be 8.
If we are receiving, the receive shift register is zeroed out and we can start putting data
in as it comes every falling edge of SCLK.
If we are sending, the send shift register is set to the value on the DIN bus. It is assumed
that the data is placed correctly (i.e <32 bit data is placed as the MSBs).
Figure 4.7 illustrates the difference between sending and receiving, mainly that data
is to be placed on the MOSI line every rising edge of the clock, while it is read at the
falling edge, the same principle applies when the FPGA is reading from the tag.
Figure 4.7: Single register write timing [Fig. 59 17, p. 63]
30
4.4 ADC module
Figure 4.8 shows the ADC CTRL module’s inputs and outputs, refer to figure 4.1 for
a complete system overview. The module acts as an abstraction layer for the CTRL
module to more easily sample data. Description of module inputs (right arrows) and
outputs (left arrows):
→ CLK FPGA master clock, used to clock the XADC as well as the control FSM
→ EN Global module enable signal, can be continuously high, at which point it will
perform back to back conversions
→ BUSY Active high signal indicating that the XADC is busy
→ DRDY Data ready, indicates when the conversion data is ready to be read from
the ADC’s data bus
→ EOC End Of Conversion, goes high for one clock cycle once conversion is
finished
→ DOUT Dynamic Reconfiguration Port (DRP) output data
← ADC-DONE Active high signal indicating ADC data is ready
← ADC-OUT 12 bit XADC output
← DCLK XADC clock, the 100 MHz master clock is used
← DEN Data enable, has to be pulsed in order for the ADC’s data bus to be enabled
← CONVST Conversion start, should be held high for one clock cycle in order to
initialize a conversion
← DADR Internal XADC register address to read
CLK ADC-DONE
ADC
EN CTRL / ADC-OUT
12
/ /
16
7
BUSY
DRDY
EOC
DCLK
DEN
CONVST
DOUT
DADR
Figure 4.8: ADC control module diagram
31
4.4.2 FSM diagram
Figure 4.9 shows all the states of the XADC module.
EN=0 or BUSY
Read
Idle
data
EN=1 DRDY=1
Pulse DRDY
DRDY=0
convst wait
EOC EOC=1 Pulse

wait DEN
EOC=0
Figure 4.9: XADC functionality overview
4.4.3 XADC Configuration
The ADC control module is responsible for instantiating and controlling the XADC.
Technical details of its setup can be found in UG480 [20]. A brief description will be
provided here.
In order to utilize the XADC, Vivado provides an IP wizard which generates the
module for us.
32
Option name Configuration
Interface DRP
Startup channel Single channel
AXI4STREAM Disabled
DCLK freq. 100 MHz
ADC conversion rate 50 KSPS
Timing mode Event
Event trigger convst_in
Alarms Off
Channel VAUXP6 VAUXN6
Sequencer Off
Averaging Off
Table 4.8: Standout XADC wizard options
With a configuration like in table 4.8, the result of a conversion is read from the
XADC’s status registers. Channel 0 starts at address 0x10 and since we have chosen
channel 6, its results are stored at address 0x16 (table and figure 3-1 in UG480). We are
only interested in the 12 MSBs, the rest of the data is invalid.
As we are only reading one channel/register, the XADC’s DADR input is kept constant
at 0x16 by the ADC control module.
4.4.4 Sampling
In the idle state, we wait for EN to go high, while BUSY has to be low (there is no point
in trying to start a conversion if the ADC is busy). If both requirements are met, we
enter the Pulse convst state which pulls CONVST up and immediately goes to the
next state.
EOC wait pulls CONVST back down (it is important that it is kept high for only one
clock cycle) and waits for EOC from the XADC to go high. Once it does, the same
process is repeated but with DEN and DRDY instead of CONVST and EOC.
In the final state, the 12 MSBs from DOUT are placed on ADC-OUT and ADC-DONE
goes high for one clock before it is reset upon entering the idle state.
33
4.5 Control module
Figure 4.1 shows how the control module is connected to the other modules of the
system, while figure 4.10 shows all its inputs (left) and outputs (right), but does not
include their source or destination.
Short description of inputs (right arrow) and outputs (left arrow):
→ CLK Master 100 MHz clock input

→ EN Module active high enable signal
→ SCLK SPI clock from SPI module, used for a clock divider
→ SS Rising edge is used to determine when SPI commands have completed
→ IRQ Interrupt directly from NFC tag
→ ADC-DONE Input from ADC control module
→ ADC-OUT Data output from ADC
→ DOUT SPI data out, as before this is data out from SPI module (into the FPGA)
← SPI-EN Enable signal for SPI module
← ADC-EN Enable signal for ADC control module
← CMD SPI command bits
← ADR SPI address bits
← DIN SPI data in, as before this is data into the SPI module (out of the FPGA)
CLK SPI-EN
EN
SCLK
SS ADC-EN
IRQ
ADC-DONE
CTRL
/ CMD
module 3
ADC-OUT / / ADR
12 7
DOUT / / DIN
32 32
Figure 4.10: Main control module diagram
34
4.5.2 FSM diagram
Figure 4.11 is a lower level illustration of the control module’s states, complementing
figure 4.2. Essentially all states of this module require multiple clock cycles, the only
exceptions being the two decision states (check ir0 and check data). The FSM is
clocked at 100 MHz, this is dictated by the XADC’s enable and ready signals.
SS=0
t<20ms t<20ms
Write t≥20ms Clear SS=1 Clear

timeout EEPROM timeout
SS=1
ms
20
t≥
SS=0
SS=0
Write en=0 or irq=0 Read
EEPROM =1 ir0
q
1,ir
en=
EOC=1
SS=1
Idle
EOC=0
SS=0
Sample Read
ir1
t
es
No
u
req
wr
Request
SS=1
No
ite
Check SS=1 Read Write Check

data EEPROM ir0
SS=0
Figure 4.11: Main control module FSM
35
4.5.3 Interrupt and its registers
Once an interrupt is received, we must read both of the AS3955’s interrupt registers.
The control module uses the falling edge of SS to determine when data transmission
has started and the rising edge for transmission end. Each of the register reads takes
16 SCLK cycles.
The results are stored in two internal 8 bit buffers, the content of the first interrupt
register is checked to see whether or not the EEPROM was written to over NFC, more
specifically, it checks whether bit 4 (I_eew_rf) is set or not. If it is, we can proceed to
the next step, reading the EEPROM to check for a request. If it is not, we return to idle
and wait for the next interrupt.
This architecture allows the system to be easily expanded to enable checking of other
bits in either register, such as parity checks, verifying the outcome of commands and
more.
It is important to restate that reading both registers is crucial, even though we are only
interested in one of the 16 total bits. Failure to read both will result in the IRQ input
remaining high indefinitely, defeating the purpose of an event driven model.
4.5.4 Reading EEPROM

Once we have determined that the cause of our interrupt was an EEPROM write, we
can then read a specific address and check whether a sample request was made or not.
A request is indicated by the presence of a 1 as the LSB of EEPROM address 0x0A
(the address itself is an arbitrary choice, it just has to be user-accessible), the other 31
bits are ignored but more complex commands can easily be added by modifying the
check data state. If a request was made, SPI enable is brought low while ADC enable
is brought high, if not we return to idle.
All EEPROM commands take 48 SCLK cycles to complete, again the edges of SS are
used to determine when they start and end.
4.5.5 Sample and write

At this point, there is no going back to the idle state prematurely. Once a sample
has been requested, the control module waits for ADC-DONE and sends an EEPROM
write command with the ADC data at address 0x0B. This address choice is also
arbitrary, though it should not be the same address we check for sample requests.
When performing EEPROM writes, we must make sure to not violate the NFC tag’s
specification (see section 4.1.2). A separate delay process clocked at SCLK is used to
wait 4096 cycles after any write command. At an SCLK period of 5.12µs, the delay is
about 21 ms, quite a bit longer than the specced minimum waiting period. The reason
for this choice was that we can use a simple 12 bit local variable, without resorting to
more complex definitions. An 11 bit counter should also work, but it was deemed
unnecessary to get so close to the specification when speed is not a factor for the
application.
In addition to writing the ADC data, the request command address is zeroed out, i.e
we write 32 zeroes to address 0x0A. This is done in order to ensure we do not sample
again unless it was explicitly requested. As this is a write operation, another 21 ms
wait insures before we can return to idle.
36
4.5.6 Overall timing
Excluding timeouts, the overwhelming majority of the time is spent on waiting for SPI
commands to complete. In order, a complete sample request performs the following
operations:
1. Read both interrupt registers, in total 32 SCLK cycles
2. Read EEPROM, 48 SCLK cycles
3. Wait for ADC data, about 3.3 SCLK cycles
4. Write ADC data to EEPROM, 48 SCLK cycles
5. Write 0’s to request command address, 48 SCLK cycles
The total number of SCLK cycles required is 180, however this excludes the two 21 ms
delays after writes.
OP Cycles Time
SCLK us
Reg RW 16 81.92
ROM RW 48 245.76
ADC 3.3 16.8
Total 180 918
Table 4.9: Time to perform various operations
Table 4.9 summarizes how long each operation takes. Notice how the total "active"
time is under 1 ms, while the waiting period is 42 ms total. Effectively then, a request
is completed in just under 43 ms, with the potential to be cut in half. The application
has very loose timing requirements, it is expected to be under one per second so even
at 43 ms it is much faster than necessary.
37
38
Chapter 5
PCB
5.1 Why a custom PCB?

Designing and manufacturing a custom PCB is necessary if we wish for this system to
be implantable. All testing has so far been conducted on the Basys3 board with wires
soldered on to an AS3955 board included in the demo kit for the chip.
As seen in figure 5.1, this solution is much too large to be implanted. This is
to be expected because the Basys3 was never intended for such a purpose, it is a
development platform for Artix 7 FPGAs. Fortunately, the FPGA itself is small (it is
the chip in the middle of the board) and while it requires other ICs in order to function,
the overall package should be small enough once we remove all unnecessary features
(buttons, switches, LEDs, ports).
Figure 5.1: Basys3 prototype system
39
There are smaller commercially available FPGA boards, one such example is
the Digilent Cmod S7 [21] which is 1.8x7.7 cm but this is also too large. Another
consideration is the fact that commercially available boards would have to be
connected to an NFC tag externally (using wires).
5.2 Proposal limitations

For this thesis, only a PCB proposal has been made. The schematic and board layout
are not final and have several flaws:
1. Some components are EOL and should be replaced, notably the SPI flash memory
2. No NFC antenna on the board
3. No way to program the SPI flash or FPGA directly, possibly include a USB
controller or at least a JTAG interface
4. No battery holder
5. Rushed board layout
6. Development versions are advisable, possibly with a BGA socket
7. No instrumentation amplifier
The design of the PCB is based on the Cmod S7 [22] and Basys3 [23], both having public
schematics available from Digilent.
The software used was Autodesk’s EAGLE, all packages were either generated using
the package generator tool or manually drawn using data from the various ICs
datasheets.
In order to get the autorouter to work for the board, unrealistic design rules with very
tight tolerances were used. The main problem being the pitch of the BGA, it is too small
for traces to go between and regular vias are too large. To get this board manufactured,
one would require several layers as well as potentially micro vias. These features are
very expensive to include on PCBs, design optimization could help somewhat (for
example choosing pins on the FPGA which are on the edges of the BGA).
5.3 FPGA Package

As per the Xilinx product portfolio [24], the smallest and therefore cheapest FPGA with
all required features is from the Spartan 7 series, XC7S25 and up (XC7S6 and XC7S15
do not have the XADC).
Further, IO bank 15 (needed as it contains the XADC auxiliary inputs) is not bonded
out in the FTGB196 package, we must therefore use the CSGA225 or CSGA324
packages, the former was chosen for this proposal. [25, p. 36]
A Python script was written to read the ASCII package description files and output
XML that could be pasted in the EAGLE library file. This saves a long time but the
resulting schematics for the banks aren’t ideal. One issue is that the pins are placed in
the same order as they appear in the file, it is better to group them by function instead.
Another problem is that the symbols are simply vertical blocks, making a clean looking
schematic more difficult.
40
5.4 Configuration
The FPGA requires some kind of flash memory so that it can reprogram itself on power-
up, this is most easily done with an SPI NOR flash chip such as the Cypress S25FL032P
[26]. The important characteristics are that it can run on the main 3.3 V supply and the
8-pin SO package is small (5x8mm).
In addition, the board requires an external way of reprogramming the FPGA and/or
the SPI flash. The Basys3 and Cmod S7 have USB controllers as well as JTAG
connections, neither of these features are included in this proposal.
The schematic for the configuration bank is found in figure 5.2.
5.5 ADC
The ADC requires at least two auxiliary inputs as it is capable of differential input. An
extra pair of inputs was wired out in case they would be needed. The differential pairs
are filtered and output to a 6-pin female header. This could be improved by removing
the extra pair and soldering the inputs directly to the source, using headers is likely to
introduce noticeable noise in the system.
In addition to the inputs, it requires filtering for its VCC and GND connections. This is
done using two 600Ω ferrite chokes, but as seen later in section 7.1, a separate power
supply and more filtering is required to achieve 12 bit accuracy. The schematic for the
XADC inputs is found in figure 5.3.
41
5.6 Digital IO
Bank 14 was chosen for use with digital signals. The SPI flash, AS3955 and 100 MHz
clock generator are connected to various pins on it.
The SPI flash is connected to dedicated pins as described by the 7 series pinout
specification. [25]
The AS3955 is connected in a similar fashion as it is on the prototype implementation
using the Basys3 demo board, available pins from bank 14 were chosen and connected
to the tag.
The FPGA master clock is also going into bank 14, it is generated by a Microchip
DSC1033 [27]. Any 3.3 V 100 MHz oscillator can be used.
Pin Function
P14 CLK
K14 SS
J15 SCLK
K15 MOSI
L13 MISO
M13 IRQ
C6 AD0P
C7 AD0N
D7 AD8P
D8 AD8N
Table 5.1: Pin assignment for PCB design
Table 5.1 is an overview of the main pins one must take care of when writing a
constraints file for this board. The schematic for the digital IO is found in figure 5.4.
42
5.7 Power Supply
The FPGA requires the following voltages in order to function: 1.0 V, 1.8 V and 3.3 V.
These voltages have to be generated from a 5 V input, this is taken care of by
two Analog Devices regulators, a LTC3621 [28] and a LTC3633 [29]. The former is
configured for 1.8 V and the latter 1.0 V and 3.3 V.
Both of these parts are relatively old, there is potential to replace them with a single
three channel regulator instead.
The schematic for the power supply is found in figure 5.5.
43
44
5.8 Schematics
Figure 5.2: Bank 0 with its configuration IC
45
Figure 5.3: Bank 15, used for analog inputs. 332-06 is a female 6 pin header.
46
Figure 5.4: Bank 14 with its connections to the AS3955 and main clock generator
47
Figure 5.5: Power supplies
48
Figure 5.6: Board layout, dimensions are in mm
49
5.9 Bill-Of-Materials
Part Number Qty Total Component name Other

price
CR0201-J/-000GLF 3 0.5 Thick Film Resistors -
SMD 0ohm 1% 250ppm
GWCR0201-1K8FT10 2 0 Thick Film Resistors bulk only
0.05W 1.8K Ohm 1%
CR0201-JW-101GLF 12 1.04 Thick Film Resistors
- SMD 100ohm 1%
250ppm
CR0201-JW-104GLF 1 0.2 Thick Film Resistors -
SMD 100K 1% 250ppm
CR0201-FW-1002GLF 6 1.52 Thick Film Resistors -
SMD 10K 1% 250ppm
GWCR0201-13KFT10 1 0 Thick Film Resistors - bulk only
SMD 0.05W 13K Ohm
1%
SMD 1K 1% 250ppm
CR0201-JW-201GLF 1 0.183 Thick Film Resistors
- SMD 200ohm 1%
250ppm
CR0201-FW-3093GAS 1 0.3 Thick Film Resistors - bulk only
SMD 309k OHMS 1%
0201 Anti-Sulfer
SMD 33K 1% 250ppm
SMD 4.7K 1% 250ppm
GWCR0201-560KFT10 1 0.087 Thick Film Resistors - bulk only
SMD 0.05W 560K Ohm
1%
SMD 56K 1% 250ppm
SMD 61.9K 1% 250ppm
GWCR0201-620KFT10 1 0.253 Thick Film Resistors - bulk only
SMD 0.05W 620K Ohm
1%
SMD 86.6K 1% 250ppm
GWCR0201-9K1FT10 1 0.253 Thick Film Resistors - bulk only
SMD 0.05W 9.1K Ohm
1%
50
CC0201KRX5R5BB104 6 0.52 Multilayer Ceramic
Capacitors MLCC -
SMD/SMT 100nF 6.3V
X5R 10%
C0201C104K9PAC 2 0.33 Multilayer Ceramic
Capacitors MLCC -
SMD/SMT 6.3V 0.1uF
10% X5R
C0201C103K4PACTU 2 0.28 Multilayer Ceramic
Capacitors MLCC
- SMD/SMT 16V
10000pF X5R 10%
ZRB15XC80J106ME05D 1 0.419 Multilayer Ceramic
Capacitors MLCC -
SMD/SMT 6.3V 10uF
CBR02C130F3GAC 1 0.367 Multilayer Ceramic
Capacitors MLCC -
SMD/SMT 25V 13pF
C0G 0201 1%
GRM033R71C161JA01D 1 0.087 Multilayer Ceramic
Capacitors MLCC -
SMD/SMT 160UF 16V
5% 0201
GRM0335C1H181JA01D 1 0.087 Multilayer Ceramic
Capacitors MLCC -
SMD/SMT 0201 180pF
50volts C0G 5%
GCM0335C1H180FA16D 1 0.087 Multilayer Ceramic
Capacitors MLCC -
SMD/SMT 50V 18pF
GRM0335C1E102GA01D 2 0.122 Multilayer Ceramic
Capacitors MLCC -
SMD/SMT 25V 1000pF
GRM033R61A105ME15J 1 0.367 Multilayer Ceramic
Capacitors MLCC -
SMD/SMT 10V 1uF
GRM033R61A225KE47J 4 0.94 Multilayer Ceramic
Capacitors MLCC -
SMD/SMT 2.2UF 10V
10% 0201
UMK063BJ222KP-F 1 0.114 Multilayer Ceramic
Capacitors MLCC -
SMD/SMT 2200pF 50V
X5R 10% 0201
51
C0402C223K5RECAUTO 1 0.14 Multilayer Ceramic
Capacitors MLCC -
SMD/SMT 50V 0.022uF
X7R 0402 10% AEC-
Q200
GRM033R71E472KE14D 1 0.087 Multilayer Ceramic
Capacitors MLCC -
SMD/SMT 0201 4700pF
25volts X7R 10%
GRM0335C1E471JA01D 1 0.087 Multilayer Ceramic
Capacitors MLCC -
SMD/SMT 0201 470pF
25volts C0G 5%
CC0402KRX7R6BB472 3 0.087 Multilayer Ceramic
Capacitors MLCC -
SMD/SMT 4700pF 10%
10V MLCC
CGA1A2C0G1E560J030BA 2 0.087 Multilayer Ceramic
Capacitors MLCC -
SMD/SMT CGA 0201
25V 56pF C0G 5%
AEC-Q200
GJM0335C1H6R2BB01J 2 0.192 Multilayer Ceramic
Capacitors MLCC -
SMD/SMT 50V 6.2pF
GRM0335C1E620GA01D 1 0.087 Multilayer Ceramic
Capacitors MLCC -
SMD/SMT 0201 62pF
25volts C0G +/-2%
NR5040T1R5N 1 0.38 Fixed Inductors 5040
1.5uH 26mOhms +/-
30%Tol 3.6A HiCur
NR5040T2R2N 1 0.376 Fixed Inductors 5040
2.2uH 28.6mOhms
+/-30%Tol 3.5A HiCur
NR4018T3R3M 1 0.393 Fixed Inductors 4018
3.3uH 84mOhms +/-
20% 1230mA LwPrfl
419-10-206-00-006000 1 3.78 Pin & Socket Connec- ADC input pins
tors .100" 6P 2R SPRING
MATE W/.042" PLNGR
BLM31KN601SH1L 2 0.5 Ferrite Beads 1206
600ohms 2.9A
AECQ200 Pwrtrain/Saf
AS3955A-ATDM-S4 1 2.14 RFID Transponders
AS3955A-ATDM-S4
MLPD10 LF T&RDP
52
DSC1033DI1-100.0000T 1 1.66 Standard Clock Oscilla- 100MHz clock
tors MEMS Oscillator, generator
3.3V, -40C-85C, 50ppm
FDV301N 3 0.79 MOSFET N-Ch Digital
LTC3621IMS8E 1 5.94 Switching Voltage Reg- 1.8V regulator
ulators 17V, 1A, 1MHz
Synchronous Step-
Down Regulator with
Ultralow Quiescent
Current
LTC3633AEFE 1 9.3 Switching Voltage Reg- 1V and 3.3V regu-
ulators Dual 3A, 20Vin, lator
4MHz, Monolithic Syn-
chronous Step-Down
Regulator
319-10-102-00-006000 1 3.17 Pin & Socket Connec- 2pin header for
tors .100" 2P 1R SPRING 5V/GND
MATE W/.042" PLNGR
S25FL032P0XMFA013 1 3.18 NOR Flash
122-2121-ND 1 31.06 Xilinx XC7S25- DigiKey
2CSGA225C FPGA
Table 5.2: BOM, totalling 77.3 Euro
All prices in Euros, components are sourced from Mouser Electronics, with the
exception of the FPGA which is from Digikey.
Some components are only available in bulk (10 000 or more), it is advisable to change
their packaging from 0201 to 0402 in order to use cheaper parts available for purchase
in lower volumes.
53
54
Part III
Results
55
Chapter 6
Simulation
The main clock frequency for all simulations is 100 MHz (clock period of 10 ns). The
resulting SCLK frequency is 195.3 kHz (5.12 µs).
Major milestones are annotated on the figures, as well as writing the binary value that
is being sent or received. When interpreting these graphs, it is important to recall that
data is always being read at the falling edge of SCLK.
Whenever the FPGA is sending data, MOSI is what’s being read (by the tag) and when
it is receiving data, we are interested in MISO.
Hexadecimal equivalents of each section are included, notice how the data buses match
the serial data.
6.1 SPI
This section presents simulation results from the SPI module.
6.1.1 Register R/W

These operations only require the MODE byte and the data in/out byte. They therefore
take exactly 16 SCLK cycles to complete. An example register write operation is shown
in figure 6.1 and a read in figure 6.2.
In order to be able to read, a random MISO signal is generated every rising edge of
SCLK (approximately 50% chance to be 1).
Data is sampled at the falling edge of the clock and output once SS goes high, in the
example shown in figure 6.2 the result is 0x55 and it is stored in the 8 LSBs of the 32 bit
output bus (notice the lack of trailing 0’s).
57
CMD 0x0 Address 0x1 Sending data 0xAC
0 0 0 0 0 0 0 1 1 0 1 0 1 1 0 0
Figure 6.1: Writing 10011001 to register at address 01
CMD 0x1 Address 0x1 Receiving data 0x1A
0 0 1 0 0 0 0 1 0 0 0 1 1 0 1 0
Figure 6.2: Reading from register at address 01
58
6.1.2 EEPROM R/W
These operations require the MODE byte and additional address byte before the data
can be read or written. Note that the NFC tag only reads the 7 MSBs of the address
byte, this is why it is written in parenthesis on the plots (it is ignored).
The command phase then lasts 16 SCLK cycles, after which data is sent or received for
the next 32 cycles.
A complete operation takes exactly 48 SCLK (245.76 µs).
These simulations also use randomly generated MISO.
Example EEPROM read/write operations are shown in figure 6.3.
59
CMD 0x2 Trailer 0x00 Address 0x01 Send byte 1 0xAC Send byte 2 0x0A Send byte 3 0x0C Send byte 4 0x0A
0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 (0) 1 0 1 0 1 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 1 0
(a) Writing to EEPROM at address 01
60
CMD 0x3 Trailer 0x1F Address 0x01 Read byte 1 0xC6 Read byte 2 0x16 Read byte 3 0x56 Read byte 4 0x2B
0 1 1 1 1 1 1 1 0 0 0 0 0 0 1 (0) 1 1 0 0 0 1 1 0 0 0 0 1 0 1 1 0 0 1 0 1 0 1 1 0 0 0 1 0 1 0 1 1
Figure 6.3: EEPROM R/W

(b) Reading from EEPROM at address 01
6.2 XADC
16610 16630 16650 16670 16690 16710 16730 16750 16770 16790 16810 16830 16850 16870 16890 16910 16930
The XADC has special functionality
idle
available when we’re simulating, namely
800
the capability read a text file containing done_wait
analog data at various times. This allows read_drp
us to still get data out of the ADC when it
is being simulated.
The period where the ADC is working was
cut out because nothing is happening while
BUSY is high. wait_drp
start_drp
A single conversion takes 16.8001 µs (1680
CLK cycles or 3.3 SCLK cycles).
The result for this simulation run was
0x800 (as can be seen on the DOUT bus at
the end).
Time [ns]
10 20 30 40 50 60 70 80 90 100110
wait_eoc
start_conv
STATE idle
DOUT X
EN
CLK
CONVST
BUSY
EOC
DRDY
Figure 6.4: Simulation of single ADC con-

version
61
6.3 System
If we wish to simulate the entire system, we must also simulate the NFC tag’s
responses. For this purpose, a simplified NFC tag model was written. An FSM, much
like the one for the SPI controller, is used to read MOSI every falling edge of SCLK
and respond to SPI commands as the NFC tag would, i.e by setting MISO 1 or 0 at the
rising edge of SCLK.
This extra module includes 4 internal registers, two 8 bit registers for each of the
interrupt registers (set to 0x10 and 0x1F respectively) and two 32 bit registers for
EEPROM address 0x0A and 0x0B. The module has no additional connections, its only
inputs and outputs are the 4 SPI lines, exactly like the AS3955.
A change in the code was made for aesthetic purposes in order to reduce the write
delay from 21 ms down to a couple microseconds, the delay is only needed for the
real hardware to function and serves no purpose when demonstrating functionality
through simulation.
Figure 6.10 shows the entire system operation in one plot, there are also figures for
each major stage (register read, ROM read, ADC sample and ROM writes).
One might notice that not all states described in previous sections are visible in the
following plots, this is because the FSM’s are clocked at 100 MHz while SPI operates
over 500 times slower, at 195 kHz. An aesthetic decision was made to exclude these
states from the plots, only the most recent state within approximately 10 µs is shown.
The result is that instead of going from "Read ir1" to "Check ir0" and finally to "Read
EEPROM", it goes straight from waiting for SPI to finish reading ir1 ("Read ir1" in FSM
diagram 4.11 and "wait_irq1" on simulation plot) to preparing to read the EEPROM.
62
6.3.1 Reading registers
In figure 6.5 both interrupt reg-
isters are read.
After this, bit 4 of register 0 is
1
checked and if it is 1 then we pro-
1
ceed to read from EEPROM ad-
1
dress 0A.
0 0 0 1 1
Data byte in 0x1F
For this simulation, bit 4 will al-
ways be 1. Note that even if it was
not, we would read the second in-
terrupt register before going back
1
to idle.
Address 0x0B
0 1 0 1
0 0 1
CMD
Short timeout
0 0 0 1 0 0
0
0
Data byte in 0x10
0
Address 0x0A
0 1 0 1
0 0 1
CMD
Figure 6.5: Reading interrupt registers
63
6.3.2 Reading ROM
In figure 6.6 the EEPROM is
read and the LSB is checked.
0 1 0 1 0 1 0 1
Note how in this example, address
0x0A has 0101 in it, but as long
Byte 4 0x55
as the LSB is 1, it will continue
performing a single conversion.
Again notice how several states
0 1 0 1 0 1 0 1
are missing, it is going straight
from waiting for SPI to finish to
waiting for the ADC to finish,
Byte 3 0x55
this is because the ADC’s state
transitions typically occur every
10 nanoseconds, the scale of the 0 1 0 1 0 1 0 1
figures here is 1000 times longer at

10 microseconds.
Byte 2 0x55
0 0 0 1 0 1 0 (0) 0 1 0 1 0 1 0 1
Address 0x0A Byte 1 0x55
1 1 1 1 1
Trailer
0 1 1
CMD
Figure 6.6: Reading ROM address 0A
64
6.3.3
ADC sample
takes 16.55 µs in the simulator.

the ADC to finish converting. This
In figure 6.7 we are waiting for
SCLK
65
SS
MOSI
MISO
DRDY
BUSY
EOC
CMD 3 2
ADR A B
DIN 0 8F5
DOUT 1F 55555555
Figure 6.7: Waiting for ADC

ADC_OUT 0 8F5C
IRQ0 10
ROM_0A 55555555
ROM_0B 0
STATE wait_read adc_wait prep_write_rom
475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494
Time [us]
6.3.4 ROM write
In figure 6.8 we are writing the
result to the NFC tag EEPROM.
1 0 1
Note that after this write, we typ-
ically wait 20 ms before the next
1 1 1 1 0
step.
Byte 4 0xF5
Notice how the fake NFC tag’s
ROM data at address 0x0B has
changed to match ADC_OUT, both
0 0 0
are now 0x8F5, remember that we
only take the 12 MSBs from the
0 0 0 0 1
ADC’s output.
Byte 3 0x08
0 0 0
0 0 0 0 0
Byte 2 0x00
0 0 0
0 0 0 0 0
Byte 1 0x00
1 1 (0)
0 0 0 1 0
Address 0x0B
0 0 0 0 0
Trailer
0 1 0
CMD
Figure 6.8: Writing ADC result at ROM address 0B
66
6.3.5 ROM clear
In figure 6.9 we are writing all
zeroes to address 0A. Another 20
0 0 0
ms waiting period would typically
follow this step.
0 0 0 0 0
Notice how the tag’s data at ad-
Byte 4 0x00
dress 0x0A has now changed from
0x55555555 to all zeroes.
After this step we go back to idle
0 0 0
and wait for another interrupt to
repeat the process.
0 0 0 0 0
If this simulation were to continue
Byte 3 0x00
as is, it would return to idle after
reading EEPROM, the only way to
perform another conversion is to
0 0 0
manually modify the data in tag

memory.
0 0 0 0 0
Byte 2 0x00
0 0 0
1 0 (0) 0 0 0 0 0
Byte 1 0x00
0 0 0 1 0
Address 0x0A
0 0 0 0 0
Trailer
0 1 0
CMD
Figure 6.9: Writing 0s to address 0A
67
Read EEPROM address 0x0A
Read IR0 Read IR1 Data in 0x55555555 ADC Write 0x8F5 to EEPROM address 0x0B Write 32 0's to EEPROM address 0x0A
68
Figure 6.10: Complete simulation
Chapter 7
Measurements
7.1 ADC
Basic measurements were taken in order to validate the XADC’s performance. A
multimeter was used to measure the input voltage at the FPGA’s input pins, the voltage
was set using a potentiometer placed between 3.3 V and ground, the input voltage was
stable within 0.1 mV according to the multimeter.
The display on the Basys3 was used to output the raw data coming out of the ADC
in hexadecimal. Steps of 100 mV were used with extra points at the minimum and
maximum measurable values. Only the minimum and maximum value at each step
was recorded due to the output on the display changing every sample.
The theoretical value is calculated by using formula 2.1.
Rather surprisingly, the raw data had lower accuracy than expected with an error
averaging 0x6 (1.465 mV). A 12 bit ADC is expected to have an accuracy of 0.244 mV
(7.1), but these measurements are between a 9 (7.3) and 10 bit ADC (7.2).
The reason for this error is unknown, although the Xilinx ADC documentation [20,
p. 77] talks about PCB design decisions to achieve full 12 bit accuracy. The Basys3
schematics do not seem to include some of these measures, this would explain at least
some of the accuracy losses.
1000
= 0.244 mV (7.1)
212
1000
= 0.976 mV (7.2)
210
1000
= 1.953 mV (7.3)
29
69
Vin Theoretical Min Max Avg
[mV] [hex] [hex] [hex] [hex]
0.10 000 006 009 007
2.30 009 00F 011 010
100.10 199 19E 1A2 1A0
200.60 335 33C 340 33E
300.00 4CC 4D0 4D5 4D2
400.20 666 66E 671 66F
499.20 7FC 803 809 806
600.60 99B 9A2 9A9 9A5
699.80 B31 B37 B3F B3B
800.00 CCC CD1 CD9 CD5
901.20 E6A E74 E7A E77
994.50 FE8 FF4 FFF FF9
Table 7.1: ADC measurements
FF9
E77
CD5
B3B
9A5
806
66F
4D2
33E
1A0
007
0.0001 0.1001 0.2006 0.3000 0.4002 0.4992 0.6006 0.6998 0.8000 0.9012 0.9945
Figure 7.1: Plot of data in table 7.1
70
Part IV
Conclusion
71
Chapter 8
Discussion
In this thesis we have presented an embedded system based on an FPGA for

communicating with a passive NFC tag.
Reflecting on the goals set forth in section 1.
+ Suitable components were found
+ A demo kit for the AS3955 was acquired, this kit included 3 NFC tags with easily
accessible solder pads on them
- Failed to modify or extend its functionality as a result of the microcontroller
becoming impossible to reprogram
± Performance was evaluated but power consumption was not, difficult to measure
with development boards
+ A barebones PCB proposal was made
+ Preliminary BOM and board size estimate (60x66 mm) were made available
Reflecting on the objective to: "Find suitable components, implement on test board,
propose design of implantable PCB". Components were found, but only one of them
(the NFC tag) was used with the test board. An implantable PCB proposal was made,
skipping over a testing PCB design to verify functionality once everything is integrated
together.
A short video demonstrating the Basys3 prototype can be found on YouTube at [30].
8.1 Areas of improvement

8.1.1 FPGA
Currently the implemented design utilizes 120 LUTs and 161 FFs, this is small enough
to fit on any commercially available FPGA but could yet be reduced. Consider the
following VHDL code optimizations:
• Remove unnecessary instantiations, some modules can be merged
• Reduce the number of local variables used in processes
• Handle more than one interrupt
• Don’t pass SCLK into the control module, use master clock instead
73
8.1.2 PCB
The PCB design needs a significant amount of work before it can be printed and tested.
• Implement NFC antenna into the PCB
• JTAG or USB interface to (re)program FPGA
• Board layout uses many layers and has unrealistic design rules set
• Some passive components with high values are better suited to larger packages,
such as 0201 to 0402
8.2 Possible applications

The Basys3 implementation cannot be used for medical implant scenarios due to its
physical size, however a custom PCB using an FPGA with the architecture detailed in
this paper could be implantable in the future. Although the PCB proposal lacks several
required components, there is space left on the 60x66 mm board with the potential to
use both sides of the PCB instead of just one as it currently stands.
The code can be used for any device where one would want analog input to be
digitized and readable using NFC. Some examples in medical applications would be
bladder pressure and blood glucose sensors for diabetic patients.
8.3 Future Work

Designing a test platform for the custom PCB would be the next step for this project. It
is advisable that such a board uses a socket for the FPGA as it would require multiple
iterations and the FPGA is the single most expensive component on the board and des-
oldering BGA is a difficult and high risk operation. Using a socket would dramatically
increase the size and cost of the board but the advantages far outweigh the disadvan-
tages during a prototyping stage.
An alternative way forward is to replace the FPGA with a microcontroller as it was

initially intended. This would potentially reduce the power draw enough for the sys-
tem to be powered by the power harvesting capabilities of the NFC tag. This would be
a very significant advantage as all present solutions rely on external power supplies,
including the one presented in this thesis.
Investigate other protocols, one example is Bluetooth. There are presently two main
issues with such an implementation, it is not legally implantable and it uses drastically
more power. There are also security concerns as Bluetooth has much longer range than
NFC, potentially leading to unauthorized access. That is not to say that it is not worth
investigating. Bluetooth, like NFC, is a universal standard now included in all modern
mobile phones. The range can also be an advantage as it increases convenience and
ease of use due to not having to find a precise spot to place the reader at. An embedded
system based on Bluetooth is being investigated as of this writing.
74
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77

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Medical Implant NFC Embedded System

Thesis submitted for the degree of

Medical Implant NFC Embedded System

Printed: Reprosentralen, University of Oslo

2.1 AMS Demo App . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1 Microcontroller system diagram based on the AMS SL13A . . . . . . . . 13

4.1 System diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.1 Basys3 prototype system . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

6.1 Writing 10011001 to register at address 01 . . . . . . . . . . . . . . . . . . 58

7.1 Plot of data in table 7.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

1 Abbreviations used in this paper . . . . . . . . . . . . . . . . . . . . . . . xiv

3.1 Proposed components to be used in project . . . . . . . . . . . . . . . . . 15

4.1 Table of registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.1 Pin assignment for PCB design . . . . . . . . . . . . . . . . . . . . . . . . 42

7.1 ADC measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

This thesis is part of my masters studies for a degree in Nanoelectronics at the

ADC Analog to Digital Converter

Table 1: Abbreviations used in this paper

Goals of this thesis

Scope: – Research suitable components

2.2 Previous work

2.3 Fundamental Concepts

2.3.3 Android Application

(a) Information page (b) Memory page

Figure 2.1: AMS Demo App

Figure 2.2: Vivado main project menu

2.3.7 Basys3 development platform

Figure 2.3: Example usage illustration

3.1 Microcontroller Based Design

3.1.1 All-in-One NFC Tag

Mobile Preamp Pressure

Figure 3.1: Microcontroller system diagram based on the AMS SL13A

• MSP430FR2100 More expensive but seemingly a better choice, 1 kB of memory

3.1.4 NFC Tag

• Claimed energy harvesting up to 5 mA at 4.5 V (22.5 mW)

• Only slave in SPI, but can send interrupts

Mobile TI Preamp Pressure

Figure 3.2: Proposed system diagram

Manufacturer Name Power use Price (100 units)

Table 3.1: Proposed components to be used in project

Figure 3.3: AS3955 demo kit contents

3.1.7 PIC Reprogramming

3.2 FPGA Based Design

Mobile Preamp Pressure

Figure 3.4: FPGA system diagram

This section is focused on explaining the AS3955’s capabilities and functionality.

4.1.1 Power supply

The chip is advertised as being capable of supplying up to 5 mA at 4.5 V (22.5

4.1.2 Data structures

Table 4.1: Table of registers

Block [hex] Description Access

Table 4.2: Table of EEPROM blocks

Mode Command Trailer Extra

Table 4.3: SPI commands used

4.1.4 Interrupt registers

Bit Name Trigger

Table 4.4: Interrupt register 0

Bit Name Trigger

Table 4.5: Interrupt register 1