Compal La 1711 rx02 D Schematics

5 4 3 2 1
D D
Prescott & Springdale Schematic with Capture CIS

and Function field
C C
uFCPGA Prescott
2003-07-23
Cature library ball out check document
Prescott : Prescott processor Electrial,Mechanical and

REV: X02-D
Thermal Specification Rev0.5 [Check by HW:Henry,Steve]
B B
Springdale(GMCH): Springdale GMCH External Design

Specification (EDS) REV1.0 [Check by HW: Henry,Rita]
ICH5: N/A
@ : Depop Component
1@ : Depop on Nimitz(Inspiron)
2@ : Depop on Beijing(Precision)
A A
Compal Electronics, Inc.

Title
Cover Sheet
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
X02-D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-1711
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. D ate: W ednesday, July 23, 2003 Sheet 1 of 60
5 4 3 2 1
5 4 3 2 1
Compal confidential Block Diagram

D
Prescott D
ADT7460 Thermal sensor

page 19
478 uFCPGA CPU
page 7,8,9
Memory Fan Control

page 14
HA#( 3..31) System Bus HD#(0..63) BUS(DDR)
533/800MHz 2.5V
266/333/400MHz
Channel A SO-DIMM
BANK 0, 1, 2,3 page 15
VGA Springdale
Board AGP CONN. AGP4X/8X(1.5V) GMCH
page Channel B SO-DIMM Clock Generator
932 FC-BGA 10,11,12,13 BANK 0, 1, 2,3 page 16
[CRT CONN. & TV-OUT] page 18
2.5V CK409
266/333/400MHz
C page 6 C
HUB Link
MINI PCI 1.5V DC IN
66Mhz
page 41
266MB/S
page 32
BATT
PCI BUS 3.3V 24.576MHz AC-LINK
IN page 42
ICH5 MDC
3.3V ATA100 page 27
460 BGA 3.3V/5V
3.3V 33MHz
IDSEL:AD20
AC97 page 43
(PIRQA/B#,GNT#2,REQ#2)
ATA100
Page SATA Codec
CardBus Controller
20,21,22
B LAN HDD STAC9750 1.5V/+VTT_GMCH B
ATA100 page 24
B CM5705M PCI7510/PCI4510
page 44
BCM4401 page 30 page 21

page 28
CDROM 1.25V/2.5V
AMP& Phone Subwoofer
LPC BUS Jack Interface
page 45
1394, Smart Slot 0 3.3V 33MHz USB
Transformer USBPORT 4 page 50
page 29 card page31 FDDpage 23 page 25
VCORE
page31
page 47
RJ45 X BUS Macallen USBPORT 1

BT
page 29 LPC to X-BUS USBPORT 2 VCORE_CTRL
& Super I/O USB2.0 BACK
Page USBPORT 3 page 46
DOG
SST39VF080
33,34
USBPORT 4
MOD
page 35
page 26 CHARGER
A page 27 USBPORT 5 BACK page 48 A
USBPORT 6
Touch Pad Int.KBD BACK
page 35
page 35 Compal Electronics, Inc.
Title
Block Diagram
X02-D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: W ednesday, July 23, 2003 Sheet 2 of 60
5 4 3 2 1
5 4 3 2 1
PM TABLE MCH Rev. ICH5 Rev.

RG828SDGES FW82801EB
power +3VRUN Bring up A1(QE18) A1(QE16ES)
plane +3VALW +3VSUS
+5VRUN RG828SDGP FW82801EB
+5VALW +5VSUS SST-Build
+1.5VRUN A2(QE45) A3(QE51ES)
+2.5V_MEM
+VCC_CORE
+3.3VRTC PT-Build
State +12V
D
+RTC_PWR D
+VCCVID
ST-Build
V_1P25V_DDR_VTT
QT-Build
S0 ON ON ON
Pilot-Build
S1 ON ON ON
S3 ON ON OFF
Configuration List
S5 S4/AC ON OFF OFF
S5 S4/AC don't exist

OFF OFF OFF
BOM Structure
PCI TABLE
C Function C
PCI DEVICE IDSEL REQ#/GNT# PIRQ
CARD BUS AD17 1 D,C
LAN AD16 4 C
MINI PCI AD19 3 D,B(NP)
VGA A,B(NP)
B B
Note : "@" means all model depop
USB TABLE "1@" means Nimitz depoped only
"2@" means Beijing depoped only
USB PORT# DESTINATION
Model Nimitz Beijing
0 Reserved Function
1 BT Smart Card No YES
2 BACK
LAN
10/100 1000
3 DOG (4401) (5705M)
4 MOD Dog House YES YES
5 BACK
6 BACK
A A
7 Reserved

Title
Index and Config.
X02-D
5 4 3 2 1
5 4 3 2 1
RBAT
D D
ADAPTER +RTCSRC +RTC_PWR +5VALW +5VSUS
PWR_SRC
+3.3VRTC +3VALW +3VSUS
SUSPWROK
BATTERY
DOCK _PWR_SRC
C C
+5VSUS +3VSRC +2.5VMEMP +VCCP +VCC_CORE +12V
B B
+5VHDD +5VMOD +5VRUN +1.5VRUN VDDA +3VRUN V3P3LAN +3VSUS +2.5V_MEM V_1P25V_DDR_VTT
A A

Title
Power Rail
X02-D
5 4 3 2 1
5 4 3 2 1
ICH_SMBCLK +3VRUN CK_SCLK

D ICH5 7002
CLK GEN. D
ICH_SMBDATA +3VSUS CK_SDATA

7002
V_3P3_LAN
LAN_SMBCLK
DIMM0 DIMM1 7002 7002
NIC
LAN_SMBDATA
7002 7002
CLK_SMB +3VALW
7002
DAT_SMB MPCI
7002
C C
24C05 ADT7460 AD7414 PCA9561 DH PORT
EC SMBus Address
SIO CPU Temp.(ADT7460ARQ) : 5Ch/5Dh (P.19)

DDR Temp.(AD7414ART-0) : 90h/91h (P.15)
Macallen CPU Power Temp.(AD7414ART-0) : 92h/93h (P.?)

EC EEPROM(FM24C05U) : A0h/A1h/A2h/A3h (P.37)
SBAT_SMBCLK +5VALW VID Select(PCA9561PW) : 9Ch/9Dh (P.38)
SBAT_SMBDAT VGA
B B
PBAT_SMBCLK
1'nd
PBAT_SMBDAT +5VALW BATTERY
CHARGER
A A

Title
SMBUS TOPOLOGY
X02-D
5 4 3 2 1
5 4 3 2 1
+ 3VRUN
Place near each pin

+ 3VRUN CK_VDD_MAIN
W>40 mil
1
1
L17
R529 R518 BLM21PG600SN1D_0805~D
R215 @ 0_0402_5%~D Trace wide=20 mils
1K_0603_1%~D 1K_0603_1%~D 2 1 1 2
2
2
R206 0_0402_5%~D 2 1 1 1 1 1 1 1
D D
CLKSEL0 2 1 C204 C586 C587 C585 C554 C552 C551 C588
CPU_CLKSEL0 <8>
R508 0_0402_5%~D
CLKSEL1 2 1 10U_1206_6.3V7K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D
CPU_CLKSEL1 <8> 1 2 2 2 2 2 2 2
R509 @ 0_0402_5%~D
2 1 Bring Up: Populate R509 (Because CPU
is Northwood-MT, Frequency 533MHz)
1
R530 R519
2K_0603_1%~D 2K_0603_1%~D
CK_XTAL_IN and CK_XTAL_OUT equal length traces, 1 1
2
Please place R_J between Pins 4,5 of CK409 Pins C553 C 193
MCH_CLKSEL0 <10> before X'tal 4.7U_0805_6.3V6K~D
0.1U_0402_10V6K~D
2 2
MCH_CLKSEL1 <10>
1
<21> CK_14M_ICH 2 R538 1

R214 R208 33_0402_5%~D
<34> CK_14M_SIO 2 R539 1
2.49K_0603_1%~D 2.49K_0603_1%~D 33_0402_5%~D
10
16
24
34
36
42
48
2
3
<24> CK_14M_CODEC 2 R611 1 U 39
@ 33_0402_5%~D
VDD_3V66
VDD_48
VDD_PCI
VDD_PCI
VDD_SRC
VDD_CPU
VDD_CPU
VDD_REF
C LKREF1 1
C LKREF0 REF_1
2
C597 REF_0
45
@ 10P_0402_50V8J~D VSS_CPU
Close to X'tal pin 2 1 CK_XTAL_IN 4
XTAL_IN C K_CPU2 R488 2 CK_BCLK
47 1 CK_BCLK <7>
CPUCLKT2
1
33_0402_5%~D
1
SL0 SL1 CPU 3V66[0..3] REF0 REF1 SRC USB/Dot X6 R548 1 R472 2
@ 2M_0603_5%~D R_J 49.9_0402_1%~D
0 0 100 66 14.3 14.3 100/200 48 C598 14.31818MHz_20P_1BX14318CC1A~D 1 R473 2
2
@ 10P_0402_50V8J~D 49.9_0402_1%~D
2 1 CK_XTAL_OUT 5 46 C K_CPU2# 1 R489 2 CK_BCLK#
XTAL_OUT CPU_CLKC2 CK_BCLK# <7>
C 0 MID REF REF REF REF REF REF 33_0402_5%~D C
44 C K_CPU1 1 R490 2 CK_ITP
CPUCLKT1 CK_ITP <8>
Place crystal within 33_0402_5%~D
0 1 200 66 14.3 14.3 100/200 48 500 mils of CK409 1 R474 2
CLKSEL0 51 49.9_0402_1%~D
CLKSEL1 56
SEL0
SEL1
CK409
1 0 133 66 14.3 14.3 100/200 48 1 R475 2
49.9_0402_1%~D
43 C K_CPU1# 1 R491 2 CK_ITP#
CPUCLKC1 CK_ITP# <8>
1 1 166 66 14.3 14.3 100/200 48 ICH_SLP_S1# 21 33_0402_5%~D
<21> ICH_SLP_S1# PWRDWN#
H_STP_PCI# 49 41 C K_CPU0 1 R492 2 C K_HCLK
PCI_STP# CPUCLKT0 C K_HCLK <10>
CLK_STP_CPU# 50 33_0402_5%~D
<36> CLK_STP_CPU# CPU_STP#
1 MID Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 1 R476 2
49.9_0402_1%~D
<37> CK_VTT_PG#
CK_VTT_PG# 35
VTT_PWRGD# R 477
Place near CK409
1 2
49.9_0402_1%~D
C K_CPU0# R493 2 C K_HCLK#
Place near CK409 CK_SCLK 28
CPUCLKC0
40 1
33_0402_5%~D
CK_HCLK# <10>
CK_SD ATA SCLK
R479 30 29
SDATA 48/66MHZ_OUT/3V66_4
1 2
+ 3VRUN 27 CLK66M_OUT3 1 R543 2
49.9_0402_1%~D 66MHZ_OUT3/3V66_3 CK_66M_AGP <18>
R485 33_0402_5%~D
1 2 CK_SATA# 37 26
<21> CK_100M_ICH# SRCLKN_100MHZ 66MHZ_OUT2/3V66_2
33_0402_5%~D
1
23 CLK66M_OUT1 1 R547 2
66MHZ_OUT1/3V66_1 CK_66M_MCH <12>
R 192 R478 33_0402_5%~D
1K_0603_1%~D 1 2 22 CLK66M_OUT0 1 R546 2
66MHZ_OUT0/3V66_0 CK_66M_ICH <20>
R484 33_0402_5%~D
49.9_0402_1%~D
1 2 CK_SATA 38 9 PCICLK_F2 1 R540 2
<21> CK_100M_ICH SRCLKP_100MHZ PCICLK_F2 CK_33M_ICHPCI <20>
2
H_STP_PCI# 33_0402_5%~D 33_0402_5%~D

8
PCICLK_F1
+ 3VRUN 2 R501 1 CLK48M_OUT0 31 7
<20> CK_48M_ICH USB_48MHZ PCICLK_F0
33_0402_5%~D
2 R500 1 CLK48M_OUT1 32
<30> CK_48M_SCR DOT_48MHZ
1
33_0402_5%~D 20 PCICLK6 1 R545 2

B PCICLK6 CK_33M_MINIPCI <32> B
R 218 33_0402_5%~D
@ 1K_0603_1%~D R199 19 PCICLK5 1 R542 2
PCICLK5 CK_33M_CBPCI <30>
1 2 52 33_0402_5%~D
IREF
Check SPEC (250mA,300 ohm) 18
PCICLK4
2
475_0603_1%~D
ICH_SLP_S1# L45 15
BLM11A601S_0603~D PCICLK3
1 2 CLK_VDD_PLL 55 14 PCICLK2 1 R541 2
+3VRUN VDD_PLL PCICLK2 CK_33M_LANPCI <28>
33_0402_5%~D
1 1 13 PCICLK1 1 R544 2
PCICLK1 CK_33M_SIOPCI <34>
C166 C550 33_0402_5%~D
PCICLK0
VSS_3V66
VSS_IREF
12 1 2
VSS_SRC
VSS_REF
PCICLK0 CK_33M_CPLD <36>
VSS_PCI
VSS_PCI
10U_1206_6.3V7K~D 0.1U_0402_16V4Z~D
VSS_48
54
2 2 VSS_PLL R587 33_0402_5%~D
CY28409ZCT_TSSOP56~D
6
11
17
25
33
39
53
+ 3VRUN
1
R524 R536
100K_0402_5%~D 100K_0402_5%~D
2
ICH_SM BDATA 1 3 CK_SD ATA

D
<15,16,21,32> ICH_SMBDATA
Q68
2N7002_SOT23~D
G
2
+ 3VRUN
2
G
A Q69 A
ICH_SMBCLK 1 3 2N7002_SOT23~D CK_SCLK
<15,16,21,32> ICH_SMBCLK
D
D
1
G 2 3 S Compal Electronics, Inc.
Title
2N7002 Clock Generator

X02-D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Wednesday, July 23, 2003 Sheet 6 of 60
5 4 3 2 1
5 4 3 2 1
+ VCC_CORE
D D
AC10
AC12
AC14
AC16
AC18
AD11
AD13
AD15
AD17
AD19
AA10
AA12
AA14
AA16
AA18
AB11
AB13
AB15
AB17
AB19
AE10
AE12
AE14
AE16
AE18
AE20
AF11
AF13
AF15
AF17
AF19
AF21
AC8
AD7
AD9
AA8
AB7
AB9
AE6
AE8
AF2
AF5
AF7
AF9
C10
C12
C14
C16
C18
C20
D11
D13
D15
D17
D19
A10
A12
A14
A16
A18
A20
B11
B13
B15
B17
B19
E10
C8
D7
D9
A8
B7
B9
J C P UA
VCC_0
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73
<10> H_A#[3..31] H_D#[0..63] <10>
H_A#3 K2 B21 H _D#0
H_A#4 A#3 D#0 H _D#1
K4 B22
H_A#5 A#4 D#1 H _D#2
L6 A23
H_A#6 A#5 D#2 H _D#3
K1 A25
H_A#7 A#6 D#3 H _D#4
L3 C21
H_A#8 A#7 D#4 H _D#5
M6 D22
H_A#9 A#8 D#5 H _D#6
L2 B24
H_A#10 A#9 D#6 H _D#7
M3 C23
H_A#11 A#10 D#7 H _D#8
M4 C24
H_A#12 A#11 D#8 H _D#9
N1 B25
H_A#13 A#12 D#9 H_D#10
M1 G22
H_A#14 A#13 D#10 H_D#11
N2 H21
H_A#15 A#14 D#11 H_D#12
N4 C26
H_A#16 A#15 D#12 H_D#13
N5 D23
H_A#17 A#16 D#13 H_D#14
T1 J21
H_A#18 A#17 D#14 H_D#15
R2 D25
H_A#19 A#18 D#15 H_D#16
P3 H22
H_A#20 A#19 D#16 H_D#17
P4 E24
H_A#21 A#20 D#17 H_D#18
R3 G23
H_A#22 A#21 D#18 H_D#19
T2 F23
H_A#23 A#22 D#19 H_D#20
U1 F24
H_A#24 A#23 D#20 H_D#21
P6 E25
H_A#25 A#24 D#21 H_D#22
U3 F26
H_A#26 A#25 D#22 H_D#23
T4 D26
H_A#27 A#26 D#23 H_D#24
V2 L21
H_A#28 A#27 D#24 H_D#25
R6 G26
H_A#29 A#28 D#25 H_D#26
W1 H24
H_A#30 A#29 D#26 H_D#27
T5 M21
H_A#31 A#30 D#27 H_D#28
U4 L22
A#31 D#28 H_D#29
V3 J24
A#32 D#29
C
W2
Y1
AB1
A#33
A#34
Prescott D#30
D#31
K23
H25
M23
H_D#30
H_D#31
H_D#32
C
A#35 D#32 H_D#33

N22
D#33 H_D#34
P21
<10> H_REQ#[0..4] H_REQ#0 D#34 H_D#35
J1 M24
H_REQ#1 REQ#0 D#35 H_D#36
K5 N23
J4 M26
J3 N26
H3 N25
REQ#4 D#39 H_D#40
G1 R21
<10> H _ADS# ADS# D#40 H_D#41
P24
D#41 H_D#42
R25
D#42 H_D#43
AC1 R24
R339 AP#0 D#43 H_D#44
V5 T26
@ 62_0402_5% AP#1 D#44 H_D#45
AA3 T25
H _ IERR# BINIT# D#45 H_D#46
+ VCC_CORE 1 2 AC3 T22
IERR# D#46 H_D#47
T23
R371 200_0402_5% D#47 H_D#48
+ VCC_CORE 1 2 U26
D#48 H_D#49
<10> H _BR0# H6 U24
BR0# D#49 H_D#50
<10> H_BPRI# D2 U23
BPRI# D#50 H_D#51
<10> H _ BNR# G2 V25
BNR# D#51 H_D#52
<10> H_LOCK# G4 U21
LOCK# D#52 H_D#53
V22
D#53 H_D#54
V24
CK_BCLK D#54 H_D#55
<6> CK_BCLK AF22 W26
CK_BCLK# BCLK0 D#55 H_D#56
<6> CK_BCLK# AF23 Y26
BCLK1 D#56 H_D#57
W25
D#57 H_D#58
Y23
D#58 H_D#59
Y24
D#59 H_D#60
<10> H_HIT# F3 Y21
HIT# D#60 H_D#61
E3 AA25
BOOTSELECT
<10> H_HITM# HITM# D#61
E2 AA22 H_D#62
<10> H _ DEFER# DEFER# D#62
AA24 H_D#63
D#63
VCC_81
VCC_82
VCC_83
VCC_84
VCC_85
VCC_80
VCC_79
VCC_78
VCC_77
VCC_76
VCC_75
VCC_74
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
H1
H4
H23
H26
A11
A13
A15
A17
A19
A21
A24
A26
A3
A9
AA1
AA11
AA13
AA15
AA17
AA19
AA23
AA26
AA4
AA7
AA9
AB10
AB12
AB14
AB16
AB18
AB20
AB21
AB24
AB3
AB6
AB8
AC11
AC13
AC15
AC17
AC19
AC2
AC22
AC25
AC5
AC7
AC9
AD10
AD12
AD14
AD16
AD18
AD21
AD23
AD4
AD8
AD1
F13
F15
F17
F19
F9
F11
E8
E20
E18
E16
E14
E12
B B
AMP_3-1565030-1_Prescott~D
+VCC_CORE
VCORE_BOOTSELECT <49>
Reference Intel document
Desktop P4 Spec.: 10988 P4 0.13u 512KB L2 EMTS Rev.2.0
Desktop Prescott Spec.: 11910 Prescott EMTS Rev.0.5
Pin number Northwood Comment Prescott Comment Northwood MT Comment Northwood Prescott Northwood
Pin name Pin name Pin name MT
Pull-up 62ohm Connect to PLD
A6 TESTHI11 Pull-up 200ohm TESTHI11 to +VCC_CORE G HI CPUPREF through
to +VCC_CORE 0ohm P op P op P op
B6 FERR# Pull-up 62ohm FERR#/PBE# Pull-up 62ohm FERR#
to +VCC_CORE to +VCC_CORE Pull-up 62ohm P op P op P op
to +VCC_CORE
AA20 ITPCLKOUT0 Pull-up56ohm TESTHI6 Pull-up 62ohm ITPCLKOUT0 Pull-up56ohm
to +VCC_CORE to +VCC_CORE to +VCC_CORE P op P op P op
AB22 ITPCLKOUT1 Pull-up 56ohm TESTHI7 Pull-up 62ohm ITPCLKOUT1 Pull-up 56ohm
to +VCC_CORE to +VCC_CORE to +VCC_CORE P op P op P op
A D2 NC float VIDPWRGD Pull-up 2.43K ohm NC float
to +VCCVID Depop P op Depop
Note: AD2,AD3 pop(bring up)
A D3 NC float VID5 Pull-up1Kohm to NC float
+3VRUN & connect Depop P op Depop
A A
to PWRIC
A F3 NC float VCCVIDLB Connect to +VCCVID NC float Depop P op Depop
AD20 VCCA Connect to CPU VCCIOPLL Connect to CPU VCCA Connect to CPU
Filter Filter Filter
AF23 VCCIOPLL Connect to CPU VCCA Connect to CPU VCCIOPLL Connect to CPU
Filter Filter Filter
AE26 V SS Connect to GND OPTIMIZED/ float V SS Connect to GND

Title
COMPAT# P op Depop P op
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Prescott Processor in uFCPGA478
Pull-up 200ohm Pull-up 62ohm Connect to PLD AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C X02-D
AD25 TESTHI12 to +VCC_CORE TESTHI12 to +VCC_CORE DPSLP through 0ohm P op P op P op
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-1711
Date: Wednesday, July 23, 2003 Sheet 7 of 60
5 4 3 2 1
5 4 3 2 1
+VCC_CORE
+ VCC_CORE
R131 62_0402_5% Place near ICH CPLD Enable
1
1 2 H _ FERR# R 71 T1 Pop R76, R78
R 76
R129 62_0402_5% 1 2 @ P AD @ 200_0402_5%
1 2 H_THERMTRIP#
0_0402_5%~D
AE11
AE13
AE15
AE17
AE19
AE22
AE24
AF10
AF12
AF14
AF16
AF18
AF20
AF26
AE7
AE9
AF1
AF6
AF8
C11
C13
C15
C17
C19
C22
C25
D10
D12
D14
D16
D18
D20
D21
D24
B10
B12
B14
B16
B18
B20
B23
B26
E11
E13
E15
E17
E19
E23
E26
2
F10
F12
F14
F16
F18
F22
F25
R 78 @ 0_0402_5%~D
C2
C5
C7
C9
D3
D6
D8
B4
B8
E1
E4
E7
E9
F2
F5
J C P UB 1 2 H_DPSLP#
<36> DPSLP#
R 111 130_0402_5% Place near CPU
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
SKTOCC#
1 2 H_PROCHOT#
R 87 300_0402_5%~D
<10> H_RS#[0..2]
1 2 H _P WRGOOD H_RS#0 F1 J26
D
H_RS#1 RS#0 DP#0 D
G5 K25
R 84 @ 62_0402_5% H_RS#2 RS#1 DP#1 +CPU_GTLREF
F4 K26
RS#2 DP#2
1 2 H_RESET# AB2 L25
RSP# DP#3
<10> H _ TRDY# J6
TRDY#
AA21 Pop: Northwood
GTLREF0
AA6 Depop: Prescott
GTLREF1
F20 R_G
GTLREF2
<21> H_A20M# C6 F6
H _ FERR# A20M# GTLREF3 R 70 0_0402_5%~D
B6
<21> H _ FERR# FERR#
<21> H _IGNNE# B2 AE26 1 2
IGNNE# OPTIMIZED/COMPAT# +VCC_CORE
<21> H_SMI# B5
H _P WRGOOD SMI#
<21> H _P WRGOOD AB23
PWRGOOD H_T ESTHI0 R 77
<36> H_STPCLK# Y4 AD24 1 2 62_0402_5%
STPCLK# TESTHI0 H_T ESTHI1 R344
AA2 1 2 62_0402_5%
TESTHI1
<21> H_INTR D1 AC21
LINT0 TESTHI2
<21> H_NMI E5 AC20
LINT1 TESTHI3 H_T ESTHI2_7 R 82
<21> H_INIT# W5 AC24 1 2 62_0402_5%
H_RESET# INIT# TESTHI4
<10> H_RESET# AB25 AC23
RESET# TESTHI5
AA20
TESTHI6
AB22
TESTHI7 H_T ESTHI8 R354 62_0402_5%
<10> H _D B SY# H5 U6 1 2
DBSY# TESTHI8 H_T ESTHI9 R350 62_0402_5%
<10> H _D R D Y# H2 W4 1 2 RH
DRDY# TESTHI9 H_T ESTHI10 R347 62_0402_5%
<6> CPU_CLKSEL0 AD6 Y3 1 2 Pop: Prescott
BSEL0 TESTHI10 H_T ESTHI11 R382 62_0402_5%
<6> CPU_CLKSEL1 AD5 A6 1 2
BSEL1 TESTHI11 H_DPSLP# R 79 62_0402_5%
Depop: Northwood MT
AD25 1 2
TESTHI12 H_TESTHI12 R_H
H_THER MDA B3
<19> H_THERMDA H_THERM DC THERMDA R 380 1
C4 2 @ 0_0402_5%~D C P UPREF# <36>
<19> H_THERMDC THERMDC
E22 H_DSTBN#0 <10>
DSTBN#0
+ VCC_CORE
<21,37> H_THERMTRIP#
H_THERMTRIP# A2
THERMTRIP# Prescott DSTBN#1
DSTBN#2
K22
R22
W22
H_DSTBN#1
H_DSTBN#2
<10>
<10>
CPLD Enable
DSTBN#3 H_DSTBN#3 <10>
R 338 1 2 62_0402_5% I TP_BPM#0 AC6 Pop R380
R 341 62_0402_5% I TP_BPM#1 BPM#0
1 2 AB5
R 337 62_0402_5% I TP_BPM#2 BPM#1
1 2 AC4 F21 H_DSTBP#0 <10>
R 346 62_0402_5% I TP_BPM#3 BPM#2 DSTBP#0
1 2 Y6 J23 H_DSTBP#1 <10>
1 2 AA5 P23 H_DSTBP#2 <10>
C 1 2 AB4 W23 H_DSTBP#3 <10>
C
BPM#5 DSTBP#3
10uH, DC current of 100mA parts
and close to cap I TP_TCK D4 L5
TCK ADSTB#0 H_ADSTB#0 <10>
I TP_TDI C1 R5
TDI ADSTB#1 H_ADSTB#1 <10>
I TP_TDO D5
+ VCC_CORE TDO
ITP_TMS F7
ITP_TRST# TMS
E6 E21 H _DINV#0 <10> Closely Pin AE25
L40 10U_LQH31MN100K01_100mA_10%_1206~D TRST# DBI#0
G25 H _DINV#1 <10>
DBI#1
1 2 AD20 P26 H _DINV#2 <10> C660
H _ VCCA VCCIOPLL DBI#2
AE23 V21 H _DINV#3 <10>
VCCA DBI#3
1 2 1
A5 AE25 ITP_DBRESET#
<46> V CCSENSE VCCSENSE DBR# ITP_DBRESET# <37>
+ C 368 A4 @ 1000P_0402_50V7K~D
33U_D2_8M_R35~D <46> VSSSENSE VSSSENSE
+ VCCVID 1 2 AF3
VCCVIDLB H_PROCHOT#
R333 0_0402_5%~D C3 H_PROCHOT# <10>
2 H_VSSA PROCHOT#
1 2 AD22 V6
VSSA MCERR#
R_D AB26 H_CPUSLP# <36>
L41 10U_LQH31MN100K01_100mA_10%_1206~D SLP#
CK_ITP_CPU AC26 A22 + VCC_CORE
CK_ITP_CPU# ITP_CLK0 NC1
AD26 A7
ITP_CLK1 NC2 R 83
Pop: Prescott AF25 1 2 @ 62_0402_5%
NC3
PLL Layout note : Depop: Northwood L24
COMP0 NC4
AF24
P1 AE21
VIDPWRGD
COMP1 NC5
1.Place cap within 600 mils of
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VCCVID
the VCCA and VSSA pins.
1
VID0
VID1
VID2
VID3
VID4
VID5
2.H_VCCIOPLL,HVCCA,HVSSA trace wide R 97 R349 RE
12 mils(min) 61.9_0603_1% 61.9_0603_1% Pop: Prescott
Depop: Northwood
F8
G21
G24
G3
G6
J2
J22
J25
J5
K21
K24
K3
K6
L1
L23
L26
L4
M2
M22
M25
M5
N21
N24
N3
N6
P2
P22
P25
P5
R1
R23
R26
R4
T21
T24
T3
T6
U2
U22
U25
U5
V1
V23
V26
V4
W21
W24
W3
W6
Y2
Y22
Y25
Y5
AE5
AE4
AE3
AE2
AE1
AD3
AD2
AF4
R_E
2
AMP_3-1565030-1_Prescott~D + VCCVID
R N9
+ VCCVID
CK_ITP 4 1 CK_ITP_CPU R336
CK_ITP# 3 2 CK_ITP_CPU# 681_0603_1%
+3VSUS 1 2
0_4P2R_0404_5%~D
B R152 C 131 B
H _V ID_PWRGD
+3VSUS 1 2 1 2
R N8
CK_ITP# 4 1 CK_I TP_JITP# 10K_0402_5%~D
<6> CK_ITP# 0.1U_0402_16V4Z~D <36> H _VID0
5
CK_ITP 3 2 CK_ITP_JITP U 6A
<6> CK_ITP <36> H _VID1 +3VRUN
P
@ 0_4P2R_0404_5%~D +VCC_CORE H _V ID_PWRGD <36> H _VID2

<46> VI D _PWRGD 1 6
I O <36> H _VID3
<36> H _VID4
G
R 37 1K_0402_5%~D
SN74LVC2G07DBVR_SOT23-6~D <36> H _VID5 V ID5 1 2
<36,46> V ID5
2
+3VSUS R 35 1K_0402_5%~D
1
C 386 V ID4 1 2
R155 10K_0402_5%~D <36,46> V ID4
29
0.1U_0402_10V6K~D JITP U 6B 1 2 +3VSUS V ID3 5 4

2 <36,46> V ID3 V ID2 6 3
GND6
<36,46> V ID2 V ID1

28 3 4 VCORE_ENLL <46> 7 2
VTT1 I O <36,46> V ID1 V ID0
27 C121 8 1
+VCC_CORE VTT0 <36,46> V ID0
G
26
R363 ITP_DBRESET# VTAP SN74LVC2G07DBVR_SOT23-6~D RN7 1K_8P4R_1206_5%~D
25
DBR#
Level shift 1 2
GTL Reference Voltage
2
54.9_0603_1%~D 24
I TP_TDO I TP_BPM#0 DBA#
1 2 23
BPM0# 0.1U_0402_16V4Z~D Layout note :
R358 22
GND5
54.9_0603_1%~D I TP_BPM#1 21
BPM1#
1. +CPU_GTLREF Trace wide
1 2 H_RESET# 20
GND4 +CPU_GMCH_GTLREF + VCC_CORE 12mils(min),Space 15mils
I TP_BPM#2 19
BPM2#
18
GND3 2. Place R_A and R_B near CPU. B_VID5 B_VID4 B_VID3 B_VID2 B_VID1 B_VID0
Close to the ITP I TP_BPM#3 17 3. Place decoupling cap 220PF near CPU. O PEN O PEN O PEN OP EN O PEN O PEN
BPM3#
2
16
GND2
1
I TP_BPM#4 15 +CPU_GMCH_GTLREF trace
2
R361 BPM4# R357
14 wide 12mils(min),Space
+ VCC_CORE 150_0402_5%~D I TP_BPM#5 GND1 +CPU_GTLREF
13 R_A
H_RESET# 1 BPM5# 15mils 200_0603_1%~D
2 12
R377 I TP_TCK RESET#
11
FBO
2
@ 47_0402_5%~D 10 2 1
ITP_TMS R364 CK_ITP_JITP GND0
2 1 9
BCLKP
1
47_0402_5%~D CK_I TP_JITP# 8 R 340
BCLKN
1
R108 150_0402_5%~D I TP_TDO 1 2 7 2 0_0603_5%~D 1

TDO
1
A 1 2 I TP_TDI 6 R356 C369 A
I TP_TCK NC2 C372 @ @ @ @ @ @
1 2 5 R_B
I TP_TCK R370 27.4_0603_1%~D TCK 169_0603_1% 0.1U_0402_16V4Z~D 220P_0402_50V7K
2 1 4
ITP_TRST# NC1 1 2
3
TRST#
2
R379 @47_0402_5%~D + VCC_CORE 1 2 ITP_TMS 2

TMS
GND7
I TP_TDI 1
R376 TDI
Close to the CPU
39.2_0603_1%~D
@ MOLEX_52435-2891_28P~D
30
R381 Close to the ITP

680_0402_5%~D
1 2 ITP_TRST#
Title
Between the CPU and ITP Prescott Processor in uFCPGA478
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-1711 X02-D
5 4 3 2 1
5 4 3 2 1
Place 11 North of Socket(Stuff 6)

+VCC_CORE
1 1 1 1 1 1 1 1
C 31 C 27 C 28 C 29 C 32 C 30 C 77 C331 Note:For PT-phase
22U_1206_6.3VAM~D @ 22U_1206_6.3VAM~D 22U_1206_6.3VAM~D 22U_1206_6.3VAM~D @ 22U_1206_6.3VAM~D 22U_1206_6.3VAM~D @ 22U_1206_6.3VAM~D @ 22U_1206_6.3VAM~D
2 2 2 2 2 2 2 2
22uF depop reference
Springdale Chipset Platform Design Guide Rev1.2(12837)
D D
Inside the socket cavity 12 pcs (all stuffed)
North side 12pcs (4 sites stuffed)
Delete south side
22uF depop reference
Place 12 Inside Socket(Stuff all) Springdale Chipset Platform Design Guide Rev1.11(12474)
+VCC_CORE
1 1 1 1 1 1 1 1 1 1
C 46 C 56 C 55 C 45 C394 C403 C 404 C412 C395 C382
22U_1206_6.3VAM~D 22U_1206_6.3VAM~D 22U_1206_6.3VAM~D 22U_1206_6.3VAM~D 22U_1206_6.3VAM~D 22U_1206_6.3VAM~D 22U_1206_6.3VAM~D 22U_1206_6.3VAM~D 22U_1206_6.3VAM~D 22U_1206_6.3VAM~D
2 2 2 2 2 2 2 2 2 2
+VCC_CORE
1 1
C381 C 411
22U_1206_6.3VAM~D 22U_1206_6.3VAM~D
2 2
C C
Place 9 South of Socket(Unstuff all)

+VCC_CORE
1 1 1 1 1 1 1 1
C 76 C 71 C 72 C 75 C 69 C 70 C 73 C 74
@ 22U_1206_6.3VAM~D @22U_1206_6.3VAM~D @ 22U_1206_6.3VAM~D @ 22U_1206_6.3VAM~D @ 22U_1206_6.3VAM~D @ 22U_1206_6.3VAM~D @ 22U_1206_6.3VAM~D @ 22U_1206_6.3VAM~D
2 2 2 2 2 2 2 2
B B
470uF _ERS10m ohm* 15, ESR=0.5m ohm

+ VCC_CORE
1 1 1 1 1 1
+ C 303 + C302 + C304 + C301 + C300 + C 305
470U_D4_2.5V_R10M~D 470U_D4_2.5V_R10M~D 470U_D4_2.5V_R10M~D @470U_D4_2.5V_R10M~D 470U_D4_2.5V_R10M~D 470U_D4_2.5V_R10M~D
2 2 2 2 2 2
+ VCC_CORE
1 1 1 1 1 1
+ C 299 + C294 + C298 + C296 + C295 + C 297
@470U_D4_2.5V_R10M~D 470U_D4_2.5V_R10M~D 470U_D4_2.5V_R10M~D @470U_D4_2.5V_R10M~D 470U_D4_2.5V_R10M~D @ 470U_D4_2.5V_R10M~D
2 2 2 2 2 2
+VCC_CORE Decoupling Reference Document:

Springdale Chipset Platform Design guide Rev1.11
(12474)page239
A A
1 1 1
Decoupling Reference Requirement:
+ C 68 + C423 + C422
470U_D4_2.5V_R10M~D @ 470U_D4_2.5V_R10M~D 470U_D4_2.5V_R10M~D 560uF Polymer, ESR:5m ohm(each) * 10
2 2 2 22uF X5R * 32
Title
CPU Decoupling
5 4 3 2 1
5 4 3 2 1
U 3F
<7> H_A#[3..31] H_D#[0..63] <7>
U 3A AR32 AE11 U 3G
H_A#3 H _D#0 VSS VSS
D26 B23 AR29 AE10 L31 F16
H_A#4 HA3# HD0# H _D#1 VSS VSS VSS VSS
D30 E22 AR27 AE4 L26 F14
D
H_A#5 HA4# HD1# H _D#2 VSS VSS VSS VSS D
L23 B21 AR25 AE1 L25 F12
E29 D20 AR23 AD33 L24 F10
B32 B22 AR20 AD30 K33 F8
K23 D22 AR16 AD28 K29 F5
C30 B20 AR13 AD10 K27 F3
C31 C21 AR11 AD9 K25 F1
J25 E18 AR9 AD8 K22 E3
B31 E20 AN32 AD6 K20 E1
H_A#13 HA12# HD9# H_D#10 VSS VSS VSS VSS
E30 B16 AN30 AD3 K18 D35
B33 D16 AN28 AC35 K16 D33
J24 B18 AN26 AC32 K14 D31
F25 B17 AN24 AC4 K12 D29
D34 E16 AN22 AC1 K11 D27
C32 D18 AN20 AB33 J35 D25
F28 G20 AN18 AB30 J32 D23
C34 F17 AN16 AB28 J28 D21
J27 E19 AN14 AB27 J22 D19
G27 F19 AN12 AB26 J20 D17
F29 J17 AN10 AB10 J18 D15
E28 L18 AM35 AB9 J16 D13
H27 G16 AM29 AB8 J14 D11
GND
K24 G18 + 3VRUN AM27 AB6 J12 D9
E32 F21 AM25 AB3 J10 D1
F31 F15 AM23 AA32 H33 C28
G30 E15 AM21 AA4 H30 C26
J26 E21 AM19 AA1 H26 C24
HA30# HD27# VSS VSS VSS VSS
1
H_A#31 G26 J19 H_D#28 AM17 Y35 H24 C22
HA31# HD28# H_D#29 R 90 VSS VSS VSS VSS
G14 AM15 Y33 H22 C20
HD29# H_D#30 1.24K_0402_1%~D VSS VSS VSS VSS
E17 AM13 Y30 H20 C18
<7> H_REQ#[0..4] H_REQ#0 HD30# H_D#31 VSS VSS VSS VSS
B29 K17 AM11 Y28 H18 C16
H_REQ#1 HREQ0# HD31# H_D#32 VSS VSS VSS VSS
J23 J15 AM9 Y27 H16 C14
HREQ1# HD32# VSS VSS VSS VSS
2
H_REQ#2 L22 L16 H_D#33 AL32 Y26 H14 C12
C29 J13 H_PROCHOT_SIO# <34> AL1 Y10 H12 C10
J21 F13 AK28 Y9 H9 C8
HREQ4# HD35# H_D#36 VSS VSS VSS VSS
B30 F11 AK26 Y8 H8 C4
<8> H_ADSTB#0 HADSTB0# HD36# VSS VSS VSS VSS
1
D28 E13 H_D#37 Q24 R 91 10K_0402_5%~D AK24 Y6 H5 A32
<8> H_ADSTB#1 HADSTB1# FSB HD37# H_D#38 VSS VSS VSS VSS
K15 2 1 2 + VCC_CORE AK22 Y3 H2 A29
HD38# H_D#39 VSS VSS VSS VSS
C
<6> C K_HCLK B7 G12 AK20 W32 G35 A27 C
HCLKP HD39# H_D#40 MMBT3904_SOT23~D VSS VSS VSS VSS
<6> CK_HCLK# C7 G10 AK18 W18 G31 A25
HCLKN HD40# VSS VSS VSS VSS
GND
L15 H_D#41 AK16 W17 G28 A23
HD41# C 670 VSS VSS VSS VSS
B19 E11 H_D#42 AK14 W4 F26 A20
<8> H_DSTBP#0 HDSTBP0# HD42# H_D#43 VSS VSS VSS VSS
C19 K13 2 1 AK12 V33 F24 A16
<8> H_DSTBN#0 HDSTBN0# HD43# H_D#44 VSS VSS VSS VSS
<8> H _DINV#0 C17 J11 AK10 V30 F22 A13
DINV0# HD44# H_D#45 VSS VSS VSS VSS
L19 H10 AK8 V28 F20 A11
<8> H_DSTBP#1 HDSTBP1# HD45# H_D#46 100P_0402_50V8J~D VSS VSS VSS VSS
K19 G8 AK3 V27 F18 A9
<8> H_DSTBN#1 HDSTBN1# HD46# H_D#47 VSS VSS VSS VSS
<8> H _DINV#1 L17 E9 AJ35 V26 A7
DINV1# HD47# H_D#48 VSS VSS VSS
G9 B13 AJ32 V19
<8> H_DSTBP#2 HDSTBP2# HD48# H_D#49 VSS VSS RG828SDGES_FCBGA932_SPRINGDALE~D
F9 E14 AJ9 V17
<8> H_DSTBN#2 HDSTBN2# HD49# H_D#50 H_PROCHOT# VSS VSS
<8> H _DINV#2 L14 B14 Settig CPU Output H_PROCHOT# <8> AJ4 V10
DINV2# HD50# H_D#51 VSS VSS
D12 B12 AJ1 V9
<8> H_DSTBP#3 HDSTBP3# HD51# H_D#52 VSS VSS
E12 B15 R605 AH33 V8
<8> H_DSTBN#3 HDSTBN3# HD52# H_D#53 VSS VSS
<8> H _DINV#3 C15 D14 AH30 V6
DINV3# HD53# H_D#54 VSS VSS
C13 1 2 VCORE_PHOT# <34,46> AH24 V3
HD54# H_D#55 VSS VSS
<7> H_ADS# F27 B11 AH22 U32
ADS# HD55# H_D#56 @ 0_0402_5%~D VSS VSS
D24 D10 AH20 U19
<8> H _ TRDY# HTRDY# HD56# H_D#57 VSS VSS
<8> H _D R D Y# G24 C11 AH18 U18
DRDY# HD57# H_D#58 VSS VSS
L21 E10 AH16 U4
<7> H _DEFER# DEFER# HD58# H_D#59 VSS VSS
<7> H_HITM# E23 B10 AH14 T35
HITM# HD59# H_D#60 VSS VSS
<7> H_HIT# K21 C9 AH12 T33
HIT# HD60# H_D#61 VSS VSS
<7> H_LOCK# E25 B9 AH10 T30
HLOCK# HD61# H_D#62 VSS VSS
B24 D8 AH6 T28
<7> H_BR0# BREQ0# HD62# H_D#63 VSS VSS
<7> H _ BNR# B28 B8 AH3 T27
BNR# HD63# VSS VSS
B26 R608 AG35 T26
<7> H_BPRI# BPRI# VSS VSS
<8> H _D BSY# E27 AG32 T10
H_RS#0 DBSY# H_PROCHOT# VSS VSS
G22 L20 1 2 AG28 T9
H_RS#1 RS0# PROCHOT# VSS VSS
C27 AG26 T8
H_RS#2 RS1# 0_0402_5%~D VSS VSS
B27 AG24 T6
RS2# VSS VSS
<8> H_RS#[0..2] E8 L13 MCH_CLKSEL0 <6> AG22 T3
<8> H_RESET# CPURST# BSEL0 VSS VSS
<21,37> PW RGD_3V AE14 L12 MCH_CLKSEL1 <6> AG20 T1
PWROK# BSEL1 VSS VSS
AG18 R32
H D RCOMP VSS VSS
E24 AG16 R4
H D _ SWING HDRCOMP VSS VSS
C25 AG14 R1
HDSWING VSS VSS
+GMCH_GTLREF F23 AG8 P33
HDVREF VSS VSS
AG4 P30
RG828SDGES_FCBGA932_SPRINGDALE~D VSS VSS
AF33 P28
B VSS VSS B
AF30 P27
VSS VSS
AF25 P26
VSS VSS
AF24 P9
VSS VSS
AF22 P8
VSS VSS
AF20 P6
VSS VSS
AF18 P3
+VTT_GMCH VSS VSS
Follow Intel design guide R1.11(12474) page80 AF16 N35
VSS VSS
AF14 N32
VSS VSS
AF11 N4
VSS VSS
AF9 N1
VSS VSS
GTL Reference Voltage AF6
VSS VSS
M33
1
AF3 M30
R331 VSS VSS
Layout note : AE35
VSS VSS
M28
301_0402_1%~D AE32 M27
VSS VSS
Trace width 12mils,Space 1. +GMCH_GTLREF Trace wide AE26
VSS VSS
M26
10mils 12mils(min),Space 15mils. AE25 M6
VSS VSS
2
AE13 M3
VSS VSS
H D _ SWING 2. Place decoupling cap 220PF near GMCH. AE12
VSS VSS
L35
+CPU_GMCH_GTLREF +VTT_GMCH
1 RG828SDGES_FCBGA932_SPRINGDALE~D
1
C365
R332
102_0402_1%~D 0.01U_0402_16V7K~D +GMCH_GTLREF
2
1
R 323
2
200_0603_1%~D
2
R329
2 1
Trace width 10mils,Space
7mils 0_0603_5%~D
H D RCOMP 1
C366
220P_0402_50V7K
2
1
A R335 A
20_0603_1%~D
2
Create
Title
Springdale-Host/GND
LA-1711 X02-D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Thursday, July 24, 2003 Sheet 10 of 60
5 4 3 2 1
5 4 3 2 1
DDRA_SDQ[0..63]
DDRA_SDQ[0..63] <15,17> DDRB_SDQ[0..63]
DDRB_SDQ[0..63] <16,17>
DDRA_SMA[0..12]
<15,17> DDRA_SMA[0..12] U 3B DDRB_SMA[0..12] U 3C
DDRA_SMA0 <16,17> DDRB_SMA[0..12]
AJ34 AN11 D D RA_SDQS0 <15,17>
DDRA_SMA1 SMAA_A0 SDQS_A0 DDRB_SMA0
AL33 AP12 DDRA_SDM0 <15,17> AG31 AF15 D DRB_SDQS0 <16,17>
DDRA_SMA2 SMAA_A1 SDM_A0 D D RA_SDQ0 DDRB_SMA1 SMAA_B0 SDQS_B0
AK29 AP10 AJ31 AG11 DDRB_SDM0 <16,17>
DDRA_SMA3 SMAA_A2 SDQ_A0 D D RA_SDQ1 DDRB_SMA2 SMAA_B1 SDM_B0 D D RB_SDQ0
AN31 AP11 AD27 AJ10
DDRA_SMA4 SMAA_A3 SDQ_A1 D D RA_SDQ2 DDRB_SMA3 SMAA_B2 SDQ_B0 D D RB_SDQ1
AL30 AM12 AE24 AE15
D
DDRA_SMA5 SMAA_A4 SDQ_A2 D D RA_SDQ3 DDRB_SMA4 SMAA_B3 SDQ_B1 D D RB_SDQ2 D
AL26 AN13 AK27 AL11
AL28 AM10 AG25 AE16
AN25 AL10 AL25 AL8
AP26 AL12 AF21 AF12
AP24 AP13 AL23 AK11
DDRA_SM A10 SMAA_A9 SDQ_A7 DDRB_SMA9 SMAA_B8 SDQ_B6 D D RB_SDQ7
AJ33 AJ22 AG12
DDRA_SM A11 SMAA_A10 DDRB_SM A10 SMAA_B9 SDQ_B7
AN23 AP15 D D RA_SDQS1 <15,17> AF29
DDRA_SM A12 SMAA_A11 SDQS_A1 DDRB_SM A11 SMAA_B10
AN21 AP16 DDRA_SDM1 <15,17> AL21 AG13 D DRB_SDQS1 <16,17>
SMAA_A12 SDM_A1 DDRB_SM A12 SMAA_B11 SDQS_B1
AJ20 AG15 DDRB_SDM1 <16,17>
D D RA_SDQ8 SMAA_B12 SDM_B1
AL34 AP14
SMAB_A1 SDQ_A8 D D RA_SDQ9 D D RB_SDQ8
AM34 AM14 AE27 AE17
SMAB_A2 SDQ_A9 D DRA_SDQ10 SMAB_B1 SDQ_B8 D D RB_SDQ9
AP32 AL18 AD26 AL13
SMAB_A3 SDQ_A10 D DRA_SDQ11 SMAB_B2 SDQ_B9 D DRB_SDQ10
AP31 AP19 AL29 AK17
AM26 AL14 AL27 AL17
AN15 AE23 AK13
SDQ_A13 D DRA_SDQ14 SMAB_B5 SDQ_B12 D DRB_SDQ13
DDR Channel A
DDR Channel B
AB34 AP18 AJ14
<15,17> D D RA_SWE# SWE_A# SDQ_A14 D DRA_SDQ15 SDQ_B13 D DRB_SDQ14
Y34 AM18 W27 AJ16
<15,17> D DRA_SCAS# SCAS_A# SDQ_A15 <16,17> D D RB_SWE# SWE_B# SDQ_B14 D DRB_SDQ15
AC33 W31 AJ18
<15,17> D DRA_SRAS# SRAS_A# <16,17> D DRB_SCAS# SCAS_B# SDQ_B15
AP23 D D RA_SDQS2 <15,17> W26
SDQS_A2 <16,17> D DRB_SRAS# SRAS_B#
AE33 AM24 DDRA_SDM2 <15,17> AG21 D DRB_SDQS2 <16,17>
<15,17> DDRA_SBS0 SBA_A0 SDM_A2 SDQS_B2
AH34 AE21 DDRB_SDM2 <16,17>
<15,17> DDRA_SBS1 SBA_A1 D DRA_SDQ16 SDM_B2
AP22 Y25
D DRA_SCS#0 SDQ_A16 D DRA_SDQ17 <16,17> DDRB_SBS0 SBA_B0 D DRB_SDQ16
AA34 AM22 AA25 AE19
<15,17> D DRA_SCS#0 D DRA_SCS#1 SCS_A0# SDQ_A17 D DRA_SDQ18 <16,17> DDRB_SBS1 SBA_B1 SDQ_B16 D DRB_SDQ17
Y31 AL24 AE20
<15,17> D DRA_SCS#1 SCS_A1# SDQ_A18 D DRA_SDQ19 D DRB_SCS#0 SDQ_B17 D DRB_SDQ18
Y32 AN27 U26 AG23
SCS_A2# SDQ_A19 D DRA_SDQ20 <16,17> DDRB_SCS#0 D DRB_SCS#1 SCS_B0# SDQ_B18 D DRB_SDQ19
W34 AP21 T29 AK23
SCS_A3# SDQ_A20 D DRA_SDQ21 <16,17> DDRB_SCS#1 SCS_B1# SDQ_B19 D DRB_SDQ20
AL22 V25 AL19
D DRA_CKE0 SDQ_A21 D DRA_SDQ22 SCS_B2# SDQ_B20 D DRB_SDQ21
AL20 AP25 W25 AK21
<15,17> D DRA_CKE0 D DRA_CKE1 SCKE_A0 SDQ_A22 D DRA_SDQ23 SCS_B3# SDQ_B21 D DRB_SDQ22
AN19 AP27 AJ24
<15,17> D DRA_CKE1 SCKE_A1 SDQ_A23 D DRB_CKE0 SDQ_B22 D DRB_SDQ23
AM20 AK19 AE22
SCKE_A2 <16,17> D DRB_CKE0 D DRB_CKE1 SCKE_B0 SDQ_B23
AP20 AM30 D D RA_SDQS3 <15,17> AF19
SCKE_A3 SDQS_A3 <16,17> D DRB_CKE1 SCKE_B1
AP30 DDRA_SDM3 <15,17> AG19 AH27 D DRB_SDQS3 <16,17>
SDM_A3 SCKE_B2 SDQS_B3
AK32 AE18 AJ28 DDRB_SDM3 <16,17>
<15> D DRA_CLK0 SCMDCLK_A0 D DRA_SDQ24 SCKE_B3 SDM_B3
AK31 AP28
<15> DDRA_CLK0# SCMDCLK_A0# SDQ_A24 D DRA_SDQ25 D DRB_SDQ24
AP17 AP29 AG29 AK25
<15> D DRA_CLK1 SCMDCLK_A1 SDQ_A25 D DRA_SDQ26 <16> D DRB_CLK0 SCMDCLK_B0 SDQ_B24 D DRB_SDQ25
AN17 AP33 AG30 AH26
<15> DDRA_CLK1# SCMDCLK_A1# SDQ_A26 D DRA_SDQ27 <16> DDRB_CLK0# SCMDCLK_B0# SDQ_B25 D DRB_SDQ26
N33 AM33 AF17 AG27
<15> D DRA_CLK2 SCMDCLK_A2 SDQ_A27 D DRA_SDQ28 <16> D DRB_CLK1 SCMDCLK_B1 SDQ_B26 D DRB_SDQ27
C N34 AM28 AG17 AF27 C
<15> DDRA_CLK2# SCMDCLK_A2# SDQ_A28 D DRA_SDQ29 <16> DDRB_CLK1# SCMDCLK_B1# SDQ_B27 D DRB_SDQ28
AK33 AN29 N27 AJ26
SCMDCLK_A3 SDQ_A29 D DRA_SDQ30 <16> D DRB_CLK2 SCMDCLK_B2 SDQ_B28 D DRB_SDQ29
AK34 AM31 N26 AJ27
SCMDCLK_A3# SDQ_A30 D DRA_SDQ31 <16> DDRB_CLK2# SCMDCLK_B2# SDQ_B29 D DRB_SDQ30
AM16 AN34 AJ30 AD25
SCMDCLK_A4 SDQ_A31 SCMDCLK_B3 SDQ_B30 D DRB_SDQ31
AL16 AH29 AF28
SM_VREF_A SCMDCLK_A4# SCMDCLK_B3# SDQ_B31
SM_VREF_A trace width of 12mils and space P31 AF34 D D RA_SDQS4 <15,17> AK15
SCMDCLK_A5 SDQS_A4 +2.5V_MEM SM_VREF_B SCMDCLK_B4
12mils(min) P32 AF31 DDRA_SDM4 <15,17> AL15 AD29 D DRB_SDQS4 <16,17>
SCMDCLK_A5# SDM_A4 SCMDCLK_B4# SDQS_B4
SM_VREF_B trace width of N31 AC31 DDRB_SDM4 <16,17>
D DRA_SDQ32 SCMDCLK_B5 SDM_B4
E34 AH32 12mils and space N30
SMVREF_A SDQ_A32 D DRA_SDQ33 SCMDCLK_B5# D DRB_SDQ32
AG34 AE30
SMXRCOMP SDQ_A33 D DRA_SDQ34
12mils(min) SDQ_B32 D DRB_SDQ33
AK9 AF32 2 AP9 AC27
SMXRCOMP SDQ_A34 D DRA_SDQ35 C 62 SMVREF_B SDQ_B33 D DRB_SDQ34
2 2 AD32 AC30
C 48 C 47 SMXRCOMPVOH SDQ_A35 D DRA_SDQ36 SMYRCOMP SDQ_B34 D DRB_SDQ35
AN9 AH31 AA33 Y29
SMXRCOMPVOH SDQ_A36 SMYRCOMP SDQ_B35
1
AG33 D DRA_SDQ37 2.2U_0805_16VFZ~D AE31 D DRB_SDQ36
2.2U_0805_16VFZ~D 0.1U_0402_16V4Z~D SM XRCOMPVOL SDQ_A37 D DRA_SDQ38 R104 1 SMYRCOMPVOH SDQ_B36 D DRB_SDQ37
AL9 AE34 R34 AB29
1 1 SMXRCOMPVOL SDQ_A38 D DRA_SDQ39 SMYRCOMPVOH SDQ_B37 D DRB_SDQ38
AD34 AA26
SDQ_A39 150_0603_1%~D SMYRCOMPVOL SDQ_B38 D DRB_SDQ39
R33 AA27
SMYRCOMPVOL SDQ_B39
V34 D D RA_SDQS5 <15,17>
SDQS_A5
2
Close to GMCH W33 DDRA_SDM5 <15,17> U30 D DRB_SDQS5 <16,17>
SDM_A5 SDQS_B5
U31 DDRB_SDM5 <16,17>
D DRA_SDQ40 SDM_B5
AC34
SDQ_A40 D DRA_SDQ41 D DRB_SDQ40
AB31 2 2 AA30
SDQ_A41 SDQ_B40
1
V32 D DRA_SDQ42 C 52 C 50 W30 D DRB_SDQ41
SDQ_A42 D DRA_SDQ43 R100 SDQ_B41 D DRB_SDQ42
V31 U27
SDQ_A43 D DRA_SDQ44 2.2U_0805_16VFZ~D 0.1U_0402_16V4Z~D SDQ_B42 D DRB_SDQ43
AD31 T25
SDQ_A44 D DRA_SDQ45 150_0603_1%~D 1 1 SDQ_B43 D DRB_SDQ44
AB32 AA31
SDQ_A45 D DRA_SDQ46 SDQ_B44 D DRB_SDQ45
U34 V29
SDQ_A46 SDQ_B45
2
U33 D DRA_SDQ47 U25 D DRB_SDQ46
SDQ_A47 SDQ_B46 D DRB_SDQ47
Close to GMCH R27
SDQ_B47
M32 D D RA_SDQS6 <15,17>
SDQS_A6
M34 DDRA_SDM6 <15,17> L27 D DRB_SDQS6 <16,17>
+2.5V_MEM SDM_A6 SDQS_B6
M29 DDRB_SDM6 <16,17>
D DRA_SDQ48 SDM_B6
T34
SDQ_A48 D DRA_SDQ49 +2.5V_MEM D DRB_SDQ48
Trace width of 12mils and space T32 P29
10mils(min) K34 R30
K32 K28
T31 L30
SDQ_A52 SDQ_B51
1
P34 D DRA_SDQ53 2 R31 D DRB_SDQ52

B
R372 SDQ_A53 D DRA_SDQ54 C 66 SDQ_B52 D DRB_SDQ53 B
L34 R26
SDQ_A54 SDQ_B53
1
42.2_0603_1%~D L33 D DRA_SDQ55 P25 D DRB_SDQ54
SDQ_A55 R110 2.2U_0805_16VFZ~D SDQ_B54 D DRB_SDQ55
L32
42.2_0603_1%~D 1 SDQ_B55
2 H31 D D RA_SDQS7 <15,17>
SDQS_A7
2
C 64 H32 J30
SDM_A7 DDRA_SDM7 <15,17> SDQS_B7 D DRB_SDQS7 <16,17>
SMXRCOMP J31
SDM_B7 DDRB_SDM7 <16,17>
2
2.2U_0805_16VFZ~D J33 D DRA_SDQ56 Trace width of 12mils
1 SDQ_A56 D DRA_SDQ57 SMYRCOMP D DRB_SDQ56
H34 and space 10mils(min) K30
E33 H29
SDQ_A58 SDQ_B57
1
F33 D DRA_SDQ59 F32 D DRB_SDQ58

R367 SDQ_A59 D DRA_SDQ60 SDQ_B58 D DRB_SDQ59
K31 G33
SDQ_A60 SDQ_B59
1
42.2_0603_1%~D J34 D DRA_SDQ61 N25 D DRB_SDQ60
SDQ_A61 D DRA_SDQ62 R109 SDQ_B60 D DRB_SDQ61
G34 M25
SDQ_A62 D DRA_SDQ63 42.2_0603_1%~D SDQ_B61 D DRB_SDQ62
F34 J29
SDQ_A63 SDQ_B62
2
G32 D DRB_SDQ63
RG828SDGES_FCBGA932_SPRINGDALE~D SDQ_B63
2
RG828SDGES_FCBGA932_SPRINGDALE~D
+2.5V_MEM
+2.5V_MEM
Trace width of 12mils and space

+2.5V_MEM 10mils(min)
+2.5V_MEM Trace width of 12mils and space 2
1
10mils(min) C 59
1
Trace width of 12mils and space 2 1 R106
10mils(min) C 53 R102 2.2U_0805_16VFZ~D 30.9K_0603_1%~D
Trace width of 12mils and space C636 10K_0603_1%~D 1 *
2
1
2 1 C 63 10mils(min) 2.2U_0805_16VFZ~D 0.01U_0402_16V7K~D
2
1 2
1
C 65 R374 SMYRCOMPVOL
2
C637 10K_0603_1%~D 2.2U_0805_16VFZ~D R 373 SMYRCOMPVOH
2.2U_0805_16VFZ~D 0.01U_0402_16V7K~D 1 30.9K_0603_1%~D
1 2
1
* 1 1 1
2
1
SMXRCOMPVOH 1 R105
2
SM XRCOMPVOL C 57 R101 C 61 10K_0603_1%~D C 58

A 1 1U_0603_6.3V6M~D 30.9K_0603_1%~D C 54 1U_0603_6.3V6M~D 0.01U_0402_16V7K~D A
2 2 2
1
1 1 * 0.01U_0402_16V7K~D
2
2
1
C406 R369 1
2
1U_0603_6.3V6M~D 30.9K_0603_1%~D C400 C407 R 368
2 1U_0603_6.3V6M~D 10K_0603_1%~D C 401
* 0.01U_0402_16V7K~D
2 2 Close to GMCH <1" Close to GMCH <1"
0.01U_0402_16V7K~D
2
2
2
Close to GMCH <1" Close to GMCH <1"

Follow Intel design guide
Title
R1.11(12474) page124,125
Note: Intel recommend is 31.12K,the value isn't popularize.
Follow Dell's DT team use 30.9K
Springdale-DDR Interface
LA-1711 X02-D
5 4 3 2 1
5 4 3 2 1
+1.5VRUN +12V +1.5VRUN Note:

AGP_SWING_MCH, trace width of
12mils and space 10mils
1
+1.5VRUN
R 48 R 59
1
8.2K_0402_5%~D 60.4_0603_1% Close GMCH ball less than 250mils
R 45
8.2K_0402_5%~D
R 55
2
1
AGP_SWING
R 64 GC_DET_R EF 1 2
2
43.2_0603_1%~D 2 1
1
39.2_0603_1%~D C 38 C362
R 58
2
1
Q10 D 39.2_0603_1%~D 0.1U_0402_16V4Z~D 0.01U_0402_16V7K~D
GRCOMP 2 2 1 2
<18> AGP8X_DET_GC
G Q13
R 66
2
MMBT3904_SOT23~D S 2N7002_SOT23~D 2 1 0_0402_5%~D
VR EFGC <18>
3
+1.5VRUN VR EFCG
D VR E FCG <18> D
1 2 2 Follow Springdale Chipset Platform Design guide Rev1.11(12474)

R 57 100_0603_1%~D
1
C361
R328 Close to VGA Conn. 2 1 0.01U_0402_16V7K~D Note:
1
Springdale Customer Schematic R1.2 page18
52.3_0603_1%~D C385 0.1U_0402_16V4Z~D
AGP_SWING only had 0.1u cap ; But Springdale Chipset Platform Design
2
Close GMCH ball guide Rev1.11(12474) page138 had a 0.01uf cap. need confirm with Intel.
HI_RCOMP_MCH less than
250mils
U 3D
<18> G_C/BE#[0..3]
G_C/BE#0 Y7 AC6
GCBE0 GADSTBF0 G_AD_STBF0 <18>
G_C/BE#1 W5 AC5
GCBE1 GADSTBS0# G_AD_STBS0# <18>
G_C/BE#2 AA3
GCBE2 G_AD[0..31] <18>
G_C/BE#3 U2 AE6 G_AD0
GCBE3 GAD0 G_AD1
AC11
+1.5VRUN GAD1 G_AD2
<18> G_FRAME# U6 AD5
CK_66M_MCH GFRAME GAD2 G_AD3
<6> CK_66M_MCH H4 AE5
GCLKIN GAD3 G_AD4
<18> G_DEVSEL# AB4 AA10
GDEVSEL GAD4 G_AD5
<18> G_I R DY# V11 AC9
GIRDY GAD5
1
AB5 AB11 G_AD6

R330
<18> G _TRDY#
W11
GTRDY AGP GAD6
AB7 G_AD7
<18> G_STOP# GSTOP GAD7
G_PAR AB2 AA9 G_AD8
<18> G _PAR GPAR/ADD_DETECT GAD8
226_0603_1%~D Note: N6 AA6 G_AD9
<18> G_REQ# GREQ GAD9
HI_SWING_MCH, trace width of M7 AA5 G_AD 10
<18> G_GNT# GGNT GAD10
2
W10 G_AD 11
12mils and space 10mils GRCOMP GAD11 G_AD 12
AC2 AA11
H I_SWING_MCH AGP_SWING GRCOMP/DVOBCGCOMP GAD12 G_AD 13
AC3 W6
VR EFGC GVSWING GAD13 G_AD 14
AD2 W9
GVREF GAD14 G_AD 15
V7
GAD15
1
2 1 <18> G _RBF# R10

R 68 C355 GRBF
<18> G _WBF# R9 V4 G_AD_STBF1 <18>
C364 GWBF GADSTBF1
<18> G_PIPE#_DBI_HI M4 V5 G_AD_STBS1# <18>
147_0603_1%~D 0.1U_0402_16V4Z~D DBI_HI GADSTBS1#
0.01U_0402_16V7K~D <18> G_DBI_LO M5 G_AD[0..31] <18>
1 2 DBI_LO G_AD 16
AA2
<18> G_ST[0..2] GAD16
2
C Close to GMCH ball <250mils G_ST0 N3 Y4 G_AD 17 C

G_ST1 GST0 GAD17 G_AD 18
N5 Y2
G_ST2 GST1 GAD18 G_AD 19
N2 W2
HI_VREF_MCH GST2 GAD19 G_AD 20
<20> HUB_HL[0..10] Y5
H UB_HL0 GAD20 G_AD 21
AF5 V2
H UB_HL1 HI0 GAD21 G_AD 22
AG3 W3
HI1 GAD22
1
2 1 H UB_HL2 AK2 U3 G_AD 23

R 69 C 41 H UB_HL3 HI2 GAD23 G_AD 24
AG5 T2
HUB
C 42 AK5 T4
113_0603_1% 0.1U_0402_16V4Z~D H UB_HL5 HI4 GAD25 G_AD 26
0.01U_0402_16V7K~D AL3 T5
1 2 H UB_HL6 HI5 GAD26 G_AD 27
AL2 R2
HI6 GAD27
2
Close to GMCH ball <250mils H UB_HL7 AL4 P2 G_AD 28

AJ2 P5
AH2 P4
HUB_HL10 HI9 GAD30 G_AD 31
Note: AJ3 M2
HI10 GAD31
HI_VREF_MCH trace width of <20> HUB_HLSTRF AH5
HISTRF
<20> HUB_HLSTRS AH4 U11 G_SB_STBF <18>
10mils and space 7mils HISTRS GSBSTBF
T11 G_SB_STBS# <18>
HI_RCOMP_MCH GSBSTBS#
AD4 G_SBA#[0..7] <18>
H I_SWING_MCH HI_RCOMP G_SBA#0
AE3 R6
HI_VREF_MCH HI_SWING GSBA0# G_SBA#1
AE2 P7
HI_VREF GSBA1# G_SBA#2
R3
GSBA2# G_SBA#3
AK7 R5
CI0 GSBA3# G_SBA#4
AH7 U9
CI1 GSBA4# G_SBA#5
AD11 U10
CI2 GSBA5# G_SBA#6
AF7 U5
+1.5VRUN CI3 GSBA6# G_SBA#7
AD7 T7
CI4 GSBA7#
AC10
CI5 0_0402_5%~D
CSA
Note: AF8 H3 R 42 2 1
CI6 DDCA_DATA
1
AG7 F2 R 41 2 1 0_0402_5%~D
CI_SWING_MCH, CI_VREF_MCH CI7 DDCA_CLK
R 74 Trace 10mils, space 7mils AE9 Analog RGB/CRT guidelines for Springdale-P
trace width of 12mils and CI8 R 39 0_0402_5%~D
AH9 F4 2 1
226_0603_1%~D space 20mils CI9 RED
AG6 E4
CI10 RED# R 43 0_0402_5%~D
AJ6 H6 2 1
CISTRF GREEN
2
VGA
0.8V 52.3_0603_1%~D AJ5 G5
CISTRS GREEN# R 44 0_0402_5%~D
H7 2 1
CI_SWING_GMCH R 81 BLUE
+1.5VRUN 1 2 AG2 G6
CI_SWING_GMCH CI_RCOMP BLUE#
AF2
B
CI_VREF_GMCH CI_SWING B
AF4 G3
CI_VREF HSYNC
1
2 1 E2
C 43 R 75 R 40 0_0402_5%~D VSYNC
2 1 G4
C 44 DREFCLK R 38 0_0402_5%~D
AP8 D2 2 1
0.1U_0402_16V4Z~D 147_0603_1%~D EXTTS# REFSET
0.01U_0402_16V7K~D AJ8
1 2 <21> I C H _S YNC# ICH_SYNC#
<20,36> PCI_PCIRST# AK4 A3
RSTIN# NC_1
2
A33
NC_2
AG10 A35
RESERVED_1 NC_3
0.35V AG9 AF13
CI_VREF_GMCH RESERVED_2 NC_4
AN35 AF23
RESERVED_3 NC_5
AP34 AJ12
RESERVED_4 NC_6
1
2 1 AR1 AN1
C360 R334 RESERVED_5 NC_7
AP2
C363 NC_8
AR3
0.1U_0402_16V4Z~D 113_0603_1% NC_9
0.01U_0402_16V7K~D AR33
1 2 NC_10
AR35
NC_11
2
B2
NC_12
B25
CK_66M_MCH NC_13
B34
NC_14
C1
NC_15
1
C23
R320 NC_16
C35
@ 22_0402_5%~D NC_17
E26
NC_18
M31
NC_19
R25
NC_20
2
1
RG828SDGES_FCBGA932_SPRINGDALE~D
C324
@ 10P_0402_50V8J~D
+1.5VRUN 2
2
R 61
@ 10K_0402_5%~D
A A
1
G_PAR
1: External AGP
0: Internal Graphics
Title
Springdale-AGP/HUB/VGA/CSA
5 4 3 2 1
5 4 3 2 1
Note:
Placed less than 100 mils from ball
+1.5VRUN
+2.5V_MEM
+VTT_GMCH +1.5VRUN
U 3E
D D
VT T_DCAP1 A15 J6
VT T_DCAP2 VTT VCC
A21 J7 1 1 1
VTT VCC
1 1 A4 J8
VTT VCC C337 C358 C396
A5 J9
C348 C 356 VTT VCC 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D
0.82uH, DC current of 30mA A6 K6
0.47U_0603_16V7K~D 0.47U_0603_16V7K~D VTT VCC 2 2 2
parts and close to cap B5 K7 Place near ball
2 2 VTT VCC
B6 K8 Place near GMCH Y11,routing trace Place near GMCH
+1.5VRUN L34 VTT VCC
C5 K9
VTT VCC from cap to ball
C6 L6
0.82U_LQM21NNR82K10_150mA_10%_0805~D VTT VCC
D5 L7
VTT VCC
Trace 14mils D6 L9
VCCA_FSB1 V CCA_FSB VTT VCC
2 1 1 2 +VTT_GMCH D7 L10
VTT VCC
1 E6 L11
R301 VTT VCC
Trace 14mils 2 E7 M8
0_0603_5%~D + C 276 C280 VTT VCC
F7 M9
VTT VCC
M10
100U_D_10VM~D 0.1U_0402_16V4Z~D VCC +2.5V_MEM
AA35 M11
2 1 VCC_DDR VCC
2 +2.5V_MEM AL6 N9
VCC_DDR VCC
Close to GMCH AL7 N10
C414 VCC_DDR VCC
AM1 N11
VCC_DDR VCC
0.1U_0402_10V6K~D AM2 P10 1 1 1 1 1
1 VCC_DDR VCC
AM3 P11
VCC_DDR VCC C374 C391 C 390 C377 C376
AM5 R11
VCC_DDR VCC @ 0.1U_0402_10V6K~D @ 0.1U_0402_10V6K~D @ 0.1U_0402_10V6K~D @ 0.1U_0402_10V6K~D @ 0.1U_0402_10V6K~D
AM6 T16
VCC_DDR VCC 2 2 2 2 2
AM7 T17
VCC_DDR VCC
AM8 T18
VCC_DDR VCC
AN2 T19
VCC_DDR VCC
AN4 T20
VCC_DDR VCC +2.5V_MEM
POWER
AN5 U16
VCC_DDR VCC
AN6 U17
VCC_DDR VCC
AN7 U20
VCC_DDR VCC
AN8 V16
VCC_DDR VCC
AP3 V18 1 1 1 1 1
VCC_DDR VCC
AP4 V20
VCC_DDR VCC C389 C378 C 373 C393 C375
AP5 W16
VCC_DDR VCC @ 0.1U_0402_10V6K~D @ 0.1U_0402_10V6K~D @ 0.1U_0402_10V6K~D @ 0.1U_0402_10V6K~D @ 0.1U_0402_10V6K~D
AP6 W19
C405 0.1U_0402_10V6K~D VCC_DDR VCC 2 2 2 2 2
AP7 W20
VC C _DDR_DCAP5 VCC_DDR VCC
C 1 2 AR15 Y16 C
VC C _DDR_DCAP4 VCC_DDR VCC
1 2 AR21 Y17
VCC_DDR VCC
C 419 0.22U_0603_10V7M~D AR31 Y18
VCC_DDR VCC
AR4 Y19
C 49 0.47U_0603_16V7K~D VCC_DDR VCC
AR5 Y20
VCC_DDR VCC
1 2 AR7
VC C _DDR_DCAP1 VCC_DDR
E35
VCC_DDR
1 2 R35 J1
+ 3VRUN VCC_DDR VCC_AGP
0.22U_0603_10V7M~D J2
C 410 VCC_AGP
G1 J3
VCC_DAC VCC_AGP
G2 J4
C367 0.1U_0402_10V6K~D VCC_DAC VCC_AGP
Trace 14mils J5
VCC_AGP_DCAP2 VCC_AGP
1 2 AG1 K2
VCCA_AGP VCC_AGP
+1.5VRUN Y11 K3 +1.5VRUN
C371 0.1U_0402_10V6K~D VCCA_AGP VCC_AGP
K4
VT T_DCAP3 VCC_AGP
1 2 A31 K5
V CCA_FSB VCCA_FSB VCC_AGP
B4 L1
R314 VCCA_FSB VCC_AGP
2 1 0_0402_5%~D VCCA_DPLL B3 L2
VCCA_DPLL VCC_AGP
R315 2 1 0_0402_5%~D VC CA_DAC C2 L3 1 1 1 1
VCCA_DAC VCC_AGP
L4 C354
VC C _DDR_DCAP2 VCC_AGP C 387 C379 C338 C353
1 2 AL35 L5
C 421 0.1U_0402_10V6K~D VCCA_DDR VCC_AGP VCC_AGP_DCAP1 @ 0.1U_0402_10V6K~D @ 0.1U_0402_10V6K~D @ 0.1U_0402_10V6K~D @ 0.1U_0402_10V6K~D
AB25 Y1 1 2
VCCA_DDR VCC_AGP 2 2 2 2
AC25
VCCA1P5_DDR _SM VCCA_DDR 0.1U_0402_10V6K~D
AC26 D3
VCCA_DDR VSSA_DAC
1uH(0.54uH-D-IN), DC current of RG828SDGES_FCBGA932_SPRINGDALE~D
1000mA parts and close to cap +1.5VRUN
Note:
+1.5VRUN L42 Placed less than 100 mils from ball
Trace 50mils, min:35mils on ball field 1 1 1 1
1U_LQH32CN1R0M11_1A_20%_1210~D
C 319 C359 C346 C351
2 1 VC C A_DDR 1 2 VCCA1P5_DDR _SM Decoupling Reference Document: @ 0.1U_0402_10V6K~D @ 0.1U_0402_10V6K~D @ 0.1U_0402_10V6K~D @ 0.1U_0402_10V6K~D
2 2 2 2
R351 1 2
0_0603_5%~D C 402 (12474)page246,248
B B
+ C398
100U_D_10VM~D 0.1U_0402_16V4Z~D
1 +1.5VRUN
2
Close to GMCH
Decoupling Reference Document:
1 1 1
C 380 C347 C345
@ 0.1U_0402_10V6K~D @ 0.1U_0402_10V6K~D @ 0.1U_0402_10V6K~D
2 2 2
Bulk Decopuling
+VTT_GMCH
1
2 2 2 1 1
+ C308 C 327 C 288 C287 C289
C290
470U_D4_2.5V_R10M~D 0.1U_0402_16V4Z~D 4.7U_0805_6.3V6K~D 4.7U_0805_6.3V6K~D 1U_0603_6.3V6M~D 0.47U_0603_16V7K~D
2 1 1 1 2 2
+1.5VRUN +1.5VRUN
A +2.5V_MEM A
Place between the VR and GMCH

1 2 2 1
C384 C370 C 322 2
+ C 329 C284
22U_1206_10V4Z~D 4.7U_0805_6.3V6K~D 10U_0805_10V4M~D 470U_D4_2.5V_R10M~D
2 1 1 4.7U_0805_6.3V6K~D
2 1
Title
Springdale-Decoupling
Place at the output of the 1.5V VR LA-1711 X02-D
5 4 3 2 1
5 4 3 2 1
C 1
B E 2 3
FAN1 Control and Tachometer
+12V +12V 2222 SYMBOL(SOT23-NEW)
D D
1
C117 +3VRUN
0.1U_0402_16V4Z~D +5VRUN
2
1
U30B
LM358M_SO8~D Q31
2
SI3457DV-T1_TSOP6~D R133
8
R136 10K_0402_5%~D
4
R286 5 10K_0402_5%~D
P
IN+
2
FAN1_ON S
100K_0402_5%~D 7 3
FAN1VREF O G FAN1_TACH <34>
<34> FAN1_PWM 1 2 6
IN-
1
G
R137
1
D 1K_0402_5%~D Q30
4
1 1 1 2 FAN1TACH_ON 2
1
2
5
6
PMBT2222_SOT23~D
C254 C102
3
1U_0805_10V6K~D C108 0.47U_0603_16V7K~D
2 @ 2200P_0603_50V7K~D 2
FAN1_VFB 1 2 FAN1
R151
300K_0402_5%
1 2 FAN1_VOUT
FAN1_VOUT <25>
1 FAN1_TACH_FB SI3457DV P channel
FAN1_TACH_FB <25>
1
1
R150 D2 + C110 Vds max: +/- 30V
100K_0402_5%~D 47U_D_16VM_R70~D
RB751V_SOD323~D
Vgs max: +/- 20V
2 Id max: 4.3A @ Vgs = -10V
2
2
65mohm @ Vgs = -10V
C C
FAN2 Control and Tachometer

+12V +3VRUN
+12V
+5VRUN
1
Q72
U30A 2 R287
SI3457DV-T1_TSOP6~D 10K_0402_5%~D
8
LM358M_SO8~D R289
4
R291 3 IN+ 10K_0402_5%~D

P
2
S
100K_0402_5%~D 1 FAN2_ON 3
B FAN2VREF O G FAN2_TACH <34> B
<34> FAN2_PWM 1 2 2 IN-
1
G
R290
1
D 1K_0402_5%~D Q61
4
1 1 1 2 FAN2TACH_ON 2
1
2
5
6
C255 C256 PMBT2222_SOT23~D

1U_0805_10V6K~D
3
C625 0.47U_0603_16V7K~D
2 @ 2200P_0603_50V7K~D 2
FAN2_VFB 1 2 FAN2
R580
300K_0402_5% JFAN2
1 2 FAN2_VOUT 4 4
1 3
3
1
FAN2_TACH_FB 2
R288 D17 + C622 2
1
100K_0402_5%~D 47U_D_16VM_R70~D 1
RB751V_SOD323~D MOLEX_53398-0490~D
2
2
A A

Title
FAN CONTROL
X02-D
5 4 3 2 1
5 4 3 2 1
+2.5V_MEM
DDRA_SDQ[0..63]
<11,17> DDRA_SDQ[0..63] +2.5V_MEM +2.5V_MEM DDRA_VREF trace width of
DDRA_SDQS[0.. 7]
<11,17> DDRA_SDQS[0..7] 12mils and space 12mils(min)
1
DDRA_SMA[0..12] JDIM1
<11,17> DDRA_SMA[0..12] D D R A_VREF R442
1 2
DDRA_SDM[0. .7] VREF VREF
3 4 2
<11,17> DDRA_SDM[0..7] D D RA_SDQ0 VSS VSS D D RA_SDQ1 75_0603_1%~D
5 6
D D RA_SDQ5 DQ0 DQ4 D D RA_SDQ4 C507
7 8
DQ1 DQ5
2
9 10 0.1U_0402_16V4Z~D
D DRA_SDQS0 VDD VDD DDRA_SDM0 1
11 12
D D RA_SDQ7 DQS0 DM0 D D RA_SDQ2
13 14
DQ2 DQ6
15 16
VSS VSS
1
D D RA_SDQ6 17 18 D D RA_SDQ3
D D RA_SDQ8 DQ3 DQ7 D D RA_SDQ9 R440
19 20
DQ8 DQ12
21 22
D
D DRA_SDQ13 VDD VDD D DRA_SDQ12 75_0603_1%~D
D
23 24
D DRA_SDQS1 DQ9 DQ13 DDRA_SDM1
25 26
DQS1 DM1
2
27 28
D DRA_SDQ10 VSS VSS D DRA_SDQ14
29 30
D DRA_SDQ15 DQ10 DQ14 D DRA_SDQ11
31 32
DQ11 DQ15
33 34
VDD VDD
<11> D DRA_CLK1 35 36
CK0 VDD
<11> DDRA_CLK1# 37 38
CK0# VSS
39 40
VSS VSS
D DRA_SDQ20 41 42 D DRA_SDQ16
43 44
DQ17 DQ21
45 46
D DRA_SDQS2 VDD VDD DDRA_SDM2
47 48
D DRA_SDQ22 DQS2 DM2 D DRA_SDQ18
49 50
DQ18 DQ22
51 52
53 54
55 56
DQ24 DQ28
57 58
D DRA_SDQ29 VDD VDD D DRA_SDQ25
59 60
61 62
DQS3 DM3
63 64
65 66
67 68
DQ27 DQ31
69 70
VDD VDD
71 72
CB0 CB4
73 74
CB1 CB5
75 76
VSS VSS
77 78
DQS8 DM8
79 80
CB2 CB6
81 82
VDD VDD
83 84
CB3 CB7
85 86
DU DU/RESET#
87 88
VSS VSS
<11> D DRA_CLK0 89 90
CK2 VSS
<11> DDRA_CLK0# 91 92
CK2# VDD
C 93 94 C
D DRA_CKE1 VDD VDD D DRA_CKE0
<11,17> D DRA_CKE1 95 96 D D RA_CKE0 <11,17>
CKE1 CKE0
97 98
DDRA_SM A12 DU/A13 DU/BA2 DDRA_SM A11
99 100
DDRA_SMA9 A12 A11 DDRA_SMA8
101 102
A9 A8
103 104
DDRA_SMA7 VSS VSS DDRA_SMA6
105 106
107 108
109 110
111 112
A1 A0
113 114
DDRA_SM A10 VDD VDD DDRA_SBS1
115 116 DDRA_SBS1 <11,17>
DDRA_SBS0 A10/AP BA1 D DRA_SRAS#
<11,17> DDRA_SBS0 117 118 D DRA_SRAS# <11,17>
D D RA_SWE# BA0 RAS# D DRA_SCAS#
<11,17> D D RA_SWE# 119 120 D DRA_SCAS# <11,17>
D DRA_SCS#0 WE# CAS# D DRA_SCS#1
<11,17> D DRA_SCS#0 121 122 D DRA_SCS#1 <11,17>
S0# S1#
123 124
DU DU
125 126
127 128
129 130
DQ33 DQ37
131 132
D DRA_SDQS4 VDD VDD DDRA_SDM4
133 134
135 136
DQ34 DQ38
137 138
139 140
141 142
DQ40 DQ44
143 144
145 146
147 148
DQS5 DM5
149 150
151 152
153 154
DQ43 DQ47
155 156
VDD VDD
157 158 D DRA_CLK2# <11>
VDD CK1#
159 160 D DRA_CLK2 <11>
VSS CK1
161 162
163 164
165 166
DQ49 DQ53
167 168
B
D DRA_SDQS6 VDD VDD DDRA_SDM6 B
169 170
171 172
DQ50 DQ54
173 174
175 176
177 178
DQ56 DQ60
179 180
181 182
183 184
DQS7 DM7
185 186
187 188
189 190
DQ59 DQ63
191 192
VDD VDD
<6,16,21,32> ICH_SMBDATA 193 194
SDA SA0
<6,16,21,32> ICH_SMBCLK 195 196
SCL SA1
197 198
+3VSUS VDD_SPD SA2
199 200
VDD_ID DU
AMP_1565917-1~D
DIMM0
STANDARD
Follow
System Memory Decoupling caps Decoupling Reference Document:

+2.5V_MEM
each Channel(two DIMMs) requirement 22uF*1 ; 0.1uF*21
1 1 1 1 1 1 1 1 1 1 1
C111
C107 C113 C 106 C109 C114 C112 C 101 C 79 C 104 C 81
22U_1206_10V4Z~D
2 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D
A Decoupling Reference Document: A

+2.5V_MEM (12474)pag 271 each DIMM(two) requirement 0.1uF*42
1 1 1 1 1 1 1 1 1 1 1
C103 C134 C124 C 132 C129 C123 C128 C126 C 92 C 133 C105
2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D
Title
DDR-SODIMM SLOT1
X02-D
5 4 3 2 1
5 4 3 2 1
+2.5V_MEM
DDRB_SDQ[0..63]
<11,17> DDRB_SDQ[0..63] +2.5V_MEM +2.5V_MEM DDRB_VREF trace width of
DDRB_SDQS[0.. 7] 12mils and space 12mils(min)
<11,17> DDRB_SDQS[0..7] JDIM2
1
DDRB_SMA[0..12] 1 2 D D R B_VREF
<11,17> DDRB_SMA[0..12] VREF VREF R 418
3 4
DDRB_SDM[0. .7] D D RB_SDQ5 VSS VSS D D RB_SDQ7
5 6 2
<11,17> DDRB_SDM[0..7] D D RB_SDQ4 DQ0 DQ4 D D RB_SDQ0 75_0603_1%~D
7 8
DQ1 DQ5 C458
9 10
VDD VDD
2
D DRB_SDQS0 11 12 DDRB_SDM0 0.1U_0402_16V4Z~D
D D RB_SDQ6 DQS0 DM0 D D RB_SDQ2 1
13 14
DQ2 DQ6
15 16
D D RB_SDQ1 VSS VSS D D RB_SDQ3
17 18
DQ3 DQ7
1
D D RB_SDQ9 19 20 D DRB_SDQ12
DQ8 DQ12 R 415
21 22
D DRB_SDQ13 VDD VDD D DRB_SDQ11
23 24
D DRB_SDQS1 DQ9 DQ13 DDRB_SDM1 75_0603_1%~D
25 26
D DQS1 DM1 D
27 28
VSS VSS
2
D DRB_SDQ14 29 30 D D RB_SDQ8
D DRB_SDQ10 DQ10 DQ14 D DRB_SDQ15
31 32
DQ11 DQ15
33 34
VDD VDD
<11> D DRB_CLK1 35 36
CK0 VDD
<11> DDRB_CLK1# 37 38
CK0# VSS
39 40
VSS VSS
D DRB_SDQ20 41 42 D DRB_SDQ16
43 44
DQ17 DQ21
45 46
D DRB_SDQS2 VDD VDD DDRB_SDM2
47 48
D DRB_SDQ19 DQS2 DM2 D DRB_SDQ23
49 50
DQ18 DQ22
51 52
D DRB_SDQ22 VSS VSS D DRB_SDQ18
53 54
55 56
DQ24 DQ28
57 58
59 60
D DRB_SDQS3 DQ25 DQ29 DDRB_SDM3
61 62
DQS3 DM3
63 64
65 66
67 68
DQ27 DQ31
69 70
VDD VDD
71 72
CB0 CB4
73 74
CB1 CB5
75 76
VSS VSS
77 78
DQS8 DM8
79 80
CB2 CB6
81 82
VDD VDD
83 84
CB3 CB7
85 86
DU DU/RESET#
87 88
VSS VSS
<11> D DRB_CLK0 89 90
CK2 VSS
<11> DDRB_CLK0# 91 92
CK2# VDD
93 94
D DRB_CKE1 VDD VDD D DRB_CKE0
<11,17> D DRB_CKE1 95 96 D DRB_CKE0 <11,17>
CKE1 CKE0
C 97 98 C
DDRB_SM A12 DU/A13 DU/BA2 DDRB_SM A11
99 100
DDRB_SMA9 A12 A11 DDRB_SMA8
101 102
A9 A8
103 104
DDRB_SMA7 VSS VSS DDRB_SMA6
105 106
107 108
109 110
111 112
A1 A0
113 114
DDRB_SM A10 VDD VDD DDRB_SBS1
115 116 DDRB_SBS1 <11,17>
DDRB_SBS0 A10/AP BA1 D DRB_SRAS#
<11,17> DDRB_SBS0 117 118 D DRB_SRAS# <11,17>
D D RB_SWE# BA0 RAS# D DRB_SCAS#
<11,17> D D RB_SWE# 119 120 D DRB_SCAS# <11,17>
D DRB_SCS#0 WE# CAS# D DRB_SCS#1
<11,17> DDRB_SCS#0 121 122 D DRB_SCS#1 <11,17>
S0# S1#
123 124
DU DU
125 126
127 128
129 130
DQ33 DQ37
131 132
133 134
135 136
DQ34 DQ38
137 138
139 140
141 142
DQ40 DQ44
143 144
145 146
147 148
DQS5 DM5
149 150
151 152
153 154
DQ43 DQ47
155 156
VDD VDD
157 158 DDRB_CLK2# <11>
VDD CK1#
159 160 D DRB_CLK2 <11>
VSS CK1
161 162
163 164
165 166
DQ49 DQ53
167 168
169 170
171 172
B DQ50 DQ54 B
173 174
175 176
177 178
DQ56 DQ60
179 180
181 182
183 184
DQS7 DM7
185 186
187 188
189 190
DQ59 DQ63
191 192
VDD VDD
<6,15,21,32> ICH_SMBDATA 193 194 +3VSUS
SDA SA0
<6,15,21,32> ICH_SMBCLK 195 196
SCL SA1
197 198
+3VSUS VDD_SPD SA2
199 200
VDD_ID DU
AMP_1565918-1~D
DIMM1
REVERSE Follow
System Memory Decoupling caps Decoupling Reference Document:

each Channel(two DIMMs) requirement 0.1uF*24
+2.5V_MEM
1 1 1 1 1 1 1 1 1 1 1 1
C116 C100 C 82 C 84 C 98 C 95 C 87 C125 C 85 C 93 C 96 C130
2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D
A A
+2.5V_MEM
1 1 1 1 1 1 1 1 1 1 1 1
C 94 C 86 C 97 C 80 C 90 C 78 C 91 C 83 C 127 C 99 C122 C115
2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D

Title
DDR-SODIMM SLOT2
X02-D
5 4 3 2 1
5 4 3 2 1
Channel A(DIMM0) Termination Channel B(DIMM1) Termination

resistors & Decoupling caps resistors & Decoupling caps
V_1P25V_DDR_VTT V_1P25V_DDR_VTT V_1P25V_DDR_VTT V_1P25V_DDR_VTT V_1P25V_DDR_VTT V_1P25V_DDR_VTT
R433 56_0402_5%~D
1 2 D DRA_SCS#0
R N 97 56_4P2R_0404_5%~D R N 77 56_4P2R_0404_5%~D R N66 56_4P2R_0404_5%~D R N 38 56_4P2R_0404_5%~D R N 25 56_4P2R_0404_5%~D R N 60 56_4P2R_0404_5%~D R405 56_0402_5%~D
D D RA_SDQ1 1 4 4 1 D DRA_SDQS3 4 1 D DRA_SDQ42 D D RB_SDQ7 1 4 4 1 D DRB_SDQS3 4 1 D DRB_SDQ42 1 2 D DRB_SCS#0
D D RA_SDQ4 2 3 3 2 D DRA_SDQ29 3 2 D DRA_SDQ43 R N103 56_4P2R_0404_5%~D D D RB_SDQ0 2 3 3 2 D DRB_SDQ25 3 2 D DRB_SDQ47
4 1 DDRA_SMA8
3 2 DDRA_SMA6 R N 24 56_4P2R_0404_5%~D
R N 85 56_4P2R_0404_5%~D R N106 56_4P2R_0404_5%~D R N89 56_4P2R_0404_5%~D R N 32 56_4P2R_0404_5%~D R N 34 56_4P2R_0404_5%~D R N 17 56_4P2R_0404_5%~D 4 1 DDRB_SM A12
D D RA_SDQ5 1 4 4 1 D DRA_SDQ25 4 1 D DRA_SDQ48 D D RB_SDQ4 1 4 4 1 D DRB_SDQ26 4 1 D DRB_SDQ49 3 2 D DRB_CKE1
D D RA_SDQ0 2 3 3 2 DDRA_SDM3 3 2 D DRA_SDQ53 R N104 56_4P2R_0404_5%~D D D RB_SDQ5 2 3 3 2 D DRB_SDQ30 3 2 D DRB_SDQ52
D
4 1 D DRA_CKE0 D
3 2 DDRA_SM A11 R N 23 56_4P2R_0404_5%~D
R N 84 56_4P2R_0404_5%~D R N 64 56_4P2R_0404_5%~D R N65 56_4P2R_0404_5%~D R N 31 56_4P2R_0404_5%~D R N 58 56_4P2R_0404_5%~D R N 59 56_4P2R_0404_5%~D 4 1 DDRB_SMA7
D D RA_SDQ7 1 4 4 1 D DRA_SDQ51 4 1 D DRA_SDQ49 D D RB_SDQ6 1 4 4 1 DDRB_SDM6 4 1 D DRB_SDQ53 3 2 DDRB_SMA9
D DRA_SDQS0 2 3 3 2 D DRA_SDQS6 3 2 D DRA_SDQ52 R N73 56_4P2R_0404_5%~D D DRB_SDQS0 2 3 3 2 D DRB_SDQ55 3 2 D DRB_SDQ54
4 1 DDRA_SMA3
3 2 DDRA_SMA5 R N 56 56_4P2R_0404_5%~D
R N 96 56_4P2R_0404_5%~D R N 63 56_4P2R_0404_5%~D R N88 56_4P2R_0404_5%~D R N 39 56_4P2R_0404_5%~D R N 15 56_4P2R_0404_5%~D R N 16 56_4P2R_0404_5%~D 4 1 DDRB_SMA8
DDRA_SDM0 1 4 4 1 D DRA_SDQ60 4 1 DDRA_SDM6 DDRB_SDM0 1 4 4 1 D DRB_SDQ60 4 1 D DRB_SDQ48 3 2 DDRB_SMA6
D D RA_SDQ2 2 3 3 2 D DRA_SDQ54 3 2 D DRA_SDQ55 R N72 56_4P2R_0404_5%~D D D RB_SDQ2 2 3 3 2 D DRB_SDQ51 3 2 D DRB_SDQS6
4 1 DDRA_SM A10
3 2 DDRA_SMA1 R N 21 56_4P2R_0404_5%~D
R N 95 56_4P2R_0404_5%~D R N 87 56_4P2R_0404_5%~D R N76 56_4P2R_0404_5%~D R N 37 56_4P2R_0404_5%~D R N 52 56_4P2R_0404_5%~D R N 42 56_4P2R_0404_5%~D 4 1 DDRB_SM A10
D D RA_SDQ3 1 4 4 1 D DRA_SDQ50 4 1 D DRA_SDQ27 D D RB_SDQ3 1 4 4 1 D DRB_SDQ50 4 1 D DRB_SDQ27 3 2 DDRB_SMA1
D D RA_SDQ9 2 3 3 2 D DRA_SDQ56 3 2 D DRA_SDQ30 D DRB_SDQ12 2 3 3 2 D DRB_SDQ61 3 2 D DRB_SDQ31
R N110 56_4P2R_0404_5%~D
4 1 DDRA_SMA4
R N 83 56_4P2R_0404_5%~D R N 86 56_4P2R_0404_5%~D R N105 56_4P2R_0404_5%~D 3 2 DDRA_SMA2 R N 30 56_4P2R_0404_5%~D R N 14 56_4P2R_0404_5%~D R N 43 56_4P2R_0404_5%~D
D D RA_SDQ8 1 4 4 1 D DRA_SDQ57 4 1 D DRA_SDQ26 D D RB_SDQ9 1 4 4 1 D DRB_SDQS7 4 1 D DRB_SDQ29
D D RA_SDQ6 2 3 3 2 DDRA_SDM7 3 2 D DRA_SDQ31 D D RB_SDQ1 2 3 3 2 D DRB_SDQ59 3 2 DDRB_SDM3 R431 56_0402_5%~D
1 2 D DRB_SCS#1
R N 94 56_4P2R_0404_5%~D R N 62 56_4P2R_0404_5%~D R N100 56_4P2R_0404_5%~D R N74 56_4P2R_0404_5%~D R N 29 56_4P2R_0404_5%~D R N 51 56_4P2R_0404_5%~D R N 13 56_4P2R_0404_5%~D

D DRA_SDQ12 1 4 4 1 D DRA_SDQS7 4 1 D DRA_SDQ63 4 1 DDRA_SMA7 D DRB_SDQS1 1 4 4 1 D DRB_SDQ63 4 1 D DRB_SDQ56 R N 22 56_4P2R_0404_5%~D
DDRA_SDM1 2 3 3 2 D DRA_SDQ61 3 2 D DRA_SDQ58 3 2 DDRA_SMA9 D DRB_SDQ13 2 3 3 2 DDRB_SDM7 3 2 D DRB_SDQ57 4 1 DDRB_SMA3
3 2 DDRB_SMA5
R N 82 56_4P2R_0404_5%~D R N 92 56_4P2R_0404_5%~D R N61 56_4P2R_0404_5%~D R N102 56_4P2R_0404_5%~D R N 36 56_4P2R_0404_5%~D R N 12 56_4P2R_0404_5%~D R N 50 56_4P2R_0404_5%~D

D DRA_SDQS1 1 4 4 1 D DRA_SDQ37 4 1 D DRA_SDQ59 4 1 DDRA_SMA0 D DRB_SDQ11 1 4 4 1 D DRB_SDQ39 4 1 D DRB_SDQ58 V_1P25V_DDR_VTT
D DRA_SDQ13 2 3 3 2 D DRA_SDQ34 3 2 D DRA_SDQ62 3 2 DDRA_SBS1 DDRB_SDM1 2 3 3 2 D DRB_SDQ38 3 2 D DRB_SDQ62
D DRA_SBS1 <11,15>
R N 81 56_4P2R_0404_5%~D R N 91 56_4P2R_0404_5%~D R N101 56_4P2R_0404_5%~D R N 28 56_4P2R_0404_5%~D R N 41 56_4P2R_0404_5%~D

D DRA_SDQ15 1 4 4 1 DDRA_SDM4 4 1 D DRA_SRAS# D DRB_SDQ10 1 4 4 1 D DRB_SDQ32 R N 55 56_4P2R_0404_5%~D R N 57
D DRA_SRAS# <11,15>
D DRA_SDQ10 2 3 3 2 D DRA_SDQ38 3 2 D DRA_SCAS# D DRB_SDQ14 2 3 3 2 D DRB_SDQ36 4 1 DDRB_SMA4 D DRB_CKE0 1 4
D DRA_SCAS# <11,15>
3 2 DDRB_SMA2 DDRB_SM A11 2 3
R N 93 56_4P2R_0404_5%~D R N 70 56_4P2R_0404_5%~D R443 56_0402_5%~D R N 47 56_4P2R_0404_5%~D R N 11 56_4P2R_0404_5%~D 56_4P2R_0404_5%~D

C D DRA_SDQ14 1 4 4 1 D DRA_SDQ32 1 2 D DRA_SCS#1 D D RB_SDQ8 1 4 4 1 D DRB_SDQ33 C
D DRA_SDQ11 2 3 3 2 D DRA_SDQ36 D DRB_SDQ15 2 3 3 2 D DRB_SDQS4 R N 20
D D RB_SWE# 1 4
DDRB_SBS0 2 3
R N 80 56_4P2R_0404_5%~D R N 69 56_4P2R_0404_5%~D D DRA_CKE0 R N 27 56_4P2R_0404_5%~D R N 40 56_4P2R_0404_5%~D
D DRA_SDQ17 1 <11,15> D DRA_CKE0
4 4 1 D DRA_SDQ33 D DRA_CKE1 D DRB_SDQ21 1 4 4 1 DDRB_SDM4 56_4P2R_0404_5%~D
D DRA_SDQ20 2 <11,15> D DRA_CKE1
3 3 2 D DRA_SDQS4 V_1P25V_DDR_VTT D DRB_SDQ20 2 3 3 2 D DRB_SDQ34 R N 54 56_4P2R_0404_5%~D
D DRA_SCS#0 4 1 DDRB_SMA0
<11,15> D DRA_SCS#0 D DRA_SCS#1 3 2 DDRB_SBS1
R N109 56_4P2R_0404_5%~D R N 99 56_4P2R_0404_5%~D <11,15> D DRA_SCS#1 R N 45 56_4P2R_0404_5%~D R N 10 56_4P2R_0404_5%~D
D DRA_SDQ16 1 4 4 1 D DRA_SDQ39 DDRB_SDM2 1 4 4 1 D DRB_SDQ46
D DRA_SDQ21 2 3 3 2 D DRA_SDQ40 R N 75 D DRB_SDQ23 2 3 3 2 D DRB_SDQ37 R N 53 56_4P2R_0404_5%~D
DDRA_SM A12 1 4 4 1 D DRB_SRAS# D DRB_SRAS# <11,16>
D DRA_CKE1 2 3 3 2 D DRB_SCAS# D DRB_SCAS# <11,16>
R N 79 56_4P2R_0404_5%~D R N 68 56_4P2R_0404_5%~D R N 33 56_4P2R_0404_5%~D R N 49 56_4P2R_0404_5%~D
D DRA_SDQ22 1 4 4 1 D DRA_SDQ44 56_4P2R_0404_5%~D D DRB_SDQ19 1 4 4 1 D DRB_SDQ35 D D RB_SWE#
D DRA_SDQS2 2 <11,16> D D RB_SWE#
3 3 2 D DRA_SDQ35 D DRB_SDQS2 2 3 3 2 D DRB_SDQ43
DDRB_SBS0
<11,16> DDRB_SBS0 DDRB_SBS1
R N 71
R N108 56_4P2R_0404_5%~D R N 98 56_4P2R_0404_5%~D D D RA_SWE# 1 R N 44 56_4P2R_0404_5%~D R N 19 56_4P2R_0404_5%~D <11,16> DDRB_SBS1
4
DDRA_SDM2 1 <11,15> D D RA_SWE# DDRB_SDQ[0..63]
4 4 1 D DRA_SDQ41 DDRA_SBS0 2 3 D DRB_SDQ18 1 4 4 1 D DRB_SDQS5 D DRB_CKE0
D DRA_SDQ18 2 <11,15> DDRA_SBS0 <11,16> DDRB_SDQ[0..63] <11,16> D DRB_CKE0
3 3 2 DDRA_SDM5 D DRB_SDQ28 2 3 3 2 D DRB_SDQ44 D DRB_CKE1
56_4P2R_0404_5%~D DDRB_SDQS[0.. 7] <11,16> D DRB_CKE1
<11,16> DDRB_SDQS[0..7] D DRB_SCS#0
R N 78 56_4P2R_0404_5%~D R N 67 56_4P2R_0404_5%~D DDRA_SDQ[0..63] R N 26 56_4P2R_0404_5%~D R N 48 56_4P2R_0404_5%~D DDRB_SMA[0..12] <11,16> D DRB_SCS#0 D DRB_SCS#1
D DRA_SDQ28 1 <11,15> DDRA_SDQ[0..63] <11,16> DDRB_SMA[0..12] <11,16> D DRB_SCS#1
4 4 1 D DRA_SDQS5 D DRB_SDQ24 1 4 4 1 D DRB_SDQ40
D DRA_SDQ19 2 3 3 2 D DRA_SDQ45 DDRA_SDQS[0.. 7] D DRB_SDQ22 2 3 3 2 DDRB_SDM5 DDRB_SDM[0. .7]
<11,15> DDRA_SDQS[0..7] <11,16> DDRB_SDM[0..7]
DDRA_SMA[0..12]
R N107 56_4P2R_0404_5%~D R N 90 56_4P2R_0404_5%~D <11,15> DDRA_SMA[0..12] R N 46 56_4P2R_0404_5%~D R N 18 56_4P2R_0404_5%~D
D DRA_SDQ23 1 4 4 1 D DRA_SDQ47 DDRA_SDM[0. .7] D DRB_SDQ16 1 4 4 1 D DRB_SDQ45
D DRA_SDQ24 2 <11,15> DDRA_SDM[0..7]
3 3 2 D DRA_SDQ46 D DRB_SDQ17 2 3 3 2 D DRB_SDQ41
V_1P25V_DDR_VTT
V_1P25V_DDR_VTT
B B
1 1 1 1 1 1 1 1
1 1 1 1 1 1
C488 C482 C481 C 487 C477 C483 C436 C437
C 519 C514 C515 C516 C517 C 511
2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D
2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D
V_1P25V_DDR_VTT
V_1P25V_DDR_VTT
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
C 504 C512 C518 C513 C503 C661 C662 C 663
C484 C478 C476 C 485 C479 C480 C439 C440
2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 @ 0.1U_0402_10V6K~D 2 @ 0.1U_0402_10V6K~D 2 @ 0.1U_0402_10V6K~D
2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D
V_1P25V_DDR_VTT
V_1P25V_DDR_VTT
1 1 1 1 1 1 1 1
C 492 C498 C501 C500 C438 C 493 C496 C502 1 1 1 1 1 1 1 1
C505
2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D C443 C442 C434 C 441 C664 C665 C666
4.7U_1206_16V6K~D
2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 2 @ 0.1U_0402_10V6K~D 2 @ 0.1U_0402_10V6K~D 2 @ 0.1U_0402_10V6K~D
V_1P25V_DDR_VTT
1 1 1 1 1 1 1 1
C490 C510
A C 499 C494 C486 C495 C667 C 668 A
4.7U_1206_16V6K~D 4.7U_1206_16V6K~D Decoupling Reference Document:
2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 0.1U_0402_10V6K~D 2 2 2 @ 0.1U_0402_10V6K~D 2 @ 0.1U_0402_10V6K~D
Springdale Customer Schematic R1.2 page26 We used one DIMM, so place 4.7uF*1 ; 0.1uF*20(11/6/02')
each Channel(two DIMMs) requirement 4.7u*2 ;
0.1uF*26
Decoupling Reference Document:

Springdale Customer Schematic R1.2 page22 We used one DIMM, so place 4.7uF*2 ; 0.1uF*23(11/6/02') Title
each Channel(two DIMMs) requirement 4.7u*2 ; DDR Termination Resistors
0.1uF*28 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number R ev
5 4 3 2 1
5 4 3 2 1
G_ PWR_SRC PW R _ SRC
PW R _SRC G_ PWR_SRC
0.1U_0603_25V7M~D
0.1U_0603_25V7M~D
0.1U_0603_25V7M~D
0.1U_0603_25V7M~D
0.1U_0603_25V7M~D
Q8
<12> G_ST[0..2]
2 2 2 2 1 SI4435DY_SO8~D
C 26
C 23
C 24
C 22
C 21
<12> G_AD[0..31] 1 8
0.1U_0603_25V7M~D
2 7
1 1 1 1 2 3 6
<12> G_C/BE#[0..3] 2 5
C 19
2
C 12
GPW R_SRC_ON 4
G_SBA#[ 0..7]
<12> G_SBA#[0..7] 1
100K_0402_5%~D
0.1U_0603_25V7M~D
1
2
J V ID
R 30
CK_66M_AGP
<6> CK_66M_AGP
G_REQ#
<12> G_REQ#
G_ST0
D <12> G_ST0 G_ST1 D
<12> G_ST1
1
G_ST2 1 2
<12> G_ST2 G_ PWR_SRC 1 2 G_ PWR_SRC
3 4
3 4
5 6 Make R571
5 6
7 8 100K ohm
7 8
9 10
9 10
1
11
11 12
12 after 6th
13 14 August R 28
GND GND 100K_0402_5%~D
15 16
15 16
AGP8X_DET_GC : low -->AGP3.0 ; High -->AGP2.0 +3VRUN 17 18 + 3VRUN
17 18
AGP8X_DET_CG : low -->MB 19 20
19 20
A GP_PWRON# 2
support AGP3.0 21 22
21 22
23 24
CK_66M_AGP 23 24
Note: 25 26 +1.5VRUN
25 26
AGP8X_DET_GC :Pull low by an AGP3.0 graphics card 27 28
R322 0_0402_5%~D AGP8X_DET_CG 27 28 AGP8X_DET_GC
2 1 29 30 AGP8X_DET_GC <12>
Floating by an AGP2.0 graphics card PCI_PIRQB# 29 30 PCI_PIRQA#
31 32 PCI_PIRQA# <20>
<20,32> PCI_PIRQB# 31 32
33 34
G_ST0 33 34 G_REQ#
35 36
35 36
1
G_ST2 G_ST1 D
37 38
37 38 Q7
39 40 <33,37,39,44> R U N _ ON 2
GND GND G_SBA#0 2N7002_SOT23~D
41 42 G
+1.5VRUN G_SBA#2 41 42 G_SBA#1
43 44 S
43 44
3
G_SBA#4 45 46
45 46 G_SBA#3
47 48
G_SB_STBF 47 48 G_SBA#5
49 50
G_SB_STBS# 49 50
51 52
51 52 G_SBA#6
53 54
53 54 G_SBA#7
55 56
+1.5VRUN AGP_RST# 55 56 G_DEVSEL#
57 58
57 58
59 60
G_I R DY# 59 60 G _RBF#
61 62 G _RBF# <12>
G _TRDY# 61 62 G _WBF#
63 64 G_ WBF# <12>
R U N P WROK 63 64 G_PIPE#_DBI_HI
<34,37,43,44,46> R U N P WROK 65 66
65 66
67 68
G_STOP# GND GND G_AD 30
69 70
G_FRAME# 69 70 G_AD 28
71 72
G_C/BE#3 71 72 G_AD 26
C 73 74 C
73 74
75 76
G_AD 31 75 76 G_AD 24
77 78 FOXCONN QT00160A-9120L
G_AD 29 77 78 G_AD 22
79 80
79 80
81 82 Shielding Ground Pin
G_AD _STBS1# 81 82 G_AD 20
83 84
G_AD_STBF1 83 84 G_AD 18
85 86
85 86
87 88 13,14
G_AD 27 87 88 G_AD 23
89 90
G_AD 25 89 90 G_AD 17
91 92 39,40
91 92
93 94
G_C/BE#2 GND GND G_AD 16
95 96 67,68
G_AD_STBF0 G_AD 21 95 96 G_DBI_LO
<12> G_AD_STBF0 97 98
G_AD _STBS0# 97 98
<12> G_AD_STBS0# 99 100 93,94
G_AD_STBF1 G_AD 19 99 100 G_C/BE#1 R 88
<12> G_AD_STBF1 101 102
G_AD _STBS1# VR EFCG 101 102 VR EFGC_R
<12> G_AD_STBS1# <12> VR EFCG 103 104 1 2 VR EFGC <12> 121,122
G_SB_STBF 103 104
<12> G_SB_STBF 105 106
G_SB_STBS# G_AD 15 105 106 G_AD 14 @ 0_0402_5%~D
<12> G_SB_STBS# 1 107 108 147,148
G_AD 13 107 108 G_AD 12
109 110
C388 G_AD 11 109 110 G_AD 10
111 112
G_FRAME# 0.1U_0402_16V4Z~D G_AD9 111 112
<12> G_FRAME# 113 114
G_DEVSEL# 2 113 114 G_AD8
<12> G_DEVSEL# 115 116
G_I R DY# G_AD _STBS0# 115 116 G_AD7
<12> G_I R DY# 117 118
G _TRDY# G_AD_STBF0 117 118 G_AD6
<12> G _TRDY# 119 120
G_STOP# 119 120
<12> G_STOP# 121 122
G_PAR G_AD5 GND GND
<12> G _PAR 123 124 +1.5VRUN
G_REQ# G_AD3 123 124 G_AD4
<12> G_REQ# 125 126
G_GNT# 125 126
127 128
<12> G_GNT# G_PIPE#_DBI_HI G_AD1 127 128 G_AD2
<12> G_PIPE#_DBI_HI 129 130 CPLD Disable
G_DBI_LO 129 130 +3VRUN
<12> G_DBI_LO 131 132 Pop R96, Depop R98
G_AD0 131 132 G_C/BE#0
133 134
F PV CC 133 134
<34> F PV CC 135 136 G_AGPBUSY#
135 136
2
137 138 G_GNT#
+1.5VRUN 137 138 G_PAR R 96
139 140
139 140 10K_0402_5%~D
<24> S P_DIF 141 142
F PV CC 141 142 SBAT_SMBDAT
143 144 SBAT_SMBDAT <34>
ICH_SU S_STAT# 143 144 SBAT_SMBCLK R 98
<21> ICH_SUS_STAT# 145 146 SBAT_SMBCLK <34>
145 146
1
2 147 148 @ 0_0402_5%~D
B GND GND STP_AGP_R# B
+12V 149 150 1 2 STP_AGP# <36>
C317 149 150
151 152
0.1U_0402_10V6K~D GC_BL_SUSPEND 151 152
<33> GC_BL_SUSPEND 153 154 +5VALW
1 153 154
155 156 + 5VRUN
155 156
+5VSUS 157 158
157 158
+3VSUS 159 160 LID_CL# <33>
159 160
FOX_QT00160A-9120L~D +5VSUS + 3VRUN +1.5VRUN
0.047U_0402_10V4M~D
0.047U_0402_10V4M~D
0.047U_0402_10V4M~D
0.047U_0402_10V4M~D
0.047U_0402_10V4M~D
0.047U_0402_10V4M~D
0.047U_0402_10V4M~D
0.047U_0402_10V4M~D
0.047U_0402_10V4M~D
0.047U_0402_10V4M~D
0.047U_0402_10V4M~D
1 1 1 1 1 1
C397
C352
C357
1 1 1 1 1
C417
C418
C339
C334
C325
C342
C336
C409
CLOSE
+3VSUS TO PIN 2 2 2 2 2 2
2 2 2 2 2
U7
@ TC7SH32FU_SSOP5~D
5
1 SYS _SUSPEND
P
INB SYS _SUSPEND <33,41>

AGP_RST# 4
O PCIRST _AGP#
2 PCIRST_AGP# <20>
INA
G
3
R156
A 0_0402_5%~D +12V +5VRUN +5VALW A
2 1
1 1 1
C 413 C416 C415
0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D
2 2 2

Title
VGA Daughter Board Conn.

X02-D
5 4 3 2 1
5 4 3 2 1
+3VALW
CPU Temperature Sensor
6.8K_0402_5%~D
6.8K_0402_5%~D
2
2
D D
R375
R378
1
1
+3VRUN
C408
U37
1 2 3 14 H_THERMDA <8>
VCC 2.5VIN
1
0.1U_0402_16V4Z~D 13 H_THERMDA MCH_THERMDA
DAT_SMB D1+ H_THERMDC C420
<26,34,35,47> DAT_SMB 16 12
SDA D1-
1
CLK_SMB 1 2200P_0603_50V7K~D 1
<26,34,35,47> CLK_SMB SCL 2
11 MCH_THERMDA Q73 2
D2+ H_THERMDC <8>
10 MCH_THERMDC C657
FAN3_TACH D2- 2200P_0603_50V7K~D MMBT3904_SOT23~D
6
TACH1
3
7 15 FAN3_PWM 2
TACH2 PWM1 R366 MCH_THERMDC
4
TACH3
9 5 1 2 ATF_INT# <33,47>
TACH4 PWM2/ALERT#
2 8 1 2 0_0402_5%~D +3VRUN
GND PWM3
ADT7460ARQ_QSOP16~D R365 10K_0402_5%~D
Put 3904 between MCH and DDR
Address 0101 110X (X=1-->Read; X=0-->Write)
Put Cap near pin 10,11 of U37
C C
+3VRUN
FAN3 Control and Tachometer +5VRUN
1
2
R125
R118 10K_0402_5%~D
10K_0402_5%~D
2
FAN3_TACH
1
+12V R120
1
1K_0402_5%~D Q29
1 2 FAN3TACH_ON 2
1 PMBT2222_SOT23~D
2
3
R609 +12V C89
10K_0402_5%~D 0.47U_0603_16V7K~D
2
FAN3
1
+3VRUN
Q28
R610 SI4435DY_SO8~D
1
2 1 1 8
1
B R117 JFAN3 D1 B
2 7 1 1
10K_0402_5%~D 2.7K_0402_5% 3 6 FAN3_ON 1
1 C88 C673
5 2 2
1
D 10U_1206_16V4Z~D
3 @ 22U_1206_16V4Z_V1
3
2
FAN3_PWM RB751V_SOD323~D 2 2
2
4
2
G Q75 SUYIN_250019MR003G400ZL~D
S 2N7002_SOT23~D
3
+12V
8
U46A
R616 3
P
@ 10K_0402_5%~D IN+
1
O
1 2 2
IN-
G
@ LM358M_SO8~D
4
1
C672
C671 @ 2200P_0603_50V7K~D
@ 1U_0805_10V6K~D 1 2
2
R617
@ 300K_0402_5%
A A
1 2
1
R618
@ 100K_0402_5%~D Item101: Reserved Op amp circuit (NP) to the High side FET
2

Title
CPU Thermal Sensor & FAN Control

X02-D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Thursday, July 24, 2003 Sheet 19 of 60
5 4 3 2 1
5 4 3 2 1
+ 3VRUN + 3VRUN
R N3 R N 35
1
2
3
4
1
2
3
4
8.2K_8P4R_1206_5%~D 8.2K_8P4R_1206_5%~D
U 5A
PCI_AD[0..31] <28,30,32>
PCI_FRAME# D2 P2 PCI_AD31
<28,30,32> PCI_FRAME# FRAME# AD31
PC I _ IRDY# M3 F4 PCI_AD30
8 <28,30,32> PC I _ IRDY# IRDY# AD30
7
6
5
8
7
6
5
PCI_DEVSEL# ICH_GPIO2_PI RQE# P CI_TRDY# E4 P4 PCI_AD29
<28,30,32> PC I_TRDY# TRDY# AD29
PCI_STOP# ICH_GPIO3_PIR QF# PCI_DEVSEL# L3 F5 PCI_AD28
<28,30,32> PCI_DEVSEL# DEVSEL# AD28
P CI_TRDY# ICH_GPIO4_PIR QG# PCI_STOP# E5 N2 PCI_AD27
<28,30,32> PCI_STOP# STOP# AD27
PCI_FRAME# ICH_GPIO5_PIRQH# P CI_PAR F1 D3 PCI_AD26
<28,30,32> P CI_PAR PAR AD26
PCI_PERR# K2 P3 PCI_AD25
<28,30,32> P CI_PERR# PERR# AD25
+ 3VRUN R425 PCI_PLOC K# L2 E6 PCI_AD24
+ 3VRUN @ 10K_0402_5%~D PCI_SERR# PLOCK# AD24 PCI_AD23
<28,30,32> P CI_SERR# L4 N4
ICH_PME# SERR# AD23 PCI_AD22
2 1 V2 C4
D +3VSUS PME# AD22 D
1
R N2 R398 PCI_PCI RST# V4 N5 PCI_AD21
<33> ICH_PME# <12,36> PCI_PCIRST# PCIRST# AD21
1
2
3
4
8.2K_8P4R_1206_5%~D 8.2K_0402_5%~D CK_33M_ICH PCI N1 H3 PCI_AD20

<6> CK_33M_ICHPCI PCICLK AD20
2
@ P5 PCI_AD19
R393 PCI_PIRQA# AD19 PCI_AD18
<18> PCI_PIRQA# B3 B2
10K_0402_5%~D PCI_PIRQB# PIRQA# AD18 PCI_AD17
<18,32> PCI_PIRQB# E1 L1
PIRQB# AD17
2
PCI_GNTA# PCI_PIRQC# A2 G4 PCI_AD16
<28,30> PCI_PIRQC# PIRQC# AD16
8
7
6
5
PC I _ IRDY# PCI_PIRQD# C2 G5 PCI_AD15

<30,32> PCI_PIRQD# PIRQD# AD15
1
ICH_GPIO2_PI RQE# D7 K1 PCI_AD14
PCI_SERR# PCI_REQA# ICH_GPIO3_PIR QF# PIRQE#/GPI2 AD14 PCI_AD13
A6 G2
PCI_PERR# ICH_GPIO4_PIR QG# PIRQF#/GPI3 AD13 PCI_AD12
E2 L5
ICH_GPIO5_PIRQH# PIRQG#/GPI4 AD12 PCI_AD11
B1 H4
+ 3VRUN PIRQH#/GPI5 AD11 PCI_AD10
M4
R414 PCI_REQ0# AD10 PCI_AD9
D5 F2
CK_33M_ICH PCI PCI_REQ1# REQ0# AD9 PCI_AD8
2 1 <30> PCI_REQ1# C1 K5
REQ1# AD8
1
R N4 R119 PCI_REQ2# C5 J2 PCI_AD7

REQ2# AD7
CLK_ICH _TERM
1
2
3
4
8.2K_8P4R_1206_5%~D 8.2K_0402_5%~D @ 10_0402_5%~D PCI_REQ3# B6 J3 PCI_AD6

<32> PCI_REQ3# REQ3# AD6
PCI_REQ4# C6 H2 PCI_AD5
<28> PCI_REQ4# REQ4#/GPI40 AD5
PCI_REQA# A5 H5 PCI_AD4
PCI_REQB# REQA#/GPI0 AD4 PCI_AD3
<30> PCI_REQB# E7 K4
REQB#REQ5#/GPI1 AD3
2
PCI_PLOC K# G3 PCI_AD2
AD2
8
7
6
5
PCI_REQ0# D4 J5 PCI_AD1
PCI_REQB# PCI_GNT1# GNT0# AD1 PCI_AD0
A3 J4
PCI_PIRQB# <30> PCI_GNT1# GNT1# AD0
1 B7
PCI_PIRQA# PCI_GNT3# GNT2#
C7 M2 PCI_C_BE3# <28,30,32>
C465 <32> PCI_GNT3# PCI_GNT4# GNT3# C/BE3#
A4 N3 PCI_C_BE2# <28,30,32>
+ 3VRUN @ 8.2P_0402_50V8J~D <28> PCI_GNT4# PCI_GNTA# GNT4#/GPO48 C/BE2#
E8 J1 PCI_C_BE1# <28,30,32>
2 PCI_GNTB# GNTA#/GPO16 C/BE1#
B4 E3 PCI_C_BE0# <28,30,32>
R N1 <30> PCI_GNTB# GNTB#/GNT5#/GPO17 C/BE0#
1
2
3
4
8.2K_8P4R_1206_5%~D FW82801EB_mBGA460_ICH5~D
8
7
6
5
PCI_PIRQD#
PCI_PIRQC#
PCI_REQ2#
+1.5VRUN
C + 3VRUN C
R124
1
HI_RCOMP_ICH
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
1 2
R386
R113
R387
U 5B
<12> HUB_HL[0..10]
52.3_0603_1%~D H UB_HL0 H20 C23
H UB_HL1 HI0 USBP0P
H21 D23
H UB_HL2 HI1 USBP0N
J20 A22 USBP1+ <26>
HI2 USBP1P
2
+1.5VRUN H UB_HL3 H23 B22

HI3 USBP1N USBP1- <26>
PCI_REQ4# H UB_HL4 M23 C21
HI4 USBP2P USBP2+ <26>
H UB_HL5 M21 D21
HI5 USBP2N USBP2- <26>
PCI_REQ1# H UB_HL6 N21 A20
HI6 USBP3P USBP3+ <26> USB_OC2# <26>
1
H UB_HL7 M20 B20

HI7 USBP3N USBP3- <26> USB_OC3# <26>
PCI_REQ3# R 411 H UB_HL8 L22 C19
HI8 USBP4P USBP4+ <26> USB_OC4# <23>
Note: H UB_HL9 J22 D19 USB_OC IS 5V
HI9 USBP4N USBP4- <26> USB_OC5# <26>
226_0603_1%~D HI_SWING_MCH, HI_VREF_MCH R406 61.9_0603_1% HUB_HL10 K21 A18
HI10 USBP5P USBP5+ <26> TOLERANT
1 2 G22 B18 USBP5- <26>
trace width of 12mils and HI11 USBP5N
2
+ 3VRUN C17
space 10mils USBP6P USBP6+ <26>
<12> HUB_HLSTRF K23 D17 USBP6- <26>
H I _ SWING_ICH HI_STBF USBP6N +5VSUS
<12> HUB_HLSTRS J24 A16
HI_STBS USBP7P
1
1
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
HI_RCOMP_ICH N24 B16

HIRCOMP USBP7N
R139
H I _ SWING_ICH L20
HI_VSWING
1
R401
R426
2 1 H I _VREF_ICH L24
R 410 C460 CK_66M_ICH HIREF USB_OC0# R N111
N22 C15
C455 CLK66 OC0# USB_OC1#
D15 1 8
OC1#
2
147_0603_1%~D 0.1U_0402_16V4Z~D 0.01U_0402_16V7K~D C10 D14 USB_OC2# 2 7

1 2 LAN_RXD0 OC2# USB_OC3#
C9 C14 3 6
LAN_RXD1 OC3#
2
IDE_IRQ15 Close to ICH ball <250mils C11 B14 USB_OC4# 4 5

IDE_IRQ15 <21,23> LAN_RXD2 OC4#/GPI9
D9 A14 USB_OC5#
IDE_IRQ14 LAN_TXD0 OC5#/GPI10 USB_OC6# 10K_1206_8P4R_5%~D
IDE_IRQ14 <21> E9 D13
H I _VREF_ICH LAN_TXD1 OC6#/GPI14 USB_OC7#
B12 C13
I RQ_SERIRQ LAN_TXD2 OC7#/GPI15 R394 22.6_0603_1%~D R N112
I RQ_SERIRQ <21,30,33> D10
R430 0_0402_5%~D LAN_RSTSYNC USBRBIAS 2
E10 A24 1 4 5
LAN_CLK USBRBIAS
1
2 1 2 1 LAN_RST# AA1 B24 3 6

R 409 C456 LAN_RST# USBRBIAS# R404 2 7
C452 B11 F24 CK_48M_ICH 2 1 1 8
113_0603_1% 0.1U_0402_16V4Z~D EE_DIN CLK48
0.01U_0402_16V7K~D B10
1 2 R392 @ 1K_0402_5%~D EE_CS @ 10_0402_5%~D 10K_1206_8P4R_5%~D
A12
EE_SHCLK
2
B B
NC_EE_DOUT
CK_48M _ICH_TERM
Close to ICH ball <250mils 1 2 B9 USB_OC6# <26>
EE_DOUT
I C H _A C_SYNC_R B8 Note:
ICH_AC_RST _R# AC_SYNC
C12 CK_48M_ICH <6> USBRBIAS keep less than 500mils
ICH_AC_SDOUT _R AC_RST#
A9
I CH_AC_SDIN0 AC_SDOUT
<24> I CH_AC_SDIN0 E12
I CH_AC_SDIN1 AC_SDIN0
<27> I CH_AC_SDIN1 D12
AC_SDIN1
A13
AC_SDIN2
<24> ICH_AC_BITCLK D8
AC_BIT_CLK
2
2
C118 FW82801EB_mBGA460_ICH5~D C431
0.1U_0402_16V4Z~D R396 @ 4.7P_0402_50V8C~D
+3VSUS 2 1 @ 10_0402_5%~D 1
U 8A
14
1
74VHC08MTC_TSSOP14~D R162
PCI_PCI RST# 1 33_0402_5%~D
P
ICH_AC_BITCLK_TERM
IN1 PCIRSTB1# PCIRST _AGP# CK_66M_ICH
3 1 2 PCIRST_AGP# <18> <6> CK_66M_ICH
OUT
2
IN2
2
G
0.1"~6" R 413
7
@ 10_0402_5%~D
ICH_AC_RST _R# 2 1 ICH_AC_RST# <24,27>
1
U 8B R389 33_0402_5%~D
33_0402_5%~D I C H _A C_SYNC_R
CK_66M _ICH_TERM
4 2 1 I C H _A C_SYNC <24,27>
IN1 PCIRSTB2# PCIRST _SIO# R385 33_0402_5%~D
6 1 2 PCIRST_SIO# <33> 2
OUT
5
IN2 R160 ICH_AC_SDOUT _R C427
2 1 ICH_AC_SDOUT <24,27>
33_0402_5%~D R390 33_0402_5%~D @10P_0402_50V8J~D
1 2 1
PCIRST_CB# <30>
U 8C R383 2
A 74VHC08MTC_TSSOP14~D R153 @ 1K_0402_5%~D A
10 33_0402_5%~D ICH_AC_SDOUT 1 2 C464
IN1 + 3VRUN
8 PCIRSTB3# 1 2 PCIRST_1# ICH_AC_BI TCLK @10P_0402_50V8J~D
OUT PCIRST_1# <28> 1
9 I CH_AC_SDIN0
IN2 I CH_AC_SDIN1
@10K_0402_5%~D
@10K_0402_5%~D
@10K_0402_5%~D
U 8D
1
13 33_0402_5%~D
IN1
OUT
11 PCIRSTB4# 1 2 PCIRST_2#
PCIRST_2# <32> Compal Electronics, Inc.
R395
R402
R397
12
IN2 Title
ICH5-PCI/HUB/USB/AC97
2
X02-D
5 4 3 2 1
5 4 3 2 1
U 5C
+ 3VRUN
IDE_SDD[0..15] <23>
R 274 IDE_PDD15 AB17 AA23 IDE_SDD15 J HDD
4.7K_0402_5%~D IDE_PDD14 AA16
PDD15 SDD15
AB24 IDE_SDD14 Top View IDE_RST_HD D_5V
I D E_P DIORDY IDE_PDD13 PDD14 SDD14 IDE_SDD13 I DE_PDD7 1 2 I DE_PDD8
2 1 Y16 AC24
IDE_PDD12 PDD13 SDD13 IDE_SDD12 I DE_PDD6 3 4 I DE_PDD9
AC16 AB22
R 562 IDE_PDD11 PDD12 SDD12 IDE_SDD11 I DE_PDD5 5 6 IDE_PDD10
AA15 AA20
4.7K_0402_5%~D IDE_PDD10 PDD11 SDD11 IDE_SDD10 I DE_PDD4 7 8 IDE_PDD11
AD16 AC22
I D E_S DIORDY I DE_PDD9 PDD10 SDD10 I DE_SDD9 I DE_PDD3 9 10 IDE_PDD12
2 1 Y15 AD22
I DE_PDD8 PDD9 SDD9 I DE_SDD8 I DE_PDD2 11 12 IDE_PDD13
AD15 Y19
R 279 I DE_PDD7 PDD8 SDD8 I DE_SDD7 I DE_PDD1 13 14 IDE_PDD14
AB14 AC20
0_0402_5%~D I DE_PDD6 PDD7 SDD7 I DE_SDD6 + 5VHDD I DE_PDD0 15 16 IDE_PDD15
AD14 AB20 2
I D E_PDDREQ R PD DREQ I DE_PDD5 PDD6 SDD6 I DE_SDD5 17 18
1 2 AC15 AC21
I DE_PDD4 PDD5 SDD5 I DE_SDD4 R PD DREQ 19 20
AA14 AB21 12/17/02 Changed by
R 558 I DE_PDD3 PDD4 SDD4 I DE_SDD3 I DE_PDIOW# 21 22 R570
AC14 AD24 1 Dell's Require
PDD3 SDD3 23 24
1
0_0402_5%~D I DE_PDD2 Y14 AD23 I DE_SDD2 IDE_PDIOR# 470_0402_5%~D
I D E_SDDREQ R SD DREQ I DE_PDD1 PDD2 SDD2 I DE_SDD1 I D E_P DIORDY 25 26 IDE_CSEL_PRI
1 2 R SD D REQ <23> Y13 AB23 2 1
D
I DE_PDD0 PDD1 SDD1 I DE_SDD0 R 568 I DE_PDDACK# 27 28 D
AB16 AA22
PDD0 SDD0 IDE_IRQ14 29 30
@ 33P_0603_50V8J~D
@33P_0603_50V8J~D
1K_0402_5%~D T13
I DE_PDIOW# I DE_SDIOW# IDE_PDA1 31 32 ATA_66_PRI/PDIAG @ PAD
2 2 AA17 Y22 I DE_SDIOW# <23> 44
PDIOW# SDIOW# 33 34
2
I DE_PDDACK# AC18 W20 I DE_SDDACK# IDE_PDA0 IDE_PDA2
PDDACK# SDDACK# I DE_SDDACK# <23> 35 36
C251
C608
I D E_PDDREQ AC17 Y20 I D E_SDDREQ IDE_PDCS1# IDE_PDCS3#
IDE_PDIOR# AD18
PDDREQ SDDREQ
Y23 IDE_SDIOR# 43 PIDEACT# 37 38
1 1 PDIOR# SDIOR# I DE_SDIOR# <23> <38> PIDEACT# 39 40
I D E_P DIORDY AA18 Y21 I D E_S DIORDY
PIORDY SIORDY I D E_S DIORDY <23> + 5VHDD 41 42 + 5VHDD
IDE_SDA[0..2] <23> 43 44
IDE_PDA2 AC19 W21 IDE_SDA2
IDE_PDA1 PDA2 SDA2 IDE_SDA1
AD19 W23 45
IDE_PDA0 PDA1 SDA1 IDE_SDA0 SGND
AA19 W22 Connector on 49 46
PDA0 SDA0 B1 SGND
4.7U_1206_16V6K~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
50 47
IDE_PDCS3# IDE_SDCS3# B2 SGND
IDE_PDCS1#
Y18
PDCS3# SDCS3#
V20
IDE_SDCS1#
IDE_SDCS3# <23> HH99227-S9 bottom side SGND
48
AB19 V22 IDE_SDCS1# <23> 1 2 2
PDCS1# SDCS1#
C238
C240
C237
FOX_HH99227-S9~D
Y17 Y24 IDE_IRQ15
<20> IDE_IRQ14 IRQ14 IRQ15 IDE_IRQ15 <20,23>
FW82801EB_mBGA460_ICH5~D 2 1 1
+5VMOD +5VHDD
2
R269 R262
@ 1K_0603_5%~D @ 1K_0603_5%~D
R263 R 265
0_0402_5%~D 0_0402_5%~D
1
1 2 1 2
3 1 3 1 IDE_RST_HD D_5V
<33> IDE_RST_MOD IDE_RST_MOD_5V <23> <33> IDE_RST_HDD
Q46 Q51
C SIO_SLP_S3# 1 2 @ MMBT3904_SOT23~D @ MMBT3904_SOT23~D C
ICH_SLP_S1# <6>
2
R 266 R271
R439 0_0402_5%~D @ 10K_0402_5%~D @ 10K_0402_5%~D
1 2 IDE_RST_MOD_SFTON 1 2 IDE_RST_MOD_SFTON
+ 3VRUN + 3VRUN
R114
S PKR 1 2 +3VRUN
LK2-->USB2P0_SMI
@ 1K_0402_5%~D
U 5D
+ 3VRUN Disable timer timeout T22 R5 R417 1 2 10K_0402_5%~D

<34> SIO_A20GATE A20GATE GPIO6
V23 U3 R421 1 2 10K_0402_5%~D + 3VRUN
<8> H_A20M# A20M# GPIO7 SIO_EXT_SMI#
@10K_0402_5%~D
@10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
P22 Y2
<36> CPUSLP# CPUSLP# GPIO8
2
U24 AC3 LAN _PME# R142 1 2 10K_0402_5%~D +3VSUS SIO_EXT_SMI#

SIO_EXT_SMI# <33>
+ 3VRUN <8> H _F ERR# FERR# SMBALERT#/GPI11 SIO_EXT_RTE#
<8> H _IGNNE# R21 W4
IGNNE# GPIO12
R399
R116
R123
R128
R23 W5 SI O_EXT_SCI# SIO_EXT_RTE#

<8> H_INIT# INIT# GPIO13 SIO_EXT_RTE# <33>
U23 U21
<8> H_INTR INTR GPO18 + 3VRUN +3VSUS SI O_EXT_SCI#
R22 T20 SIO_EXT_SCI# <33>
<8> H_NMI NMI GPO19
1
@ 1K_0402_5%~D
P23 U22
<33> S IO_RCIN# RCIN# GPIO20 S USCLK
@ 220_0402_5%
@ 220_0402_5%
@ F23 R1
<20,30,33> I RQ_SERIRQ SERIRQ GPIO21 S USCLK <36>
1
10K_0402_5%~D 2 1 R130 B ID0 2 1 SMI# V24 U20

<8> H_SMI# R 134 2 SMI# GPIO22
1 0_0402_5%~D T24 F22
<36> STPCLK# STPCLK# GPIO23
1
R167
R169
R161
B ID1
10K_0402_5%~D
@ 10K_0402_5%~D 2 1 R126 AC1
R127 GPIO24
2.7K_0402_5%
2.7K_0402_5%
P20 W3
0_0402_5%~D DPRSLPVR(Mobile) GPIO25
1
R388
10K_0402_5%~D 2 1 R115 B ID2 R24 V3 B ID2
DPSLP#(Mobile) GPIO27
2
W2 B ID0
GPIO28
R 148
R 143
10K_0402_5%~D 2 1 R403 B ID3 AA8 T1 B ID1
SATA0TXP GPIO32
2
AB8 G23 SAT A_LED#
SATA0TXN GPIO33
1
Q33 Q32 AD7 F21 B ID3

SATA0RXN GPIO34 ICH_SMBCLK <6,15,16,32>
2
2 2 AC7 ICH_SMBDATA <6,15,16,32>
SATA0RXP ICH_SMBCLK
AD2
@ MMBT3904_SOT23~D @ MMBT3904_SOT23~D SMBCLK ICH_SM BDATA
AD1
SMBDATA 10K_0402_5%~D
3
BID3 BID2 BID1 BID0 R EV AA10 AD3 ICH_SMLI NK0 R149 1 2 +3VSUS
<23> SATA_MODTX+ SATA1TXP SMLINK0 ICH_SMLI NK1
<12> I C H _S YNC# AB10 AA2 1 2
B <23> SATA_MODTX- SATA1TXN SMLINK1 LINK_ALERT# 1 B
0 0 0 0 X 00 AD9 V5 2 +3VSUS R132 10K_0402_5%~D
<23> SATA_MODRX- SATA1RXN LINKALERT# R427 10K_0402_5%~D
Note: AC9
<23> SATA_MODRX+ SATA1RXP S PKR
0 0 0 1 X 01 <10,37> P WRGD_3V SATABIAS keep E24 S PKR <24>
SAT ABIAS SPKR I C H_RI#
1 2 Y11 AB3
less than R423 24.9_0603_1%~D SATARBIASP RI#
0 0 1 0 X 02 Y9 Y4 SIO_PWRBTN# <33>
500mils SATARBIASN PWRBTN# S USCLK
Y1
SUSCLK ICH_BATLOW# R135 1
0 0 1 1 X 03 AC5 AB2 2 10K_0402_5%~D +3VSUS
<6> CK_100M_ICH CLK100P TP0
<33> LPC_LAD[0..3] AD5 AB1 ICH_SUS_STAT# <18>
<6> CK_100M_ICH# CLK100N SUS_STAT# SIO_SLP_S3#
0 1 0 0 X 04 W1 SIO_SLP_S3# <33>
LPC_LAD0 SLP_S3# SIO_SLP_S4#
T5 U2 R424 1 2 @ 0_0402_5%~D SIO_SLP_S4_S5# <33>
LPC_LAD1 LAD0 SLP_S4# SIO_SLP_S5#
BAT54C R4 AA3 R429 1 2 0_0402_5%~D
CMOS_CLR LPC_LAD2 LAD1 SLP_S5# R122 1
R3 U1 2 10K_0402_5%~D +3VSUS
@ SHORT PADS LPC_LAD3 LAD2 SYS_RESET# V RM_PWRGD @ 10K_0402_5%~D
U4 R20 V RM_PWRGD <36> R434
LPC_LFR AME# LAD3 VRMPWRGD V CC_RTC
K2 K1 <33> LPC_LFRAME#
T4
LFRAME# CPUPWRGD/GPO49
P24 H _P WRGOOD <8> 1 2
LPC_LDRQ0# U5 T21 H_THERM TRIP_R#
R471 <34> LPC_LDRQ0# LDRQ0# THRMTRIP#
R154 1 LPC_LDRQ1# R2 T2 SIO_THRM# R 435 330K_0402_5%~D
<33> LPC_LDRQ1# LDRQ1#/GPI41 THRM# SIO_THRM# <33>
1 2 ICH_RTC RST# 2 1 1 2 AD10 ICH_INTVR MEN 1 2
2 1 ICH_RTCX1 INTVRMEN
2 3 AC11 F20 CK_14M_ICH <6>
180K_0402_5%~D 1K_0402_5%~D ICH_RTCX2 RTCX1 CLK14 ICH_THERM_PWRD N#
A2 A1 AB12
RTCX2 INTRUDER#
Y12 +3VRUN
2 ICH_RTC RST# AA12
RTCRST#
R438 <36,37> SU SPWROK AB13 A11
RSMRST# NC
2
C119 1 2 PW RGD_OK AC12 R416
+3VSUS PWROK R400 V RM_PWRGD 1
0.1U_0402_10V6K~D 0_0402_5%~D 2
1 D3 FW82801EB_mBGA460_ICH5~D @ 10_0402_5%~D 10K_0402_5%~D
R158 SIO_THRM# 1 2
1K_0402_5%~D +VCC_CORE R420 10K_0402_5%~D
CK_14M _ICH_TERM 1
+3.3VRTC 1 2 3 2 ICH_SYNC# PWRGD_3V PWRGD_OK R428
10K_0402_5%~D
10K_0402_5%~D
1 2
1
0 0 0
10K_0402_5%~D
R436
R432
BAT54C_SOT23~D 0 1 0 R422
1
V CC_RTC H_THERM TRIP_R# 1 2 H_THERMTRIP# <8,37>

1 0 0
2
@ 0_0402_5%~D
V CC_RTC 1 1 1
1
@ 4.7P_0402_50V8C~D
2
A +3VSUS C469 A
C120 @ 0.1U_0402_16V4Z~D 2
2 +3.3VRTC R441
1U_0805_10V6K~D1
C428
10K_0402_5%~D
100K_0402_5%~D
1
1 2 ICH_THERM_PWRD N#
C509 1
R138
15P_0603_50V8J~D
ICH_THERM_PWRDN# <37>
2 1 ICH_RTCX1
+ 3VRUN CPLD Disable
2
2
X4 R437 R 419 I C H_RI# 2 1 CBS_RI#

C BS_RI# <30>
Depop R141 Compal Electronics, Inc.
10M_0402_5%~D @ 10K_0402_5%~D Title
32.768KHZ_12.5P_MC-306~D LPC_LDRQ0# R 140
C508
1 2
@ 0_0402_5%~D ICH5-IDE/LPC/PM/GPIO/LAN
2
15P_0603_50V8J~D R 121 Size Document Number R ev

1
ICH_RTCX2 @ 10K_0402_5%~D X02-D

2 1
1 2 LPC_LDRQ1#
1 2 CPLD_WAKE# <36> AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D LA-1711
R141 0_0402_5%~D Date: Wednesday, July 23, 2003 Sheet 21 of 60
5 4 3 2 1
5 4 3 2 1
+ 3VRUN +1.5VRUN Place0.1u near ball(VSS)

+ 3VRUN +1.5VRUN G24,H24,K24,M24,AD4
U 5E
and AD18; 0.01u near to
D C432 C491 ball AD8. D
B5 K10 Place near ball(VSS)
VCC3_3 VCC1_5 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D
F6 K12 D1,A7,H1,P1W24 and A21
VCC3_3 VCC1_5
G1 K13 2 1 2 1
VCC3_3 VCC1_5
H6 L19
VCC3_3 VCC1_5
K6 P19 C457 C451
VCC3_3 VCC1_5
L6 R10
VCC3_3 VCC1_5 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D
M10 R6
VCC3_3 VCC1_5
N10 H24 2 1 2 1
VCC3_3 VCC1_5
P6 J19
VCC3_3 VCC1_5
R13 K19 C453 C454
VCC3_3 VCC1_5
V19 M15
VCC3_3 VCC1_5 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D
W15 N15
VCC3_3 VCC1_5
W17 N23 2 1 2 1
+ 5VRUN + 3VRUN VCC3_3 VCC1_5
W24 E15
VCC3_3 VCC1_5
AD13 F15 C463 C474
VCC3_3 VCC1_5
AD20 F14
VCC3_3 VCC1_5
2
D 14 G19 W19 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D

R391 VCC3_3 VCC1_5
G21 R12 2 1 2 1
VCC3_3 VCC1_5
W9
1K_0402_5%~D RB751V_SOD323~D VCC1_5
+3VSUS E18 W10 C449 C497
VCCSUS3_3 VCC1_5
B15 W11
VCCSUS3_3 VCC1_5
1
E11 W6 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D

I C H _V5REF_RUN VCCSUS3_3 VCC1_5
F10 W7 2 1 2 1
VCCSUS3_3 VCC1_5
2 2 2 F11 W8
C468 C471 C472 VCCSUS3_3 VCC1_5
E13 E22 C466 C448
1U_0805_10V6K~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D VCCSUS3_3 VCC1_5
E14
VCCSUS3_3 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D
U6 AA6 Place near
1 1 1 VCCSUS3_3 VCCSATAPLL
V6 AB6 ball (VSS)A19 2 1 2 1
VCCSUS3_3 VCCSATAPLL
F16 C24
VCCSUS3_3 VCCUSBPLL C430 0.01U_0402_16V7K~D
Place near ball A8 F17
VCCSUS3_3 VCCSUS15_A C450
F18 F19 1 2
VCCSUS3_3 VCCSUS1_5_A 0.01U_0402_16V7K~D
K15 Y5
+5VSUS +3VSUS VCCSUS3_3 VCCSUS1_5_B C475 0.01U_0402_16V7K~D
AA4 Place near 1 2
VCCSUS1_5_B VCCSUS15_B
A8 AB4 1 2 ball (VSS)AD4
V5REF VCCSUS1_5_B
W14 F7
V5REF VCCSUS1_5_C
2
D 13 F8 V CCSUS15_C 1 2
R 384 VCCSUS1_5_C C433 0.01U_0402_16V7K~D
E16
1K_0402_5%~D V5REF_SUS
C R15 Place near C
RB751V_SOD323~D V_CPU_IO
V CC_RTC AD11 R19 + VCC_CORE ball (VSS)A7
VCCRTC V_CPU_IO
T19
V_CPU_IO
1
ICH_V5REF_SUS 2
2 2 2 C 506 FW82801EB_mBGA460_ICH5~D
C447 C445 C 444
1U_0805_10V6K~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_10V6K~D
1
1 1 1
Place near ball AD11
Place near ball(VSS) A17
U 5F
A1 G6
VSS VSS
A7 G20
VSS VSS +1.5VRUN +1.5VRUN
A10 G24
VSS VSS + VCC_CORE
A15 H1
VSS VSS
A17 H19 C429 Place near ball D24 C473 Place near ball AD6
VSS VSS
A19 H22 Place near
VSS VSS 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D
A21 J6 ball T22
VSS VSS
A23 J21 2 2 1 2 1
VSS VSS
AA5 J23
VSS VSS C470
AA7 K3
VSS VSS 0.1U_0402_16V4Z~D C426 C489
AA9 K11
VSS VSS 1 0.01U_0402_16V7K~D 0.01U_0402_16V7K~D
AA11 K14
VSS VSS
AA13 K20 1 2 1 2
VSS VSS
AA21 K22
VSS VSS
AA24 K24
VSS VSS
AB5 L10
B VSS VSS B
AB7 L11
VSS VSS
AB9 L12
VSS VSS
AB11 L13 Place0.1u near ball(VSS)
VSS VSS
AB15 L14 A17,A23,V1.Addition cap near
VSS VSS +3VSUS
AB18 L15
VSS VSS A15,A19
AC2 L21
VSS VSS
AC4 L23
VSS VSS C435
AC6 M1
VSS VSS 1U_0603_6.3V6M~D
AC8 M5
VSS VSS
AC10 M11 1 2
VSS VSS
AC13 M12
VSS VSS
AC23 M13 C467
VSS VSS
AD4 M14
VSS VSS 0.1U_0402_16V4Z~D
AD6 M22
VSS VSS
AD8 M24 2 1
VSS VSS
AD17 N11
VSS VSS
AD21 N12 C424
VSS VSS
AD12 N13
B13 N14
VSS VSS
B17 N20 2 1
VSS VSS
B19 P1
VSS VSS
B21 P10 C446
VSS VSS
B23 P11
C3 P12
VSS VSS
C8 P13 2 1
VSS VSS
C16 P14
VSS VSS
C18 P15
VSS VSS C425
C20 P21
VSS VSS 0.01U_0402_16V7K~D
C22 R11
VSS VSS
D1 R14 1 2
VSS VSS
D6 T23
VSS VSS
D11 T3
VSS VSS
D16 T6 Decoupling Reference Document:
VSS VSS
D18 U19
VSS VSS Springdale Chipset Platform Design guide Rev1.11
D20 V1
VSS VSS
D22 V21 (12474)page278
VSS VSS
D24 W16
VSS VSS
A E17 W18 A
VSS VSS
E19 Y3
VSS VSS
E20 Y6
VSS VSS
E21 Y7
VSS VSS
E23 Y8
VSS VSS
F3 Y10
VSS VSS
F9
VSS
FW82801EB_mBGA460_ICH5~D

Title
ICH5 Power & Decoupling

X02-D
5 4 3 2 1
5 4 3 2 1
<21> IDE_SDD[0..15]
IDE_SDD0
IDE_SDD1
IDE_SDD2 +5VMOD +3VMOD
IDE_SDD3
IDE_SDD4 JMOD1
69
71
73
IDE_SDD5
IDE_SDD6 1 1
M1
IDE_SDD7 C613 C612
IDE_SDD8 1
IDE_SDD9 1 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D
2 2
IDE_SDD10 2 2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
4.7U_1206_16V6K~D
swap by Dell require 3 3
D IDE_SDD11 D
Please see sketch 4 1 1 1 1
IDE_SDD12 4
5
IDE_SDD13 5
C617
C614
C615
C616
6
IDE_SDD14 6
7
IDE_SDD15 7 2 2 2 2
8
<21> SATA_MODRX+ 8
9 +3VMOD
9
<21> IDE_SDA[0..2] 10
<21> SATA_MODRX- 10 +3VRUN
11
IDE_SDA0 11
12
IDE_SDA1 12 SATA_MOD_DETECT#
13 SATA_MOD_DETECT# <33> R569
IDE_SDA2 13 R567
14
<21> SATA_MODTX+ 14 MOD_PIN15
15 1 2 USB_OC4# USB_OC4# <20>
SATA_MOD_DETECT# 1 2
IDE_SDCS1# 15 @ 0_0402_5%~D
<21> IDE_SDCS1# 16
IDE_SDCS3# <21> SATA_MODTX- 16 100K_0402_5%~D
<21> IDE_SDCS3# 17
17
18
18 USBP4_D+
19 USBP4_D+ <26>
IDE_SDDACK# 19
Reserved USB+ 20
<21> IDE_SDDACK# 20 USBP4_D-
21 USBP4_D- <26>
IDE_SDIOR# 21
<21> IDE_SDIOR#
Reserved USB- 22
IDE_SDIOW# 22
<21> IDE_SDIOW# 23
IDE_SD IORDY 23
24
<21> IDE_SDIORDY 24 SIDEACT#
25 1 2 +3VMOD
IDE_SDCS3# 25
26
26 IDE_SDCS1# R564 1K_0402_5%~D
27
IDE_SDA2 27
28
INT_CD_R 28
29
<24> INT_CD_R IDE_SDA0 29 T12
30
30 PDIAG# @ PAD
31
INT_CD_L IDE_SDA1 31
32
<24> INT_CD_L 32 IDE_IRQ15
33
33
34
34 IDE_SDDACK#
35
C IDE_IRQ15 CSEL2 35 C
36
<20,21> IDE_IRQ15 36 IDE_SD IORDY
37
IDE_SDIOR# 37
38
BAY_MODPRES# 38
470_0402_5%~D
39
<33> BAY_MODPRES# 39
2
IDE_SDIOW# 40
40 RSDDREQ
41
RSDDREQ IDE_SDD15 41
R563
<21> RSDDREQ 42
42 IDE_SDD0
43
43
44 1
44
1
45 IDE_SDD14
IDE_SDD1 45
46
46 IDE_SDD13
47
IDE_SDD2 47
48
48
49
IDE_SDD12 49
50
50 IDE_SDD3
51 2
IDE_SDD11 51
52
52 IDE_SDD4
53
53
54
54 IDE_SDD10
55
IDE_SDD5 55
56 3
56 IDE_SDD9
57
IDE_SDD6 57
58
58
59 6
R555 IDE_SDD8 59
60 4
0_0402_5%~D 60 IDE_SDD7
61
IDE_RST_MOD_5V MOD_RST 61
<21> IDE_RST_MOD_5V 1 2 62 62
63
USB_IDE# 63
<33> USB_IDE# 64 64
65 INT_CD_R
R554 CD_AUDIORET 66
65 INT_CD_R <24> 5
<24> CD_AUDIORET 66
100K_0402_5%~D 67 INT_CD_L
B BAY_MODPRES# 67 INT_CD_L <24> B
WF1F068N1A
+3VRUN 1 2 +3VRUN 1 2 68 68
47P_0402_50V8J~D
47P_0402_50V8J~D
R553
M2
G
100K_0402_5%~D 1 1
70
72
74
C602
C601
2 2
FOX_QL11343-A6B3-HT~D
D-MODULE Detect
MB side Module side
JMOD1 Pin68 Pin64 Pin13
Connector
Device BAY_MODPRES# USB_IDE# SATA_MOD_DETECT#
Parallel IDE TOP VIEW
RX+ TX+ LOW LOW HIGH
RX- TX- USB Device
LOW HIGH HIGH
Host Chip Device Chip
TX+ RX+ S-ATA IDE
A ICH5 LOW HIGH LOW A
TX- RX-
None
HIGH X X

Title
Direct connect D- MODULE
X02-D
5 4 3 2 1
5 4 3 2 1
VD DA
+5VSUS
U 22 VDDA=4.75V
1 5 5 4
IN OUT
0.1U_0402_16V4Z~D
0.01U_0402_16V7K~D
0.1U_0402_16V4Z~D
2.2U_0805_16VFZ~D
1U_0805_10V6K~D
2
GND VD DA
1 1 2 1 1
C208
C209
C198
C215
C216
A UDIO_AVDD_ON 3 4 TPS793475_BYPASS
<34> A UDIO_AVDD_ON EN BYPASS
2
0.1U_0402_16V4Z~D
TPS793475DBVR_SOT23-5~D
2 2 1 2 2 L23
1
C224
BLM11A121S_0603~D
1 2 3
2
1
Z2401
single gate TTL
D D
U 21 1
5
SN74AHCT1G86DCKR_SC70-5~D C212
1 0.1U_0402_16V4Z~D
P
<21> S PKR A
4
Y 2
<33> BEEP 2
B
G
+ 5VRUN
5
U 20 R223 C192
1 20K_0402_5% 0.1U_0402_16V4Z~D
P
A Z2403 Z2404 PC_BEEPIN
4 1 2 1 2
Z24022 Y
1 <30> CBS_SPK B 2
1
G
2
C158 SN74AHCT1G86DCKR_SC70-5~D C190
3
0.1U_0402_16V4Z~D SP DIF_SHDN R237 R221 @1000P_0402_50V7K~D
2 43K_0402_5%~D 8.2K_0402_5%~D 1
2
1
5
U 12
OE#
P
SP DIF 2 4
A Y S P_DIF <18>
G
SN74AHCT1G125DCKR_SC70-5~D
3
+ 3VRUN L16
BLM31A260SPT_1206~D
W=30 mil AU DIO_AVCC 1 2
VD D A
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2.2U_0805_16VFZ~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2 2 2 2 2
C170
C576
C161
C580
C559
C 1 1 1 1 1 C
25
38
1
9
U 16
DVDD1
DVDD2
AVDD1
AVDD2
ICH_AC_R ST# 11 23
<20,27> ICH_AC_RST# RESET# LINE_IN_L
R531 I C H _A C_SYNC 10
<20,27> I C H _A C_SYNC SYNC
33_0402_5%~D ICH_AC_SDOUT 5
<20,27> ICH_AC_SDOUT SDATA_OUT
1 2 24
<20> ICH_AC_BITCLK R525 LINE_IN_R C195 1U_0805_10V6K~D
33_0402_5%~D 18 C D _L 1 2
CD_L INT_CD_L <23>
1 2 R_ICH_AC_BI TCLK 6
<27> MDC_AC_BITCLK BIT_CLK C196 1U_0805_10V6K~D
R534 19 CD_C OMM 1 2 CD_AUDIORET
CD_C CD_AUDIORET <23>
33_0402_5%~D
@ 27P_0603_50V8J~D
@ 27P_0603_50V8J~D
1 2 R _ICH_AC_SDIN0 8 C197 1U_0805_10V6K~D

<20> I C H_AC_SDIN0 SDATA_IN
1 1 20 C D _R 1 2
CD_R I NT_CD_R <23>
C575 1000P_0402_50V7K~D
C571
C579
1 2 AFLT1 29 14
2 2 C171
1
1000P_0402_50V7K~D
2 AFLT2 30
AFLT1
STAC9750 AUX_L
AFLT2 C201
15
AUX_R
1 2 C176 VREFOUT 28 0.22U_0603_10V7M~D
@ 0.1U_0603_16V7K~D VREFOUT CNB_MICIN
21 1 2 NB_MICIN <25>
AC97VREFI MIC1
27
VREF
2.2U_0805_16VFZ~D
0.1U_0402_16V4Z~D
22 1 2
MIC2
C186
C578
2 2
C AP2 32 16 C199
CAP2 VIDEO_L 0.1U_0402_16V4Z~D
2 SPK_SHUTDOW N# 43 17
1 1 <25,50> SPK_SHUTDOWN# GPIO0/NC VIDEO_R
C573
0.1U_0402_16V4Z~D
SP DIF_SHDN 44
1 GPIO1/NC
13 1 2
PHONE
B B
SP DIF 48 C200
SPDIF PC_BEEPIN 0.1U_0402_16V4Z~D
12
E APD PC_BEEP
47
<25> E APD EAPD
31 39 HP_OUT_L <25>
ICH_AC_SDOUT NC/BPCFG HP_OUT_L
C162
1U_0805_10V6K~D
1
40 HP_COMM 1 2
HP_COMM
2
33
R526 R512 NC/FLTIN
47_0402_5%~D 10K_0402_5%~D
41 HP_OUT_R <25>
HP_OUT_R
2
1
37
ICH_AC_SD OUT_TERM
MONO_OUT AUD_MONO_OUT <50>

R614 34
NC/FLTOUT
1 2 46
C183 @ 0_0402_5%~D CID1
45 35 AUD_LINE_OUT_L <25>
22P_0402_50V8J~D CID0 LOUT_L
1 2 XTL_24M+ 3 2
XTL_OUT
2
X2 C569
1000P_0402_50V7K~D
1
1 24.576 MHz_20P_1BX24576CC1A~D
C168 PACKAGE : 8X4.5X1.5mm
C 570 22P_0402_50V8J~D
1
@ 22P_0402_50V8J~D 1 2 XTL_24M- 2 36
DVSS1
DVSS2
AVSS1
AVSS2
2 XTL_IN LOUT_R AUD_LINE_OUT_R <25>
R 613 2
1 2 STAC9750_TQFP48~D C565
<6> CK_14M_CODEC
4
7
26
42
1000P_0402_50V7K~D
1
1
@ 0_0402_5%~D
A R612 A
1
@ 10_0402_5%~D
R 619
0_0402_5%~D
2
1
2
C 669
7/22/2003 Dell request (Mr. Richard) @4.7P_0402_50V8C~D
2
Title
AC97 Codec
X02-D
5 4 3 2 1
5 4 3 2 1
VD D A + 3VRUN + 3VRUN
VD DA
1
1
L46 R 459 C529
2
10K_0402_5%~D 1U_0603_6.3V6M~D
R 511 BLM11A121S_0603~D 2
1K_0402_5%~D
19
10
2
W=15mils U 38
1
AMPVCC
PVDD
SVDD
1
HP_NB_SEN SE 14 11 HP_OUT_RMAX
SHDNR# OUTR
1U_0805_10V6K~D
R_IN T_MIC+ 2 2
18 9 H P_OUT_LMAX
SHDNL# OUTL
2
1K_0402_5%~D
2 C157 C545
2
0.1U_0402_16V4Z~D
C 169
2.2U_0805_16VFZ~D R 503
1 1
R517
100K_0402_5%~D
C535
D 1 1U_0603_6.3V6M~D 4
D
NC-4
1
1 2 A UD_LINE_IN_R 15
<24> AUD_LINE_OUT_R INR
1
C561 6
0.1U_0402_16V4Z~D AUD_LINE_IN _L NC-6
<24> AUD_LINE_OUT_L 1 2 13
U 13 INL
8
INT _MIC- C_IN T_MIC- C539 NC-8
<38> INT_MIC- 1 2 5 4
INT_MIC- VSUP 1U_0603_6.3V6M~D 12
IN T_MIC+ C_IN T_MIC+ EXT_MIC_BIAS NC-12
<38> INT_MIC+ 1 2 6 3
INT_MIC+ EXT_MIC_BIAS
1 16
C179 C1P NC-16
7 2 NB_MICIN <24> 1
GND OUT
PGND
SGND
0.1U_0402_16V4Z~D 3 20
PVss
SVss
R505 EXT_MIC_PLUG C537 C1N NC-20
8 1
1K_0402_5%~D EXT_MIC_IN MIC_SELECT 1U_0603_6.3V6M~D
CMAMP110M_MSOP8~D 2 MAX4411ETP-T_TQFN20~D
17
1
R_IN T_MIC-
1U_0805_10V6K~D
C178
2 0.1U_0402_16V4Z~D
2
C 165
R497 C_EXT_MIC+ 1 2 EMICIN
1K_0402_5%~D
1 1
+ 3VRUN C547
1
1U_0603_6.3V6M~D
2
2
J AU DO
R197 EXT_MIC_PLUG 1 2 HP_NB_SEN SE
100K_0402_5%~D 1 2
3 4
EXT_MIC_BIAS 3 4 H P_OUT_LMAX
5 6
EMICIN 5 6 HP_OUT_RMAX
7 8
7 8
1
SPK_SHUTDOW N# 9 10
<24,50> SPK_SHUTDOWN# 9 10
+5VRUN 11 12
11 12
13 14
13 14
1
1
D D D
15 16
Q39 HP_NB_SEN SE 2 Q40 Q38 15 16
<24> E APD 2 2 <14> FAN1_VOUT 17 18 FAN1_TACH_FB <14>
<33> NB_MUTE 2N7002_SOT23~D 17 18
G G G 19 20
2N7002_SOT23~D 2N7002_SOT23~D 19 20
S S S
3
3
NAIS_AXN320C038P~D
C C
60mil single end connection near JACK
TRACE>15 mil J SPK

MOLEX_53398-0890~D
9
INT_SPK_L2 1
9
INT_SPK_L1 1
2
INT_SPK_R2 2
3
C639 INT_SPK_R1 3
4
22U_1206_16V4Z_V1 INT_SPK_L2 4
5
INT_SPK_L1 I NT_TWT_L1 5
1 2 6
INT_SPK_R2 6
7
INT_SPK_R1 IN T_TWT_R1 7
1 2 8
10
L48 8
1 2 + 5VRUN C638
10
22U_1206_16V4Z_V1
BLM21A05_0805
W=40mils
+5VAMPVCC
1 1 1 1
C626 C627 C628 C629
0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 10U_0805_10V4M~D 0.1U_0402_16V4Z~D + 5VRUN
2 2 2 2 Gain Setting INT_SPK_L1
B B
INT_SPK_L2
INT_SPK_R1
16
15
6
U 18 INT_SPK_R2
PVDD1
PVDD2
VDD
1
D7 D6 D9 D8
C 630
1
R582 R 583 @ D DA204U @ D DA204U @ D DA204U @ D DA204U
1 2 7 2 A UD_GAIN0 10K_0402_5%~D @ 10K_0402_5%~D
RIN+ GAIN0
0.47U_0603_16V4Z A UD_GAIN1
3
GAIN1
2
C631
<24> HP_OUT_R 1 2 17
RIN-
3
18 INT_SPK_R1 A UD_GAIN0
0.47U_0603_16V4Z ROUT+
+ 5VRUN
A UD_GAIN1
C 632 INT_SPK_R2
14
ROUT-
1 2 9
LIN+
0.47U_0603_16V4Z
1
1
4 INT_SPK_L1
C633 LOUT+ R584 R 585
1 2 5 @ 10K_0402_5%~D 10K_0402_5%~D
<24> HP_OUT_L LIN-
8 INT_SPK_L2
0.47U_0603_16V4Z LOUT-
2
12
NC
10 BY PASS
BYPASS
<24,50> SPK_SHUTDOWN# 19
SHUTDOWN
1 1 GAIN0 GAIN1 AV(inv) INPUT
GND1
GND2
GND3
GND4
IMPEDANCE
C634 C635
0.47U_0603_16V4Z @ 0.1U_0402_16V4Z~D
TPA6017A2PWPR_TSSOP20~D 2 2
0 0 6dB 90K ohm
20
13
11
1
A A
0 1 10dB 70K ohm
* 1 0 15.6dB 45K ohm
1 1 21.6dB 25K ohm

Title
AMP and Phone Jack Interface
X02-D
5 4 3 2 1
5 4 3 2 1
L27
BLM21PG600SN1D_0805~D
1 2
USB PORT# DESTINATION
R8 0_0402_5%~D U SBP5_PWR
150U _D2_6.3VM~D
0.1U_0402_16V4Z~D
1 2
1 0 Reserved
1
C262
C257
L2 +
@ DLW21SN900SQ2_0805~D
PLACE CHOKE(Resistors)
1 2 USBP5_D- NEAR CONNECTOR J USB1 1 BT
<20> USBP5- 1 2 2 2 USBP5_VCC
L30 USBP5_D- 1
4 3 USBP5_D+ BLM21PG600SN1D_0805~D USBP5_D+ 2 2 BACK
<20> USBP5+ 4 3 3
1 2 USBP5_GND
4
R7 0_0402_5%~D C3 C4 SUYIN_2569A-04G3T 3 DOG
@ 47P_0402_50V8J @ 47P_0402_50V8J
1 2
4
D
R408 0_0402_5%~D
MOD D
1 2
5 BACK
J USB2
L44 USBP2_VCC
@ DLW21SN900SQ2_0805~D U SBP2_PWR
1
L24
2
USBP2_D- 1 6
USBP1_D+ USBP2_D+ 2 BACK
150U _D2_6.3VM~D
0.1U_0402_16V4Z~D
1 2 BLM21PG600SN1D_0805~D
<20> USBP1+ 1 2 USBP1_D+ <27> 3
USBP2_GND
1
1
4 7
Reserved
C261
C258
4 3 USBP1_D- + SUYIN_2569A-04G3T
<20> USBP1- 4 3 USBP1_D- <27>
R407 0_0402_5%~D C462 C461
1 2 @ 47P_0402_50V8J @ 47P_0402_50V8J 2 2
R6 0_0402_5%~D 1 2
1 2 L25
L1
@ DLW21SN900SQ2_0805~D
1 2 USBP2_D- L29
<20> USBP2- 1 2 BLM21PG600SN1D_0805~D
1 2
USBP2_D+ U SBP6_PWR
<20> USBP2+ 4 3
4 3
150U _D2_6.3VM~D
0.1U_0402_16V4Z~D
1 J USB3
R5 0_0402_5%~D C2 C1 1 USBP6_VCC
1
C 263
C 259
1 2 @ 47P_0402_50V8J @ 47P_0402_50V8J + USBP6_D-
USBP6_D+ 2
R 12 0_0402_5%~D USBP6_GND 3
2 2 4
1 2
L28 SUYIN_2569A-04G3T
L4 BLM21PG600SN1D_0805~D
@DLW21SN900SQ2_0805~D 1 2
1 2 USBP3_D-
<20> USBP3- 1 2
C 4 3 USBP3_D+ C
<20> USBP3+ 4 3
R 11 0_0402_5%~D C8 C7
1 2 @ 47P_0402_50V8J @ 47P_0402_50V8J
R565 0_0402_5%~D
1 2 L31
L47 1 2
USBP3_PWR
@ DLW21SN900SQ2_0805~D
1 2 USBP4_D+ 1
<20> USBP4+ 1 2 USBP4_D+ <23>
2
C 265 + J D OG
4 3 USBP4_D- 150U _D2_6.3VM~D C260 USBP3_VCC 1
<20> USBP4- 4 3 USBP4_D- <23> T1
0.1U_0402_16V4Z~D USBP3_D- 2
R566 0_0402_5%~D 2 1 USBP3_D+ T2
3
C610 C611 USBP3_GND T3
1 2 1 2 4
@ 47P_0402_50V8J @ 47P_0402_50V8J L26 T4
BLM21PG600SN1D_0805~D D H_PORT_PWRSRC 5
DH_SMBDAT PWR_SRC
6
+5VSUS SMB_DATA
7
<34> DH_MOD_PRES# DH_SMBCLK SMB_ALERT
8
SMB_CLK
9
R 10 0_0402_5%~D +5VSUS GND
2
1 2 10
R 27 D AT_SMB DH_SMBDAT SHILD1
1 3 11
S
<19,34,35,47> DAT_SMB SHILD2
L3 10K_0402_5%~D 12
SHILD3
2
@ DLW21SN900SQ2_0805~D Q6 13
USBP6_D- R 17 2N7002_SOT23~D SHILD4
1 2
G
<20> USBP6- 1 2
2
10K_0402_5%~D FOX_UB11193-P01-TR~D
4 3 USBP6_D+
<20> USBP6+ 4 3
1
2
G
1
R9 0_0402_5%~D C5 C6 D
1 2 @ 47P_0402_50V8J @ 47P_0402_50V8J D H_POWER_EN# 2 Q1 CLK_SMB 1 3 DH_SMBCLK
B <19,34,35,47> CLK_SMB B
G 2N7002_SOT23~D
S
S Q2
3
2N7002_SOT23~D
1
D
D H _POWER_EN 2 Q4
G 2N7002_SOT23~D PW R _ SRC
S
3
2
R318
100K_0402_5%~D
Follow LK2 and need confirm final SPEC
3
2
1
Q66
SI4435DY_SO8~D
U SBP6_PWR Z2501 4
F1 L5
U SBP3_PWR
100K_0402_5%~D
1.8A_33VDC_SMD185~D BLM21PG600SN1D_0805~D
1
+5VSUS
1 2 D H _F USE_PWRSRC 1 2 D H_PORT_PWRSRC
R317
0.022U_0603_50V4Z~D
5
6
7
8
U 32
1 8 + 3VRUN
GND OC1# USB_OC6# <20> 1 1
2
2 7
IN OUT1
C292
1 3 6 F2 C9
C268 EN1# OUT2 D H _PW RSRC 0.1U_0603_25V7M~D
4 5
Z2502
EN2# OC2# USB_OC3# <20> 2 2
1
100K_0402_5%~D
0.1U_0402_16V4Z~D TPS2042ADR_SO8~D @ R AY _RUE250 R 316
2
2
10K_0402_5%~D
Q9
1
D
R306
2N7002_SOT23~D
2
U SBP5_PWR 2 D H _P WRSRC_OC
D H _ POWER_EN <33> D H _PW RSRC_OC <33>
A G A
1
S
1
+5VSUS U SBP2_PWR D
2 1 D H _ PWR_OC# 2 Q64
U 31 G 2N7002_SOT23~D
1 8 R307 S
GND OC1# USB_OC5# <20>
3
2 7 100K_0402_5%~D
IN OUT1
1 3 6
C269 EN1# OUT2
4 5 USB_OC2# <20>
EN2# OC2#
0.1U_0402_16V4Z~D
2
TPS2042ADR_SO8~D
Title
USB(2.0) Connector
<33> USB_EN# AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
X02-D
5 4 3 2 1
5 4 3 2 1
TOP view
MDC cable wire clip +3VSUS
1
1
L43
D D
BLM11A601S_0603~D
PAD2
2
1
MDC_CLIP
BT_PWR
PAD3 C459
0.1U_0402_16V4Z~D 10
1
2
MDC_CLIP FOX_HS6210_10P
JBT
10
10
9
<38> BT_ACTIVE 9
8
COEX2_WLAN_ACTIVE 8
<32> COEX2_WLAN_ACTIVE 7
T2 HW_RADIO_DIS# 7
<32,34> HW_RADIO_DIS# 6 12
PAD COEX1_BT_ACTIVE 6 12
<32> COEX1_BT_ACTIVE 5 11
@ COEX3 5 11
4
USBP1_D- 4
<26> USBP1_D- 3
USBP1_D+ 3
<26> USBP1_D+ 2
2
1
1
@10K_0402_5%~D
1
JST_BM10B-SRSS-TB~D
R412
C C
2
+3VSUS
JMDC
0.1U_0402_16V4Z~D
4.7U_1206_16V6K~D
2 1
AUDIO_PWDN MONO_OUT/PC_BEEP
MDM_MONO_PHONE 4 3 1 1
MONO_PHONE AGND
C159
C525
6 5
RESERVED AUXA_RIGHT
8 7
GND AUXA_LEFT
10 9
R449 +5V CD_GND 2 2
12 11
@ 10K_0402_5%~D RESERVED CD_RIGHT
14 13
Z2602 RESERVED CD_LEFT
1 2 16 15
+3VSUS
18
PRIMARY_DN
RESERVED
GND
3.3Vaux
17 W=20 mil
20 19
R457 RESERVED GND
<20,24> ICH_AC_SYNC 22 21
33_0402_5%~D AC97_SYNC 3.3Vmain
24 23 ICH_AC_SDOUT <20,24>
MDC_SDIN AC97_SDATA_IN1 AC97_SDATA_OUT
<20> ICH_AC_SDIN1 1 2 26 AC97_SDATA_IN0 AC97_RESET# 25 ICH_AC_RST# <20,24>
28 27
GND GND Z2604
30 AC97_BITCLK AC97_MSTRCLK 29
1
1
7/28 Changed to NP R454
2
@ 0_0402_5%~D
C527 @ 10K_0402_5%~D AMP_3-1612118-0~D
B by Dell's require @22P_0402_50V8J~D B
R463
R458
2 @ 10_0402_5%~D
2
1
ICH_AC_SDOUT_MDCTERM
<24> MDC_AC_BITCLK
2
R462
@ 10_0402_5%~D
1
MDC_AC_BITCLK_TERM
2
C526
@10P_0402_50V8J~D
1
2
C530
@10P_0402_50V8J~D
1
A A

Title
BT PORT and MDC
X02-D
5 4 3 2 1
5 4 3 2 1
+3VSRC
V_2P5_LAN
Q18 Nimitz 4401 Beijing 5705M
10U_1206_6.3V7K~D
0.1U_0402_16V4Z~D
SI3456DV-T1_TSOP6~D
L37 BCP69 2 2 @ Depop Depop
D
BLM31A260SPT_1206~D
6
C
S
VAUX_LAN
C25
C291
5 4 1 2 V_3P3_LAN
1@ Depop Pop
2
2 1 1
10U_1206_6.3V7K~D
10U_1206_6.3V7K~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1 2@ Pop Depop
2 2 2 2 2 2 2 2
G
Q5
B C E R311(1.27K_1%) R311(1.24K_1%)
3
C350
C343
C281
C282
C272
C286
C278
C275
1@ BCP69_SOT-223
<39> ENAB_3VLAN V_1P2_LAN
1 4 3 L32(H1238) L32(H5015T)
1 1 1 1 1 1 1 1 LAN_CTRL_1P2V 1
L33
BLM11A601S_0603~D
D V_1P2_PLLVDD_PHY D
V_1P2_LAN 1 2
2
4
2.2U_0805_16VFZ~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
10U_1206_6.3V7K~D
10U_1206_6.3V7K~D
20mils trace width 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2
2 1
C11
C17
C266
C267
C328
C335
C283
C320
C313
C274
C326
C307
C314
C306
C318
C309
C285
C293
V_3P3_LAN
+3V_LOM_PCI 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0.1U_0402_16V4Z~D
10U_1206_6.3V7K~D
1 2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2 2
2 2 2 2 2 2
C341
C332
C316
C310
C315
C330
C340
C323
Q65
1 1
3
1@ BCP69_SOT-223
1 1 1 1 1 1
LAN_CTRL_2P5V 1
Place within 100 mils to pins H14
Signal 4401 5705M
V_2P5_LAN
2
4
10U_1206_6.3V7K~D
10U_1206_6.3V7K~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
LAN_EECLK_SPROM_CLK No pullup for 16KB Pullup for 376KHz mode
1 1 2 2 2
LAN_EEDATA_SPROM_CS Pullup for 16KB No pullup
C333
C344
C312
C270
C279
2 2 1 1 1
R299 is poped for 4401 with AT93C86 (16KB)
R299 is poped for 5705M EEPROM 376KHz mode
R299 is depop for 4401 with AT93C46 (1KB)
<20,30,32> PCI_AD[0..31]
U2A V_3P3_LAN
PCI_AD31 B8 E13 LAN_TX3+
PCI_AD30 AD31 TRD3+ LAN_TX3- LAN_TX3+ <29>
A8 E14 LAN_TX3- <29>
C PCI_AD29 AD30 TRD3- LAN_TX2+ C
C7 D13 LAN_TX2+ <29>
PCI_AD28 AD29 TRD2+ LAN_TX2-
C6 D14 LAN_TX2- <29>
PCI_AD27 AD28 TRD2- LAN_RX1+
1@ 1K_0402_5%~D
1@ 0.1U_0402_16V4Z~D
B6 C13 LAN_RX1+ <29>
PCI_AD26 AD27 TRD1+ LAN_RX1-
1@ 10K_0402_5%~D
1@ 4.7K_0402_5%~D
B5 C14 LAN_RX1- <29>
AD26 TRD1-
1
PCI_AD25 A5 B13 LAN_TX0+ V_1P2_LAN
AD25 TRD0+ LAN_TX0+ <29> 1
PCI_AD24 LAN_TX0-
R302
R299
R296
B4 B14 LAN_TX0- <29>
PCI_AD23 AD24 TRD0-
C277
B2
PCI_AD22 AD23
B1
PCI_AD21 AD22 2
C1 B9
AD21 REGSUP12 V_2P5_LAN
2
PCI_AD20 D3 B10 LAN_CTRL_1P2V LAN_SMBCLK U2B
PCI_AD19 AD20 REGCTL12 LAN_SMBDATA LAN_SMBCLK <32>
D2 A9 LAN_SMBDATA <32>
PCI_AD18 AD19 REGSEN12 V_1P2_LAN
D1 E12 B7
PCI_AD17 AD18 VDDC_E12 VSS_B7
E3 B11 H5 D4 POP
PCI_AD16 AD17 REGSUP25 V_3P3_LAN VDDC_H5 VSS_D4
K1 C11 LAN_CTRL_2P5V H6 D5
PCI_AD15 AD16 REGCTL25 VDDC_H6 VSS_D5
PCI_AD14
L2
L1
AD15 REGSEN25
C10
V_2P5_LAN
H7
H8
VDDC_H7 VSS_D6
D6
D7
5705
PCI_AD13 AD14 VDDC_H8 VSS_D7 U33
M3 P1 +3VRUN J5 D8
PCI_AD12 AD13 VESD1 VDDC_J5 VSS_D8
M2 G2 J6 D9 8 1
PCI_AD11 AD12 VESD2 VDDC_J6 VSS_D9 LAN_EEPROM_W VCC A0
M1 A1 J7 E2 7 2
PCI_AD10 AD11 VESD3 VDDC_J7 VSS_E2 LAN_EECLK_SPROM_CLK WP A1
N2 J8 E5 6 3
PCI_AD9 AD10 VDDC_J8 VSS_E5 SCL NC
N3 P10 LAN_EEDATA_SPROM_CS J9 E6 LAN_EEDATA_SPROM_CS 5 4
PCI_AD8 AD9 EEDATA VDDC_J9 VSS_E6 SDA GND
P3 M10 LAN_EECLK_SPROM_CLK J10 E7
PCI_AD7 AD8 EECLK VDDC_J10 VSS_E7 1@ AT24C256N-10SC_SO8
N4 K5 E8
PCI_AD6 AD7 V_3P3_LAN +3VRUN VDDC_K5 VSS_E8
P4 H12 LAN_GPIO0 T8 @ PAD K6 E9
PCI_AD5 AD6 GPIO0 VDDC_K6 VSS_E9
M5 K13 LAN_EEPROM_W K7 F5
PCI_AD4 AD5 GPIO1 VDDC_K7 VSS_F5
N5 J13 LAN_GPIO2 T7 @ PAD K8 F6
PCI_AD3 AD4 GPIO2 VDDC_K8 VSS_F6 V_3P3_LAN
P5 AD3 K9 VDDC_K9 VSS_F7 F7
PCI_AD2
2@ BLM11A601S_0603~D
1@ BLM11A601S_0603~D
P6 K10 F8
PCI_AD1 AD2 VDDC_K10 VSS_F8 U34
M7 AD1 L5 VDDC_L5 VSS_F9 F9
2
PCI_AD0 N7 L10 F10 LAN_EEDATA_SPROM_CS 1 8
AD0 LINK_LED_10# VDDC_L10 VSS_F10 LAN_EECLK_SPROM_CLK CS VCC
G13 M14 G4 2 7
BCM5705M LINKLEDB
H13 LINK_LED_100#
LINK_LED_10# <29>
N14
VDDC_M14 VSS_G4
G5 LAN_SPROM_DOUT 3
SK NC
6
B SPD100LEDB LINK_LED_1000# LINK_LED_100# <29> VDDC_N14 BCM5705M VSS_G5 LAN_SPROM_DIN DI ORG B
L39
L38
SPD1000LEDB G12 LINK_LED_1000# <29> P8 VDDC_P8 VSS_G6 G6 4 DO GND 5
PCI_C_BE3# LAN_ACT#
2@ 10K_0402_5%~D
<20,30,32> PCI_C_BE3# C4 G14 LAN_ACT# <29> P12 G7
PCI_C_BE2# CBE3 TRAFFICLEDB VDDC_P12 VSS_G7 2@ AT93C46-10SI-2.7_SO8~D
<20,30,32> PCI_C_BE2# F3 CBE2 OR P13 VDDC_P13 OR VSS_G8 G8
1
PCI_C_BE1# L3 P14 G9
<20,30,32> PCI_C_BE1# CBE1 VDDC_P14 VSS_G9
1
PCI_C_BE0# M4 BCM4401 H14 V_1P2_PLLVDD_PHY BCM4401 G10
<20,30,32> PCI_C_BE0# CBE0 PLLVDD2 VSS_G10 POP
R312
P7 H9
R49 NC VSS_H9
100_0402_5%~D A7
VSS_K2 K2
L6
4401
PCI_AD16 +3V_LOM_PCI VDDIO-PCI_A7 VSS_L6
1 2 LAN_IDSEL A4 C12 B3 L9
IDSEL TCK VDDIO-PCI_B3 VSS_L9
2
PCI_FRAME# F2 D12 C5 M6
<20,30,32> PCI_FRAME# PCI_IR DY# FRAME TDI VDDIO-PCI_C5 VSS_M6
F1 B12 R310 2 E1 M12
<20,30,32> PCI_IRDY# IRDY TDO VDDIO-PCI_E1 VSS_M12
PC I_TRDY# G3 A12 4.7K_0402_1%~D C349 E4 M13
2@ 0.01U_0402_16V7K~D
<20,30,32> PCI_TRDY# PCI_DEVSEL# TRDY TMS LAN_TRST# 2 VDDIO-PCI_E4 VSS_M13
H3 D11 1 10U_1206_6.3V7K~D G1 N1
<20,30,32> PCI_DEVSEL# PCI_STOP# DEVSEL TRST VDDIO-PCI_G1 VSS_N1
<20,30,32> PCI_STOP# H1 K3 N12 1
PCI_PERR# STOP 1 VDDIO-PCI_K3 VSS_N12
J2 PERR L4 VDDIO-PCI_L4 VSS_N13 N13
<20,30,32> PCI_PERR# PCI_SERR#
C311
A2 N6
<20,30,32> PCI_SERR# PCI_PAR SERR VDDIO-PCI_N6 L36
<20,30,32> PCI_PAR J1 P2
CK_33M_LANPCI PAR V_2P5_LAN VDDIO-PCI_P2 BLM11A601S_0603~D 2
<6> CK_33M_LANPCI A3
PCI_CLK AVDD1P2
K14 F12 1 2 V_1P2_LAN
V_2P5_LAN VDDP_K14 AVDDL_F12
XTALVDD J14 L13 VDDP_L13 AVDDL_F13 F13
N10 XTALO P11 F14 AVDD2P5 1 2
PCI_PIRQC# XTALO XTALI VDDP_P11 AVDD_F14 V_2P5_LAN
1U_0805_10V6K~D
1@ 0.1U_0402_16V4Z~D
H2 N11 X1 A13 L6
<20,30> PCI_PIRQC# PCIRST_1# INTA XTALI 25MHz_20P_1BX25000CK1A~D AVDD_A13 1@BLM11A601S_0603~D
<20> PCIRST_1# C2 A11 2 2
PCI_GNT4# PCI_RST V_3P3_LAN VDDIO_A11
<20> PCI_GNT4# J3 GNT 2 2 1 2 F11 VDDIO_F11
PCI_REQ4#
C273
C20
C3 REQ SO
G11 K12
VDDIO_K12
<20> PCI_REQ4# C18 C34
SI E10 L12 VDDIO_L12
Place within 100 mils of ASIC
22P_0402_50V8J~D 22P_0402_50V8J~D 1 1
E11 pins, 10-20mils trace width
R303 SCLK 1 1
CS H11 C8 CSTSCHG
1K_0402_5%~D Place within 100 mils to pins N10 and N11 5705M_CLKRUN# H4 L11
LAN_AUXPWR CLKRUN NC_L11
2 1 J12 VAUXPRSNT H10 NC_H10 NC_L14 L14
V_3P3_LAN LAN_BIAS
10K_0402_5%~D
F4 A14 J4 M8
M66EN BIASVDD NC_J4 NC_M8
2
SYS_PME# A6 D10 LAN_RDAC K4 M9 R300 1@ 0_0603_5%~D

A <30,32,33> SYS_PME# PME RDAC NC_K4 NC_M9 5705M_LOWPWR A
R321
1 2 V_2P5_LAN J11 M11 1 2 LAN_LOW_PWR <34>

L35 NC_J11 LOW_POWER
K11 N8
2@ 1.27K_0402_1%~D
BLM11A601S_0603~D NC_K11 NC_N8 R313 2@ 0_0402_5%~D LAN_SPROM_DOUT

2 L7 N9 1 2
LAN_SMBCLK NC_L7 NC_N9 LAN_SPROM_DIN
SMB_CLK A10 L8 NC_L8 NC_P9 P9 1 2
1
C9 LAN_SMBDATA C271 R308 2@ 0_0402_5%~D

SMB_DATA
1
1000P_0402_50V7K~D 1@ BCM5705M_FBGA196~D
1@ 1.24K_0402_1%~D
2@ BCM4401
1
R311
1@ BCM5705M_FBGA196~D 2@ BCM4401 Should be pulled down for both 4401 and 5705M
Place within 100 mils of ASIC Title
R319 C321 Place within 50 mils of pin A14, 10mils trace width
ETHERNET
2
@ 10_0402_5%~D @ 8.2P_0402_50V8J~D ASIC pin D10

CK_33M_LANPCI 2 1 CLK_82540_TERM 1 2 5705M :1.24K_0402_1% 8-10mils trace width AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
X02-D
4401: 1.27K_0402_1% DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-1711
5 4 3 2 1
5 4 3 2 1
JLOM
V_2P5_LAN B2
V_2P5_LAN B2
V_3P3_LAN B1 B1 YEL B3 LAN_ACTLED_YEL#
GRN A3 LED_10_GRN#
R20 1 2 49.9_0402_1%~D LAN_TX0- A2
R19 49.9_0402_1%~D LAN_TX0+ A2
Magnetics pop options 1 2
4401: H1238 R22 1 2 49.9_0402_1%~D LAN_RX1- A1 LED_100_ORG#
R21 49.9_0402_1%~D LAN_RX1+ AMBER
5705M: H5015D 1 2
R24 1 2 1@ 49.9_0402_1%~D LAN_TX2- NB_LAN_TX+ 1
R23 LAN_TX2+ NB_LAN_TX- P1_1
1 2 1@ 49.9_0402_1%~D 2 P1_2
R26 1 2 1@ 49.9_0402_1%~D LAN_TX3- NB_LAN_RX+ 3
R25 LAN_TX3+ NB_LAN_TX2+ P1_3
1 2 1@ 49.9_0402_1%~D 4 P1_4
L32 NB_LAN_TX2- 5
D Z2805 NB_LAN_RX- P1_5 D
1 24 6
P1_6
1:1 NB_LAN_TX3+ 7
NB_LAN_TX3- P1_7
8 17
JPH_RJ P1_8 SGND1
18
LAN_TX3- NB_LAN_TX3- RJ_RING SGND2
<28> LAN_TX3- 2 23 1
1
RJ_TIP 2 RJ45/LED
2 RJ_TIP
6 10
6 RJ_RING P2_2
2 7 9
C16 7 P2_1
5
0.01U_0402_16V7K~D 5 RJ11
1@ JST_SM05B-SRSS-TB~D FOX_JM34F23-P3552-TR~D
1
LAN_TX3+ 3 22 NB_LAN_TX3+
<28> LAN_TX3+
D22
T1 T5 2 R33
<28> LAN_ACT#
10K_0402_5%~D
4 21 Z2806 1 2 1
1:1 V_3P3_LAN
3
1 2 LAN_ACTLED_YEL#
LAN_TX2- 5 20 NB_LAN_TX2- BAT54A_SOT23~D
<28> LAN_TX2-
R32
1
D 150_0402_5%~D
2
C14 2
<32> WLAN_LED_ACTIVITY
0.01U_0402_16V7K~D G Q3
1@ S 2N7002_SOT23~D
3
1
1
LINK CS 21.5
R600 V_3P3_LAN
10K_0402_5%~D
C C
1
LAN_TX2+ 6 19 NB_LAN_TX2+
<28> LAN_TX2+
R297
T2 T6 10K_0402_5%~D
7 18 Z2807
2
1:1
<28> LINK_LED_10#
LAN_RX1- 8 17 NB_LAN_RX- V_3P3_LAN
<28> LAN_RX1-
2
1
C13
1
0.01U_0402_16V7K~D D11
RB495D_SOT23~D R293
1 10K_0402_5%~D
2
<28> LINK_LED_100#
LAN_RX1+ 9 16 NB_LAN_RX+
<28> LAN_RX1+ LINK_LED_1000# <28>
T3 T7 V_3P3_LAN D12
Z2808 R305
10 15 3
1
1:1 1 2 1
2
D10 1@ 10K_0402_5%~D
LAN_TX0- 11 14 NB_LAN_TX- RB495D_SOT23~D
<28> LAN_TX0- 1@ RB495D_SOT23~D
2
C15
3
B 0.01U_0402_16V7K~D B
R304 R292
1 10K_0402_5%~D 200_0402_5%~D
1 2 1 2 LED_100_ORG#
V_3P3_LAN
1
Q63
LAN_TX0+ 12 13 NB_LAN_TX+ R309
<28> LAN_TX0+
10K_0402_5%~D DTC144EKA_SOT23~D
47K
T4 T8 <32> LED_WLAN5_RADIOSTATE 2 1 2
1@ H5015D~D 2@ H1238
DTC144EKA 47K
3
1
R295 R298
C 10K_0402_5%~D 200_0402_5%~D
1
2 3 1 2 1 2 LED_10_GRN#
R601 V_3P3_LAN
10K_0402_5%~D
B E
5
6
7
8
1
RN6 Q62
2
75_1206_8P4R_5%~D R294
10K_0402_5%~D DTC144EKA_SOT23~D
47K
C264 2 1 2
<32> LED_WLAN24_RADIOSTATE
4
3
2
1
1000P_1808_3KV7K~D
1 2
1
47K
Nimitz 4401 Bejing 5705M R602
3
10K_0402_5%~D
A A
@ Depop Depop GND

2
CHASIS
1@ Depop Pop
2@ Pop Depop Compal Electronics, Inc.
Title
LAN TRANSFOMER
Size Document Number R ev
X02-D
LA-1711
Date: W ednesday, July 23, 2003 Sheet 29 of 60
5 4 3 2 1
5 4 3 2 1
<20,28,32> PCI_AD[0..31] Remove R756

CBS_CAD[0..31] <31>
U9A 8/12 Changed by
PCI_AD31 J5 E8 CBS_CAD31 +3V_CBSD
PCI_AD30 AD31 CAD31/D10 CBS_CAD30 +3V_CBSD +3V_CBSA Dell's Require
J6 AD30 CAD30/D9 C8
PCI_AD29 K2 B8 CBS_CAD29
PCI_AD28 AD29 CAD29/D1 CBS_CAD28 R483 U9B
K3 AD28 CAD28/D8 E9
PCI_AD27 K5 F9 CBS_CAD27 1K_0402_5%~D G1
PCI_AD26 AD27 CAD27/D0 CBS_CAD26 PHY_CPS VCC
K6 AD26 CAD26/A0 F11 2 1 P10 CPS VCC M1
2
PCI_AD25 CBS_CAD25
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
L2 E11 R510 R1
PCI_AD24 AD25 CAD25/A1 CBS_CAD24 VCC
R191
R177
R174
L3 C11 10K_0402_5%~D W8
PCI_AD23 AD24 CAD24/A2 CBS_CAD23 PHY_CNA VCC
M2 AD23 CAD23/A3 A12 1 2 P17 CNA VCC L19
PCI_AD22 M3 C12 CBS_CAD22 H19
PCI_AD21 AD22 CAD22/A4 CBS_CAD21 VCC
M6 AD21 CAD21/A5 E12 VCC E19
1
PCI_AD20 CBS_CAD20
D PCI_AD19
PCI_AD18
M5
N2
N3
AD20
AD19 PCI7510 CAD20/A6
CAD19/A25
C13
A14
E13
CBS_CAD19
CBS_CAD18
@ @ @ CBS_PC0
CBS_PC1
V10
W10
PC0
VCC
VCC
A13
A8
A5
D
PCI_AD17 AD18 CAD18/A7 CBS_CAD17 CBS_PC2 PC1 VCC

PCI_AD16
PCI_AD15
N6
P1
R6
AD17
AD16
CAD17/A24
CAD16/A17
B14
F18
G17
CBS_CAD16
CBS_CAD15 R495 PCI4510_R0
P9
W13
PC2
PCI7510 G14
CBS_VCC
AD15 CAD15/IOWR# R0 VCCCB
2
PCI_AD14 CBS_CAD14
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
P7 F19 @ 1M_0603_5%~D A11
PCI_AD13 AD14 CAD14/A9 CBS_CAD13 PCI4510_R1 VCCCB
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
R188
R186
R171
V5 G18 1 2 V13 1 1
PCI_AD12 AD13 CAD13/IORD# CBS_CAD12 R1
C541
C538
U6 H15 L1
PCI_AD11 AD12 CAD12/A11 CBS_CAD11 VCCP
V6 H14 1 2 W5
PCI_AD10 AD11 CAD11/OE# CBS_CAD10 R487 VCCP
R7 H17
AD10 CAD10/CE2#
1
PCI_AD9 P8 H18 CBS_CAD9 6.34K_0603_1%~D G2 2 2
PCI_AD8 AD9 CAD9/A10 CBS_CAD8 IEEE1394_TPA0P VR_PORT +1.8V_CBSD
U7 J14 <31> IEEE1394_TPA0P V12 L18
PCI_AD7 AD8 CAD8/D15 CBS_CAD7 TPA0P VR_PORT
W7 J17
PCI_AD6 AD7 CAD7/D7 CBS_CAD6 IEEE1394_TPA0N
R8 K14 <31> IEEE1394_TPA0N W12 This shall be output
PCI_AD5 AD6 CAD6/D13 CBS_CAD5 R507 TPA0N +3V_CBSD
U8 J19 E6 CBS_VCCD0# <31>
PCI_AD4 AD5 CAD5/D6 CBS_CAD4 @ 1K_0402_5%~D VD1/VCCD0
V8 K17 B5 CBS_VCCD1# <31>
PCI_AD3 AD4 CAD4/D12 CBS_CAD3 IEEE1394_TPA1P VD0/VCCD1
W9 K15 2 1 V15
PCI_AD2 AD3 CAD3/D5 CBS_CAD2 TPA1P
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
V9 L14 2 2
PCI_AD1 AD2 CAD2/D11 CBS_CAD1 IEEE1394_TPA1N
C531
C555
U9 K18 2 1 W15 A4 CBS_VPPD0 <31>
PCI_AD0 AD1 CAD1/D4 CBS_CAD0 R496 TPA1N VD3/VPPD0
R9 L15 C5 CBS_VPPD1 <31>
AD0 CAD0/D3 @ 1K_0402_5%~D VD2/VPPD1
IEEE1394_TPB0P V11 1 1
<31> IEEE1394_TPB0P TPB0P
B11 CBS_CC/BE3# IEEE1394_TPB0N W11 E1
CC/BE3/REG# CBS_CC/BE3# <31> <31> IEEE1394_TPB0N TPB0N GND
PCI_C_BE3# L6 C14 CBS_CC/BE2# K1
<20,28,32> PCI_C_BE3# PCI_C_BE2# C/BE3 CC/BE2/A12 CBS_CC/BE1# CBS_CC/BE2# <31> IEEE1394_TPB1P GND
<20,28,32> PCI_C_BE2# P2 G15 CBS_CC/BE1# <31> 2 1 R502 V14 N1
PCI_C_BE1# C/BE2 CC/BE1/A8 CBS_CC/BE0# 1K_0402_5%~D TPB1P GND R452 +3V_CBSD
<20,28,32> PCI_C_BE1# U5 J15 CBS_CC/BE0# <31> W6
PCI_C_BE0# C/BE1 CC/BE0/CE1# IEEE1394_TPB1N GND
<20,28,32> PCI_C_BE0# V7 2 1 R486 W14 P19 @ 10K_0402_5%~D
C/BE0 CBS_CRST# 1K_0402_5%~D TPB1N GND
B13 CBS_CRST# <31> K19 2 1
CRST/RESET CBS_CFRAME# IEEE1394_TPBIAS0 GND
CFRAME/A23 B15 CBS_CFRAME# <31> <31> IEEE1394_TPBIAS0 U12
TPBIAS0 GND
G19
F13 CBS_CIRDY# A15 R451
CIRDY/A15 CBS_CTRDY# CBS_CIRDY# <31> IEEE1394_TPBIAS1 GND
CTRDY/A22 E14 CBS_CTRDY# <31> 2 1 R515 U15
TPBIAS1 GND
A10 0_0402_5%~D
C PCI_PAR CBS_CDEVSEL# @ 1K_0402_5%~D C
<20,28,32> PCI_PAR W4 A16 CBS_CDEVSEL# <31> A7 2 1
PAR CDEVSEL/A21 CBS_CSTOP# GND
E17 CBS_CSTOP# <31>
CSTOP/A20 CBS_CPERR# R446
CPERR/A14 F15 CBS_CPERR# <31> 2 1
E10 CBS_CSERR# H5 1V8_VR_EN# 10K_0402_5%~D
CSERR/WAIT# CBS_CPAR CBS_CSERR# <31> VR_EN
F14 C167 2 1
PCI_DEVSEL# CPAR/A13 CBS_CREQ# CBS_CPAR <31> +3V_CBSD
R2 B12 1U_0805_10V6K~D R11
<20,28,32> PCI_DEVSEL# DEVSEL CREQ/INPACK# CBS_CREQ# <31> +3V_CBSA ANALOGVCC
PCI_FRAME# N5 D19 CBS_CGNT# R494 U13 G3 TI_SUSPEND#_INTERNAL 2 1
<20,28,32> PCI_FRAME# PCI_GNT1# FRAME CGNT/WE# CBS_CGNT# <31> ANALOGVCC SUSPEND TI_SUSPEND# <34>
<20> PCI_GNT1# J1 C15 CBS_CCLK_INTERNAL 2 1 CBS_CCLK
CBS_CCLK <31> U14
GNT CCLK/A16 47_0402_5%~D ANALOGVCC D15
PCI_IR DY# P3 A9 CBS_CSTSCHNG U11 RB751V_SOD323~D
<20,28,32> PCI_IRDY# PCI_PERR# IRDY CSTSCHG/BVD1 CBS_CCLKRUN# CBS_CSTSCHNG <31> CBS_CCD1# <31> ANALOGGND SYS_PME#
0_0402_5%~D
0_0402_5%~D
R3 B9 CBS_CCLKRUN# <31> CBS_CCD2# <31> R12 J3 SYS_PME# <28,32,33>
<20,28,32> PCI_PERR# PERR CCLKRUN/WP ANALOGGND RI_OUT/PME
2
PCI_REQ1# J2 R13
<20> PCI_REQ1# PCI_SERR# REQ CBS_CBLOCK# ANALOGGND CBS_SPK
R516
R482
T1 E18 CBS_CBLOCK# <31> E2 CBS_SPK <24>
<20,28,32> PCI_SERR# PCI_STOP# SERR CBLOCK/A19 CBS_CINT# SPKROUT
<20,28,32> PCI_STOP# P5 STOP CINT/READY C10 CBS_CINT# <31> +3V_CBSA
P15
VDPLL
PC I_TRDY# P6 F5 PCI_PIRQD#
<20,28,32> PCI_TRDY# PCIRST_CB# TRDY CBS_CAUDIO MFUNC0 PCI_PIRQC# PCI_PIRQD# <20,32>
<20> PCIRST_CB# H3 PCIRST CAUDIO/BVD2
F10 CBS_CAUDIO <31> MFUNC1
G6 PCI_PIRQC# <20,28>
1
C9 CBS_CCD2#_INTERNAL F3 PCI_REQB#
CCD2/CD2# MFUNC2 PCI_REQB# <20>
CBS_GRST# H2 L17 CBS_CCD1#_INTERNAL F2 IRQ_SERIRQ
<33> CBS_GRST# GRST CCD1/CD1# MFUNC3 CBS_RI# IRQ_SERIRQ <20,21,33>
N14 G5 CBS_RI# <21>
CBS_CVS2 VSPLL/RSVD MFUNC4 PCI_GNTB#
@ 270P_0603_50V7K~D
@ 270P_0603_50V7K~D
R470 100_0402_5%~D F12 C557 F1 +3V_CBSD
PCI_AD17 CBS_IDSEL CVS2/VS2# CBS_CVS1 CBS_CVS2 <31> FILTER0 MFUNC5 CBS_MFUNC6 PCI_GNTB# <20>
1 2 L5 B10 0.1U_0402_10V6K~D T19 H6 1 2
IDSEL CVS1/VS1# CBS_CVS1 <31> FILTER1 FILTER0 MFUNC6
1 2 1 2 R17 R455 10K_0402_5%~D
R481 @ 10K_0402_5%~D CBS_RSVD/D2 FILTER1
F8 CBS_RSVD/D2 <31>
CRSVD/D2 CBS_RSVD/A18
<6> CK_33M_CBPCI H1 F17 CBS_RSVD/A18 <31> N15
PCICLK CRSVD/A18 CBS_RSVD/D14 RSVD CBS_SCL
J18 CBS_RSVD/D14 <31> 2 2 E3
CRSVD/D14 SCL
2
M14 D1 CBS_SDA +3V_CBSD

RSVD SDA
C566
C540
R163 N17 RSVD PHY_TEST_MA
@ 10_0402_5%~D N18 P18 2 1
1@ PCI7510GHK_PBGA209~D 1 1 SCR_IF_GPIO5 RSVD PHY_TEST_MA R504 4.7K_0402_5%~D
<31> SCR_IF_GPIO5 N19 SC_GPIO5
2@ PCI4510 M15 U10 CBS_TEST0 2 1
RSVD SKT_SEL0
1
SCR_IF_GPIO4 M17 R450 200_0402_5%~D

<31> SCR_IF_GPIO4 SC_GPIO6
SCR_IF_GPIO3 M18 R10 CBS_TEST1 2 1
CK33M_CBS_TERM
B <31> SCR_IF_GPIO3 SCR_IF_GPIO2 SC_GPIO1 SKT_SEL1 B

M19 R447 200_0402_5%~D
<31> SCR_IF_GPIO2 SC_GPIO0
F6 CK_48M_SCR
SCR_DETECT CLK_48 CK_48M_SCR <6>
<31> SCR_DETECT B7 SC_CD
2
+3VSUS +3V_CBSA SCR_IF_RST C7
L13 <31> SCR_IF_RST SCR_IF_CLK SC_RST PCI4510XI R453
F7 SC_CLK XI R18
BLM21A601SPT_0805~D <31> SCR_IF_CLK SCR_IF_DATA
<31> SCR_IF_DATA A6 @ 10_0402_5%~D
SCR_IF_PWR SC_DATA
1 2 B6
<31> SCR_IF_PWR SCR_IF_GPIO0 SC_GPIO3
0.047U_0402_10V4M~D
0.047U_0402_10V4M~D
0.047U_0402_10V4M~D
0.047U_0402_10V4M~D
<31> SCR_IF_GPIO0 E7
SC_GPIO2
1
SCR_IF_GPIO1 PCI4510XO
10U_0805_10V4M~D
<31> SCR_IF_GPIO1 C6 SC_GPIO4 XO R19
CK48M_CBS_TERM
2 2 1 2 2
C160
C164
C536
C542
C544
2 X3
1@ PCI7510GHK_PBGA209~D 24.576MHz_16P_1BG24576CKIA~D
C139 2@ PCI4510 1 2
@ 4.7P_0402_50V8C~D 1 1 2 1 1
1
22P_0402_50V8J~D
22P_0402_50V8J~D
1 1
C184
C185
+1.8V_CBSD 2 2
2
L15 +3V_CBSD C523
BLM21A601SPT_0805~D @ 4.7P_0402_50V8C~D
1
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1 2
+3VSUS
0.047U_0402_10V4M~D
0.047U_0402_10V4M~D
0.047U_0402_10V4M~D
0.047U_0402_10V4M~D
0.047U_0402_10V4M~D
0.047U_0402_10V4M~D
1 1
10U_0805_10V4M~D
10U_0805_10V4M~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C520
8/12 Changed by
C560
1 1 1 1 1 1 1 1 1 1
Dell's Require
2 2
C562
C532
C173
C172
C521
C522
C524
C533
C556
C543
R444 R445 +3V_CBSD

220_0402_5%~D @ 2.7K_0603_5%~D
2 2 2 2 2 2 2 2 2 2 CBS_SCL
2 1 2 1
A CBS_SDA A
2 1 2 1
R165
220_0402_5%~D R164
@ 2.7K_0603_5%~D

Title
PCMCIA Controller
X02-D
5 4 3 2 1
5 4 3 2 1
JCBUS
Nimitz PCI4510 Beijing PCI7510 80 80 40 40
CBS_CCD2# 79 39 CBS_CCLKRUN#
CBS_CAD31 79 39 CBS_RSVD/D2
@ Depop Depop 78 78 38 38
CBS_CAD30 77 37 CBS_CAD29
1@ Depop Pop 76 76 36 36
CBS_CSTSCHNG 75 35 CBS_CAD26
+3VSUS 75 35 CBS_CAD25
2@ Pop Depop 74 74 34 34
CBS_CAUDIO 73 33 CBS_CAD24
R468 CBS_CC/BE3# 73 33 SCR_DETECT_C
72 72 32 32 SCR_DETECT_C <34>
10K_0402_5%~D CBS_CREQ# 71 31 CBS_CAD23
SCR_IF_GPIO0 +5VSUS CBS_CSERR# 71 31 CBS_CAD22
2 1 70 70 30 30
69 29 SCR_VCC_C
R464 R185 CBS_CRST# 69 29 CBS_CAD21
68 68 28 28
10K_0402_5%~D @ 0_0402_5%~D CBS_CVS2 67 27 CBS_CAD20
D R194 SCR_IF_GPIO1 SCR_VPP_PIN66 67 27 SCR_RST_C D
2 1 1 2 66
66 26
26
T3 @ 0_0402_5%~D CBS_CAD19 65 25 CBS_CAD18
PAD NC_SCR_C4 SCR_C4_C R202 C656 CBS_CAD17 65 25 CBS_CC/BE2#
2 1 64
64 24
24
@ 10K_0402_5%~D 1 2 SCR_DATA_C 63 23 SCR_CLK_C
SCR_IF_GPIO2 CBS_CFRAME# 63 23 CBS_CIRDY#
2 1 62
62 22
22
R193 1@ 100P_0402_50V8J~D CBS_CTRDY# 61 21 CBS_CCLK
T4 @ 0_0402_5%~D R203 SCR_C8_C 61 21 SCR_C4_C
60 20
NC_SCR_C8 60 20
PAD 2 1 SCR_C8_C 10K_0402_5%~D
CBS_VPP 59
59 19
19 CBS_VPP
@ 2 1 SCR_IF_GPIO3 58 18
CBS_VCC CBS_CDEVSEL# 58 18 CBS_CINT# CBS_VCC
57 17
R201 CBS_CSTOP# 57 17 CBS_CGNT#
Depop if support Smart Card 56 16
R172 10K_0402_5%~D CBS_CBLOCK# 56 16 CBS_CPERR#
55 15
SCR_DETECT SCR_DETECT_C SCR_IF_GPIO4 CBS_RSVD/A18 55 15 CBS_CPAR
2 1 2 1 54 14
<30> SCR_DETECT CBS_CAD16 54 14 CBS_CC/BE1#
53 13
2@ 0_0402_5%~D R200 R204 CBS_CAD15 53 13 CBS_CAD14
52 12
10K_0402_5%~D 0_0603_5%~D CBS_CAD13 52 12 CBS_CAD12
51 11
51 11
1
2 1 SCR_IF_GPIO5 1 2 CAGE50_GND 50 10 CAGE10_GND

SCR_VCC_C CBS_CVS1 50 10 CBS_CAD11
0.1U_0402_16V4Z~D
R173 49 9
49 9
2
10K_0402_5%~D R461 CBS_CAD10 48 8 CBS_CAD9
10K_0402_5%~D CBS_CAD8 48 8 CBS_CC/BE0# R205
1 47 7
SCR_IF_PWR CBS_RSVD/D14 47 7 CBS_CAD7
C175
2 1 46 6 @ 0_0603_5%~D
46 6
2
Place near ncn6000 44 4
44 4
1
2 CBS_CAD2 CBS_CAD1
43 3
CBS_CCD1# 43 3 CBS_CAD0
42 2
42 2
41 1
41 1
1@
<30> IEEE1394_TPBIAS0 81 82
G G
83 84
+3VSUS G G
85 86
85 86
1U_0805_10V6K~D
1
1
U17 L14 FOX_QT8R080A-1910_LB~D
56.2_0603_1%~D
56.2_0603_1%~D
2
C SCR_IF_GPIO2 1@ 22U_LQH43MN220J01K_2OHM_1812~D C
<30> SCR_IF_GPIO2 1 20
SCR_IF_GPIO3 A0 VBAT LOUT_H
R480
R469
C163
2 19 1 2 J1394
<30> SCR_IF_GPIO3 SCR_IF_GPIO0 A1 LOUT_H LOUT_L
3 18 L7 8
<30> SCR_IF_GPIO0 PGM# LOUT_L 1 SGND4
SCR_IF_PWR 4 17 5 4 7
<30> SCR_IF_PWR PWR_ON PWR_GND 5 4 SGND3
2
SCR_IF_GPIO1 5 16 6
<30> SCR_IF_GPIO1 SCR_IF_GPIO5 STATUS GROUND SCR_VCC_C SGND2
<30> SCR_IF_GPIO5 6 15 5
SCR_IF_RST CS# CRD_VCC SCR_DATA_C SGND1
<30> SCR_IF_RST 7 14 6 3
SCR_IF_DATA RESET# CRD_IO SCR_CLK_C IEEE1394_TPA0P 6 3 TPA0+
<30> SCR_IF_DATA 8 13 <30> IEEE1394_TPA0P 7 2 4
SCR_IF_GPIO4 I/O CRD_CLK SCR_RST_C IEEE1394_TPA0N 7 2 TPA0- 4
<30> SCR_IF_GPIO4 9 12 <30> IEEE1394_TPA0N 3
SCR_IF_CLK INT# CRD_RST SCR_DETECT_C IEEE1394_TPB0P TPB0+ 3
<30> SCR_IF_CLK 10 11 <30> IEEE1394_TPB0P 2
CLOCK_IN CRD_DET IEEE1394_TPB0N TPB0- 2
<30> IEEE1394_TPB0N 8 1 1
1@ NCN6000_TSSOP20~D 8 1 1
@ 857CM-0009~D MOLEX_54515-0411~D
56.2_0603_1%~D
56.2_0603_1%~D
2
2
R144
0_0402_5%~D
R460
R456
1 2
+3VSUS R145
0_0402_5%~D
1
SCR_VCC_C SCR_RST_C SCR_CLK_C 1 2
Z3008
470P_0402_50V7K~D
R146
1@ 56P_0402_50V8J~D
1@ 4.7U_1206_16V6K~D
270P_0603_50V7K~D
1@ 10U_1206_6.3V7K~D
1@ 0.1U_0402_16V4Z~D
1@ 10K_0402_5%~D
1@ 0.1U_0402_16V4Z~D
0_0402_5%~D
1
1@ 22K_0402_5%
1@ 22K_0402_5%
5.1K_0603_1%~D
1 1 1 1 1 2
1
2
C151
1 1 2 R147
C174
C182
R170
C150
C149
C154
C528
R448
0_0402_5%~D
R187
R189
1 2
2 2 2 2
2
2 2 1
2
1
CBS_CCLK CBS_CAD[0..31] <30>
1@
CBS_CCLK <30>
CBS_CC/BE3# CBS_CAD31
B CBS_CC/BE2# CBS_CC/BE3# <30> CBS_CAD30 B
CBS_CC/BE2# <30>
CBS_CC/BE1# CBS_CAD29
Place near NCN6000 Place near connector CBS_CC/BE0# CBS_CC/BE1# <30> CBS_CAD28
CBS_CC/BE0# <30> CBS_CAD27
CBS_CRST# CBS_CAD26
CBS_CRST# <30>
CBS_CFRAME# CBS_CAD25
CBS_CIRDY# CBS_CFRAME# <30> CBS_CAD24
CBS_CTRDY# CBS_CIRDY# <30> CBS_CAD23
L10
CBS_CDEVSEL# CBS_CTRDY# <30> CBS_CAD22
1000P_0402_50V7K~D
0.1U_0402_16V4Z~D
BLM31A260SPT_1206~D
CBS_CDEVSEL# <30>
TPS2211VCC CBS_CSTOP# CBS_CAD21
10U_1206_6.3V7K~D
1 2 CBS_CSTOP# <30>
CBS_VCC CBS_CPERR# CBS_CAD20
CBS_CPERR# <30>
1 1 1 CBS_CSERR# CBS_CAD19
CBS_CPAR CBS_CSERR# <30> CBS_CAD18
C135
C136
1
C143
SHDN# VPPD1 VPPD0 CBS_VPP CBS_CREQ# CBS_CPAR <30> CBS_CAD17
C137
CBS_CREQ# <30>
U10 4.7U_1206_16V6K~D 1 0 0 CBS_CAD16
13 2 2 2 CBS_CGNT# CBS_CAD15
AVCC1 2 CBS_CGNT# <30>
12 1 0 1 CBS_CSTSCHNG CBS_CAD14
AVCC2 CBS_CCLKRUN# CBS_CSTSCHNG <30> CBS_CAD13
0.1U_0402_16V4Z~D
4.7U_1206_16V6K~D
9 11 CBS_CCLKRUN# <30>
+12V 12V AVCC3 CBS_CBLOCK# CBS_CAD12
1 CBS_VPP 1 1 0 CBS_CBLOCK# <30>
C144 1 1 CBS_CINT# CBS_CAD11
CBS_CINT# <30>
CBS_CAUDIO CBS_CAD10
C145
C142
0.1U_0402_16V4Z~D 1 1 1
CBS_CVS2 CBS_CAUDIO <30> CBS_CAD9
2 CBS_CVS1 CBS_CVS2 <30> CBS_CAD8
10 AVPP:150mA 0 X X CBS_CVS1 <30>
AVPP 2 2 CBS_CAD7
5 CBS_CAD6
+5VSUS 5V_1 CBS_RSVD/D14 CBS_CAD5
1 6 5V_2 SHDN# VCCD1# VCCD0# CBS_VCC CBS_RSVD/D2
CBS_RSVD/D14 <30>
CBS_CAD4
C156
CBS_VCCD0# CBS_RSVD/A18 CBS_RSVD/D2 <30> CBS_CAD3
0.1U_0402_16V4Z~D 1 1 0 0
VCCD0# CBS_VCCD1# CBS_VCCD0# <30> CBS_RSVD/A18 <30> CBS_CAD2
2 CBS_VCCD1# <30>
2 VCCD1# CBS_VPPD0 CBS_CAD1
VPPD0 15 CBS_VPPD0 <30> 1 0 1
14 CBS_VPPD1 CBS_CCD1# CBS_CAD0
VPPD1 CBS_VPPD1 <30> CBS_CCD1# <30>
A
1 1 0 A
3 CBS_CCD2#
+3VSUS 3.3V_1 CBS_CCD2# <30>
1 4 8 1 1 1
SHDN#
C155 3.3V_2 OC#

GND
0.1U_0402_16V4Z~D AVCC:1A 0 X X
2 TPS2211ADBR_SSOP16~D
7
16

Title
SUSPWROK_5V <39,43,45>
CardBus Socket
X02-D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Monday, August 11, 2003 Sheet 31 of 60
5 4 3 2 1
5 4 3 2 1
<20,28,30> PCI_AD[0..31]
+3VRUN +3VRUN
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4 JPCI
PCI_AD5 1 2
PCI_AD6 TIP RING
PCI_AD7
PCI_AD8 3 4
PCI_AD9 8PMJ-3 8PMJ-1
5 8PMJ-6 8PMJ-2 6
PCI_AD10 7 8
PCI_AD11 8PMJ-7 8PMJ-4
9 8PMJ-8 8PMJ-5 10
D PCI_AD12 WLAN_LED_ACTIVITY LED_WLAN24_RADIOSTATE D
11 12 LED_WLAN24_RADIOSTATE <29>
PCI_AD13 <29> WLAN_LED_ACTIVITY HW_RADIO_DIS# LED1_GRNP LED2_YELP LED_WLAN5_RADIOSTATE
13 14 LED_WLAN5_RADIOSTATE <29>
PCI_AD14 <27,34> HW_RADIO_DIS# LED1_GRNN LED2_YELN
15 16
PCI_AD15 PCI_PIRQD# CHSGND RESERVED
17 18 +5VRUN
PCI_AD16 <20,30> PCI_PIRQD# INTB# 5V PCI_PIRQB#
19 20 PCI_PIRQB# <18,20>
PCI_AD17 3.3V INTA#
21 22
PCI_AD18 RESERVED RESERVED
23 24 V_3P3_LAN
PCI_AD19 CK_33M_MINIPCI GROUND 3.3VAUX PCIRST_2#
<6> CK_33M_MINIPCI 25 26 PCIRST_2# <20>
PCI_AD20 CLK RST#
27 28 2 2
PCI_AD21 PCI_REQ3# GROUND 3.3V PCI_GNT3# C252 C253
29 30 PCI_GNT3# <20>
PCI_AD22 <20> PCI_REQ3# REQ# GNT# 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D
31 32
PCI_AD23 PCI_AD31 3.3V GROUND SYS_PME#
33 34 SYS_PME# <28,30,33>
PCI_AD24 PCI_AD29 AD31 PME# R250 1 1
35 36 1 2 COEX1_BT_ACTIVE <27>
PCI_AD25 AD29 RESERVED @ 0_0402_5%~D PCI_AD30 R249
37 38
PCI_AD26 R255 PCI_AD27 GROUND AD30 @ 10K_0402_5%~D
39 40
PCI_AD27 @ 0_0402_5%~D PCI_AD25 AD27 3.3V PCI_AD28
41 42 2 1
PCI_AD28 AD25 AD28 PCI_AD26
<27> COEX2_WLAN_ACTIVE 1 2 43
RESERVED AD26
44
PCI_AD29 PCI_C_BE3# 45 46 PCI_AD24
PCI_AD30 <20,28,30> PCI_C_BE3# PCI_AD23 C/BE3# AD24 MINIDSEL PCI_AD19
47 48 1 2
PCI_AD31 AD23 IDSEL
49 50
PCI_AD21 GROUND GROUND PCI_AD22 R261
51 52
PCI_AD19 AD21 AD22 PCI_AD20 100_0402_5%~D
53 54
CK_33M_MINIPCI AD19 AD20 PCI_PAR
55 56 PCI_PAR <20,28,30>
PCI_AD17 GROUND PAR PCI_AD18
57 58
AD17 AD18
2
PCI_C_BE2# 59 60 PCI_AD16
<20,28,30> PCI_C_BE2# PCI_IR DY# C/BE2# AD16
R248 61 62
<20,28,30> PCI_IRDY# IRDY# GROUND PCI_FRAME#
@ 10_0402_5%~D 63 64
PCI_CLKRUN# 3.3V FRAME# PC I_TRDY# PCI_FRAME# <20,28,30>
65 66 PCI_TRDY# <20,28,30>
PCI_SERR# CLKRUN# TRDY# PCI_STOP#
<20,28,30> PCI_SERR# 67 68 PCI_STOP# <20,28,30>
SERR# STOP#
1
69 70
PCI_PERR# GROUND 3.3V PCI_DEVSEL#
<20,28,30> PCI_PERR# 71 72 PCI_DEVSEL# <20,28,30>
PCI_C_BE1# PERR# DEVSEL#
73 74
CK_33M_MINPCI_TERM
C <20,28,30> PCI_C_BE1# PCI_AD14 C/BE1# GROUND PCI_AD15 C

75 76
AD14 AD15 PCI_AD13
77 78
PCI_AD12 GROUND AD13 PCI_AD11
79 80
PCI_AD10 AD12 AD11
81 82
AD10 GROUND PCI_AD9
83 84
PCI_AD8 GROUND AD9 PCI_C_BE0#
85 86 PCI_C_BE0# <20,28,30>
PCI_AD7 AD8 C/BE0#
87 88
AD7 3.3V PCI_AD6
89 90
PCI_AD5 3.3V AD6 PCI_AD4
91 92
AD5 AD4 PCI_AD2
93 94
PCI_AD3 RESERVED AD2 PCI_AD0
95 96
AD3 AD0 LAN_SMBCLK
2 97 98
+5VRUN PCI_AD1 5V RESERVED LAN_SMBDATA R278
99 100
C230 AD1 RESERVED 1K_0402_5%~D
101 102
@ 4.7P_0402_50V8C~D GROUND GROUND MPCI_M66EN
103 104 2 1
1 AC_SYNC M66EN
105 106
AC_SDATA_IN AC_SDATA_OUT
107 108
AC_BIT_CLK AC_CODEC_ID0#
109 110
AC_CODEC_ID1# AC_RESET#
111 112
MOD_AUDIO_MON RESERVED
113 114
AUDIO_GND GROUND
115 116
SYS_AUDIO_OUT SYS_AUDIO_IN R284
117 118
SYS_AUDIO_OUT GND SYS_AUDIO_IN GND 10K_0402_5%~D
119 120
+5VRUN AUDIO_GND AUDIO_GND MPCIACT#
121 122 1 2 +3VSUS
RESERVED MCPIACT#
123 124 V_3P3_LAN
VCC5A 3.3VAUX
PCI_CLKRUN# AMP_1318644-1~D
2
2
1
C229
R264 C249 0.1U_0402_16V4Z~D
10K_0402_5%~D 0.1U_0402_16V4Z~D 1
B 1 B
2
V_3P3_LAN
2
R270 R268
10K_0402_5%~D 10K_0402_5%~D
1
ICH_SMBDATA NIC_MINI_SMBDAT LAN_SMBDATA
S
3 1 1 3
D
S
<6,15,16,21> ICH_SMBDATA LAN_SMBDATA <28>
Q53
Q52 2N7002_SOT23~D
+3VSUS 2N7002_SOT23~D
G
G
2
2
2
2
G
Q49
ICH_SMBCLK 3 1 NIC_MINI_SMBCLK 1 3 2N7002_SOT23~D LAN_SMBCLK
<6,15,16,21> ICH_SMBCLK LAN_SMBCLK <28>
Q48
S
2N7002_SOT23~D
+3VRUN
A
2 2 2 2 2 2 2 2 2 A
C232 C241 C227 C246 C234 C242 C247 C231 C244
0.047U_0402_10V4M~D 0.047U_0402_10V4M~D 0.047U_0402_10V4M~D 0.047U_0402_10V4M~D 0.047U_0402_10V4M~D 0.047U_0402_10V4M~D 0.047U_0402_10V4M~D 0.047U_0402_10V4M~D 0.047U_0402_10V4M~D

1 1 1 1 1 1 1 1 1

Title
MINIPCI
X02-D
5 4 3 2 1
5 4 3 2 1
+3VALW
1
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
R233
R465
R181
R182
+3VRUN
1
+3VRUN
PWRSW_SIO# R195
ATF_INT# U15A R523 100K_0402_5%~D
SYS_PME# 4.7K_0402_5%~D +3VRUN
DEBUG_ENABLE H4 LPCPD# 1 2
LPCPD#
2
H3 PCIRST_SIO#
D LRESET# PCIRST_SIO# <20> D
CBS_GRST# F13
<30> CBS_GRST# 0_0402_5%~D SGPIO30 D_DLRQ1#
<42,50> SUB_DETECT#
D4 <36> GV_HI_LO#
R615 1 2
VAUX_EN
F14
E16
E15
SGPIO31
SGPIO32 LPC47N254 DLDRQ1#
DLFRAME#
R2
T2
KSO_17 <39,43> VAUX_EN KSO17 SGPIO33

2 1 E12
SGPIO34 MACALLEN DLAD0
N2
<35,38> KSO_17 USB_EN# E13 P1
<26> USB_EN# SGPIO35 DLAD1
1
RB751V_SOD323~D BAY_MODPRES# D16 P2
<23> BAY_MODPRES# USB_IDE# SGPIO36 DLAD2
D15 N3 R183 R184
<23> USB_IDE# SGPIO37 DOCK LPC DLAD3
R4 D_SERIRQ 100K_0402_5%~D 100K_0402_5%~D
DSER_IRQ D_CLKRUN#
T3
DCLKRUN#
2
R3 LPC_LDRQ1#
SIO_EXT_SMI# LDRQ1# LPC_LFRAME# LPC_LDRQ1# <21> D_CLKRUN#
E14 N4 LPC_LFRAME# <21>
T6 <21> SIO_EXT_SMI# SIO_EXT_SCI# SGPIO40 LFRAME#
C16 LPC LPC_LAD[0..3] <21>
PAD <21> SIO_EXT_SCI# SIO_EXT_RTE# SGPIO41 LPC_LAD0 D_SERIRQ
C15 M3
@ <21> SIO_EXT_RTE# SIO_RCIN# SGPIO42 LAD0 LPC_LAD1
A16 R1
J1397 <21> SIO_RCIN# NB_MUTE SGPIO43 LAD1 LPC_LAD2
D14 T1
@ 1.5mm SMT <25> NB_MUTE BEEP SGPIO44 LAD2 LPC_LAD3
C14 8051 P3
<24> BEEP DEBUG_ENABLE SGPIO45 LAD3 IRQ_SERIRQ
1 C13 T4 IRQ_SERIRQ <20,21,30>
1 DEBUG_OUT SGPIO46 SER_IRQ EC_CLKRUN#
2 B14 GPIO P5 1 2
2 SGPIO47 CLKRUN# RN5
3
3 R196 10K_0402_5%~D 10K_8P4R_1206_5%~D
L3 WRPRT# 1 8
WPROT# +3VRUN
M1 RDATA# 2 7
RDATA#
L2 3 6
T5 HDSEL# INDEX#
FDD L5 4 5
PAD PWRSW_SIO# INDEX# DISKCHG#
<39> PWRSW_SIO# T5 M2
@ SIO_SLP_S3# LGPIO50 DSKCHG# TRK0#
<21> SIO_SLP_S3# N6 L4 1 2
SYS_PME# LGPIO51 TRK0#
<28,30,32> SYS_PME# L6 K1
ATF_INT# LGPIO52 MTR0# R520 +5VSUS
<19,47> ATF_INT# R6 K2
SIO_SLP_S4_S5# LGPIO53 DIR# 10K_0402_5%~D
<21> SIO_SLP_S4_S5# T6 K4
LGPIO54 STEP#
L7 K3
C <36> NOCREG LID_CL_SIO# LGPIO55 WDATA# C
P7 L1
LGPIO56 WGATE#
8
N7 K5 U42C
<49> DT/MT_SELECT LGPIO57 DS0# T11
M5
P
FPD TXD0
A15 J7 3 5 PAD
<21> SIO_PWRBTN# R UN_ON LGPIO60 DRVDEN0 A Y
D13 K7
<18,37,39,44> RUN_ON LGPIO61 DRVDEN1
G
ICH_PME# A14 @
<20> ICH_PME# SIO_THRM# LGPIO62 TC7W14FU_SSOP8~D
C12
<21> SIO_THRM# LGPIO63
4
+3VALW SUS_ON B13 G5 RXD0 R532 1 2 10K_0402_5%~D
<43> SUS_ON SYS_SUSPEND LGPIO64 RXD1 TXD0
A13 LPC G2
<18,41> SYS_SUSPEND LGPIO65 TXD1
10K_0402_5%~D
D12 H7
<23> SATA_MOD_DETECT# LGPIO66 RTS1#
2
DH_PWRSRC_OC F11 H8 CTS0# R537 1 2 10K_0402_5%~D

<26> DH_PWRSRC_OC LGPIO67 GPIO CTS# +3VRUN
R226
COM1 H6
IDE_RST_HDD DTR# DSR0# R211 10K_0402_5%~D
B12 G1 1 2
<21> IDE_RST_HDD IDE_RST_MOD LGPIO70 DSR# DCD0# R527 10K_0402_5%~D
A12 H5 1 2
<21> IDE_RST_MOD GC_BL_SUSPEND LGPIO71 DCD#
C11
<18> GC_BL_SUSPEND LGPIO72
1
Dell GPIO rev0.7 DH_POWER_EN D11 B10 R I0# R227 1 2 10K_0402_5%~D

<26> DH_POWER_EN LGPIO73 RI1# +3VALW
D-Bay USB power AC_LOW_PRES2# E11
LGPIO74
SATA_HDD_DETECT# B11
+3.3VRTC MODC_EN# LGPIO75
A11
<39> MODC_EN# HDDC_EN# LGPIO76 D_IRMODE
C10 H15 D_IRMODE <38>
<39> HDDC_EN# LGPIO77 GPIO10/WK_SE14/IRMODE/IRRX3B IRRX
K14 IRRX <38>
IRRX IRTX
IR M4 IRTX <38>
+3.3VRTC 254VCC0 IRTX
2 1 A4
VCC0/BAT
2
R232 C211
0_0402_5%~D 0.1U_0402_10V6K~D C1 ACK# R217 1 2 10K_0402_5%~D
ACK# +3VRUN
SLCTIN# F2
1
F1
INIT#
ALF# G3
G4
STROBE# BUSY 10K_0402_5%~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
M7 D4 R231 1 2
+3VALW
R13
VCC1_1 LPT BUSY
B1 PE R220 1 2 10K_0402_5%~D
B VCC1_2 PE SLCT R222 10K_0402_5%~D B
1 1 1 1 1 1 1 L11 VCC1_3 SLCT B2 1 2
ERROR# 10K_0402_5%~D
C549
C546
C589
C568
C558
C572
C581
H10 G6 R535 1 2 +3VRUN

VCC1_4 ERROR#
B16 VCC1_5 PD0 F4
F10 VCC F3
2 2 2 2 2 2 2 VCC1_6 PD1
A6 VCC1_7 PD2 E2
F5
PD3
PD4 E4
D3 D1
+3VRUN VCC2_1 PD5
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
H2 VCC2_2 PD6 D2
2 2 2 2 2 K6 E3 +3VALW
VCC2_3 PD7
C574
C577
C548
C567
C563
P4 VCC2_4
E1 C2
VCC2_5 VSS1
VSS2 F6
1 1 1 1 1 J5
VSS3
1
L12 N1
BLM11A121S_0603~D VSS4 R466
GND N5
KPLLVCC VSS5 100K_0402_5%~D
1 2 R5 T10
+3VRUN VCC2_6/PLL VSS6
R15
VSS7
2 J11
VSS8
2
VSS9 G11
C152 B15
0.1U_0402_16V4Z~D VSS10 R467
VSS11 H9
1 D6 10_0402_5%~D
VSS12 LID_CL_SIO# LID_CL#
P6 VSS13/PLL 256 - LBGA 2 1 LID_CL# <18>
A2 KAGND 1 2
AGND L22
LPC47N254V12FBGA_LBGA256~D BLM11A121S_0603~D 1
C534
0.047U_0402_10V4M~D
2
A A

Title
SIO (1/2)
X02-D
5 4 3 2 1
5 4 3 2 1
+3VALW +3VALW
+3VALW +3VALW
1
R179
1
R229 1K_0402_5%~D R234
R606 @ @ 10K_0402_5%~D
10K_0402_5%~D 100K_0402_5%~D U15B R180
2
D 10K_0402_5%~D D
2
L10 SIO_KAH_PGM 2 1
FPGM
2
2
DOCKED B9
IN0/WK_EE4 FDD_PP#
<26> DH_MOD_PRES# DOCK_SMB_INT#
FPVCC
B8
A8
C8
IN1/WK_EE2
IN2/WK_EE3 LPC47N254 FDC_PP#
A10
K12 R236
<18> FPVCC IN3/GPWKUP TEST_PIN
1
1 2 D8 10K_0402_5%~D
<39,48> ACAV SBAT_ALARM# E8
IN4/WK_SE00 MACALLEN B4 XOSEL 2 1 R228
D23 RB751V_SOD323~D IN5/WK_SE01 XOSEL 1K_0402_5%~D
SBAT_PRES# F8 K16
PBAT_PRES# IN6/WK_SE05 EC_SCI# MODE
<42> PBAT_PRES# G8 E5 2 1
IN7/WK_EE1 MODE R550
2
J12 10K_0402_5%~D
FDD_LED# BAT1_LED#
J9 BAT1_LED# <38>
+3VALW SIO_THERM_PWRDN BAT_LED# LPC_LDRQ0#
H13 M6 LPC_LDRQ0# <21>
<37> SIO_THERM_PWRDN H_PROCHOT_SIO# GPIO0/WK_SE02 LDRQ0# BAT2_LED#
<10> H_PROCHOT_SIO# H12 J10 BAT2_LED# <38>
SCR_DETECT_C GPIO1/WK_SE03 PWR_LED#
<31> SCR_DETECT_C H11
GPIO2/WK_SE04 EEPROM_WC
G10 C7 EEPROM_WC <35>
GPIO3/TRIGGER OUT0
2
KSO16 1
4.7K_0402_5%~D
G13 F7 SATA_3V_ENABLE# <39>

<35> KSO16 CAP_LED# GPIO7/WK_SE06 OUT1 HW_RADIO_DIS#
J14 B6 HW_RADIO_DIS# <27,32>
<38> CAP_LED# NUM_LED# GPIO8/WK_SE12/IRRX2 OUT2 LAN_LOW_PWR
R213
J16 E6 LAN_LOW_PWR <28>

<38> NUM_LED# SRL_LED# GPIO9/WK_SE13/IRTX2 OUT3 CHG_PBATT
G14 C6 CHG_PBATT <48>
<38> SRL_LED# GPIO17/WK_SE23/A20M OUT4 TI_SUSPEND#
<10,46> VCORE_PHOT# F15 A5 TI_SUSPEND# <30>
GPIO20/WK_SE25/PS2CLK/8051RX OUT5/DS1/KBRST
1
F12 B5 AUDIO_AVDD_ON 2 3
<41> NB_PSID GPIO21/WK_SE26/PS2DAT/8051TX OUT6/MTR1 AUDIO_AVDD_ON <24>
D7 LIVE_ON_BATT +3VALW
OUT7/SMI LIVE_ON_BATT <39>
PBAT_ALARM# OUT8/KBRST
B7
FAN2_PWM
QBUFEN# MAX6326
E7 R230
T10
GPIO OUT9/PWM2
A7 BREATH_LED FAN2_PWM <14>
10K_0402_5%~D
OUT10/PWM0 BREATH_LED <38>
@ PAD G7 FAN1_PWM 1 2 U11 2
OUT11/PWM1 FAN1_PWM <14>
SIO_MSCLK D10 1
SIO_MSDAT MSCLK RUNPWROK VCC C153
E10 K13 RUNPWROK <18,37,43,44,46>
T9 MSDAT PWRGD VCC1_PWROK 0.1U_0402_16V4Z~D
K15 3
C @ PAD VCC1_PWRGD RESET_OUT# RESET# 1 C
H1 RESET_OUT# <37>
CLK_SM1 RESET_OUT#
C4 2
DAT_SM1 EMCLK DAT_SMB GND
C3 MISC C9 DAT_SMB <19,26,35,47>
EMDAT AB1A_DATA CLK_SMB MAX6326_SOT23~D
A9 CLK_SMB <19,26,35,47>
CLK_SM2 AB1A_CLK DOCK_SMBDAT
<35> CLK_SM2 B3 E9
DAT_SM2 IMCLK AB1B_DATA DOCK_SMBCLK
<35> DAT_SM2 A1 D9
IMDAT AB1B_CLK SBAT_SMBDAT
H16 SBAT_SMBDAT <18>
CLK_KBD GPIO11/WK_SE15/AB2A_DATA SBAT_SMBCLK
J4 H14 SBAT_SMBCLK <18> VCC1_PWROK <35>
DAT_KBD KBCLK GPIO12/WK_SE16/AB2A_CLK PBAT_SMBDAT
J6 J15 PBAT_SMBDAT <42,48>
+5VRUN KBDAT GPIO13/WK_SE17/AB2B_DATA PBAT_SMBCLK
J13 PBAT_SMBCLK <42,48>
PBAT_ALARM# GPIO14/WK_SE20/AB2B_CLK FAN1_TACH
<42> PBAT_ALARM# G9 FAN1_TACH <14>
GPIO15/WK_SE21/FAN_TACH1 FAN2_TACH
F9 FAN2_TACH <14>
<35> KSO[0..15] GPIO16/WK_SE22/FAN_TACH2 SIO_A20GATE
G15 F16 SIO_A20GATE <21>
KSO15 GPIO6/WK_SE11/IRMODE/IRRX3A GPIO19/WK_SE24
4.7K_0402_5%~D
4.7K_0402_5%~D
4.7K_0402_5%~D
4.7K_0402_5%~D
G12
GPIO5/WK_SE10/KSO15
2
KSO14 G16
KSO13 GPIO4/WK_SE07/KSO14 CK_33M_SIOPCI
R506
R514
R225
R224
R7 J3 CK_33M_SIOPCI <6>
KSO12 KSO13/GPIO18 PCI_CLK +5VALW
T7 J2
KSO11 KSO12/OUT8/KBRST 24MHZ_OUT
K8 CLOCK D5
KSO10 KSO11 32KHZ_OUT CK_14M_SIO R209
J8 J1 CK_14M_SIO <6>
KSO10 CLOCKI
1
KSO9 L8 22K_0402_5%~D
KSO8 KSO9 SIO_FA0 SBAT_SMBDAT
@ 10_0402_5%~D
@ 10_0402_5%~D
M8 N12 1 2
KSO8 FA0
2
DAT_KBD KSO7 N8 T13 SIO_FA1
KSO6 KSO7 FA1 SIO_FA2
R207
R521
P8 P12 R522
CLK_KBD KSO5 KSO6 FA2 SIO_FA3 22K_0402_5%~D
T8 T14
KSO4 KSO5 FA3 SIO_FA4 SBAT_SMBCLK
R8 K/B T15 1 2
CLK_SM1 KSO3 KSO4 FA4 SIO_FA5
R9 R16
KSO3 FA5
1
KSO2 T9 N13 SIO_FA6 R198
DAT_SM1 KSO1 KSO2 FA6 SIO_FA7 22K_0402_5%~D
P9 P16
KSO0 KSO1 FA7 SIO_FA8 PBAT_SMBDAT
N9 M14 1 2
CK_33M_SIOPCI_TERM
KSO0 FA8 SIO_FA9
CK_14M_SIO_TERM
<35,38> KSI[0..7] N15
FA9 SIO_FA10 R513
FA10 N16
KSI7 M9 M13 SIO_FA11 22K_0402_5%~D
B KSI6 KSI7 FA11 SIO_FA12 PBAT_SMBCLK B
L9 KSI6 FA12 L12 1 2
KSI5 K9 M15 SIO_FA13
KSI4 K10
KSI5 FLASH FA13
M16 SIO_FA14 R528
KSI3 KSI4 FA14 SIO_FA15 10K_0402_5%~D
M10 L14
KSI2 KSI3 FA15 SIO_FA16 DOCK_SMBDAT
R10 KSI2 FA16 L13 1 2
KSI1 N10 L15 SIO_FA17
KSI0 KSI1 FA17 SIO_FA18 R533
P10 KSI0 FA18 L16
SIO_FA19 10K_0402_5%~D
@ 4.7P_0402_50V8C~D
@ 4.7P_0402_50V8C~D
K11
FA19 DOCK_SMBCLK
FA20 R14 2 2 1 2
T16
FA21
C177
C564
FA22 P13 SIO_FA[0..19] <35>
C592
22P_0402_50V8J~D P14 FR D# 1 1
FRD# FWR# FRD# <35>
N14 +3VALW
FWR# FWR# <35>
1 2 CLK_32KX2 A3 P15 FCS#
XTAL1 FCS# FCS# <35>
1
M12 SIO_FD7
FD7 SIO_FD6
R12
X5 FD6 SIO_FD5
T12
32.768KHZ_12.5P_MC-306~D FD5 SIO_FD4
FD4 P11
3.8X12.1mm N11 SIO_FD3
FD3 SIO_FD2
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
C593 M11
FD2
2
22P_0402_50V8J~D R11 SIO_FD1

FD1
1
1 2 CLK_32KX1 C5 T11 SIO_FD0
XTAL2 256 - LBGA FD0
R235
R551
R549
SIO_FD[0..7] <35>
LPC47N254V12FBGA_LBGA256~D
2
HW_RADIO_DIS#
A LAN_LOW_PWR A
CHG_PBATT

Title
SIO (2/2)
X02-D
5 4 3 2 1
5 4 3 2 1
+3VALW +3VALW
1
1
R552 C599
@ 0_0402_5%~D 0.1U_0402_16V4Z~D
2
2
U40
1 NC VCC 8
D EEPROM_WC D
2 7 EEPROM_WC <34>
+5VRUN A1 WP CLK_SMB
3 6 CLK_SMB <19,26,34,47>
A2 SCL DAT_SMB
4 5 DAT_SMB <19,26,34,47>
VSS SDA
FM24C05U_SO8~D
Address 1010 00XX

SUB_6782U
SMbus address A2
4.7K_0402_5%~D
4.7K_0402_5%~D
1
1
R166
R168
JP2
1
2
2
L8 FCS#
BLM11A601S_0603~D FR D# 2
DAT_SM2 MOUSEDAT FWR# 3
<34> DAT_SM2 1 2 4
SIO_FD7
CLK_SM2 MOUSECLK SIO_FD6 5
<34> CLK_SM2 1 2
L9 SIO_FD5 6
BLM11A601S_0603~D SIO_FD4 7
SIO_FD3 8
SIO_FD2 9
10P_0402_50V8J~D
10P_0402_50V8J~D
+5VRUN SIO_FD1 10
10P_0402_50V8J~D
10P_0402_50V8J~D
SIO_FD0 11
1 1 1 1 12
SIO_FA19
C140
C146
C138
C141
SIO_FA18 13
L11 JPALM SIO_FA17 14
2 2 2 2 BLM31A260SPT_1206~D SIO_FA16 15
MOUSEVDD 1 2 SIO_FA15 16
2 1 3 4 17
SIO_FA14
5 6 SIO_FA13 18
0.1U_0402_16V4Z~D
C 7 8 SIO_FA12 19 C
KSO_17 9 10 TP_Z SIO_FA11 20
1 <33,38> KSO_17 11 12 21
KSI3 TP_V+ SIO_FA10
KSI2 13 14 TP_Y SIO_FA9 22
C147
KSI1 15 16 TP_X SIO_FA8 23
2 KSI0 17 18 TP_GND SIO_FA7 24
19 20 SIO_FA6 25
HRS_FX6A-20P-0.8SV~D SIO_FA5 26
SIO_FA4 27
SIO_FA3 28
SIO_FA2 29
SIO_FA1 30
SIO_FA0 31
FWH_RST 32
33
Keep no nosie coupled, +3VALW 34
Especially the TP_GND @ ACES_6278-34P-DEBUG
JKYBRD
For Compal Flash Tools
KSI7
KSI6 25
KSI4 24
KSI2 23 +3VALW
KSI5 22 U14
KSI1 21 <34> SIO_FA[0..19]
KSI3 20 SIO_FA0
19 21 A0 VCC 31
KSI0 SIO_FA1
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
20 30
KSO5 18 SIO_FA2 A1 VCC
17 19 A2 VPP 11 1 1
KSO4 SIO_FA3 18
KSO7 16 TP_V+ SIO_FA4 A3 SIO_FD0
C203
C202
15 30 17 A4 D0 25
KSO6 TP_X SIO_FA5 16 26 SIO_FD1
B KSO8 14 29 TP_GND SIO_FA6 A5 D1 SIO_FD2 2 2 B
13 28 15 A6 D2 27
KSO3 TP_Y SIO_FA7 14 28 SIO_FD3
KSO1 12 27 TP_Z SIO_FA8 A7 D3 SIO_FD4
11 26 8 A8 D4 32
KSO2 SIO_FA9 7 33 SIO_FD5
KSO0 10 SIO_FA10 A9 D5 SIO_FD6
9 36 A10 D6 34
KSO12 SIO_FA11 6 35 SIO_FD7
KSO16 8 31 SIO_FA12 A11 D7
<34> KSO16 7 32 5 A12 SIO_FD[0..7] <34>
KSO15 SIO_FA13 4
KSO13 6 SIO_FA14 A13
5 33 3 A14
KSO14 SIO_FA15 2 10 FWH_RST 2 1 VCC1_PWROK
<34> KSO[0..15] KSO9 4 34 SIO_FA16 A15 RP#/RESET# VCC1_PWROK <34>
3 1 A16 WP#/RY/BY# 12
KSO15 KSO11 SIO_FA17 40 29 R219
KSO14 KSO10 2 SIO_FA18 A17 NC 0_0603_5%~D
1 13 A18 NC 38
KSO13 SIO_FA19 37
KSO12 JAE_FK2S030W11~D A19
KSO11 FCS# 22
<34> FCS# CE#
KSO10 FR D#
100P_1206_8P4C_50V8~D
100P_1206_8P4C_50V8~D
100P_1206_8P4C_50V8~D
100P_1206_8P4C_50V8~D
100P_1206_8P4C_50V8~D
100P_1206_8P4C_50V8~D
<34> FRD# 24 23
KSO9 FWR# OE# GND
<34> FWR# 9 39
KSO8 WE# GND
KSO7
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
KSO6 1 MX29LV008T/B_TSOP40~D
KSO5 C148
KSO4 100P_0603_50V8J~D
CN1
CN6
CN5
CN4
CN3
CN2
KSO3 @
KSO2 2
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
KSO1
KSO0
@ @ @ @ @ @
<34,38> KSI[0..7]
D C
KSI7
KSI6
1
KSI5 B E
A KSI4 A
G S 2 3
KSI3
KSI2
KSI1 2N7002 DTC114
KSI0

Title
INT KB & ROM
X02-D
5 4 3 2 1
5 4 3 2 1
CPLD Function options Table
No. Function Speedstep enable Speedstep disable
1 CPLD (U27) Pop U27, C233, C606, R557, Depop U27, JPLD, C233, C606, R557,
D D
2 STPCLK# (From ICH to CPU) Pop Q42, R254, Depop R259 Depop Q42, R254, Pop R259
3 CPUSLP# (From ICH to CPU) Pop Q43, R561, Depop R251 Depop Q43, R561, Pop R251
<8> H_VID0 R15 1 2 0_0402_5%~D VID0 <8,46> 4 VRMPWRGD (From Reset to ICH) Depop R243 Pop R243
<8> H_VID1 R16 1 2 0_0402_5%~D VID1 <8,46>
<8> H_VID2 R29 1 2 0_0402_5%~D VID2 <8,46> 5 STP_AGP# (PLD to AGP) Depop R96, Pop R98 (P.18) Pop R96, Depop R98 (P.18)
<8> H_VID3 R31 1 2 0_0402_5%~D VID3 <8,46>
<8> H_VID4 R34 1 2 0_0402_5%~D VID4 <8,46> 6 CPUPREF# (From PLD to CPU) Pop R380(P.8) Depop R380 (P.8)
<8> H_VID5 R36 1 2 0_0402_5%~D VID5 <8,46>
7 STPCPU_VR (From PLD to CPU Power) Pop PR94, Depop PR95 (P.46) Depop PR94, Pop PR95 (P.46)
8 DPRSLPVR (From PLD to CPU power) Pop PR93, Depop PR92 (P.46) Depop PR93, Pop PR92 (P.46)
9 PLD_WAKE# (From PLD to ICH) Pop R141 (P.21) Depop R141 (P.21)
10 PLD_DISABLE# Pop R256, Depop R252 Depop R256, Pop R252
11 DPSLP# Pop R76, R78(P.8) Depop R76, R78(P.8)
12 PCI_PCIRST#(From ICH to PLD) Pop R245 Depop R245
13 GV_HI_LO# Pop R253 Depop R253
C C
Pull low disables PLD assertion
of SSTEP or sleep and deeper
sleep on CPU
+3VSUS +3VSUS
1
Pop when use CPLD

1
R256
R253 @ 10K_0402_5%~D
@ 10K_0402_5%~D
2
2
GV_HI_LO# PLD_DISABLE#
1
+VCC_CORE R252 +3VSUS

@ 1K_0402_5%~D
JPLD
1
2
1
R246 2
@ 100_0402_5%~D 3
4
5
6
2
H_STPCLK#
@ MOLEX_53261-0690~D
B B
Depop when use CPLD +3VSUS +3VSUS
+3VRUN R243
1
U27 1 2 VRM_PWRGD
1 34 +VCC_CORE R561 +VCC_CORE R254
TDI I/O_40 0_0402_5%~D @ 470_0402_5%~D @ 470_0402_5%~D
7
TMS
26 TCK I/O_9 3 I_VRMPWRGD <37>
1
R557 1 2 @ 1K_0402_5%~D 32 15 DPSLP#

DPSLP# <8> R588
TDO I/O_21
2
1
1
R559 19 CLK_CPLD 1 2 L_CPUSLP# I_STPCLK#
I/O_25 CK_33M_CPLD <6>
@ 10K_0402_5%~D GV_HI_LO# 43 21 @ 0_0402_5%~D R603 R604
<33> GV_HI_LO# I/O_5 I/O_27 CPUPREF# <8>
44 22 O_GMUXSEL @ 680_0402_5%~D @ 680_0402_5%~D
<33> NOCREG I/O_6 I/O_28
C3/C4# 2 25 R245 1 2 @ 0_0402_5%~D PCI_PCIRST# <12,20>
I/O_8 I/O_31
2
8 I/O_14 I/O_39 33 VCORE_DSEN# <46>

<6> CLK_STP_CPU#
2
1
1
CLK_STP_CPU# LONG/SHRT# 12 Q43 Q42
I/O_18
13 35 CPLD_WAKE# <21> 2 2
<18> STP_AGP# I/O_19 I/O_41
20 37 SUSCLK <21>
<46> VCORE_DRSEN H_STPCLK# I/O_26 I/O_43 @ MMBT3904_SOT23~D @ MMBT3904_SOT23~D
<8> H_STPCLK# 14
I/O_20
3
I/O_33 27
PLD_DISABLE# 42 28
I_STPCLK# I/O_4 I/O_34
5 I/O_11 I/O_37 31 Pop when use CPLD Pop when use CPLD
L_CPUSLP# 6 CLK_CPLD
H_CPUSLP# I/O_12
10 I/O_16
<8> H_CPUSLP# <21> CPUSLP# <21> STPCLK#
<21,37> SUSPWROK 18 38
I/O_24 GND
1
VRM_PWRGD 23 36
<21> VRM_PWRGD I/O_29 GND R244 R251 R259
30
GND @ 22_0402_5%~D H_CPUSLP# H_STPCLK#
41 VCCINT GND 24 1 2 1 2
+3VSUS 17 16
VCCINT GND 0_0402_5%~D 0_0402_5%~D
9 VCCIO GND 11
2
1 1 29 4
VCCIO GND
GND 40 Depop when use CPLD
A A
C233
@0.1U_0402_16V4Z~D
C606
@0.1U_0402_16V4Z~D GND
39 1 C
2 2 @ EPM3032ATC44-10_TQFP44~D C225
@ 10P_0402_50V8J~D
1
2
B 2 3 E
Pop when use CPLD
Dell Speedstep Support PLD DTC114TKA Compal Electronics, Inc.

Title
PLD
X02-D
5 4 3 2 1
5 4 3 2 1
U25B +3VSUS
74VHC08MTC_TSSOP14~D
<44> RUNPWROK_1P5V 5 IN2
OUT 6 SD 1.11(12474 page292) is request 8.2K ohm
1
R UNOK 4
+5VRUN +5VSUS IN1 R247
+3VSUS
C228 0.1U_0402_16V4Z~D +3VSUS 150_0402_5%~D
1
1 2 +3VSUS U26B
2
R560 IMVP_PWRGD 4 74VHC08MTC_TSSOP14~D
100K_0402_5%~D IN1
1 OUT 6
C226 5
<8> ITP_DBRESET# IN2
U42B 0.1U_0402_16V4Z~D
2
8
U42A TC7W14FU_SSOP8~D U26D +3VSUS
74VHC08MTC_TSSOP14~D 2 U26C 9
P
P
D 5VRUNRC 74VHC08MTC_TSSOP14~D IN2 D
1 7 6 2 12 +3VSUS 8 PWRGD_3V <10,21>
A Y A Y IN2 OUT
11 10 10
OUT IN1 IN1
G
G
13 8 RUNPWROK 12 U25C
TC7W14FU_SSOP8~D IN1 OUT RUNPWROK <18,34,43,44,46> IN2 74VHC08MTC_TSSOP14~D
9 11
14
1 IN2 OUT
4
4
C609 13
0.22U_0603_10V7M~D <34> RESET_OUT# IN1
1 +3VSUS
P
<39> SUSPWROK_3V IN1
3 U25D
2 OUT SUSPWROK <21,36> 74VHC08MTC_TSSOP14~D
2
<45> V_2P5V_PWRGD IN2
G
THERM_FF_GATE U26A
74VHC08MTC_TSSOP14~D
POWER
7
R UN_ON SEQUENCING +3VSUS
<18,33,39,44> RUN_ON
C603 0.1U_0402_16V4Z~D
1 2
+3VSUS +3VRUN
+3VSUS
14
2
8
U25A U41C
R359 1 TC7W14FU_SSOP8~D
P
48.7K_0402_1%~D +3VSUS <44> VTT_PWRGD IN1 IMVP_PWRGD
3 3 5 CK_VTT_PG# <6>
OUT A Y
100K_0402_1%~D
2
<44,46> VCORE_PWRGD IN2
G
R362
2.21K_0402_1%~D
HYST:
1
2
48.7K_0402_1%~D 74VHC08MTC_TSSOP14~D
R581
4
2 1 THERM_CPU#
R353
R355
VCC for 10 degree +3VRUN 1 2

+3VSUS MAX6509 goes in CPU cavity.
10K_0402_5%~D +3VRUN
1
Discretes go outside. GND for 2 degree

R352 1
16.2K_0402_1%~D U36 U4 C604
C Z3804 Z3805 MAX6509SET C
2 1 1 5 1 5
IN+ VCC+ SET VCC 0.1U_0402_10V6K~D
2
2
2 2
GND GND R93 shall be VHC14
Z3806
1000P_0402_50V7K~D
1000P_0402_50V7K~D
3 4 3 4 10K_0402_5%~D
IN- OUT OUT# HYST
8
@ R556 U41A U41B
100K_0402_1%~D
LMV331__DCK @ MAX6509CHU-K_SOT23-5~D 100K_0402_5%~D TC7W14FU_SSOP8~D
P
1
MAX6509HYST IMVP_PWRGD
@ 18.2K_0603_1%~D
1 2 1 7 6 2 I_VRMPWRGD <36>
A Y A Y
2
2
thermistor
2 2 1 1
G
R94
R89
C605 shall be VHC14
2
C399 TC7W14FU_SSOP8~D
C51
C392
R360
SET-HOT Vrsion
4
0.047U_0402_10V4M~D R95 1U_0603_6.3V6M~D
1 1 2 @ 10K_0402_5%~D 2
1
1
+3VALW
1
C607 0.47U_0603_16V7K~D
1 2
2
Thermistor goes in CPU cavity. R571
10K_0402_5%~D
Dell P/N 8K573 @
Dell request populate for SST phase. 2003/0326
1
Semitech P/N 103KT2125-1P
SIO_THERM_PWRDN
SIO_THERM_PWRDN <34>
+3.3VRTC
1K_0402_5%~D
C 1
2
B B
1
1
D
R283
B E 2 3 C620 2 Q71
0.1U_0402_16V4Z~D G 2N7002_SOT23~D
2 S @
1
3
3904 SYMBOL(SOT23-NEW) Z3811
U28A
<43> THERM_STP#
2
SN74LVC74APWR_TSSOP14~D
14
4
R281
0_0402_5%~D
PRE
VCC
R607
1
D
R272 THERM_FF_GATE 5 1 2 THERM_PWRDWN 2 Q70
Q
1
+3VSUS 8.2K_0402_5%~D Z3812 2 G 2N7002_SOT23~D

D 56_0402_5%~D
2 1 S
+3VSUS
3
+VCC_CORE Z3813 3
CLK
2
6
R285 Q
GND
CLR
8.2K_0402_5%~D Q56 1
2
2N7002_SOT23~D
G
R280 C659
1
1
1
1K_0402_5%~D D Z3809 0.22U_0603_10V7M~D

1 3 ICH_THERM_PWRDN# <21>
THERM_TRUE 2 Q57 2
D
G 2N7002_SOT23~D
1
S R275
3
100K_0402_5%~D
1
Z3808 2 R282 +3VSUS

1
1
D
@ 0_0402_5%~D +3.3VRTC
Q60 C619 0.1U_0402_16V4Z~D 2 Q55
3
MMBT3904_SOT23~D 1 2 G 2N7002_SOT23~D
1
A A
S
3
5
U29
RB751V_SOD323~D
THERMTRIP_3P3# 1
P
<8,21> H_THERMTRIP# B THERM_TRUE

20K_0402_5%~D
4
O
1
THERM_CPU# 2 A
G
R572

D16
TC7SH08FU_SSOP5~D
3
Title
2
C618
0.1U_0402_16V4Z~D Thermtrip & PowerGOOD
1 2 THERM_CLEAR
<39> POWER_SW_DB# AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
X02-D
5 4 3 2 1
5 4 3 2 1
+5VHDD
OUT
IN 1 GND
2 3
3
47K
DTA114YKA +3VRUN
+3VRUN
2 Q44
<21> PIDEACT# 10K
DTA114YKA_SOT23~D JLED1
R_BT_MPCI_ACT KSO_17
D 1 2 KSO_17 <33,35> D
BAT1_LED KSI4
BAT2_LED 3 4 KSI5 KSI4 <34,35>
R60
R_BREATH_LED 5 6 KSI6 KSI5 <34,35>
470_0402_5%~D
7 8 KSI6 <34,35>
1
3
47K R_PIDEACT ACTLED
2 1
9 10
CAP_LED 11 12
Q16 NUM_LED 13 14 +3.3VRTC
<34> CAP_LED# 2 10K 15 16
DTA114YKA_SOT23~D SRL_LED
17 18 INT_MIC+
19 20 INT_MIC- INT_MIC+ <25>
21 22 INT_MIC- <25>
R56 LID_CL#
470_0402_5%~D 23 24 POWER_SW#
25 26 POWER_SW# <39>
1
3
47K R_CAP CAP_LED

2 1
27 28 POWER_SW_EMI
29 30 2 1
Q12 31 32 R47
<34> NUM_LED# 2 10K
DTA114YKA_SOT23~D 33 34 0_0402_5%~D
FOX_QTS1030A-2021~D
R52
470_0402_5%~D
1
3
47K R_NUM NUM_LED

2 1
2 Q11
<34> SRL_LED# 10K
DTA114YKA_SOT23~D
R46
470_0402_5%~D R574 R575 R573
1
R_SRL 2 1 SRL_LED 47_0805_5%~D 1.8_1206_5%~D 1.8_1206_5%~D

2 1 IR VCC 2 1 Z3903 2 1
C +3VRUN +3VRUN C
R577
+5VALW @ 0_0402_5%~D
2 1
U43
R576 6 1 IR_ANODE
0_0402_5%~D VCC IRED_ANODE
3
47K SD_MODE
1 2 5 4 IRRX <33>
<33> D_IRMODE SD_MODE RXD
4.7U_1206_16V6K~D
2 7
Q22 IRED_CATHODE MODE
<34> BAT1_LED# 2 10K 1
DTA114YKA_SOT23~D 3 8
<33> IRTX TXD GND
C623
4.7U_1206_16V6K~D
1K_0402_5%~D
0.1U_0402_16V4Z~D
TFDU6101E_TR4~D
2
1
1K_0402_5%~D
R80 2 1 TFDU6102
R579
R578
C621
C624
470_0402_5%~D
1
3
47K R_BAT1_LED BAT1_LED

2 1
1 2
2
2 Q21
<34> BAT2_LED# 10K
DTA114YKA_SOT23~D
R73
470_0402_5%~D
1
R_BAT2_LED 2 1 BAT2_LED
B B
+3VALW
+3VALW
2
2
R72 R85
150_0402_5%~D 150_0402_5%~D
1
1
Z3901
Z3902
R92 R86
1
1
10K_0402_5%~D Q19 10K_0402_5%~D
<34> BREATH_LED 1 2 BREATH_LED_B 2 MMBT3904_SOT23~D
<27> BT_ACTIVE
BT_ACTIVE 1 2 BT_MPCI_ACTIVE 2 Q23
MMBT3904_SOT23~D
3
3
R_BT_MPCI_ACT
R_BREATH_LED
A A

Title
LED Interface & IrDA

X02-D
5 4 3 2 1
5 4 3 2 1
+3.3VRTC +VCC_CORE V_1P25V_DDR_VTT +3VRUN

PWR_SRC Bridge Battery Conn.
Run Planes Enable
1
1 1 1 1
R190 R176 R175 R178
+3VSRC 100K_0402_5%~D 47_0805_5%~D 22_0805_5%~D 150_0805_5%
+3VRUN Source
1
Q27 @ @ @ @
R99 R103 SI3456DV-T1_TSOP6~D +3VRUN
2
330K_0402_5%~D 30K_0402_5%~D JRBATT
D
6 1
Z4003
Z4005
Z4006
S
<41> RBAT 1
5 4 2 2
1
4.7U_1206_16V6K~D
2 1
C67
1 R112 2 2 2 2 MOLEX_53398-0290~D
3Z4002
10K_0402_5%~D Q36 Q35 Q34
G
D @ 2N7002_SOT23~D @ 2N7002_SOT23~D @ 2N7002_SOT23~D D
3
2
1
Q26 D D D
2
Z4001 2 2 2 2
TP0610T_SOT23~D +5VSUS
+5VRUN Source G G G
1
S S S
3
Q47 +5VRUN Q37
SI3456DV-T1_TSOP6~D @ DTC144EKA_SOT23~D
D
RUN_ENABLE
0.22U_1206_25V7M~D
6
S
47K
330K_0402_5%~D
Q25 5 4 1 2
<18,33,37,44> RUN_ON
1
2N7002_SOT23~D
4.7U_1206_16V6K~D
2
1
1
D
C239
1 1 R260
C60
R107
2 10K_0402_5%~D 47K
G
<18,33,37,44> RUN_ON 2
G
3
S
3
2
2
2
+5VSUS
+12V
+5VMOD Source
1
R277
+5VSUS 100K_0402_5%~D
1
2
5
6
+12V
D Q50
2
G SI3456DV-T1_TSOP6~D
2 MOD_EN 3
1
1
R276 +5VMOD
4
1
2
5
6
100K_0402_5%~D Q59
0.01U_0402_16V7K~D
4.7U_1206_16V6K~D
C D Q54 DTC144EKA_SOT23~D C
1 1
SI3456DV-T1_TSOP6~D PWR_SRC PWR_SRC
+5HDD Source
G
2
47K
1
HDD_EN
C250
C245
3 1 1 2
<33> MODC_EN#
S R273
2 2
1
1
+5VHDD 100K_0402_5%~D
4
Q58 R62 R65 47K

0.01U_0402_16V7K~D
DTC144EKA_SOT23~D 100K_0402_5%~D 100K_0402_5%~D
2
47K
4.7U_1206_16V6K~D
<33> HDDC_EN# 2 1 1
2
1
C248
ENAB_3VLAN <28>
R267
C243
1
47K 100K_0402_5%~D D
2 2 Q17 2 Q67 R67
3
200K_0402_5%~D
2N7002_SOT23~D G 2N7002_SOT23~D 470K_0402_5%~D
2
1
D
S
3
R63
<33,43> VAUX_EN 2
2
G +12V +3VSUS
3 S
1
R257
+3VMOD Source @ 100K_0402_5%~D
+3VSRC +3VSRC +3VSUS
Q20
1
2
5
6
SI3443DV_TSOP6~D
1 D Q41
1
6 G
R51 4 5 3
100K_0402_5%~D 2 S @ SI3456DV-T1_TSOP6~D
1
4
1
Q45 +3VMOD
2
B B
@ 0.01U_0603_50V7K~D
@ DTC144EKA_SOT23~D
@ 4.7U_1206_16V6K~D
3
1 47K
C40 2
<34> SATA_3V_ENABLE#
1
Q15 4.7U_1206_16V6K~D 1 1
2N7002_SOT23~D 1 R258
2
1
D 47K @ 100K_0402_5%~D
SUSPWROK_5V 2 C33
3
0.1U_0402_10V6K~D 2 2
C236
C235
G
2
S 2
3
+3.3VRTC
<34> LIVE_ON_BATT
C600
+3.3VRTC +3VSUS
+3.3VRTC +3.3VRTC +3.3VRTC 1 2 +3.3VRTC +3.3VRTC
C220
1
0.1U_0402_16V4Z~D
1
1 2 R238
R242 100K_0402_5%~D
14
14
<38> POWER_SW#
10K_0402_5%~D 0.1U_0402_16V4Z~D U23A U24F
14
14
14
U23D 1 U24C U24D
14
IN0
2
U24A 12 3 13 12 ALW_ENABLE#
P
P
<34,48> ACAV IN0 O IN O ALW_ENABLE# <43>
2
D5 11 2 5 6 9 8
P
O IN1 IN O IN O SUSPWROK_3V <37>

G
RB751V_SOD323~D 1 2 13 1
IN O IN1
G
G
SN74LVC32APWR_TSSOP14~D SN74LVC14APWR_TSSOP14~D
7
7
G
0.1U_0402_16V4Z~D
2 1 SN74LVC32APWR_TSSOP14~D C214 SN74LVC14APWR_TSSOP14~D SN74LVC14APWR_TSSOP14~D

7
7
A SN74LVC14APWR_TSSOP14~D 0.1U_0402_16V4Z~D A
1
7
2
C223
+3.3VRTC
2
14
U24B
ALWON <43>
P
3 4 POWER_SW_DB# <37>
IN O Title
G
POWER CONTROL
PWRSW_SIO# <33> THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
7

X02-D
5 4 3 2 1
5 4 3 2 1
Fiducial Mark
@ FD2 @ FD15 @ FD10 @ FD12 @ FD13 @ FD11

1 1 1 1 1 1
CPU screw hole PCMCIA Slot screw hole FIDUCIAL MARK FIDUCIAL MARK FIDUCIAL MARK FIDUCIAL MARK FIDUCIAL MARK FIDUCIAL MARK
D D
H8 H12 H7 H11 H26 H27 H28 H29 @ FD9 @ FD8 @ FD1 @ FD14 @ FD7 @ FD4
@ H_C315D177 @ H_C315D177 @ C315D110 @ C315D110 @ C197D91 @ C197D91 @ C197D91 @ C197D91 1 1 1 1 1 1
FIDUCIAL MARK FIDUCIAL MARK FIDUCIAL MARK FIDUCIAL MARK FIDUCIAL MARK FIDUCIAL MARK
1
1
@ FD3 @ FD6 @ FD5 @ FD16 @ FD17 @ FD18
1 1 1 1 1 1
FIDUCIAL MARK FIDUCIAL MARK FIDUCIAL MARK FIDUCIAL MARK FIDUCIAL MARK FIDUCIAL MARK
@ FD19 @ FD20
1 1
FIDUCIAL MARK FIDUCIAL MARK

MCH screw hole
Others screw hole
H6 H9 H5 H23 H1 H2 H3 H4
C315D165 C315D165 C315D165 C315D165 @ H_C99D79 @ H_C150D110 @ H_O115X177D95X157@ H_C150D110 +3.3VRTC +3.3VRTC
U23C U23B
1
1
SN74LVC32APWR_TSSOP14~D SN74LVC32APWR_TSSOP14~D
14
14
9 4
P
IN0 IN0
8 6
O O
10 5
IN1 IN1
G
C C
7
H21 H19 H20
VGA Conn. screw hole @ H_C315D110 @ H_O115X177D95X157@ C150D110
H10
C315D165
1
+3.3VRTC
1
+3.3VRTC +12V
U28B
10
14
14
8
H17 H16 H30 H31 H32 H33 U24E U46B
PRE
VCC
@ C315D110 @ C315D110 @ C315D110 @ C315D110 @ C315D110 @ H_C315D110 5
P
IN+
9 11 10 7
Q IN O O
12 6
D IN-
G
MDC
1
1
11 SN74LVC14APWR_TSSOP14~D @ LM358M_SO8~D
CLK
4
Q 8
GND
CLR
H15
C217D157
13
H34 H35 H36
C315D165 @ H_O181X40D181X40N @ H_C71D71N
1
@
B B
1
+3.3VRTC
FAN Conn. screw hole
H24 H25
C315D165 C315D165 PCB
PCB
1
LA1711
1
EMI Cilps
PAD4 PAD5 PAD6 PAD10
A EMI_CLIP EMI_CLIP EMI_CLIP EMI_CLIP A

1
@ @ @ @
PAD11 PAD12 PAD13 PAD14

Title
EMI_CLIP EMI_CLIP EMI_CLIP EMI_CLIP
PAD,Screw Hole and Spare Parts
1

@ @ @ @ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
X02-D
5 4 3 2 1
5 4 3 2 1
+12V D C_IN+
2
PD 1 PD 2
RB751V-40_SOD323~D RB751V-40_SOD323~D
1
RTC_PWR Source
+RTCSRC +RTC_PWR
P R1 P U1
Z4201 1 2 Z4202 +RTCSRC Source 1
IN
1@ 19.1K_0402_1% 3
OUT
1
P C1 2@ 16.9K_0402_1%~D
PC 2
1
1000P_0402_50V7K~D P D3 1 2 RTC_SHDN# 5
#SHDN
2
D D
1
1 2 4 @ 10U_1206_6.3V7K~D
GND
PR 3 PR 2 5/3+
2
1@ 13.3K_0402_1% +RTCSRC EC10QS04_SOD106~D
2@ 8.06K_0402_1%~D 0_0402_5%~D
2
2
PFS1 P D4 @ MAX1615EUK_SOT23-5~D
RBAT 1 2 SBATT_VCC 2 1 3 1
<39> RBAT PW R _ SRC
0.75A_24V_MINISMDM075/24~D EC10QS04_SOD106~D PQ1 +3.3VRTC
1
P R4 IRLML5103_SOT23~D
PR1:19.1K;PR3:13.3K Trickle charger current is 0.45mA for Nimitz.
3.3VRTC Source
2
PW R _SRC PR1:16.9K;PR3:8.06K Trickle charger current is 0.5mA for Beijing. 100K_0402_5%~D PU 2
1
IN
2
3
Z4203 OUT
FET on when in suspend, current flow is from Rbat to N C_LDO_EN 1 2 5

PC 4 PC 6 PWR_SRC to sustain system during battery swap mode #SHDN
4
GND
5/3+
1
0.01U_0402_50V7K~D PR 5
1
2200P_0402_50V7K PC 3
1
P C7 @ 0_0402_5%~D
2
PC 5 10U_1206_6.3V7K~D
PQ2 MAX1615EUK_SOT23-5~D
2
47K
2200P_0402_50V7K 0.01U_0402_50V7K~D SYS _SUSPEND 2
<18,33> SYS _SUSPEND
DTC144EKA_SOT23~D
47K
3
C C
D
+3VALW
1 PR224
G 2 3 S
2
@ 0_0402_5%~D
1 2 P R7
IRLML5103 4.7K_0402_5%~D
DC_IN+ Source P Q4
1
D C_IN+ 2N7002_SOT23~D
PL1 PR 6
PW R _ID 2 PQ3 PS_ID N B_PSID
1 1 2 1 3
S
PS_ID SI7447DP_SO8 PS_ID N B_PSID <34>
BLM11A121S_0603~D 0_0402_5%~D
Z-series AC Adaptor 1
G
2
Connctor PL2 2 P C12 P C14
CHT_C8BBPH853025 3 5 P C10 1
1 2 + DC_IN 0.1U_0805_50V7M~D 0.1U_0805_50V7M~D
1
2
1
0.01U_0402_50V7K~D P D28
1
P JPDC1 + P R13
4
2
1 P C9 1 2
Low_PWR
1
2
9 P C15 P R8 P C11 @ VZ0603M220APT_0603
GND_4 1000P_0402_50V7K~D PC13 2 P C8 2 0_0402_5%~D
2
DC+_1
1
8 150K_0402_5% 0.1U_0805_50V7M~D 0.1U_0805_50V7M~D @ 15U_D2_25M_R90~D

GND_3
2
3 D C IN+ 0.47U_1812_50V7M~D
B DC+_2 B
1
Z4206
7 4 P R10
GND_2 DC-_1 @ 100K_0402_5%~D
6 5
GND_1 DC-_2
1
MH1
MH2
2
P R12
HRS_HR33-DL-7~D 100K_0402_5%~D
PL4
2
CHT_C8BBPH853025
D C IN- 1 2
THE POINT THESE CAPS MUBT BE

NEXT TO JCHG
NOTE: "THE POINT LOCATED
AT PS MODULE
A A

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DC-IN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
X02-D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-1711
5 4 3 2 1
5 4 3 2 1
D D
+5VALW
ESD Diodes
PBATT+
2
PD5 PD6 PD7 PD8
1
PL21
Primary Battery Connector
@ @ @ @ CHT_C8BBPH853025
1
DA204U_SOT323~D DA204U_SOT323~D DA204U_SOT323~D DA204U_SOT323~D
+5VALW
1
PJPB1
1 SUBOUT1 PR14
SUB_OUT1 SUBOUT2 10K_0402_5%~D
2
SUB_OUT2
2
3 SUB_DETECT# <33,50>
SUB_DETECT PC16
4
BATT2-(GND)
2
5 0.1U_0805_50V7M~D
BATT1-(GND)
1
6 PBAT_ALARM# <34>
BAT_ALERT
7
SYS_PRES#
8 1 PR17 2 PBAT_PRES# <34>
BATT_PRES#
2
9 PR15 1 PR16 2 100_0402_5%~D

SMB_DAT PBAT_SMBDAT <34,48>
PC17 10 1 2 100_0402_5%~D
SMB_CLK PBAT_SMBCLK <34,48>
14 11 100_0402_5%~D
G BATT2+
1
C C
13 12
2200P_0402_50V7K G BATT1+
SUYIN_200275MR012G536ZL~D
SUBOUT1
SUBOUT2
TRACE
1
THE POINT
PD31 PD32
DA204U_SOT323~D DA204U_SOT323~D
@ @
3
+12V
12 Please closely PJPB1
11
10
8 PR238
SUBOUT2 1 2 SUB_OUT2
B 7 SUB_OUT2 <50> B
2
PC227 0_0402_5%~D
6 @ 1000P_0402_50V7K~D
1
5
4
2
PC226
3 @ 1000P_0402_50V7K~D
PR237
1
2 SUBOUT1 1 2 SUB_OUT1
SUB_OUT1 <50>
1 0_0402_5%~D
SUYIN_200275MRQ12G536ZL_12P
TOP view
A A

Title
Battery CONN.
X02-D
5 4 3 2 1
5 4 3 2 1
VCC_MAX1999 VCC_MAX1999
Adding RC filter
R EF
PL5
PC20
HCB4532K-800T90_1812~D @ 15U_D2_25M_R90~D
2
1 2 P R19
PW R _SRC
2
1 1 P C21
2
18.2K_0402_1% P R20 P R22
1
P C18 + + PR18 P C23 PR32
@ 15U_D2_25M_R90~D 4.7_1206_5% P C22 @ 0_0402_5%~D
1
10U_1210_25V6K~D PC19 ILIM5 20K_0402_1% P R21 0_0402_5%~D
1
2 2 +5VALW 2200P_0402_50V7K @
1
10U_1210_25V7M~D VCC_MAX1999 0.1U_0805_50V7M~D ILIM3 @ 0_0402_5%~D
P R23
2 1 P RO#
1
PC27 PC28 Place these CAPs SKI P#
1
0.1U_0805_50V7M~D 47_0402_5%~D TON
Current limit at 4A for +3.3V close to FETs
1
PC201 PD 9 P C24 PC25
2
D D
2
0.1U_0805_50V7M~D P C26 PR27
2
P R24
Current limit at 6A for +5VSUSP
5
6
7
8
2
4.7U_1210_25V6K~D 1U_0603_6.3V6M~D 4.7U_0805_6.3V6K~D 1U_0603_6.3V6M~D 43K_0402_1%~D 0_0402_5%~D PR37
P R25 P R26
Place these CAPs 0_0402_5%~D
1
PC29 PQ56 20K_0402_1% 0_0402_5%~D
close to FETs
1
RB717F_SOT323~D
1
8
7
6
5
2200P_0402_50V7K BST_5 4 SI4800DY_SO8~D
2
PQ58 PU 3
P C30
SI4800DY_SO8~D 20 18 PR28 +5VSUSP
V+ LDO5
3
2
1
4 2.2_0402_5% 0.1U_0805_50V7M~D PL6
+3VSRCP 17 14 BST5 1 2 1 2 1 2
PC31 VCC BST5
5
6
7
8
PL7 6 16 D H5 2 PR218 1 4.7U_SPC-1205P-4R7B_+40-20%~D
SHDN DH5 Adding SKIP control
2
0.1U_0805_50V7M~D P R29 PQ57
1
2
3
1 2 2 1BST_3 1 2BST328 15 LX5 0_0402_5%~D SI4810DY_SO8~D
BST3 LX5 PR227
1
8
7
6
5
1
1 4.7U_SPC-1205P-4R7B_+40-20%~D 2.2_0402_5% 26 19 D L5 PC33 PC32 @ 0_0402_5%~D
DH3 DL5
2
1
PC34 4 PD11 +
1
1
PR228 + PC35 PQ59 LX3 27 21

LX3 OUT5
1
N.C.
2
2
2
@ 0_0402_5%~D 0.1U_0805_50V7M~D P D10 SI4810DY_SO8~D 24 9 EP10QY03
DL3 FB5 Add the current limit
2
2
330U_E_6.3VM~D 2 4 D L3 10 P RO# 0.1U_0805_50V7M~D 150U _D2_6.3VM~D PR229
PRO
1
3
2
1
EP10QY03 22 0_0402_5%~D
OUT3 ILIM5
11
ILIM5
2
7 5 ILIM3
FB3 ILIM3
1
PR230 SKI P# 12 8 R EF
SKIP REF
1
2
3 3 13 TON
ON3 TON
1
0_0402_5%~D 4 23
ON5 GND
2
PGOOD
1
25
LDO3
2
P C36
MAX1999EEI_QSOP28~D 1U_0805_25V4Z~D
PW R _SRC
C C
1 2 +3VSRCP
<33> S US_ON PR30
PR31 1 2
+3VALW
2K_0402_1%~D
2
P R33 P R34 0_1206_5%~D
1
P C37 P C38 1 2 PC44
1
240K_0402_5% P C41 PC43
2
10U_1206_10V4Z~D 100K_0402_5%~D 4.7U_1210_25V6K~D
2
1000P_0402_50V7K~D 1U_0805_25V4Z~D
1
2
4.7U_1210_25V6K~D
10
3
2
1
PU19
3
P U4 PQ7
IN
VH
1
G
<33> S US_ON I1
4 P R40 7 9 4 SI4835DY_SO8~D
O <18,34,37,44,46> R U N P WROK SHDN EXT
<33,39> VAUX_EN 2 <39> AL WON 1 2 (+12V+-5%,2A)
I0
P
TC7SH32FU_SSOP5~D 1K_0402_5%~D
5
PC232 2
P C45 1U_0805_25V4Z~D VL PL8 +12VP
2
2 1 <37> THERM_STP# @ 3 PR223

REF
5
6
7
8
22U_SIL104-220_2.9A_30%
0.1U_0805_50V7M~D 1 2 1 2
MAX1745_10uMAX
1
+3.3VRTC 6 0.028_2512_1%~D PR36
P C42 CS
1
PC39 5 PD13 182K_0402_1%
OUT PC224 1 1
4.7U_0805_6.3V6K~D 0.1U_0402_10V6K~D EC31QS04~D PC225
2
P C40 + +
270P_0402_50V7K~D
4 47U_16V @ 47U_16V
GND
FB 2 2
2
PR41
1
21K_0402_1%~D
B B
1
PJP1
(2A,80mils ,Via NO.= 4)
+12VP 1 2 +12V
PAD-OPEN 4x4m
+5VALW Source +3VALW Source
+5VALW
(6A,240mils ,Via NO.= 12) +3.3VRTC
PJP2
1 2 +RTC_PWR PQ13 PQ12 +3VALW
+5VSUS
+5VSUSP @SI2301DS 1P_SOT23~D @ SI2301DS 1P_SOT23~D
PAD-OPEN 4x4m
1 3 1 3
PJP3 S D S D
(4A,160mils ,Via NO.= 8)
1 2 +3VSRC
+3VSRCP
G
G
PAD-OPEN 4x4m
2
P R45
@ 100K_0402_5%~D PR46
ALW_ENABLE# 1 2 Z4704 @ 100K_0402_5%~D
<39> ALW_ENABLE#
1 2
1 1
1
P D14 + +
2 1 P C49 PD15 P C48
@ 47U_D2_6.3VM~D 2 1 @ 47U_D2_6.3VM~D
2
@ RB751V-40_SOD323~D P C51 2 2
@ RB751V-40_SOD323~D P C50
A @ 0.1U_0402_10V6K~D A
@ 0.1U_0402_10V6K~D

Title
3.3V/5V
X02-D
5 4 3 2 1
5 4 3 2 1
D
+1.5VRUNP/+VTT_GMCHP D
PL9
1 2 PW R _SRC
P C54
4.7U_1210_25V6K~D HCB4532K-800T90_1812~D
2
1
1
+ PC56 PR47 +5VSUS P R57
@15U_D2_25M_R90~D 1M_0402_5%~D 715K_0402_1%
2
P C52
1
2200P_0402_50V7K PC53 P C55 2
2
0.1U_0603_25V7M~D 4.7U_1210_25V6K~D
2
P C63
1
P D16 PR231 PR48 4.7U_1206_25V 1
10_0402_5%~D 10_0402_5%~D
1
DAP202U_SOT323~D P C61 + P C60
@15U_D2_25M_R90~D
1
2200P_0402_50V7K
2
2
2
8
7
6
5
P C62 P C64
PQ14 PC58 P C59 0.1U_0603_25V7K~D 4.7U_1206_25V
IRF7811A_SO8~D P C65 1U_0805_10V7K~D
2
1U_0603_6.3V6M~D 1U_0603_6.3V6M~D
1U_0805_10V7K~D 1 2 2 1 P C66
4
1
1
PR247 23 9
100K_0402_5%~D TON1 TON2 PC76
SC1485
1
PL10
1
2
3
1
+1.5VRUNP 1 2 P C57 25 11 1000P_0402_50V7K~D
VCCA1 VCCA2
2
2 .2U
2
1 1 1000P_0402_50V7K~D +VTT_GMCHP
2
P C69 3 17
+ + PC70 PC67 VDDP1 VDDP2
1
8
7
6
5
470U_D2_2.5VM PC220 0.1U_0805_25V7K~D PR49 PR50 PL11
4.7U_0805_6.3V6K~D 2 1 1 2 7 21 1 2 2 1 1 2
2 2 BST1 BST2
1
C PR232 0_0402_5%~D PC221 C

2
2 1 220U_D2_4VM~D PD17 0_0402_5%~D P C68 3U @ 220U_D2_4VM~D

PQ15 1 PR51 2 6 20 1 PR52 2 0.1U_0805_25V7K~D 1 1 PC71
DH1 DH2 P C74 220U_D2_4VM~D
4
1
0_0402_5%~D EC31QS04~D FDS6672A_SO8~D 0_0402_5%~D 0_0402_5%~D + +
2
1
5 19 4.7U_0805_6.3V6K~D
LX1 LX2 PR248
2
P R53 P R54 100K_0402_5%~D 2 2
1
2
3
1 2 4 18 1 2 PQ16
ILIM1 ILIM2
1 8
D1 G1
2
8.87K_0402_1%~D 6.04K_0402_1%~D 2 7
D1 S1/D2
1
P C72 2 16 3 6
DL1 DL2 G2 S1/D2
1
1
4 5
S2 S1/D2
1
P R55 P C73
36.5K_0402_1%~D @ 47P_0402_50V8J~D 24 10 SI4814DY_SO8~D P R58
VOUT1 VOUT2
2
2
2
@ 0.01U_0402_50V7K~D 30K_0402_1%
2
26 12
FBK1 FBK2
1
22 8 P R60
EN/PSV1 EN/PSV2 15.8K_0402_1%
1
27 13
P R61 PGOOD1 PGOOD2
2
18.2K_0402_1%
1 15
PGND1 PGND2
2
1
D PR240
28 14
AGND1 AGND2
1
PR236 2 4.87K_0402_1%~D
<46> CPU_PSC_LOW
1
P U7 PR214 2 1 G
VC ORE_PWRGD <37,46>
P R65 PR215 0_0402_5%~D S
SC1485
3
2 1 0_0402_5%~D PQ64
<18,33,37,39> R U N _ON
2
0_0402_5%~D 2N7002_SOT23~D
2
0_0402_5%~D
2
P R66
B B
+5VSUS 2 1 R U N PW ROK <18,34,37,43,46>
+3VSUS
@ 0_0402_5%~D
1
1
PR216
PR68 10K_0402_5%~D
10K_0402_5%~D
2
2
PJP4
+1.5VRUNP +1.5VRUN VTT_PWRGD <37>
1 2 <37> R UNPWROK_1P5V
PAD-OPEN 4x4m
PJP5
+VTT_GMCHP 1 2 +VTT_GMCH
PAD-OPEN 4x4m
A A
Dell-Compal Confidential
Title
+1.5VRUNP & +VTT_GMCHP
B LA-1711 X02-D
5 4 3 2 1
5 4 3 2 1
D D
PL12
1 2 PW R _ SRC
P C78 P C80
0.1U_0805_25V7K~D 4.7U_1210_25V6K~D HCB4532K-800T90_1812~D
1
1 PC217
1
P R69
P C77 P C81 + P C82 1M_0402_5%~D P R85 0.1U_0805_25V7K~D 1
P C79 @15U_D2_25M_R90~D +5VSUS
1
2200P_0402_50V7K 750K_0402_5%~D +
+2.5V/+1.25V
2
4.7U_1210_25V6K~D 4.7U_1210_25V6K~D 2 PC216 PC223
PC222
2
4.7U_1210_25V6K~D 2 2200P_0402_50V7K
2
@15U_D2_25M_R90~D
P R77 PR70
RB751V-40_SOD323~D + 5VRUN
PD29 10_0402_5%~D 10_0402_5%~D
DDR Termination Voltage
1
8
7
6
5
2
P D30
1
PQ17 PC218 PC219
IRF7811A_SO8~D
1U_0805_10V7K~D PC83 PC84 RB751V-40_SOD323~D 1U_0805_10V7K~D
2
1U_0603_6.3V6M~D 1U_0603_6.3V6M~D
1
4 1 2 2 1
1
PR249 23 9
100K_0402_5%~D TON1 TON2
SC1486
1
2
3
2
P C86
+2.5V_MEMP PL13 PQ47 PC85 25 11
VCCA1 VCCA2
2
1 2 FDS6672A_SO8~D 1000P_0402_50V7K~D 1000P_0402_50V7K~D
1
8
7
6
5
8
7
6
5
1
2. 2UH 3 17
VDDP1 VDDP2
1
PQ18 PR250
1
1 1 P R73 FDS6672A_SO8~D PC88 PR71 P C89 100K_0402_5%~D

P C90 @ 100_0603_5%~D P D19 2 1 1 2 7 21 1 PR72 2 2 1 PQ19 V_1P25V_DDR_VTTP
220U_D2_4VM~D + + BST1 BST2 PL14
C 1 8 C
D1 G1
2
EC31QS04~D 4 4 0.1U_0805_50V7M~D 0_0402_5%~D 0_0402_5%~D 0.1U_0805_50V7M~D 2 7
D1 S1/D2
1 2
P C91 1 P R74 2 6 20 1 P R75 2 3 6 1 2

DH1 DH2 G2 S1/D2
2
1 2 2 2 4 5 3 uH
S2 S1/D2
1
220U_D2_4VM~D P C93 0_0402_5%~D 0_0402_5%~D 150U _D2_6.3VM~D
PR234 5 19 SI4814DY_SO8~D PR80 1 1
LX1 LX2
2
1
2
3
1
2
3
0_0402_5%~D @ 100_0603_5%~D P C94 PC95
2
@ 1000P_0402_50V7K~D P C96 + + 150U _D2_6.3VM~D
2 18 1 P R79 2 4.7U_0805_6.3V6K~D
DL1 ILIM2
12
1
PR78 10.7K_0402_1% P C97 2 2
1
1 2 4 16 1000P_0402_50V7K~D
ILIM1 DL2
2
1
PC92 @
P R76 7.5K_0402_1%
47P_0402_50V8J~D 24 12
VOUT1 FBK2
2
42.2K_0402_1%~D
2
26 10
FBK1 REFOUT
1
2
22 13
P R82 EN/PSV1 PGOOD2 P R81
10K_0402_1%~D 10_0402_5%~D
27 8
PGOOD1 REFIN
2
2 1
1 15
PGND1 PGND2 PC100
1U_0603_6.3V6M~D
1
28 14
AGND1 AGND2 +2.5V_MEMP
<31,39,43> SUSPWROK_5V
PU 8
SC1486
2
1
P R86
10K_0402_5%~D PR217 PR87
@ 0_0402_5%~D 10K_0402_1%~D
1
B B
1
2
+5VSUS
1
1
PC101 PR88
10K_0402_1%~D
0.1U_0402_10V6K~D
2
2
2
PR89
10K_0402_5%~D
1
V_2P5V_PWR GD
<37> V_2P5V_PWRGD
PJP6
PAD-OPEN 4x4m
1 2
PJP7
PAD-OPEN 4x4m
+2.5V_MEMP 1 2 +2.5V_MEM
(12A,360mils ,Via NO.=24)
A A
PJP8
1 2 V_1P25V_DDR_VTT
V_1P25V_DDR_VTTP
PAD-OPEN 4x4m (3A,200mils ,Via NO.=6)
Title
1.25V/2.5V
X02-D
5 4 3 2 1
5 4 3 2 1
D D
PWR_SRC
+5VRUN
PR90
Battery Feed
2
80.6K_0402_1%~D
Forward
1
PC102
PR91
2
PR92 1U_1210_50V7M PU9
1
0_0402_5%~D PR225 32 7 2 1
@ 0_0402_5%~D VCC RAMPS
1 2
<8,36> VID4 1 VID4 10K_0402_5%~D
<8,36> VID3 2 VID3 PGOOD 39 VCORE_PWRGD <37,44>
1
<8,36> VID2 3 VID2

<8,36> VID1 4 VID1 PWM1 25 PWM1 <47>
<8,36> VID0 5 VID0
<8,36> VID5 6 VID12.5 ISEN1+ 24 ISEN1+ <47>
ISEN1- 23 ISEN1- <47>
1
<8> VCORE_ENLL 34 ENLL

<36> VCORE_DRSEN
1 PR93 2 PR95 33 DRSEN PWM2 26 PWM2 <47>
@ 0_0402_5%~D 0_0402_5%~D 27
ISEN2+ ISEN2+ <47>
2
2 PR94 1 35 28
C DSEN# ISEN2- ISEN2- <47> C
<36> VCORE_DSEN# +5VRUN
@ 0_0402_5%~D
PWM3 20 PWM3 <47>
2
1
10 OCSET
PR96 21
ISEN3+ ISEN3+ <47>
PR226 PR99 1K_0402_1%~D 22
PC103 ISEN3- ISEN3- <47>
1
@ 0_0402_5%~D PR98 @ 2 PR97 1 +5VRUN

66.5K_0402_1% 2 1 11 SOFT
1
2
@ 0_0402_5%~D PR100 31 @ 0_0402_5%~D
+5VRUN PWM4 PWM4 <47>
365_0402_1%~D
0.033U_0603_25V7M~D 30
+5VRUN ISEN4+ ISEN4+ <47>
2
9 DSV ISEN4- 29 ISEN4- <47>
1
Frequency Select PC105 PR102 PR241
1
4700P_0402_25V7K~D 10K_0402_1%~D 39K_0402_1%

8
PR101 PU20A 3 36 15 2 1 1 2
P
PC104 IN+ FS COMP

5 21K_0402_1%~D 1 O
P
IN+
2
7 O IN- 2 2 1PC106
PQ65
2
6 LM358M_SO8~D 37 13 @ 1000P_0402_50V7K~D
IN- DRSV FB
2
G
1
100P_0402_50V8K~D D 2N7002_SOT23~D
PR106
4
PU20B PR107 2 DT/MT# <49>

4
10_0402_5%~D
2 38 VR-TT# NC 14 2 1 PC109 PR115 G
1
LM358M_SO8~D PR103 0_0402_5%~D @ 1000P_0402_50V7K~D @ 0_0402_5%~D S
3
B +3VRUN 2 40 NTC VDIFF 16 2 1 2 1 B
1
10K_0402_1%~D PC108 PR112 17

VSEN
1
12 18 PR111
GND VRTN 1.87K_0402_1%~D
<8> VID_PWRGD 330K_0603_5%~D +5VRUN
2
2
2
PR104 19 8 1 2
GND OFS
1
90.9K_0603_1%~D 220P_0402_50V8J~D 0.1U_0402_10V6K~D Place close to IC PR204
1
PR114 ISL6247CR_QFN40~D
2
2
2
PR108 10K_0402_5%~D PR110 PC214
D
3 1 2 1
PR113 1M_0402_5%~D PR118
1
2
45.3K_0402_1% 32.4K_0402_1% Panasonic ERTJ0EV334J (0402) PQ45 9.31K_0402_1%~D
1
PC111 2N7002_SOT23~D
G
Locate this NTC resistor on
2
2
27K_0402_5% 1U_0603_6.3V6M~D
1
<10,34> VCORE_PHOT#
PCB between phase 2 and 3
2
1
2
for thermal compensation. PQ60
1
PR220 PR205 1 PR1162 +VCC_CORE Remote
TP0610T_SOT23~D
2 5.1K_0402_1%~D 0_0402_5%~D
Sensing
1
+3VSUS PU10 PR119
+VCCVID 604K_0402_1% 2 1 VCCSENSE <8>
1
1
1.2VDD D
2 PR117 1 1 VIN VOUT 5 PQ61 @ 0_0402_5%~D
3
1
0_0402_5%~D PC110 2 PR120 Place near +VCC_CORE
1
2N7002_SOT23~D D PQ46
4 PG
G 2 1 output capacitor
4.7U_1206_16V6K~D S <44> CPU_PSC_LOW 2 0_0402_5%~D
2
3
1
3 2 G 2N7002_SOT23~D
EN GND PC112
PR123 S 2 PR121 1 VSSSENSE <8>
3
1
A 4.7U_1206_16V6K~D PQ62 A
2
PR122 MIC5258 <49> CPU_PSC_HI 2 1 2 @ 0_0402_5%~D

<18,34,37,43,44> RUNPWROK 2 1 1. When mode control signal is
1
0_0402_5%~D 22K_0402_5%
low/ high, the VR will operate to Compal Electronics, Inc.
3
2
PR109
PR124 Northwood/ Prescott load line. MMBT3904_SOT23~D Title
100K_0402_5%~D 2. VID5(12.5) should be pulled 100K_0402_5%~D CPU_CORE_Controller
high, when the VR operates to
2
Size Document Number Rev

Nothwood load line.
1
X02-D
LA-1711
5 4 3 2 1
5 4 3 2 1
CPU_PW R_SRC PL15

PC113 Local Transistor PW R_SRC 1 2 CPU_PW R_SRC
+5VRUN PC114 PC202 Swtich Decoupling
2 1 1U_0603_6.3V6M~D 0.1U_0603_25V7M~D CHT_C8BBPH853025
5
6
7
8
5
6
7
8
PC206
1
PQ20 PQ21 PC215
PR125 0.15U_0805_16V7K~D 2200P_0402_50V7K
0_0402_5%~D IRF7811W_SO8~D IRF7811W_SO8~D PC115 0.1U_0603_25V7M~D
Input Bulk and HF Capacitors
2
10U_1210_25V6K~D CPU_PW R_SRC
4 4
U G1
PU11
6 2
VCC BOOT
3
2
1
3
2
1
PR210 PC116 PC117 PC118 PC119 PC120 PC121 PC122 PC123
1
<46> PWM1 3 1 2 1 Panasonic ETQ-P4LR56WFC
PR153 PWM UGTE 0_0402_5%~D PL16
2 1 7 8 Phase1 1 2 10U_1210_25V6K~D 10U_1210_25V6K~D 10U_1210_25V6K~D 10U_1210_25V6K~D
EN PHSE
2
Snubber
D D
2
10U_1210_25V6K~D
5
6
7
8
5
6
7
8
9
5
6
7
8
5
6
7
8
9
1
PR127 0_0402_5%~D PC133 4 5 0.56U_ETQP4LR56WFC_21A_20%~D 10U_1210_25V6K~D 10U_1210_25V6K~D 10U_1210_25V6K~D
GND LGTE
2
@ 499K_0603_1% PQ22 PQ48 PQ23 PC131
PC132 ISL6207CB-T_SO8~D SI4362DY_SO8~D FDS7064N_SO8 SI4362DY_SO8~D @ 1000P_0402_50V7K~D
2 2
0.1U_0402_10V6K~D @ 4 4 PQ49
1
1
1U_0805_25V4Z~D
PR130 PC134
4 4 PR129
@ 2.2_0805 2 1 2 1
@ FDS7064N_SO8
25.5K_0402_1%
LG1
1
0.01U_0402_50V7K~D CPU_PW R_SRC
3
2
1
3
2
1
3
2
1
3
2
1
PC139 PC143
1 1 PC137 1 1 1 1 PC141 1 1 1 1
DUAL FOOTPRINT @ 15U_D2_25M_R90~D @ 15U_D2_25M_R90~D @ 15U_D2_25M_R90~D @ 15U_D2_25M_R90~D
PR133 + + + + + + + + + +
<46> ISEN1-
<46> ISEN1+ 2 1 @ PC135
CPU_PW R_SRC 15U_D2_25M_R90~D PC136 PC138 PC140 PC142 PC144
2 2 2 2 2 2 2 2 2 2
PC145 820_0603_1%~D
PC147 @ 15U_D2_25M_R90~D @ 15U_D2_25M_R90~D @ 15U_D2_25M_R90~D @ 15U_D2_25M_R90~D @ 15U_D2_25M_R90~D
1 2 10U_1210_25V6K~D Local Transistor PTC resistor
5
6
7
8
5
6
7
8
Swtich Decoupling
2
1
PQ24 PQ25
PR134 0.15U_0805_16V7K~D PC207
0_0402_5%~D IRF7811W_SO8~D IRF7811W_SO8~D 2200P_0402_50V7K
2
PC146 PC203 Low-side two population options
4 4 1U_0603_6.3V6M~D 0.1U_0603_25V7M~D
1
U G2
PU12
6 2 SI4362DY_SO8: FDS7064N_SO8:
VCC BOOT
3
2
1
3
2
1
PR211 PQ22,PQ23,PQ26,PQ27, PQ48,PQ49,PQ50,PQ51,
<46> PWM2 3 1 2 1 Panasonic ETQ-P4LR56WFC
PWM UGTE 0_0402_5%~D PL17
PQ30,PQ31,PQ34,PQ35 PQ52,PQ53,PQ54,PQ55
7 8 Phase2 1 2 +VCC_CORE
EN PHSE
Snubber
2
C C
5
6
7
8
5
6
7
8
9
5
6
7
8
5
6
7
8
9
1
PR136 4 5 0.56U_ETQP4LR56WFC_21A_20%~D
@ 499K_0603_1% GND LGTE PQ26 PQ50 PQ27 PC148
2
ISL6207CB-T_SO8~D @1000P_0402_50V7K~D
2
PC149 SI4362DY_SO8~D 4 SI4362DY_SO8~D 4
1
+3VALW
1
2
1U_0805_25V4Z~D 4 4 Address select(7414ART-0)
PR139 PC151
PR138
@ FDS7064N_SO8 @ 2.2_0805 2
Float: 1001 000
1 2 1
GND: 1001 001
1
LG2
25.5K_0402_1%
VDD: 1001 010
3
2
1
3
2
1
3
2
1
3
2
1
1
PQ51 0.01U_0402_50V7K~D PR219
10K_0402_5%~D
@ FDS7064N_SO8
2
PU18
DUAL FOOTPRINT PR142
<46> ISEN2- 1 6 DAT_SMB <19,26,34,35>
AS SDA
<46> ISEN2+ 2 1
CPU_PW R_SRC 2 5 1 2
GND ALERT ATF_INT# <19,33>
PR222 0_0402_5%~D
PC152 820_0603_1%~D
PC154 +3VALW 3 4
VDD SCL CLK_SMB <19,26,34,35>
1 2 10U_1210_25V6K~D Local Transistor PTC resistor
5
6
7
8
5
6
7
8
PQ28 PQ29 Swtich Decoupling

2
1
0.15U_0805_16V7K~D AD7414ART-0_SOP23-6
1
PR143 PC153
0_0402_5%~D IRF7811W_SO8~D IRF7811W_SO8~D PC204 PC210
2
2
PC208 0.1U_0402_10V6K~D
2
4 4 1U_0603_6.3V6M~D 0.1U_0603_25V7M~D 2200P_0402_50V7K
1
U G3
Address 1001 001X (X=1-->Read; X=0-->Write)

PU13
6 2
VCC BOOT
3
2
1
3
2
1
PR212
<46> PWM3 3
PWM UGTE
1 2 1 PQ31 Panasonic ETQ-P4LR56WFC Notes:
0_0402_5%~D SI4362DY_SO8~D PL18
7 8 Phase3 1 2
EN PHSE
Snubber
2
B The ISL6561(ISL6427) supports lossless current sensing including B

2
5
6
7
8
5
6
7
8
9
5
6
7
8
5
6
7
8
9
PR145 PC157 4 5 0.56U_ETQP4LR56WFC_21A_20%~D

@ 499K_0603_1% GND LGTE PC155
1U_0805_25V4Z~D PQ52 @ 1000P_0402_50V7K~D Inductor DCR and MOSFET rDSon sensing. Schematic components are
1
ISL6207CB-T_SO8~D PQ30 4 4
color coded accordingly. In addition an external sense resistor
1
SI4362DY_SO8~D
2
4 4
@ FDS7064N_SO8 PR147
PR148 PC158 can be used for higher load-line accuracy but this will impact
2.2_0805 2 1 2 1
system cost and efficiency.
LG3
@
3
2
1
3
2
1
3
2
1
3
2
1
25.5K_0402_1% 0.01U_0402_50V7K~D
PQ53
Sync. Rectifiers use thermally enhanced "PowerPak" technology in
@ FDS7064N_SO8
an SO-8 form-factor. Optimal MOSFETS will be chosen based on
<46> ISEN3- thermal performance.
<46> ISEN3+ 2 1
CPU_PW R_SRC
PC159 820_0603_1%~D
PC161
10U_1210_25V6K~D
Depending on the processor final requirments and empirical
1 2 PTC resistor
5
6
7
8
5
6
7
8
thermal result testing a 3 phase solution may be possible. In

2
0.15U_0805_16V7K~D PQ32 PQ33 Local Transistor

PR152
IRF7811W_SO8~D PC160
PC209
2200P_0402_50V7K
Swtich Decoupling the 4 phase configuration a single upper mosfet may also be
0_0402_5%~D
2
IRF7811W_SO8~D
4 4 1U_0603_6.3V6M~D
PC205 sufficient.
1
0.1U_0603_25V7M~D
U G4
6
PU14
2
Add thermal venting vias to board. Vias under parts must have a
VCC BOOT
3
2
1
3
2
1
3 1 2
PR213
1 PQ35 Panasonic ETQ-P4LR56WFC
minimum pitch of 1mm and hole size of 0.3mm to avoid solder
<46> PWM4 PWM UGTE 0_0402_5%~D SI4362DY_SO8~D PL19 wicking.
Snubber
7 8 Phase4 1 2
EN PHSE
2
5
6
7
8
5
6
7
8
9
5
6
7
8
5
6
7
8
9
A PR154 PC164 4 5 0.56U_ETQP4LR56WFC_21A_20%~D A

@ 499K_0603_1% GND LGTE PQ34 PC162
1U_0805_25V4Z~D PQ54 @ 1000P_0402_50V7K~D DCR
1
ISL6207CB-T_SO8~D SI4362DY_SO8~D 4 4
Inductor
1
4 4
PR156
PR157 PC165 Sensing
@ FDS7064N_SO8 @ 2.2_0805 2 1 2 1
LG4
PQ55
25.5K_0402_1% 0.01U_0402_50V7K~D
3
2
1
3
2
1
3
2
1
3
2
1
Title
@ FDS7064N_SO8
CPU_CORE_Power-Stage
PTC resistor Size Document Number R ev
820_0603_1%~D X02-D
<46> ISEN4-
<46> ISEN4+ 1 2
LA-1711
5 4 3 2 1
5 4 3 2 1
D D
PD25
@ B540C~D
DC_IN+ discharge path 2 1 +3.3VRTC
PQ41 +5VALW DC_IN+
SI7447DP_SO8 PWR_SRC +3.3VRTC
2
1
2 PR165 PR239
PC228
1
5 3 +SDC_IN 1 2 @ 100K_0402_5%~D
DC_IN+ 0.01_2512_1%~D PR172 PR161 PR162
PU21 2 1
2
100K_0402_5%~D 1K_0402_5%~D
1
PR197 1 @ @ 75K_0402_1%~D
NC 0.1U_0402_10V6K~D
4
10K_0402_5%~D 5 PQ36
VCC
2
2
3
ACOK# 2 PR164
PR198 PR199 PR166 PR167 A ACAV 2SA1036K_SOT23~D
4 1 2 2
Y
1
PQ42 2 1 2 1 0_0402_5%~D 3 ACOK#

BSS138_SOT23~D 0_0402_5%~D GND 10K_0402_1%~D
1
1
PR200 D D 10K_0402_5%~D 100K_0402_5%~D @ TC7SH14 PR168
1
2 1 2 2 PQ43 CHAGER_SRC 1 2 ACAV
<34,39> ACAV
G G BSS138_SOT23~D
2K_0402_1%~D PR201 S S 1M_0402_5%~D
PL22
3
3
C CSSP CSSN PR170 C
2 1
1
PWR_SRC 1 2 PU15
1
2
100K_0402_5%~D PC170 12.7K_0402_1% 2 PR171
PR251 @ 0.1U_0805_25V7K~D AS2431_SOT23~D 100K_0402_5%~D
PC169 MCK4532800YAT_1812
DC_IN+ 0_0402_5%~D
1
@ @ 0.1U_0805_25V7K~D
2
1
PC213
2
3
2
1
PC166 PR169 PQ37
3
2
1
10U_1210_25V6K~D 365K_0402_1%~D PQ69 PC177 PC211
2
10U_1210_25V6K~D FDS6679Z PC175 0.1U_0805_50V7M~D 1 10U_1210_25V6K~D

PC182 4 FDS6679Z 2200P_0402_50V7K
29
28
17
1
PU6 4 +
1U_0805_25V4Z~D PC212
I.C.
CSSP
CSSN
2
PR174 PC168 31 25 2 1 10U_1210_25V6K~D

PDS DHIV
1
2
1 2 PC173 2
1U_0805_25V4Z~D 27 30 PDL <49> PC176
SRC PDL
1
49.9K_0402_1%~D PC171 0.1U_0805_50V7M~D @ 15U_D2_25M_R90~D
5
6
7
8
1 1 2
DCIN
5
6
7
8
2
2
LDO PR175 1U_0603_6.3V6M~D
1 2 3
PC172 ACIN 33_0402_5%~D
@ 0.01U_0402_50V7K~D PC180 2 PR173 1 ACOK# 32 PBATT+
<34,39> ACAV ACOK
5
6
7
8
0.01U_0402_50V7K~D 24 DLOV 2 1 PQ38
DLOV
1
1 2 2 PR178 1 @ 75K_0402_1%~D 6
CCS
PC174 FDS6672A_SO8~D PL20 PR177
0_0402_5%~D 0.1U_0402_10V6K~D 1 2 CHG_CS 1 2 PC189
1 2 2 PR179 1 7 PC190
CCI
1
PC181 PR176 26 3.2UH_12.8A 0.01_2512_1%~D 0.1U_0805_50V7M~D 4.7U_1210_25V6K~D 1
DHI
2
0.01U_0402_50V7K~D 0_0402_5%~D 1 2 C CV 8 4
CCV
1
+5VALW 20K_0402_1% 23 DLO PD22 + PC184
PC183 DLO EC31QS04~D PC187 @15U_D2_25M_R90~D
12
VDD
1
PR181
2
2
2
0.01U_0402_50V7K~D PC193
3
2
1
1
B 4.7U_1210_25V6K~D PC188 B
PGND 22
2
1U_0805_25V4Z~D 13 4.7U_1210_25V6K~D @ 1.2K_1206_5%~D

THM
1
PC192 21
1500P_0402_50V7K~D CSIP PR183
2
14 CSIP 1 2
TM <34,42> PBAT_SMBDAT SDA
2
0_0402_5%~D PR186
2
PR187 20 CSIN 1 2
CSIN
1
PR188 15
<34,42> PBAT_SMBCLK SCL
59K_0402_1%~D 19 PBATT+ 0_0402_5%~D
BATT
2
10K_0402_1%~D PAD @ PC194 PC195
1
T16 16 @ 0.1U_0603_25V7K~D @ 0.1U_0603_25V7K~D

/INT MAX1535X_QFN32~D
1
TH PR182
1
9 2 1 CHVREF
VMAX
1
1645_DAC 11 D
IMAX
GND
GND
DAC
REF
PQ40 31.6K_0603_0.1%~D ACAV 2 PQ63

2
BSS138_SOT23~D PC185 G @ BSS138_SOT23~D

2
D 0.1U_0603_25V7K~D PR189
PR185 S
CHVREF 4
5
18
10
3
2 PD23 182K_0603_0.1%~D
1
PR190 G 1 2 CHG_PBATT <34> 2 1 CHVREF

1
2
10K_0402_1%~D S
3
RB751V-40_SOD323~D 280K_0402_1%~D
1
PR191
2
100K_0402_5%~D PR184
1
PC186
182K_0402_1%
1
1U_0603_6.3V6M~D
VMAX=3.49V
A
Maximum charger voltage=17.45V A
IMAX=1.6V
Maximum charger current=8A

Title
CHARGER CONTROL
X02-D
5 4 3 2 1
5 4 3 2 1
D D
PD26
2 1
B540C~D PQ44
SI7447DP_SO8
1
2 PWR_SRC
PBATT+ 5 3
2
PC199 PC200
2200P_0402_50V7K 0.1U_0805_50V7M~D
PR252
1
1 2
DC_IN+
0_0402_5%~D
1
C PR253 C
PR202
<48> PDL 1 2 470K_0402_5%~D
0_0402_5%~D
2
@
+5VSUS
1
PC229
3
0.1U_0402_10V6K~D
E
2
2
B MMBT3906_SOT23~D
PQ66
1
C
1
PR242 PR243
10K_0402_5%~D
2.7K_0402_5%~D
2
B B
+5VSUS
1
PR244
10K_0402_5%~D
2
1
PR245 PQ67
CPU_PSC_HI <46>
<7> VCORE_BOOTSELECT 1 2 2
DT/MT# <46>
1
12K_0402_5%~D MMBT3904_SOT23~D
1
PR246
1
D 10K_0402_5%~D PC230 PC231

2 PQ68 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D
<33> DT/MT_SELECT
2
G 2N7002_SOT23~D
2
S
3
A A

Title
Battery Discharge
X02-D
5 4 3 2 1
5 4 3 2 1
+ 3VRUN
D D
C640 0.1U_0402_16V4Z~D
1 2
5
U 44
+ 3VRUN 1
P
<24,25> SPK_SHUTDOWN# B
4 SUB_SHUTDOWN#
O
2
A
G
TC7SH08FU_SSOP5~D
3
1
R589 R590
Need to FILTER!!!
10K_0402_5%~D 10K_0402_5%~D
+12V
2
2
1
D
2 Q74
<33,42> SUB_DETECT#
G 2N7002_SOT23~D 2 1
S C641
3
C 642
1U_0805_16V7K 10U_1206_16V4Z~D
1 2
C 658
1000P_0402_50V7K~D
1 2
+12V
U 45
C 655 24
VCC R591
1000P_0402_50V7K~D C643
1 2 SUB_SHUTDOWN# 5 8 1 2 1 2
SHDN BSN
C C
C644 9 51_0603_1% 0.22U_0603_16V7K
PVCC C 646
1 2 1 L49
C645 INN D 20
11 2 1
AUD_MON O_OUT 0.22U_0603_10V7M~D OUTN SUB_OUT1
<24> AUD_MONO_OUT 1 2 2 2 1 1 2
INP SUB_OUT1 <42>
10
0.22U_0603_10V7M~D SUB_GAI N0 OUTN 1U_0805_16V7K B130-13_SMA~D BLM21PG600SN1D_0805~D
3 1
GAIN0
SUB_GAI N1 4 C 647
S UB_VREF GAIN1 1000P_0402_50V7K~D
Gain Setting
C648 2
1 2 7 1
VCLAMP
S UB_VREF 1U_0805_25V4Z~D 23 C 649
VREF C 650 L50 1000P_0402_50V7K~D
D 21
2
1
22 14 2 1 2 1 1 2 SUB_OUT2
R592 R 593 BYPASS OUTP SUB_OUT2 <42>
1
100K_0402_5%~D @ 100K_0402_5%~D 21 15 B130-13_SMA~D BLM21PG600SN1D_0805~D
C 651 COSC OUTP 1U_0805_16V7K
220P_0402_50V7K
1U_0805_25V4Z~D 20 16 R594
ROSC PVCC
2
1U_0805_25V4Z~D
120K_0402_5%~D
C652
1
1 1 17 1 2 1 2
BSP
PGND
PGND
PGND
AGND
AGND
SUB_GAI N0
C653
C654
R595
51_0603_1% 0.22U_0603_16V7K
SUB_GAI N1
2 2 TPA3001D1PWP_TSSOP24~D
12
13
18
19
+12V
1
R596 R 597
@ 100K_0402_5%~D 100K_0402_5%~D
2
B B
A A

Title
Subwoofer
X02-D
5 4 3 2 1

Compal La 1711 rx02 D Schematics

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Compal La 1711 rx02 D Schematics

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5 4 3 2 1

Prescott & Springdale Schematic with Capture CIS

Prescott : Prescott processor Electrial,Mechanical and

Springdale(GMCH): Springdale GMCH External Design

Compal Electronics, Inc.

Compal confidential Block Diagram

ADT7460 Thermal sensor

Memory Fan Control

BCM4401 page 30 page 21

RJ45 X BUS Macallen USBPORT 1

PM TABLE MCH Rev. ICH5 Rev.

S5 S4/AC don't exist

PCI DEVICE IDSEL REQ#/GNT# PIRQ

CARD BUS AD17 1 D,C

MINI PCI AD19 3 D,B(NP)

4 MOD Dog House YES YES

Compal Electronics, Inc.

ADAPTER +RTCSRC +RTC_PWR +5VALW +5VSUS

+5VSUS +3VSRC +2.5VMEMP +VCCP +VCC_CORE +12V

Compal Electronics, Inc.

ICH_SMBCLK +3VRUN CK_SCLK

ICH_SMBDATA +3VSUS CK_SDATA

24C05 ADT7460 AD7414 PCA9561 DH PORT

SIO CPU Temp.(ADT7460ARQ) : 5Ch/5Dh (P.19)

Macallen CPU Power Temp.(AD7414ART-0) : 92h/93h (P.?)

SBAT_SMBCLK +5VALW VID Select(PCA9561PW) : 9Ch/9Dh (P.38)

Compal Electronics, Inc.

Place near each pin

<21> CK_14M_ICH 2 R538 1

0 0 100 66 14.3 14.3 100/200 48 C598 14.31818MHz_20P_1BX14318CC1A~D 1 R473 2

H_STP_PCI# 33_0402_5%~D 33_0402_5%~D

33_0402_5%~D 20 PCICLK6 1 R545 2

ICH_SM BDATA 1 3 CK_SD ATA

2N7002 Clock Generator

A#35 D#32 H_D#33

AE26 V SS Connect to GND OPTIMIZED/ float V SS Connect to GND

R131 62_0402_5% Place near ICH CPLD Enable

@ 0_4P2R_0404_5%~D +VCC_CORE H _V ID_PWRGD <36> H _VID2

0.1U_0402_10V6K~D JITP U 6B 1 2 +3VSUS V ID3 5 4

<36,46> V ID2 V ID1

I TP_BPM#4 15 +CPU_GMCH_GTLREF trace

R108 150_0402_5%~D I TP_TDO 1 2 7 2 0_0603_5%~D 1

R379 @47_0402_5%~D + VCC_CORE 1 2 ITP_TMS 2

R381 Close to the ITP

Place 11 North of Socket(Stuff 6)

Place 9 South of Socket(Unstuff all)

470uF _ERS10m ohm* 15, ESR=0.5m ohm

+VCC_CORE Decoupling Reference Document:

P34 D DRA_SDQ53 2 R31 D DRB_SDQ52

F33 D DRA_SDQ59 F32 D DRB_SDQ58

Trace width of 12mils and space

2 1 C 63 10mils(min) 2.2U_0805_16VFZ~D 0.01U_0402_16V7K~D

SM XRCOMPVOL C 57 R101 C 61 10K_0603_1%~D C 58

Close to GMCH <1" Close to GMCH <1"

+1.5VRUN +12V +1.5VRUN Note:

1 2 2 Follow Springdale Chipset Platform Design guide Rev1.11(12474)

AB5 AB11 G_AD6

2 1 <18> G _RBF# R10

C Close to GMCH ball <250mils G_ST0 N3 Y4 G_AD 17 C

2 1 H UB_HL2 AK2 U3 G_AD 23

Close to GMCH ball <250mils H UB_HL7 AL4 P2 G_AD 28

Place between the VR and GMCH

FAN2 Control and Tachometer