CS/EEE/ECE/INSTR F241

Microprocessor and Interfacing

BITS Pilani
Pilani Campus
Today’s Lecture
➢ Programmable Interval Timer 8253/8254

BITS Pilani, Pilani Campus

PIT- 8253/8254
➢ The 8254 solves one of the most common problems in
any microcomputer system, the generation of accurate
time delays under software control.
➢ Instead of setting up timing loops in software, the
programmer configures the 8254 to match his
requirements and programs one of the counters for the
desired delay.
➢ After the desired delay, the 8254 will interrupt the CPU.
➢ Software overhead is minimal and variable length delays
can easily be accommodated.
Counting/ Generation of Timing Signals
Software – delay routines
Adv – Flexibility
Disadv – Less precision
Hardware – 555/ RC
Adv – Precision
Disadv – Not Flexible
S/w Controlled hardware Timer- 8253/8254

BITS Pilani, Pilani Campus

Features of 8253/8254
➢ Three 16 – bit counters
➢ Max frequency
➢ 2.6MHz 8253
➢ 8MHz 8254
➢ 10MHz 8254-2
➢ Down Counters
➢ Can load a Binary/BCD Number
➢ Can operate in one of 6 possible Modes

BITS Pilani, Pilani Campus

D0 – D7 CLK0
GATE0
CS OUT0
RD
CLK1
WR
GATE1
A0
A1 OUT1
CLK2
VCC GATE2
GND OUT2
8253
Pin Out of 8253
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
8253 – Timing

OUT = CLK

Count

Count – 16-bit

BCD/ Binary

BITS Pilani, Pilani Campus

Power + 5V
CLK0
Supply GND Counter GATE0
Data
0 OUT0
D0 – D7 Bus

8 –bit internal data bus

Buffer

RD CLK1
WR Counter GATE1
R/W
A0 1
Control OUT1
A1
Logic
CS
CLK2
Counter GATE2
Control 2 OUT2
Reg

8253 Internal
Device Interface of 8253/8254
CLK0 –CLK2
– External clock – carries input frequency signal (square
wave, 33% duty cycle)
OUT0 – OUT2
– Can program wave shape: square wave, one-shot
– Various duty cycles
– No sine waves or saw-tooth shapes
GATE0 – GATE2
– Enables or disables the counter
– Sometimes needs a 0-1 pulse to enable

BITS Pilani, Pilani Campus

CS’ A1 A0 Selected

0 0 0 Counter 0

0 0 1 Counter 1

0 1 0 Counter 2

0 1 1 Control Register

1 X X 8253 Not Selected

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

D7 D6 D5 D4 D3 D2 D1 D0

SC1 SC0 RW1 RW0 M2 M1 M0 BCD

Selects Counter Read/Write Timer Mode 0–

Control 000 Interrupt on T/C binary
00 Counter 0 00 Latch 001 h/w re-Triggerable one 0000h
Counter shot FFFFh
01 Counter 1 010 rate generator
01 R/W LSB 1 – BCD
10 Counter 2 011 Square wave generator
10 R/W MSB 0000
11 Read Back 11 R/W LSB 9999
1x0 s/w triggered strobe
Command followed by
MSB 1x1 h/w triggered strobe

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Microprocessor Programming
and Interfacing
8255
BITS Pilani Prof. Vinay Chamola and Prof. G.S.S Chalapathi
Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
Today’s Lecture
 Programmable Peripheral Interface device (8255)

BITS Pilani, Pilani Campus

8255 – Programmable Peripheral Interface (PPI)
Intel has developed several peripheral control chips for 80x86 family
Intent – provide complete I/O interface to x86 chip
8255 –PPI provides 3 8-bit I/O ports in one package
Chip can be directly interfaced to the data bus of 8086
Chip ports can be programmed to function as input or output
Other peripheral devices
8253/8254 – Programmable Interval Timer (PIT)
8259 – Programmable Interrupt Controller (PIC)
8237 – Direct memory Access Controller (DMAC)

BITS Pilani, Pilani Campus

 PA3 1 40 PA4
Port A PA2 2 39 PA5 Port A
PA1 3 38 PA6
PA0 4 37 PA7
RD CS 5 36 WR RESET
GND
6 37
A1 D0
7 35
A0 D1
8 33
D2
9 32
PC4 D3
10 8255 31
Upper Port C PC5 30 D4
11
PC6 29 D5
12
PC7 28 D6
13
PC0 27 D7
14
Lower Port C PC1 15 26 VCC
PC2 25 PB7
16
PC3 24 PB6
17
PB0 PB5 Port B
18 23
Port B PB1 PB4
19 22
PB2 20 21 PB3
 Power + 5V
Supply GND Group Port PA0 –
A A (8) PA7
Control

D0 – D7 Data Group A PC0 –

Bus Port C PC3
Buffer Upper(4)
8 –bit internal
data bus Group B PC4 –
RD Port C PC7
WR Group Lower(4)
A0 R/W B
A1 Control Control
Logic Port PB0 –
RESET B(8) PB7

CSD 8255A Internal

BITS Pilani, Pilani Campus
CS’ A1 A0 Selected

0 0 0 Port A

0 0 1 Port B

0 1 0 Port C

0 1 1 Control Register

1 X X 8255 Not Selected

BITS Pilani, Pilani Campus

D7 D6 D5 D4 D3 D2 D1 D0
1 – I/O Port A Mode Port A Port C Port B Port B Port C
Mode 0 0 - Mode 0 1 – i/p Upper Mode 1 – i/p Lower
0 1 - Mode 1 0 – o/p 1 – i/p 0- Mode0 0 – o/p 1 – i/p
1 x – Mode2 0 – o/p 1- Mode1 0 – o/p

Group A Group B

BITS Pilani, Pilani Campus

D7 D6 D5 D4 D3 D2 D1 D0

0 -BSR x x x Bit2 Bit1 Bit0 Bit Set/Reset

PC 0 1 2 3 4 5 6 7 1 – Set
Don’t Care
Condition B0 0 1 0 1 0 1 0 1 0 - Reset
B1 0 0 1 1 0 0 1 1
B2 0 0 0 0 1 1 1 1

BITS Pilani, Pilani Campus

 D7

0 –BSR 1 – I/O
Affects only Port C

Mode 0 Mode 1 Mode 2

Simple I/O Handshake Handshake
(A,B,C) I/O -- (A,B) Bi-directional I/O (A)
C - Handshake C – Handshake
B – Mode 0,1

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus
BSR Mode of 8255 Port C
Example: Connect 3 LEDs to Port C. Blink one LED after another
at regular intervals of 1ms
8255- Base address 00H

BITS Pilani, Pilani Campus

 D0 – D7 PA0 – PA7

A0
System PB0 – PB7
A1
I/f Device
RD
8255
WR I/f

CS
PC0 – PC3
RESET
PC4 – PC7

BITS Pilani, Pilani Campus

 A1 A0
A2 A1

A0 CS
A3
A4
M/IO’
A5
8255
A6
A7 RD RD
WR WR

D0 – D7 D0 – D7

RESET from 8284

RESET

Interface to the processor

BITS Pilani, Pilani Campus
Output Device

Ex: LED
A R
1

BITS Pilani, Pilani Campus

Output Device

Ex: LED
A R
0 Vcc

BITS Pilani, Pilani Campus

1 1 0 PC2

1 0 1 PC1

0 1 PC0

5V
8255

Interface to the I/O Devices

 creg equ 06h
mov al,80h
out creg,al
X1: mov al,00
out creg,al
mov al,03
out creg,al
mov al,05
out creg,al
call delay_1ms
mov al,01
out creg,al
mov al,02
out creg,al
mov al,05
out creg,al

BITS Pilani, Pilani Campus

call delay_1ms
mov al,01
out creg,al
mov al,03
out creg,al
mov al,04
out creg,al
call delay_1ms
jmp x1

BITS Pilani, Pilani Campus

Mode 0 : Simple Input/Output
O/ps are latched
I/ps buffered not latched
No handshake or interrupt capability
Any of the ports - A,B,CL,CU can be programmed as i/p or o/p
E.g. Read 12 switches and display switch condition on 12 LEDs
8255H – Base Address – 00H

BITS Pilani, Pilani Campus

 PB0

PC0
PB7

8255 PC3 5V
PA0

PC4
PA7

PC7
5V
Interface to the I/O Devices
BITS Pilani, Pilani Campus
 A1 A0
A2 A1

A0 CS
A3
A4
M/IO’
A5
8255
A6
A7 RD RD
WR WR

D0 – D7 D0 – D7

RESET from 8284

RESET

Interface to the processor

BITS Pilani, Pilani Campus
creg equ 06h
porta equ 00h
portb equ 02h
portc equ 04h
mov al,10011000b
out creg,al
in al,porta
out portb,al
in al,portc
and al,f0h
mov cl,04h
ror al,cl
out portc,al

BITS Pilani, Pilani Campus

 CS/EEE/ECE/INSTR F241
Microprocessor and Interfacing
BITS Pilani
Pilani Campus
Last Lecture
➢ PIT 8253/8254

BITS Pilani, Pilani Campus

Today’s Lecture
➢ Priority Interrupt Controller, PIT 8259

BITS Pilani, Pilani Campus

XLAT
➢ Translate instruction used to translate a byte from one code
to another code.
➢ The instruction replaces a byte in the AL register with a byte
pointed to by BX in a lookup table in memory.
➢ Before using XLAT, the lookup table containing the values of new code is put in
memory
➢ Offset of the starting address of the table is loaded into BX
➢ Byte to be translated is put in AL
➢ To point to the byte in table, adds the contents of AL with BX to form a memory
address in data segment
➢ Copies the contents of this memory (BX + AL) into AL

BITS Pilani, Pilani Campus

.Model Tiny

.DATA
TABLE DB 3FH, 06H, 5BH, 4FH, 66H, 6DH
DB 7DH, 07H, 7FH, 67H

.CODE
.STARTUP
IN AL, 05H
LEA BX, TABLE
XLAT
OUT 50H,AL
.EXIT
END

BITS Pilani, Pilani Campus

➢ Interrupts can be used for
➢ read ASCII characters from keyboard
➢ Count interrupts from a timer to generate delays or produce real time clocks
➢ Detect emergency or job done conditions
➢ Each requires a separate interrupt type
➢ 8086 has two interrupt pins, NMI and INTR
➢ NMI dedicated for detection of power failure
➢ Leaves INTR for all other applications
➢ Need a device to “funnel” interrupt signals from multiple sources into a
single INTR input on processor
➢ This device is 8259, Priority Interrupt Controller

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
➢ SP = SP-2
➢ Flags ➔ Stack
➢ IF,TF = 0
➢ SP = SP-2
➢ CS ➔ Stack
➢ SP = SP-2
➢ IP ➔ Stack
➢ Send out two INTA’ pulses
➢ 1st – Ack and do some activities depending upon the mode in which it is programmed
➢ 2nd – Interrupt type.
➢ Multiplies it with 4 to generate interrupt vector no (starting address of the ISR), then
accesses – Interrupt Vector Table in memory
➢ IVT contains the new IP and CS value (4 bytes) corresponding to the address of ISR. Does an
indirect far branch to ISR and executes it.

BITS Pilani, Pilani Campus

 D0
D1
D2
D3
D4
D5
D6
D7
O7 O6 O5 O4 O3 O2 O1 O0
LS 244
I7 I6 I5 I4 I3 I2 I1 I0 G 1’ G 2’
INTA’
IRQ0

IRQ

IRQ7
 IRQ’ Interrupt
7 6 5 4 3 2 1 0 Type

1 1 1 1 1 1 1 0 FEH
1 1 1 1 1 1 0 1 FDH
1 1 1 1 1 0 1 1 FBH
1 1 1 1 0 1 1 1 F7H
1 1 1 0 1 1 1 1 EFH
1 1 0 1 1 1 1 1 DFH
1 0 1 1 1 1 1 1 BFH
0 1 1 1 1 1 1 1 7FH
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 INTA from CPU to INT to CPU at
Data
INTA of 8259 INTR i/p
Bus
D0-D7 Buffer Control Logic

RD Read/
WR Write
Control IR0
A0 IR1
Logic
IR2
CS ISR Priority IRR IR3
Interrupt
In-service
Register
Resolver Request IR4
Register
CAS0 IR5
CAS1 Cascade
IR6
CAS2 Buffer/
IR7

Comparator
SP/EN IMR Interrupt Mask Register
Mainline
STI
IR4-ISR

IR2-ISR

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 INT
INT INTA’

Priority
Resolver
0 0 0 0
1 0 1
0 0 0

IRR IMR
0 0 0 1
0 0 1
0 0 0 0 0 0 0 0 0 1 1
IR7
IR6
IR5
IR4
IR3
IR2
IR1
IR0

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Mainline
STI
IR4-ISR- STI
IR2-ISR- STI

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 INT
INT INTA’
INTA’

Priority
Resolver
0 0 0 0
1 0 0
1 0 0

IRR IMR
0 0 0 1
0 0 1
0 0 0 0 0 0 0 0 0 1 1
IR7
IR6
IR5
IR4
IR3
IR2
IR1
IR0

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Initializing 8259

◼ 4 Initialization Command Words

◼ 3 Operation Command Words
◼ Base Address 00h – 2 addresses are 00H, 02H
◼ Order of writing important

BITS Pilani, Pilani Campus

 ICW1

ICW2

NO (SNGL=1) In Cascade
Mode?

YES (SNGL=0)
ICW3

NO (ICW4=0) Is ICW4
needed?
YES (ICW4=1)
ICW4

Ready to accept Interrupts

ICWx A0 D7 D6 D5 D4 D3 D2 D1 D0

1 0 A7 A6 A5 1 LTIM ADI SNGL IC4

1=level X for 8086 1= not in 1= ICW4
triggered mode cascade mode needed
0=edge 0 =cascade 0=ICW4 not
X for 8086 triggered mode mode needed

2 1 A15 A14 A13 A12 A11 A10 A9 A8

T7 T6 T5 T4 T3 0 0 0

4 1 0 0 0 SFNM BUF M/S AEOI µPM

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

INT IR0
INTA

8259M INT
CAS0 CAS0
CAS1 CAS1
CAS2 CAS2
SP/EN 8259S
5V
INTA

SP/EN
1 1
INT IR0
0 INTA

8259M INT
0
CAS0 CAS0 Interrupt type
CAS1 0
CAS1 to CPU
CAS2 0 CAS2
SP/EN 8259S
5V
INTA

SP/EN
ICWx A0 D7 D6 D5 D4 D3 D2 D1 D0

3M 1 S7 S6 S5 S4 S3 S2 S1 S0

3S 1 0 0 0 0 0 ID2 ID1 ID0

ICW3 – used for cascade

BITS Pilani, Pilani Campus

OCWx A0 D7 D6 D5 D4 D3 D2 D1 D0

1 1 M7 M6 M5 M4 M3 M2 M1 M0

2 0 R SL EOI 0 0 L2 L1 L0

R SL EOI Purpose
0 0 1 Non-specific EOI
0 1 1 Specific EOI
1 0 1 Rotate on non-specific EOI
1 0 0 Rotate on AEOI
1 1 1 Rotate on specific EOI
1 1 0 Set priority
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
D7 D6 D5 D4 D3 D2 D1 D0

IS7 IS6 IS5 IS4 IS3 IS2 IS1 IS0

0 0 0 1 0 0 0 0

7 6 5 4 3 2 1 0

ISR4 SERVICED –EOI/AEOI

0 0 0 0 0 0 0 0

2 1 0 7 6 5 4 3

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

OCWx A0 D7 D6 D5 D4 D3 D2 D1 D0

3 0 0 ESMM SMM 0 1 P RR RIS

Purpose P RR RIS
Read IRR on next RD 0 1 0
Read ISR on next RD 0 1 1
Poll 1 x x

BITS Pilani, Pilani Campus

 BITS Pilani
BITS Pilani
Pilani | Dubai | Goa | Hyderabad

Microprocessor Programming & Interfacing

Prof. Vinay Chamola and Prof. G.S.S Chalapathi
 BITS Pilani
BITS Pilani
Pilani | Dubai | Goa | Hyderabad

Interrupt Handling
INT nn instruction BITS Pilani

Interrupt Program Execution– INT type

The term type refers to a number between 0 and 255 (00H
to FFH), which identifies the interrupt.

INT 21H - DOS INTERRUPT

INT 10H – BIOS INTERRUPT

BITS Pilani, Pilani Campus

 BITS Pilani

BITS Pilani, Pilani Campus

 BITS Pilani

BITS Pilani, Pilani Campus

GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3 BITS Pilani
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD9 7 34 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
AD6 10 8086 31 HOLD RQ/GT0
AD5 11 30 HLDA RQ/GT1
AD4 12 29 WR LOCK
AD3 13 28 M/IO S2
AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
8086 Interrupt sources
BITS Pilani

Hardware Interrupt
External input applied at non-maskable interrupt NMI
External input applied at maskable interrupt INTR

Flag Register x86

If I=1, the INTR pin is enabled STI

If I=0, the INTR pin is disabled CLI
8086 Interrupt sources
BITS Pilani

Software Interrupt
Execution of INT instruction
Exception in program execution
Trap

Flag Register x86

Interrupt Handling in Real Mode
BITS Pilani

How to handle an Interrupt?

Execute Interrupt Service Routine/Handler (ISR)
Before execution of ISR, Save the state of processor so that after the execution of ISR, the normal
instruction execution can be resumed

Where is ISR stored?

Interrupt vectors are used to find the starting address of ISR.
Interrupt vectors are stored in Interrupt Vector Tables (IVT)- Starting from 00000H
Each vector (4 byte value) contains a value for IP and CS that forms the address of the interrupt
service procedure.
The first 2 bytes contain the IP, and the last 2 bytes contain the CS.
8086 supports 256 interrupt types (INT 00H- INT FFH )
In 80x86 - the memory location from which an interrupt fetches the vector is 4 times the
value of the interrupt type number
IVT Size 00000H–003FFH (1024 bytes)
Interrupt Vector Table IVT

BITS Pilani

Int Vector No. Physical Address Contains

INT 00H 00000H IP0
00002H CS0
INT 01H 00004H IP1
00006H CS1
INT 02H 00008H IP2
0000AH CS2
…………….

INT FFH 003FCH IP255

003FEH CS255
ISR Handling in Real Mode
BITS Pilani

The contents of the flag register are pushed onto the stack.
Both the interrupt (IF) and trap (TF) flags are cleared. This disables the INTR pin and the
trap or single-step feature.
The contents of the code segment register (CS) are pushed onto the stack.
The contents of the instruction pointer (IP) are pushed onto the stack.
The interrupt vector contents are fetched, and then placed into both IP and CS so that the
next instruction executes at the interrupt service procedure addressed by the vector.
Eg: INT 4H, CS:1P- 0100:0400, Flag: 0080

BITS Pilani

SP-6 00

SP-5 04

SP-4 00

SP-3 01

SP-2 80

SP-1 00

Address of IVT- 16d= 10H

0010 00
IP
0011 08

0012 00

0013 02 SEG

0200:0800
How to exit from ISR ?
BITS Pilani

Entry to ISR
PUSHF
FAR CALL

Exit from ISR

IRET
The instruction will
(1) pop stack data back into the IP,
(2) pop stack data back into CS
(3) pop stack data back into the flag register.
BITS Pilani
Interrupts - 8086
BITS Pilani

Interrupt Type 0 –INT 0

▪ Divide by zero interrupt

▪ If the quotient is too large to fit into AL/AX

▪ Divide by zero is attempted

▪Automatically invoked by the processor on Error

Interrupt Type 1 – INT 1

o – INT 1
▪Single step Interrupt

▪If trap flag is set 80X86 will do a type 1 interrupt after every instruction execution

▪Automatically invoked by the processor if TF-1

Enable Trace/ Single Step
BITS Pilani

PUSHF

PUSH AX

MOV BP,SP

MOV AX,[BP+2]

OR AX, 0000000100000000H

MOV [BP+2],AX

POP AX

POPF

Flag Register x86

Interrupts- 8086
BITS Pilani

Interrupt Type 2 – INT 2

When 8086 receives a low to high transition on its NMI input

Type 2 interrupt response cannot be disabled (masked) by any program instruction

Interrupts - 8086
BITS Pilani

Break Point Interrupt – Type 3

▪INT 3 instruction – to implement breakpoint routines

▪The system execute instruction up to break point and then goes to break point routine debugging

▪Triggered by INT 3 instruction – to implement breakpoint routines

Overflow Interrupt – Type 4

▪INTO

▪Invoking an interrupt after overflow in an arithmetic operation

▪If no overflow it will be a NOP instruction

▪Interrupt is conditional – will be serviced only if there is an overflow error

Interrupts - 8086
BITS Pilani

8086 INTR input (Level triggered)

Allows some external signal to interrupt execution of a program
INTR can be masked ( disabled)
Clearing IF flag disables INTR
CLI - clears IF
STI - sets IF flag
8086 when reset, IF = 0
When 8086 branches to ISR, IF -0
IRET – IF -1
Interrupts - 8086
BITS Pilani

In response to INTR 8086 expects a vector number

It enters to INTA machine cycle
 BITS Pilani

D0 Tri –State Buffer to generate Vector

No.
D1
D2
D3
D4
D5
D6
D7
O7 O 6 O5 O4 O3 O 2 O1 O0
vCC
LS 244
I 7 I 7 I 6 I 6 I 5 I 5 I 4 I 4 I 3 I 3 I 2 I 2 I 1 I 1 I 0 I 0 G1 ’ G21’’
G
G2 ’
INTA’
 BITS Pilani
BITS Pilani
Pilani | Dubai | Goa | Hyderabad

Interrupt Handling
Interrupts - 8086
BITS Pilani

In response to INTR 8086 expects a vector number

 BITS Pilani

D0 Tri –State Buffer to generate Vector

No.
D1
D2
D3
D4
D5
D6
D7
O7 O 6 O5 O4 O3 O 2 O1 O0
vCC
LS 244
I 7 I 7 I 6 I 6 I 5 I 5 I 4 I 4 I 3 I 3 I 2 I 2 I 1 I 1 I 0 I 0 G1 ’ G21’’
G
G2 ’
INTA’
 BITS Pilani

D0
D1
D2
D3
D4
D5
D6
O7 O6 O5 O4 O3 O2 O1 O0
D7 LS 244
I7 I6 I5 I4 I3 I2 I1 I0 G1 ’ G2 ’
INTA’
IRQ0
INTR

IRQ7
 BITS Pilani

IRQ’ Vector
7 6 5 4 3 2 1 0 No.
1 1 1 1 1 1 1 0 FEH
1 1 1 1 1 1 0 1 FDH
1 1 1 1 1 0 1 1 FBH
1 1 1 1 0 1 1 1 F7H
1 1 1 0 1 1 1 1 EFH
1 1 0 1 1 1 1 1 DFH
1 0 1 1 1 1 1 1 BFH
0 1 1 1 1 1 1 1 7FH
 BITS Pilani
BITS Pilani
Pilani | Dubai | Goa | Hyderabad

8259A- Programmable Interrupt Controller

 Data INTA INT
BITS Pilani
Bus
D0-D7 Buffer Control Logic

RD
Read/
WR Write
A0 Control IR0
Logic IR1
IR2
CS Priority IR3
ISR IRR
Resolver IR4
CAS0 IR5
CAS1 Cascade
IR6
CAS2 IR7
Buffer/
SP/ Comparator
IMR
EN
8259 Architecture
BITS Pilani

The (Interrupt Request Register) IRR is used to store all the interrupt levels which
are requesting service.

Interrupt Mask Register (IMR) The IMR stores the bits which mask the interrupt
lines. The IMR operates on the IRR

The In-Service Register (ISR) is used to store all the interrupt levels which are being
serviced.

Priority Resolver logic block determines the priorities of the bits set in the IRR. The
highest priority is selected and strobed into the corresponding bit of the ISR during
INTA pulse.
 Data INTA INT
BITS Pilani
Bus
D0-D7 Buffer Control Logic

RD
Read/
WR Write
A0 Control IR0
Logic IR1
IR2
CS Priority IR3
ISR IRR
Resolver IR4
CAS0 IR5
CAS1 Cascade
IR6
CAS2 IR7
Buffer/
SP/ Comparator
IMR
EN
8259 Architecture
BITS Pilani

WR’
To output
Initialization command words (ICW)-4
Operation command words (OCW)-3

RD’
To send the status of the Interrupt Request Register (IRR), In Service Register (ISR),
the Interrupt Mask Register (IMR) onto the Data Bus.
 Data INTA INT
BITS Pilani
Bus
D0-D7 Buffer Control Logic

RD
Read/
WR Write
A0 Control IR0
Logic IR1
IR2
CS Priority IR3
ISR IRR
Resolver IR4
CAS0 IR5
CAS1 Cascade
IR6
CAS2 IR7
Buffer/
SP/ Comparator
IMR
EN
INT IR0 BITS Pilani

INTA

8259M INT
CAS0 CAS0
CAS1 CAS1
CAS2 CAS2
SP/EN 8259S
5V
INTA

SP/EN
1 1
INT IR0 BITS Pilani

0 INTA

8259M INT
0
CAS0 CAS0 Interrupt type
CAS1 0
CAS1 to CPU
CAS2 0 CAS2
SP/EN 8259S
5V
INTA

SP/EN
8259 Architecture
BITS Pilani

CAS0-CAS2
These pins are outputs for a master 8259A and inputs for a slave 8259A.

SP’/EN’
When in the Buffered Mode it can be used as an output to control buffer transceivers
(EN).
When not in the buffered mode it is used as an input to designate a master (SP = 1)
or slave (SP = 0).
 INTA’
BITS Pilani

INT

Priority
Resolver
0 0 0 0
1 0 0
1 0 0

IRR IMR
0 0 0 0
1 0 0
1 0 0 0 0 0 0 0 0 1 1
IR7
IR6
IR5
IR4
IR3
IR2
IR1
IR0
Mainline
STI
BITS Pilani

IR4-ISR- STI
IR2-ISR- STI
Mainline
STI
BITS Pilani

IR4-ISR

IR2-ISR
Initializing 8259
BITS Pilani

4 ICWs
3 OCWs
Base Address 00h – 2 addresses are 00H, 02H
Order of writing important

•Initialization command words(ICW)

•Operating command words(OCW)
 ICW1 BITS Pilani

ICW2

Cascade?

ICW3

ICW4?

ICW4

Ready to accept Interrupts

 BITS Pilani

ICWx A0 D7 D6 D5 D4 D3 D2 D1 D0

1 0 A7 A6 A5 1 LTIM ADI SNGL IC4

1=level X for 8086 1= not in 1= ICW4
triggered mode cascade mode needed
0=edge 0 =cascade 0=ICW4 not
triggered mode mode needed
X for 8086

2 1 A15 A14 A13 A12 A11 A10 A9 A8

T7 T6 T5 T4 T3 0 0 0

4 1 0 0 0 SFNM BUF M/S AEOI µPM

 BITS Pilani

ICWx A0 D7 D6 D5 D4 D3 D2 D1 D0

3M 1 S7 S6 S5 S4 S3 S2 S1 S0

3S 1 0 0 0 0 0 ID2 ID1 ID0

ICW3 – used for cascade

 BITS Pilani

Thank you
 BITS Pilani
BITS Pilani
Pilani | Dubai | Goa | Hyderabad

8086 Pins, Pin functions

Modes of Operations

BITS Pilani

8088/8086 can be configured to work in any of the two modes

Minimum Mode
Maximum Mode

Minimum Mode
Single processor based system
Simpler/Smaller systems

Maximum Mode
Larger systems – to be used when a co-processor exists in the system
Co-processor supplements the functions of the primary processor
Numeric Data processor (8087) –coprocessor
 BITS Pilani
BITS Pilani
Pilani | Dubai | Goa | Hyderabad

8086 PIN FUNCTIONS– Minimum Mode

 BITS Pilani

A0 Add
Bus
A19

D0 Data
Bus
8086 D15

Control
signals
 8086 BITS Pilani

Address bus
BIU
I/o Discs
ROM RAM
Ports Video

Data Bus

ALU

CLK
Control
& Timing

EU
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3 BITS Pilani
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD9 7 34 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
AD6 10 8086 31 HOLD RQ/GT0
AD5 11 30 HLDA RQ/GT1
AD4 12 29 WR LOCK
AD3 13 28 M/IO S2
AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3 BITS Pilani
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD9 7 34 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
AD6 10 8086 31 HOLD RQ/GT0
AD5 11 30 HLDA RQ/GT1
AD4 12 29 WR LOCK
AD3 13 28 M/IO S2
AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
Clock
BITS Pilani
CLK is provided to 8086 from an external clock
generator device such as 8284
One cycle of this clock is called a T-state
A T-state is measured as falling edge of one
clock pulse to falling edge of next clock pulse
Different versions of 8086 have maximum clock
frequencies of between 5MHz and 10MHz
The minimum time of one state will be between
200nS - 100nS
Clock Generator- 8284
BITS Pilani
Reset
BITS Pilani
Reset input causes the microprocessor to reset
itself if this pin is held high for a minimum of
four clocking periods.
Whenever the 8086 is reset, it begins executing
instructions at memory location FFFF0H
Disables future interrupts by clearing the IF
flag bit
 Instruction Cycle BITS Pilani

Bus/Machine Cycle

T states

A basic operation such as

Reading/writing a byte/word from/to memory or
Reading/writing a byte/word from/to a port or
accessing the interrupt controller

is referred to as a machine cycle

Machine Cycle
BITS Pilani

MEMR- Memory Read

For Opcode
For Data
MEMW- Memory Write
Data
IOR- I/O Read
IOW- I/O Write
 BITS Pilani

MOV AX, BX
Machine code: 89D8
Machine cycle: 1
 BITS Pilani

MOV CX,[1234H]
Machine code: 8B0E 3412
Machine cycle: 3
 BITS Pilani

ADD AX, [BX]

Machine code: 0307
Machine cycle: 2
 BITS Pilani

CBW
Machine code: 98
Machine cycle: 1
 BITS Pilani

ADD [1234H], AX
Machine code : 0106 3412
Machine cycle: 4
 BITS Pilani

Instruction Cycle

Bus/Machine Cycle

T states
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3 BITS Pilani
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD9 7 34 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
AD6 10 31 HOLD RQ/GT0
8086
AD5 11 30 HLDA RQ/GT1
AD4 12 29 WR LOCK
AD3 13 28 M/IO S2
AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3 BITS Pilani
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD9 7 34 BHE/S7 MN/MX’ –
logic 1
AD8 8 33 MN/MX (Minimum
AD7 9 32 RD mode)
AD6 10 31 HOLD RQ/GT0
8086 MN/MX’ –
AD5 11 30 HLDA RQ/GT1 logic 0
29 WR LOCK (Maximum
AD4 12
mode)
AD3 13 28 M/IO S2
AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
 BITS Pilani BITS Pilani
Pilani | Dubai | Goa | Hyderabad

8086 Address bus

 BITS Pilani

ADDRESS & DATA signals are MULTIPLEXED

GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3 BITS Pilani
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD9 7 34 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
AD6 10 31 HOLD RQ/GT0
8086
AD5 11 30 HLDA RQ/GT1
AD4 12 29 WR LOCK
AD3 13 28 M/IO S2
AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
 BITS Pilani

ADDRESS & DATA signals are MULTIPLEXED

De-multiplexed externally using latch

ALE
BITS Pilani

Indicates that address/data bus contains address

information
The address can be for addressing a memory or
an I/O device.
 BITS Pilani

74LS273

Octal Latch
G OE

ALE
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3 BITS Pilani
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD9 7 34 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
AD6 10 31 HOLD RQ/GT0
8086
AD5 11 30 HLDA RQ/GT1
AD4 12 29 WR LOCK
AD3 13 28 M/IO S2
AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
ALE/BHE’
BITS Pilani

Indicates that address/data bus contains address

information
The address can be for addressing a memory or
an I/O device.

The BHE’ pin enables data bus bits (D15–D8)

during a read or a write operation.
 A16-A19
S6-S3 A16-A19
BITS Pilani
LS373
BHE’/S7 BHE’
G OE’

ALE

8086
AD8-AD15 LS373 A8-A15
G OE’

AD0-AD7 LS373 A0-A7

G OE’

MN/MX’ 5V

System Bus of 8086 (Address)

 BITS Pilani
Signal Address Status

AD16/S3 AD16 S3 Segment

Access
AD17/S4 AD17 S4

AD18/S5 AD18 S5 Interrupt Flag

bit
AD19/S6 AD19 S6 0

BHE’/S7 BHE S7 1
 A16-A19
S6-S3 A16-A19
BITS Pilani
LS373
BHE’/S7 BHE’
G OE’

ALE

8086
AD8-AD15 LS373 A8-A15
G OE’

AD0-AD7 LS373 A0-A7

G OE’

MN/MX’ 5V

System Bus of 8086 (Address)

 BITS Pilani BITS Pilani
Pilani | Dubai | Goa | Hyderabad

8086 Data bus

GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3 BITS Pilani
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD9 7 34 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
AD6 10 31 HOLD RQ/GT0
8086
AD5 11 30 HLDA RQ/GT1
AD4 12 29 WR LOCK
AD3 13 28 M/IO S2
AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
Buffered Systems
BITS Pilani

Buffering of control/data/addr busses  signals

sufficiently strong to drive various IC chips
Bus buffering  Boosting the bus signals to increase the
FANOUT
Unidirectional Buffer - 74LS244
Bidirectional Buffer - 74LS245
Unidirectional Buffer
BITS Pilani

A Bus B Bus
Input Output

0
Bidirectional Buffer
BITS Pilani

A Bus
B Bus

E DIR

0 0
1
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3 BITS Pilani
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD9 7 34 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
AD6 10 31 HOLD RQ/GT0
8086
AD5 11 30 HLDA RQ/GT1
AD4 12 29 WR LOCK
AD3 13 28 M/IO S2
AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
Bidirectional Buffer – 8086 Data bus
BITS Pilani

A Bus B Bus
Inputs/Outputs Inputs/Outputs

E DIR

DEN DT/R
 BITS Pilani
8086

AD8-AD15 LS245 D8-D15

DT/R’ DIR OE’
DEN’

AD0-AD7 LS245 D0-D7

DIR OE’

MN/MX’ 5V

System Bus of 8086(Data)

 BITS Pilani BITS Pilani
Pilani | Dubai | Goa | Hyderabad

8086 Control bus

GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3 BITS Pilani
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD9 7 34 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
AD6 10 31 HOLD RQ/GT0
8086
AD5 11 30 HLDA RQ/GT1
AD4 12 29 WR LOCK
AD3 13 28 M/IO S2
AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
 BITS Pilani

M/IO’- Indicates that microprocessor address bus

contains memory/IO address
WR’ – Low indicates that the bus contains valid
data for Memory or I/O

RD’- Processor is ready to receive data from

Memory or I/O
M/IO’ IOR’ BITS Pilani

RD’
M/IO’ RD’ WR’ Bus cycle

1 0 1 MEMR’

M/IO’ IOW’ 1 1 0 MEMW’

WR’ 0 0 1 IOR’

0 1 0 IOW’

M/IO’ MEMR’
RD’

M/IO’ MEMW’
WR’
 RD
MEMR
BITS Pilani

LS244 LOGIC MEMW

WR
CIRCUIT IOR
IO/M OE’
IOW

MN/MX’ 5V

System Bus of 8086( Control)

 A16-A19
S6-S3 A16-A19
BITS Pilani
LS373
BHE’/S7 BHE’
G OE’

ALE

8086
AD8-AD15 LS373 A8-A15
G OE’

AD0-AD7 LS373 A0-A7

G OE’

MN/MX’ 5V

System Bus of 8086 (Address)

 RD
MEMR
BITS Pilani

LS244 LOGIC MEMW

WR
CIRCUIT IOR
IO/M OE’
IOW

8086
AD8-AD15 LS245 D8-D15
DT/R’ DIR OE’
DEN’

AD0-AD7 LS245 D0-D7

DIR OE’

MN/MX’ 5V

System Bus of 8086(Data + Control)

GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3 BITS Pilani
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD9 7 34 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
AD6 10 31 HOLD RQ/GT0
8086
AD5 11 30 HLDA RQ/GT1
AD4 12 29 WR LOCK
AD3 13 28 M/IO S2
AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
 A16-A19
S6-S3 A16-A19
BITS Pilani
LS373
BHE’/S7 BHE’
G OE’

ALE

8086
AD8-AD15 LS373 A8-A15
G OE’

AD0-AD7 LS373 A0-A7

G OE’

MN/MX’ 5V

System Bus of 8086 (Address)

 RD
MEMR
BITS Pilani

LS244 LOGIC MEMW

WR
CIRCUIT IOR
IO/M OE’
IOW

8086
AD8-AD15 LS245 D8-D15
DT/R’ DIR OE’
DEN’

AD0-AD7 LS245 D0-D7

DIR OE’

MN/MX’ 5V

System Bus of 8086(Data + Control)

Signals of 8086 used during a bus transfer
BITS Pilani
AD15 – AD0 – Multiplexed Address & Data
A19/S6 – A16/S3 – Higher order Address / Status
M/IO’ – Indicates whether access is to
memory or I/O Device
RD’ - Read Operation from Memory/IO
WR’ - Write Operation to Memory/IO
ALE - When set – Multiplexed AD0 – AD15
has address
DT/R’ - 8086 is transmitting/receiving data
DEN’ - Enable data buffers connected to
8086
 Tw
T1 T2 T3 T4
CLK BITS Pilani

A19-A16/S6–S3 A19 – A16 S7 – S3

AD15- AD0 A15-A0 DataData

Data
Address Setup Data Setup
M/IO’

ALE
DT/R’

RD’

DEN’

200 ns
800 ns

Bus Timings for a Read Operation

 BITS Pilani

Memory access time starts when the address appears on

the memory address bus and continues until the
microprocessor samples the memory data at T3.

(600-110-30)ns= 460ns
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3 BITS Pilani
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD9 7 34 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
AD6 10 31 HOLD RQ/GT0
8086
AD5 11 30 HLDA RQ/GT1
AD4 12 29 WR LOCK
AD3 13 28 M/IO S2
AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
READY Signal & WAIT States
BITS Pilani

If READY is a logic 0 at the end of T2, T3 is delayed

and Tw is inserted between T2 and T3.
READY is next sampled at the middle of Tw to
determine whether the next state is Tw or T3.
READY pin is tested for a logic 0 on the 1-to-0
transition of the clock at the end of T2, and for a 1
on the 0-to-1 transition of the clock in the middle of
Tw
 T1 T2 Tw T3 T4
CLK BITS Pilani

A19-A16/S6–S3 A19 – A16 S7 – S3

AD0- AD15 A15-A0 Data

Address Setup Data Setup
M/IO’

ALE
DT/R’

RD’

DEN’

200 ns
1000 ns

Bus Timings for a Read Operation

WAIT States
BITS Pilani

A wait state (Tw) is an extra clocking period, inserted

between T2 and T3 to lengthen the bus cycle.
If one wait state is inserted, then the memory access
time, normally 460 ns with a 5 MHz clock, is
lengthened by one clocking period (200 ns) to 660 ns
 T1 T2 T3 T4
CLK BITS Pilani

A19-A16/S6–S3 A19 – A16 S7 – S3

AD0- AD15 A15-A0 Data

Address Setup
M/IO’

ALE
DT/R’

WR’

DEN’

200 ns
800 ns

Bus Timings for a Write Operation

GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3 BITS Pilani
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD9 7 34 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
AD6 10 31 HOLD RQ/GT0
8086
AD5 11 30 HLDA RQ/GT1
AD4 12 29 WR LOCK
AD3 13 28 M/IO S2
AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
Interrupt Handling
BITS Pilani

NMI

INTR

INTA’
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3 BITS Pilani
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD9 7 34 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
AD6 10 31 HOLD RQ/GT0
8086
AD5 11 30 HLDA RQ/GT1
AD4 12 29 WR LOCK
AD3 13 28 M/IO S2
AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
DMA Access
BITS Pilani

HOLD

HLDA
TEST’
BITS Pilani

The TEST pin of the microprocessor is usually connected

to the BUSY pin of the 8087 numeric coprocessors. This
connection allows the microprocessor to wait until the
coprocessor finishes a task.

If the TEST pin = 0 when the WAIT instruction

executes, the microprocessor waits for the TEST pin to
return to a logic 1.

If the WAIT instruction executes while the TEST pin =

1, nothing happens and the next instruction executes.
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3 BITS Pilani
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD9 7 34 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
AD6 10 31 HOLD RQ/GT0
8086
AD5 11 30 HLDA RQ/GT1
AD4 12 29 WR LOCK
AD3 13 28 M/IO S2
AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
 Instruction Cycle BITS Pilani

Bus/Machine Cycle

T states

A basic operation such as

Reading/writing a byte/word from/to memory or
Reading/writing a byte/word from/to a port or
accessing the interrupt controller

is referred to as a machine cycle

Machine Cycle
BITS Pilani

MEMR- Memory Read

For Opcode
For Data
MEMW- Memory Write
Data
IOR- I/O Read
IOW- I/O Write
Q1. How many machine cycles will the following instructions take BITS Pilani

MOV AX, BX
Machine code: 89D8

Machine cycle: 1

1 MEMR
 BITS Pilani

MOV CX,[1234H]
Machine code: 8B0E 3412

Machine cycle: 3 MEMR

2 MEMR
1 MEMR
 BITS Pilani

ADD AX, [BX]

Machine code: 0307

Machine cycle: 2 MEMR

2 MEMR
 BITS Pilani

CBW
Machine code: 98

Machine cycle: 1

1 MEMR
 BITS Pilani

ADD [1234H], AX
Machine code : 0106 3412

Machine cycle: 4

2 MEMR for reading instruction

1 MEMR for operand fetch
1 MEMW
Interfacing to Processor
8088
 A16-A19 A16-A19
S6-S3
LS373
BHE’/S7 BHE’

G OE’

ALE

8088
A8- A15 A8-A15

AD0-AD7 LS373 A0-A7

G OE’

MN/MX’ 5V
 RD
MEMR

LS244 LOGIC MEMW

WR
CIRCUIT IOR
IO/M OE’
IOW

8088
AD0-AD7 LS245 D0-D7
DT/R’ DIR OE’
DEN’

MN/MX’ 5V
 Address Bus

 Data Bus

 Control Signals

 Based on the size of the chip

 Mem location

Address
D
Bus
E
C
O
D
E
R

Data Bus
A 2K Memory Chip

A0 -
A10

D0 -
D7 2K x 8

RD

WR
CS
 No of Memory chips

 Address Space

 Decoding logic
 8K Memory – 4 – 2K chips of memory

 Memory Mapping

 RAM1 00000H – 007FFH

 RAM2 00800H- 00FFFH
 RAM3 01000H- 017FFH
 RAM4 01800H-01FFFH
 MEMW WR
MEMR RD
Data Bus of CPU

A0 –A10 of CPU A0-A10

Remaining Address CS
address lines of Decoding
CPU Logic
 Memory Address Decoding

INPUT OUTPUT
S O0
A E ENABLE SELECT
L O1
G1 G2A G2B A B C O0 O1 O2 O3 O4 O5 O6 O7

B E 0 X X X X X 1 1 1 1 1 1 1 1
C O2 X 1 X X X X 1 1 1 1 1 1 1 1
C T
X X 1 X X X 1 1 1 1 1 1 1 1
O3
1 0 0 0 0 0 0 1 1 1 1 1 1 1
LS138 O
4 1 0 0 0 0 1 1 0 1 1 1 1 1 1
E 1 0 0 0 1 0 1 1 0 1 1 1 1 1
O5
G1 N 1 0 0 0 1 1 1 1 1 0 1 1 1 1
G2A A O6 1 0 0 1 0 0 1 1 1 1 0 1 1 1
B
G2B L 1 0 0 1 0 1 1 1 1 1 1 0 1 1
O7
E 1 0 0 1 1 0 1 1 1 1 1 1 0 1
1 0 0 1 1 1 1 1 1 1 1 1 1 0
RAM1 00000H – 007FFH
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
RAM2 00800H- 00FFFH
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
RAM3 01000H-017FFH
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1
RAM4 01800H-01FFFH
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0
0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
 S O0
A E RAM1
A13
L O1 RAM2
A12 B E
A11 C O2 RAM3
C T
A16 O3 RAM4
A17 LS138 O
A18 4
A19 E
O5
G1 N unused
A14 G2A A O6
A15 B
G2B L
O7
E

Absolute Addressing
 S O0
A E RAM1
L O1 RAM2
A12 B E
A11 C O2 RAM3
C T
O3 RAM4
LS138 O
4
E
O5
5V G1 N unused
G2A A O6
B
G2B L
O7
E

Incremental Addressing
8088
For the memory chips available each do the
interfacing for 8088

Ex: Interface
4K - 2716 (ROM) starting at 00000H
8K - 6116 (SRAM) starting at 08000H
Memory Requirements
2716 – ROM - size 2K (16/8)
ROM – 4k
Number of 2716 required – 2
6116 – RAM size 2k (16/8)
RAM – 8k
Number of 6116 required - 4
Memory Map
ROM 1 - 00000H – 007FFH
ROM2 - 00800H – 00FFFH
RAM1 - 08000H – 087FFH
RAM2 - 08800H – 08FFFH
RAM3 - 09000H – 097FFH
RAM4 - 09800H – 09FFFH
ROM1 00000H – 007FFH
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1

ROM2 00800H- 00FFFH

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
RAM1 08000H-087FFH
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
RAM2 08800H- 08FFFH
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
RAM3 09000H-097FFH
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1
RAM4 09800H-09FFFH

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0
1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
 S O0
A E ROM1
A15
L O1 ROM2
A12 B E
A11 C O2
C T unused
A16 O3
A17 LS138 O
A18 4 RAM1
A19 E
O5 RAM2
G1 N
A14 G2A A O6 RAM3
A13 B
G2B L
O7 RAM4
E

Absolute Addressing
 D0-D7
A0-A10

D0- A0- D0- A0-

D7 A10 D7 A10

A15 ROM1 ROM2

A OO CS’
A12 CS’
B O1
A11 C O2
OE’ OE’
O3
Unused
MEMR’
LS138
O4 MEMW’
A13 G2A
O5
A14 G2B CS’ RD’ WR’ CS’ RD’ WR’ CS’ RD’ WR’ CS’ RD’ WR’
G1 O6

O7
RAM1 RAM2 RAM3 RAM4

D0- A0- D0- A0- D0- A0- D0- A0-

A16 D7 A10 D7 A10 D7 A10 D7 A10
A17 A0-A10
A18
A19
D0-D7
8086/80286
 8086 has 20 bit address bus / 80286 has 24 bit address
 1 MB / 16 MB - each address represent a byte
 An Inst such as MOV [437AH] , BX
 Word written to two consecutive locations 0437AH & 0437BH
 To complete the write in one cycle memory set up as two banks
 512 K bytes each
 ODD Bank &
 EVEN Bank
 Byte- Wide Addr Even -Address Odd -Address
8088 FFFFF FFFFE 8086 FFFFF
FFFFE FFFFC FFFFD
FFFFD FFFFA FFFFB
A0- A19 A1- A19 A1- A19
FFFFC FFFF8 FFFF9

00002 00004 00005

00001 00002 00003
00000 00000 00001

D0- D7 D0- D7 D8- D15

A0 BHE’

1 MB 512 KB even 512 KB odd

BHE’ A0 Selection
0 0 Whole Word
0 1 High byte to/from odd address
1 0 Low byte to/from even address
1 1 No Selection
Address Data BHE’ A0 Bus Data lines
Type Cycles used
00000 Byte 1 0 one D0 –D7
00000 Word 0 0 one D0 –D15
00001 Byte 0 1 one D8 –D15
00001 Word 0 1 first D8 –D15
1 0 second D0 –D7
8086/80286
If memory chips available are only 2KB each do
the interfacing for 8086

Ex: Interface
4K 2716 (ROM) starting at 00000H
8K 6116 (SRAM) starting at 08000H
Memory Requirements
2716 – size 2K
ROM – 4k
Number of 2716 – 2 ROM – 4k
6116 – size 2k
RAM – 8k
RAM – 8k
Number of 6116 -4
 ROM – 4k

2k even 2k odd

RAM – 8k

4K 4K

2k even 2k odd 2k even 2k odd

Memory Map
ROM 1E - 00000H ,00002H, 00004H …….. 00FFEH
ROM 1O - 00001H, 00003H, 00005H …….. 00FFFH
RAM 1E - 08000H, 08002H, 08004H …….. 08FFEH
RAM 1O - 08001H, 08003H, 08005H ........ 08FFFH
RAM 2E - 09000H, 09002H, 09004H …….. 09FFEH
RAM 2O - 09001H, 09003H, 09005H …….. 09FFFH
ROM1 00000H – 00FFFH
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1

RAM1 08000H- 08FFFH

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
RAM2 09000H-09FFFH
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
 BHE
A0
S ROM1 ROM1E
O0
A16 A E
L O1 ROM1O
A15 B E
A12 C O2 RAM1 RAM1E
C T
O RAM2
A17 3
RAM1O
A18 LS138 O
4
A19 E
O5
G1 N RAM2E
A14 G2A A O6
A13 B RAM2O
G2B L
O7
E

Absolute Addressing
 A11 A10 D15 –D8 A11 D7 –D0
A10
2K
2K

A1 A0 A1
A17 CS A0
A18 CS
A19

G1
7
A12 C 4 A0
BHE
A15 B 1
3 3
A16 A 2
8
0
G2A G2B

A13 A14
8086-80286
Interface 1M of SRAM to 8086
Chips available are of size 256K each
A19A18A17A16 A15A14A13A12 A11A10A9A8 A7A6A5A4 A3A2A1A0

0 0 0 0 0 0 0 0 0 0 00 0000 0000
512KB
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 1
1 0 0 0 0 0 0 0 0 0 00 0000 0000
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 1 512KB
 A18 A17 D15 –D8 D7 –D0
A18 A17
256K
256K

A1 A0
CS A1 A0
CS
VCC VCC
GND GND
G1 G1
7 7
C 4 C 4
B 1 B 1
3 3
A19 A 1 A19 A 1
8 8
G2A G2B 0 G2A G2B 0

BHE GND A0 GND

8086-80286
Interface 16K of RAM to 8086 starting at 00000H

Chips available are 2KB(4 Chips) and 4KB (2 Chips)

RAM1even 00000H, 00002H, 00004H, ………….00FFEH
RAM1odd 00001H, 00003H, 00005H, ………….00FFFH
RAM2even 01000H, 01002H, 01004H, ………….01FFEH
RAM2odd 01001H, 01003H, 01005H, ………….01FFFH
RAM3even 02000H, 02002H, 02004H, ………….03FFEH
RAM3odd 02001H, 02003H, 02005H, ………….03FFFH
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1

0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
 S O0 RAM1
A14 A E
L RAM2
O1
A13 B E
A12 C O2
C T
O3 RAM3
A17
A18 LS138 O
4
A19 E
O5
G1 N
A15 G2A A O6
A16 B
G2B L
O7
E

Absolute Addressing
 4K 4K
A11 A10 D15 –D8 A11 D7 –D0
A
A1010
A1 A0 2K A1
WR A
A00 2K
2K WR
2K
BHE WR’ WR’
A17 RD’ CS A0
RD’ CS
A18
A19

G2A RD BHE
7 A0 RD
A12 C 4
A13 B 1 3
2
A 3
A16 1
8 0

G1 G2B
A14
M/IO’ A15
80286
 Interface 4K of ROM to 80286 starting at 080000H

Chips available are 2716.

ROMeven 080000H, 080002H, 080004H, ………….080FFEH

ROModd 080001H, 080003H, 080005H, ………….080FFFH

A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
 A11 A10 D15 –D8
A11 A10 D7 –D0
2K
2K

A1 A0
CS A1 A0
CS
A19 A19

7 7
A12 C 4 A12 C 4
A13 B 1 A13 B 1
A14 3 A14 3
A 1 A 1
8 8
0 0

BHE A0

A15A16A17A18
80286
Interface 8K of ROM to 80286 starting at 080000H
Chips available are 2 KB each

ROM1even 080000H, 080002H, 080004H, ………….080FFEH

ROM1odd 080001H, 080003H, 080005H, ………….080FFFH

ROM2even 081000H, 081002H, 081004H, …………. 081FFEH

ROM1odd 081001H, 081003H, 081005H, …………. 081FFFH
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1

1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1
 A11 A10 D15 –D8 D7 –D0
A11 A10
2K
2K

A1 A0
CS A1 A0
CS
A19 A19

7 7
A12 C 4 A12 C 4
A13 B 1 A13 B 1
A14 3 A14 3
A 1 A 1
8 8
0 0

BHE A0

A15A16A17A18 A19 A20 A21 A22 A23

Passing parameters in
subroutines & Macros
Passing Parameters to Procedures

 Parameters are data values or addresses passed back and forth between the
mainline program and the procedure
 Four ways to pass parameters
 In Registers
 In Dedicated memory locations accessed by name
 With pointers passed in registers
 With stack

BITS Pilani, Pilani Campus

 CALL SUMS
_____
_____
SUMS PROC NEAR
PUSH BX
PUSH CX
PUSH DX Save the contents of the
ADD BX, AX registers on the stack
ADD CX, BX which are used by
ADD DX,CX procedure and at the end,
ADD AX, DX retrieve the saved values.
POP DX
POP CX
POP BX
RET
SUMS ENDP

BITS Pilani, Pilani Campus

BCD to Binary conversion
(using parameter (data) in register)

-------------
-------------
MOV AL, BCDINPUT
The BCD number is copied from
CALL BCD_BIN memory to the AL and then
MOV BIN_VAL, AL passed to the procedure in the
----------- AL register.
------------------
Conversion example:
BCD – 16
Bin/hex -10h
(01 * 0ah ) + 6

BITS Pilani, Pilani Campus

Parameter stored in register

EX: BCD to Binary Conversion

BCD_BIN PROC NEAR
PUSHF
PUSH BX
PUSH CX Not pushing the AX register on
MOV BL , AL stack as we use it to pass a
value to the procedure and
AND BL , 0FH expect the procedure to pass a
AND AL , 0F0H different value back to the
program
MOV CL , 04
ROR AL, CL
MOV BH , 0AH
MUL BH
ADD AL, BL
POP CX Disadvantage: no of registers limit the no
POP BX of parameters that can be passed to
POPF procedures. Cant pass an array of 100
RET elements using registers.
BCD_BIN ENDP

BITS Pilani, Pilani Campus

Passing parameters stored in general memory

In the preceding example, why didn’t we simply access the BCD_INPUT and
BIN_VALUE by name from the procedure?
BCD_BIN PROC NEAR
PUSHF
PUSH AX
PUSH BX
PUSH CX
MOV AL, BCD_INPUT
MOV BL , AL
AND BL , 0FH
AND AL , 0F0H
MOV CL , 04
ROR AL, CL
MOV BH , 0AH
MUL BH
ADD AL, BL
MOV BIN_VALUE, AL
POP CX
POP BX
POP AX
POPF
RET
BCD_BIN ENDP
BITS Pilani, Pilani Campus
 Can be done but with severe limitation!!
 Procedure will always look for the named memory location BCD_INPUT to get its
data and will always put the result in BIN_VALUE.
 Or, we cant use this procedure to convert the BCD no stored somewhere else in
memory.

BITS Pilani, Pilani Campus

Passing parameters using pointers

EX: BCD to Binary Conversion

BCD_BIN PROC NEAR
PUSHF
PUSH AX More versatile than using
PUSH BX named memory location as the
PUSH CX
procedure pointers can point to
MOV AL, [SI]
MOV BL , AL
data anywhere in memory. Set
AND BL , 0FH up SI and DI acting as pointers.
AND AL , 0F0H MOV SI, OFFSET BCD_INPUT
MOV CL , 04 MOV DI, OFFSET BIN_VALUE
ROR AL, CL CALL BCD_BIN
MOV BH , 0AH NOP
MUL BH
ADD AL, BL
MOV [DI], AL
POP CX
POP BX
POP AX
POPF
RET
BCD_BIN ENDP
BITS Pilani, Pilani Campus
Passing parameters using stack

 Used in time sharing systems which consist of a mixture of high-level languages.

 Push parameters on stack before calling the procedure
 Instructions in procedure read these parameters from stack as needed.
 Parameters passed back from procedure are written on stack and read by the main-
line program.

BITS Pilani, Pilani Campus

 PUSH BP
MOV BP, SP
MOV AX, [BP + 12]
.model tiny MOV BL , AL
.data AND BL , 0FH
bcd_input db 16 AND AL , 0F0H
bin_value db (0) MOV CL , 04
.code ROR AL, CL
.startup
MOV BH , 0AH
MOV AL,BCD_INPUT
MUL BH
PUSH AX
CALL BCD_BIN ADD AL, BL
POP AX MOV [BP + 12], AX
MOV BIN_VALUE, AL POP BP
POP CX
;EX: BCD to Binary Conversion POP BX
BCD_BIN PROC NEAR POP AX
PUSHF POPF
PUSH AX
RET
PUSH BX
PUSH CX BCD_BIN ENDP
.exit
end

BITS Pilani, Pilani Campus

MOV AL, BCDINPUT
CALL BCD_BIN Using reg

BCD_BIN PROC NEAR

Using Mem
MOV AL, BCDINPUT

MOV SI, OFFSET BCDINPUT

CALL BCD_BIN Using Pointers

BCD_BIN PROC NEAR

MOV AL, [SI]

BITS Pilani, Pilani Campus

1. Write a near procedure SQRADD that squares the
contents of the CX register and adds that in BX
(storing it in BX). This procedure must not affect any
register except BX.

SQRADD PROC NEAR USES AX DX

MOV AX,CX
MUL CX
ADD BX, AX
RET
SQRADD ENDP
2. Write a procedure SUMS that sums EAX, EBX, ECX, and
EDX. If a carry occurs, place a logic 1 in EDI. If no carry
occurs, place a 0 in EDI. The sum should be found in EAX
after the execution of your procedure.
SUMS PROC NEAR
MOV EDI, 0
ADD EAX, EBX
JNC X2
MOV EDI, 01h
X2: ADD EAX, ECX
JNC X3
MOV EDI, 01h
X3: ADD EAX, EDX
JNC X4
MOV EDI, 01h
X4:
RET
SUMS ENDP
Advantages & Disadvantages

Advantage: reduces the code length for repetitive usage of a group of

instructions
– Machine code generated only once
Disadvantage: need stack and overhead time
– NOT SUITABLE if repetitive instructions are short

Solution: use MACROS

BITS Pilani, Pilani Campus

3. Develop a macro that sums a list of byte-sized data invoked by the
macro ADDM LIST, LENGTH. The label LIST is the starting address of
the data block and LENGTH is the number of data added. The result
must be a 16-bit sum found in AX at the end of the macro sequence.
ADDM MACRO LIST, LENGTH
PUSH CX
PUSH SI
PUSH BX
MOV BH, 00
MOV CX, LENGTH
MOV SI, LIST
MOV AX,0
X1: MOV BL, [SI]
ADD AX, BX
INC SI
DEC CX
JNZ X1
POP BX
POP SI
POP CX
ENDM
 BITS Pilani
Pilani Campus

MEMORY
Real & Protected Modes
REAL MEMORY

▪ First 1 MB
▪ conventional memory
▪ DOS Memory
▪ 8086/8088 – operate only in real mode
▪ Segment Registers & Monitors
▪ Code
▪ Data
▪ Stack
▪ Extra
▪ FS & GS
▪ Maximum segment size 64 K
▪ Segments - Relocatability

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus
PROTECTED MEMORY
▪ Above 1M
▪ Windows operate
▪ Segment + Offset
▪ Segment Register –Selector – Selects Descriptor from Descriptor
Table
▪ Descriptor
▪ Location
▪ Length
▪ Access Rights
▪ Instructions don’t change as still it is segment-
offset combo
▪ In 80386 & 80486 – 32-bit pointers possible

BITS Pilani, Pilani Campus

HOW DOES IT WORK?
▪ Two Descriptor Tables
▪ Global / System
▪ Apply to all programs
▪ Local /Application
▪ Apply to particular appln
▪ Each Descriptor Table has 8192 entries
▪ 16,384 descriptors
▪ 16,384 segments
▪ 4G size (80386)
▪ Virtually – 4G x 16K – 64T

BITS Pilani, Pilani Campus

 BITS Pilani
Pilani Campus

MEMORY
Protected Modes- Descriptor
DESCRIPTOR
▪ 8 bytes
▪ Total memory for GDT /LDT – 64K
▪ 80286 – upward compatible

BITS Pilani, Pilani Campus

DESCRIPTOR-80286

0000 0000 0000 0000

Access Rights Base Address

B16 – B24

Base Address Base Address

B8- B15 B0 – B7

Limit L8 - L15 Limit L0 – L7

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus
DESCRIPTOR-80386

Base Address G D 0 A Limit

B24 – B31 V L16 – L19

Access Rights Base Address B16 –

B24

Base Address Base Address

B8- B15 B0 – B7

Limit L8 - L15 Limit L0 – L7

BITS Pilani, Pilani Campus

EXAMPLE
▪ Base = Start = 1000 0000H
▪ G=0
▪ Limit – 001FFH
▪ End = 1000 0000 + 001FFH = 1000 01FFH
▪ G =1
▪ End = 1000 0000 + 001FF FFF = 101F FFFFH

BITS Pilani, Pilani Campus

 BITS Pilani
Pilani Campus

MEMORY
Protected Modes- Descriptor-The
Access Right Byte
 ACCESS RIGHT BYTES
FORMAT

P DPL DPL S E ED/C R/W A

E ED/C R/W ?
0 0 0 Data- Expands Upward –
Read Only
0 0 1 Data- Expands Upward - Write
0 1 0 Data - Expand Downward –
Read Only
0 1 1 Data- Expand Downward - Write
1 0 0 Code – Ignore DPL – Execute Only
1 0 1 Code – Ignore DPL – Read allowed
1 1 0 Code – Abide DPL – Execute Only
1 1 1 Code – Abide DPL – Read allowed BITS Pilani, Pilani Campus
 BITS Pilani
Pilani Campus

MEMORY
Protected Modes- Descriptor- Address
Translation
ACCESS RIGHT BYTES
FORMAT

P DPL DPL S E ED/C R/W A

BITS Pilani, Pilani Campus

ADDRESS TRANSLATION-
SEGMENT

Selector (15-3) TI RPL RPL

BITS Pilani, Pilani Campus

INVISIBLE REGISTERS

CS Base Address Limit Access

DS
ES
SS
FS
GS

LDTR Base Address Limit Access

TR

GDTR
IDTR

BITS Pilani, Pilani Campus

EXAMPLES 00
10
▪ DS:1000 93
20
▪ DS = 0018
00
▪ 1st 13 bits – 0000 0000 0001 1000 - GDT 00
FF
▪ GDTR + 0018 (entry no. 3)
3 FF
▪ GDTR – 00 00 00 00

▪ DS starts at – 00 20 00 00
▪ Linear Address

1 BITS Pilani, Pilani Campus

 BITS Pilani
Pilani Campus

MEMORY
Protected Modes- Descriptor- Address
Translation
EXAMPLES 00
00
▪ MOV AX,[1000H] 93
40
▪ DS:1000
00
▪ DS = 001C 00
FF
▪ 1st 13 bits – 0000 0000 0001
3 FF
1100 - LDT
▪ Selector – LDTR
▪ LDTR – 0018 – 0000 0000 0001
1000
▪ GDTR + 0018 (entry no. 3) 2
▪ GDTR – 00 00 00
▪ LDT starts at – 40 00 00

1 BITS Pilani, Pilani Campus

INVISIBLE REGISTERS

CS Base Address Limit Access

DS 40 00 00 FF FF 93
ES
SS
FS
GS

LDTR Base Address Limit Access

TR

GDTR
IDTR

BITS Pilani, Pilani Campus

EXAMPLES
00
00
▪ DS:1000 93
80
▪ DS = 001C
00
▪ 1st 13 bits – 0000 0000 0001 00
1100 - LDT 00
▪ Selector – LDTR 3 FF

▪ LDTR + 0018 (entry no. 3)

▪ GDTR – 00 00 00
▪ DS starts at – 80 00 00
▪ Linear Address – 80 10 00 2

1 BITS Pilani, Pilani Campus

 BITS Pilani
Pilani Campus

MEMORY
Real & Protected Modes- Paging
MEMORY-8086 TO 80486
▪ Segment (SR) - Offset
▪ 8086 /8088 – Real mode

▪ Segment Value shifted left by 4 bits + offset – 20 –bit address

▪ 80286
▪ Real Mode
▪ Protected Mode
▪ Segment Register – Selector – points to descriptor (LDT/GDT) – descriptor has
starting address of segment – Starting Address + Offset
▪ Virtual address – Physical Address (24-bits)
▪ Segmentation

BITS Pilani, Pilani Campus

MEMORY-8086 TO 80486
▪ 80386/80486
▪ Real Mode
▪ Protected Mode
▪ Segment Register – Selector – points to descriptor
(LDT/GDT) – descriptor has starting address of segment –
Starting Address + Offset
▪ Segmentation -Virtual address – Linear Address (32-
bits)
▪ Linear to Physical Address - Paging

BITS Pilani, Pilani Campus

DESCRIPTOR-80386 - 80486

Base GD 0 A Limit Access Rights Base

24-31 V 16-19 16-23
Base Limit
0-15

BITS Pilani, Pilani Campus

ADDRESS TRANSLATION -
SEGMENT

Selector (15-3) TI RPL RPL

BITS Pilani, Pilani Campus

EXAMPLES 00
00
93
▪ DS:0000 00
20
▪ DS = 0018
00
▪ 1st 13 bits – 0000 0000 0001 1000 FF
- GDT 18 FF
00
▪ GDTR + 0018 (entry no. 3) 00
▪ GDTR – 00 00 00 00 93
40
▪ DS starts at – 00 00 20 00 00
00
▪ Linear Address
00
10 FF

08 BITS Pilani, Pilani Campus

PAGING-80386 ONWARDS
▪ Linear – physical
▪ CR0 – CR3

▪ Page directory – 1024 entries – 4 bytes – each point to Page Table

▪ 1024 * 4 = 4k
▪ Page table – 1024 entries – 4 bytes – each point to Page
▪ 1024 *4 =4k

▪ Total no.pages
▪ 1024 * 1024 = 1 M
▪ Page block of 4k

BITS Pilani, Pilani Campus

LINEAR TO PHYSICAL

Directory 31-22 Page Table 21-12 Offset 11-0

00 00 20 00

0000 0000 0000 0000 0010 0000 0000 0000

BITS Pilani, Pilani Campus

CRO-3
▪ CR0 – MSB PG bit
▪ CR3 – BITS 12 -31- base address of Page Directory

BITS Pilani, Pilani Campus

PD/ PT ENTRY

P P
Address (31-12) D A CWUWP
DT

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus
LINEAR TO PHYSICAL
▪ 00 00 20 00
▪ 0000 0000 0000 0000 0010 0000 0000 0000
00002003 20
▪ CR3 – PD Base Address – 00 00 2 000
00002002 00
▪ Page Directory – 00 00 20 00 + 0000 0000 0000b 00002001 00
▪ PT address – 20 00 00 00 00002000 03
2000 000C
2000 000B 45
▪ PT Entry – 20 00 00 00 + 0000 00001000b
2000 000A 00
▪ PT Entry – 20 00 00 08 2000 0009 20
▪ Physical Address – 45 00 20 00 + 000 2000 0008 00
2000 0007
2000 0006
2000 0005
2000 0004
BITS Pilani, Pilani Campus
 8086-80486 Logical, string, jump & stack instruction
Subroutines

BITS Pilani Prof. Vinay Chamola and Prof. G.S.S Chalapathi

Pilani Campus Department of Electrical and Electronics
AND mem, mem not allowed.

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
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Example

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 CS/EEE/ECE/INSTR F241
Microprocessor and Interfacing
BITS Pilani
Pilani Campus
Last Lecture
➢ Interface to Analog to Digital Converter

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Today’s Lecture
➢ Programmable Interval Timer 8253/8254

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PIT- 8253/8254
➢ The 8254 solves one of the most common problems in
any microcomputer system, the generation of accurate
time delays under software control.
➢ Instead of setting up timing loops in software, the
programmer configures the 8254 to match his
requirements and programs one of the counters for the
desired delay.
➢ After the desired delay, the 8254 will interrupt the CPU.
➢ Software overhead is minimal and variable length delays
can easily be accommodated.
Counting/ Generation of Timing Signals
Software – delay routines
Adv – Flexibility
Disadv – Less precision
Hardware – 555/ RC
Adv – Precision
Disadv – Not Flexible
S/w Controlled hardware Timer- 8253/8254

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Features of 8253/8254
➢ Three 16 – bit counters
➢ Max frequency
➢ 2.6MHz 8253
➢ 8MHz 8254
➢ 10MHz 8254-2
➢ Down Counters
➢ Can load a Binary/BCD Number
➢ Can operate in one of 6 possible Modes

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D0 – D7 CLK0
GATE0
CS OUT0
RD
CLK1
WR
GATE1
A0
A1 OUT1
CLK2
VCC GATE2
GND OUT2
8253
Pin Out of 8253
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8253 – Timing

OUT = CLK

Count

Count – 16-bit

BCD/ Binary

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Power + 5V
CLK0
Supply GND Counter GATE0
Data
0 OUT0
D0 – D7 Bus

8 –bit internal data bus

Buffer

RD CLK1
WR Counter GATE1
R/W
A0 1
Control OUT1
A1
Logic
CS
CLK2
Counter GATE2
Control 2 OUT2
Reg

8253 Internal
Device Interface of 8253/8254
CLK0 –CLK2
– External clock – carries input frequency signal (square
wave, 33% duty cycle)
OUT0 – OUT2
– Can program wave shape: square wave, one-shot
– Various duty cycles
– No sine waves or saw-tooth shapes
GATE0 – GATE2
– Enables or disables the counter
– Sometimes needs a 0-1 pulse to enable

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CS’ A1 A0 Selected

0 0 0 Counter 0

0 0 1 Counter 1

0 1 0 Counter 2

0 1 1 Control Register

1 X X 8253 Not Selected

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D7 D6 D5 D4 D3 D2 D1 D0

SC1 SC0 RW1 RW0 M2 M1 M0 BCD

Selects Counter Read/Write Timer Mode 0–

Control 000 Interrupt on T/C binary
00 Counter 0 00 Latch 001 h/w re-Triggerable one 0000h
Counter shot FFFFh
01 Counter 1 010 rate generator
01 R/W LSB 1 – BCD
10 Counter 2 011 Square wave generator
10 R/W MSB 0000
11 Read Back 11 R/W LSB 9999
1x0 s/w triggered strobe
Command followed by
MSB 1x1 h/w triggered strobe

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Before you can use……
1. Initialize the mode of every counter planned to be used
2. This is done by sending individual command words for
every counter
3. These CWs are sent at A1A0 =11
4. Send counts to the counters
5. This is done at counter addresses
6. Enable gates for counting to start

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Ex:
8253 interfaced starting at 50H
C0 used in mode 1, MSB+LSB, binary
To be loaded with 4000H
C1 used in mode 0, LSB only, BCD
To be loaded with 99

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 A2 A0
A1 A1
A0
A3
CS
A5
A7
M/IO
8253
A4
A6
RD RD

WR WR

D0 – D7 D0 – D7

Interface to the processor

cnt0 equ 50h
cnt1 equ 52h
creg equ 56h
mov al,00110010b
out 56h,al
mov al,01010001b
out 56h,al
mov al,0
out 50h,al
mov al,40h
out 50h,al
mov al,99h
out 52h,al

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Timer Modes
 Mode 0

Interrupt on Terminal Count

(Event Counter)
WR’
CW LSB = 4

4 3 2 1 0 FF FE FD FC FB

CLK

GATE

OUT
 5V
2.3 V

Port
7407

LM139
L
P
E 5V
0V
D
D comparator
WR’
CW LSB = 4

4 3 2 2 2 2 2 1 0 FF FE

CLK

GATE

OUT
WR’
CW LSB = 4 LSB = 4

4 3 2 4 3 2 1 0 FF FE
CLK

GATE

OUT
➢ Mode 0
➢ Interrupt on terminal count (event counter)
➢ Out pin goes low when mode word or new count is written
➢ Now if clock is applied and gate=1, countdown begins
➢ Countdown stops if gate=0: resumes if gate=1
➢ If count written is N then OUT becomes high after N+1
clocks
➢ OUT remains high till a new count is written
➢ Countdown continues as FFFFH, FFFEH if gate =1
➢ Application – object counting

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 Mode 1

H/w Re-Triggerable One-Shot

(Programmable One- Shot)
WR’
CW LSB = 4
4 3 2 1 0 FF FE 4 3

CLK

GATE

OUT
WR’
CW LSB = 4
4 3 2 1 4 3 2 1 0

CLK

GATE

OUT
WR’
CW LSB = 4 LSB = 2
4 3 2 1 0 FF FE 2 1

CLK

GATE

OUT
➢ Mode 1
➢ Programmable one-shot- also h/w retriggerable one-shot
➢ Two step process
➢ Load count registers
➢ Send 0-to-1 pulse on GATE to trigger it
➢ When triggered  o/p goes low after one clock cycle & stays
low for N clock cycles  goes high
➢ If gate is made low it does not stop counter
➢ A +ve transition at gate reloads the counter & countdown
begins afresh
➢ A new count is not loaded till gate is triggered
➢ Application – detect ac power failure

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 Mode 2

Rate Generator
(Divide-by-N Counter)
WR’
CW LSB = 3

3 2 1 3 2 1 3 2 1 3 2

CLK

GATE

OUT
WR’
CW LSB = 3

3 2 1 3 2 2 3 2 1 3 2

CLK

GATE

OUT
WR’
CW LSB = 4 LSB = 5

4 3 2 1 5 4 3 2 1 5 4

CLK

GATE

OUT
➢ Mode 2
➢ Rate generator or divide-by-N counter
➢ Countdown starts one clock cycle after the gate is made high (or
one cycle after the count is written if gate is already high)
➢ On reaching a count of one the OUT goes low for one cycle. If
the counter is loaded with a number N, then OUT pin will go low
for one clock cycle every N input clock pulses.
➢ Now count is automatically reloaded and whole process repeats
➢ If a new count is written then it is loaded only after previous
countdown finishes
➢ If gate is made low during countdown then counting stops and
OUT is made immediately high
➢ Application : frequency generation, real time clock

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 Mode 3

Square Wave Generator

WR’
CW LSB = 4

4 2 4 2 4 2 4 2 4 2 4

CLK

GATE

OUT
WR’
CW LSB = 5
4 2 0 4 2 4 2 0 4 2 4

CLK

GATE

OUT
Mode 3
➢ Square wave generator
➢ If GATE = 1, OUT is a square wave (50% duty, or slightly off
if N is odd)
➢ If N is odd then will be high for (N+1)/2 and low for (N-1)/2
➢ Each clock pulse decrements the counter by 2
➢ Count is automatically reloaded on 2
➢ If gate is made low during countdown then counting stops
and when gate is made high again, counting continues.
➢ Application: clock input generation for other devices,
audio tone generator

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 Mode 4

Software Triggered Strobe

WR’
CW LSB = 4

4 3 2 1 0 FF FE

CLK

GATE

OUT
WR’
CW LSB = 4

4 3 2 2 2 2 2 1 0 FF FE

CLK

GATE

OUT
WR’
CW LSB = 4 LSB = 4

4 3 2 4 3 2 1 0 FF FE
CLK

GATE

OUT
Mode 4
– Software triggered strobe
– If GATE =1, OUT goes low N+1 cycles after the count is
written.
– OUT is low for one clock cycle
– Count must be reloaded to repeat the strobe
– not automatically reloaded
– If GATE→low, the OUT → high and count stops; count
resumes (from where it stopped) when GATE→high
– Application : I/O strobe

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 Mode 5

Hardware Triggered Strobe

WR’
CW LSB = 4
4 3 2 1 0 FF FE 4 3

CLK

GATE

OUT
WR’
CW LSB = 4
4 3 2 1 4 3 2 1 0 FF

CLK

GATE

OUT
WR’
CW LSB = 4 LSB = 2
4 3 2 1 0 FF FE 2 1

CLK

GATE

OUT
Mode 5
– Hardware triggered strobe
– Like mode 4, but triggering is done with GATE instead
– Count begins when 0-1 pulse hits GATE
– OUT goes low N+1 cycles after gate is triggered.
– OUT is low for one clock cycle
– Gate must be triggered again to repeat the strobe
– not automatically reloaded
– If GATE→low, it does not stop countdown
– A trigger on gate in between countdown will reload the
count and keep OUT high
– Appln: I/O handshake

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➢Reading Count
➢ For reading the count….Counting must be stopped.
➢ Can be done by removing clock, gate etc…….but not
preferred.
➢ So….
➢ Latch the count before reading…..by
➢ Sending counter latch command word at CR (A1 A0 =11) and
then read

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Read back command word (8254 only)

1 1 Count Status C2 C1 C0 0

Issued with A1 A0 =11

Can latch count in all counters simultaneously
Latch either count or status (not both)

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Microprocessor Programming and
Interfacing
Tutorial-12

8259
Problem-1
Work out the 8259 interfacing connections with 8086 given that
the 8259 address is 074X. Write an ALP (Assembly language
procedure) to initialize the 8259A with following functionalities
[IR0 is of type 80H]
• single level triggered mode
• non-buffered on special fully nested mode.
• Set the 8259A to operate with IR6 masked,
• Set IR4 as bottom priority level with rotate on specific EOI mode.
• Set special mask mode of 8259A.
• Also, read IRR and ISR into registers BH and BL respectively.
Step-1: FindingAddress
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address of Port

0 0 0 0 0 1 1 1 0 1 0 0 0 0 0 0 0740H (ICW1, OCW2, OCW3)

0 0 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0742H (ICW2,ICW4,OCW1, ICW3)

A1 connected to A0
Again the same even bus/
odd bus funda !!!
Step-2: Finding the ICW1

Don’t cares
A0 A7 A6 A5 1 LTIM ADI SNGL IC4
0 0 0 0 1 1 1 1 1 ICW1= 1FH

Don’t care for 8086 (Level Single

Address bitA0=0, triggered) mode
for ICW1 Fixed
Call ICW4
(not part of ICW) (always1)
address needed
Interval 4
Step-3: Finding ICW2

Don’t cares

1 0 0 0 0 0 0 0 ICW2=80H

ICW3 is not needed as 8259A is set in single mode.

Step-4: Finding the ICW4

Don’t cares

A0 D7 D6 D5 SFNM BUT M/S AEOI uPM

1 0 0 0 1 0 0 0 1 ICW4= 11H

Fixed Non-buffered
A0=1, forICW4 mode For 8086
For special fully microprocessor
nested mode
masking Normal
EOI
Step-5: Finding OCW1

A0 D7 D6 D5 D4 D3 D2 D1 D0
1 0 1 0 0 0 0 0 0

OCW1= 40H
IR6 is masked
Step-6: Finding the OCW2

A0 D7 D6 D5 D4 D3 D2 D1 D0
0 1 1 1 0 0 1 0 0 OCW2= E4H

Rotate on Specific Fixed Bottom priority

A0=0, forOCW2 EOI command level set at IR4
Step-8: Finding OCW3

The OCW3 sets the special mask mode and reads ISR and IRR using the following control words-
For reading IRR:
A0 D7 D6 D5 D4 D3 D2 D1 D0
0 0 1 1 0 1 0 1 0

fixed Special masked Fixed Read IRR

mode No poll command
For reading ISR: OCW3= 6AH

A0 D7 D6 D5 D4 D3 D2 D1 D0
0 0 1 1 0 1 0 1 1

fixed Special masked Fixed Read ISR

mode No poll command OCW3= 6BH
Writing ALP

Val address
ICW1 1Fh 0740h
ICW2 80h 0742h
ICW4 11h 0742h
OCW1 40h 0742h
OCW2 E4h 0740h
OCW3 6Ah (IRR) 0740h
OCW3 6Bh (ISR) 0740h
INTERRUPT PROC NEAR
MOV AL, 1FH ; Loading ICW1 to AL
MOV DX, 0740H ; Loading Address of ICW1 to DX (Variable port addressing)
OUT DX, AL ; Sending ICW1 to port (address: 0740H ) of 8259A
MOV DX, 0742H ; address of ICW2
Val address
MOV AL, 80H ; Loading ICW2 to AL which select the vector address
ICW1 1Fh 0740h
OUT DX, AL ; Sending ICW2 to port (address: 0742H ) of 8259A
ICW2 80h 0742h
MOV AL, 11H ; Loading ICW4 to AL
ICW4 11h 0742h
OUT DX, AL ; Sends ICW4 to 0742H
OCW1 40h 0742h
MOV AL, 40H ; Loading OCW1 to AL
OUT DX, AL ; Sends OCW1 to 0742H OCW2 E4h 0740h
MOV AL, E4H ; Loading OCW2 to AL OCW3 6Ah (IRR) 0740h
MOV DX, 0740H ; Address of OCW2 OCW3 6Bh (ISR) 0740h
MOV DX, AL ; Sending OCW2 to 0740H address.
MOV AL, 6AH ; Loading OCW3 for reading IRR
OUT DX, AL; Sending OCW3 to 0740H address.
IN AL, DX ; Reading IRR and store to AL
MOV BH, AL; Store IRR into BH
MOV AL, 6BH ; Loading OCW3 for reading ISR
OUT DX, AL; Sending OCW3 to 0740H address.
IN AL, DX ; Reading ISR and store to AL
MOV BL, AL; Store ISR into BL
RET
INTERRUPT ENDP
 Solution of same qn from original source

https://books.google.co.in/books?id=KJNpD2KimEsC&pg=PA259&lpg=PA259&dq=8259+solved+problem+microprocessor&source=bl&ots=eNuvVGs5Uc&sig=tvWq94QTG8Ev_LmGwTpNbHcKTHA&hl=en&sa=X&ved=0ahUKEwinveKd98LaAhVJtI
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